From 0e098678b5bf29285379759a31d7421987e64b02 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Mon, 13 Mar 2017 18:10:00 +0100 Subject: [PATCH 01/10] First pass on TB Sense (and EFR32MG12) support --- .../TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp | 6 +- .../TARGET_EFR32MG12/PeripheralNames.h | 69 + .../TARGET_EFR32MG12/PeripheralPins.c | 427 +++ .../TARGET_EFR32MG12/PeripheralPins.h | 53 + .../TARGET_THUNDERBOARD_SENSE_12/PinNames.h | 81 + .../device_peripherals.h | 56 + .../device/TOOLCHAIN_ARM_STD/efr32mg12p.sct | 15 + .../TOOLCHAIN_ARM_STD/startup_efr32mg12p.S | 320 +++ .../device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld | 215 ++ .../TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S | 360 +++ .../TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf | 33 + .../device/TOOLCHAIN_IAR/startup_efr32mg1p.s | 354 +++ .../device/efr32mg12p132f1024gl125.h | 2057 ++++++++++++++ .../device/efr32mg12p132f1024gm48.h | 2057 ++++++++++++++ .../device/efr32mg12p232f1024gl125.h | 2057 ++++++++++++++ .../device/efr32mg12p232f1024gm48.h | 2057 ++++++++++++++ .../device/efr32mg12p332f1024gl125.h | 2057 ++++++++++++++ .../device/efr32mg12p332f1024gm48.h | 2057 ++++++++++++++ .../device/efr32mg12p432f1024gl125.h | 2057 ++++++++++++++ .../device/efr32mg12p432f1024gm48.h | 2057 ++++++++++++++ .../device/efr32mg12p433f1024gl125.h | 2057 ++++++++++++++ .../device/efr32mg12p433f1024gm48.h | 2057 ++++++++++++++ .../TARGET_EFR32MG12/device/efr32mg12p_acmp.h | 1420 ++++++++++ .../TARGET_EFR32MG12/device/efr32mg12p_adc.h | 2371 +++++++++++++++++ .../device/efr32mg12p_af_pins.h | 166 ++ .../device/efr32mg12p_af_ports.h | 166 ++ .../TARGET_EFR32MG12/device/efr32mg12p_cmu.h | 2032 ++++++++++++++ .../device/efr32mg12p_cryotimer.h | 167 ++ .../device/efr32mg12p_crypto.h | 1216 +++++++++ .../TARGET_EFR32MG12/device/efr32mg12p_csen.h | 1003 +++++++ .../device/efr32mg12p_devinfo.h | 1298 +++++++++ .../device/efr32mg12p_dma_descriptor.h | 52 + .../device/efr32mg12p_dmareq.h | 110 + .../TARGET_EFR32MG12/device/efr32mg12p_emu.h | 1437 ++++++++++ .../TARGET_EFR32MG12/device/efr32mg12p_etm.h | 781 ++++++ .../device/efr32mg12p_fpueh.h | 192 ++ .../device/efr32mg12p_gpcrc.h | 185 ++ .../TARGET_EFR32MG12/device/efr32mg12p_gpio.h | 1538 +++++++++++ .../device/efr32mg12p_gpio_p.h | 56 + .../TARGET_EFR32MG12/device/efr32mg12p_i2c.h | 921 +++++++ .../TARGET_EFR32MG12/device/efr32mg12p_idac.h | 352 +++ .../TARGET_EFR32MG12/device/efr32mg12p_ldma.h | 643 +++++ .../device/efr32mg12p_ldma_ch.h | 53 + .../device/efr32mg12p_lesense.h | 1867 +++++++++++++ .../device/efr32mg12p_lesense_buf.h | 46 + .../device/efr32mg12p_lesense_ch.h | 49 + .../device/efr32mg12p_lesense_st.h | 47 + .../device/efr32mg12p_letimer.h | 620 +++++ .../device/efr32mg12p_leuart.h | 835 ++++++ .../TARGET_EFR32MG12/device/efr32mg12p_msc.h | 664 +++++ .../TARGET_EFR32MG12/device/efr32mg12p_pcnt.h | 706 +++++ .../TARGET_EFR32MG12/device/efr32mg12p_prs.h | 1089 ++++++++ .../device/efr32mg12p_prs_ch.h | 46 + .../device/efr32mg12p_prs_signals.h | 166 ++ .../TARGET_EFR32MG12/device/efr32mg12p_rmu.h | 191 ++ .../device/efr32mg12p_romtable.h | 72 + .../TARGET_EFR32MG12/device/efr32mg12p_rtcc.h | 695 +++++ .../device/efr32mg12p_rtcc_cc.h | 49 + .../device/efr32mg12p_rtcc_ret.h | 46 + .../TARGET_EFR32MG12/device/efr32mg12p_smu.h | 400 +++ .../device/efr32mg12p_timer.h | 1575 +++++++++++ .../device/efr32mg12p_timer_cc.h | 49 + .../TARGET_EFR32MG12/device/efr32mg12p_trng.h | 279 ++ .../device/efr32mg12p_usart.h | 1972 ++++++++++++++ .../TARGET_EFR32MG12/device/efr32mg12p_vdac.h | 1539 +++++++++++ .../device/efr32mg12p_vdac_opa.h | 53 + .../TARGET_EFR32MG12/device/efr32mg12p_wdog.h | 335 +++ .../device/efr32mg12p_wdog_pch.h | 46 + .../TARGET_EFR32MG12/device/em_device.h | 80 + .../device/system_efr32mg12p.c | 384 +++ .../device/system_efr32mg12p.h | 154 ++ .../TARGET_EFM32/common/CommonPinNames.h | 7 +- .../buffer_pool_allocator.c | 4 +- .../ieee802154_efr32xg12_configurator_out.c | 133 + .../ieee802154_efr32xg12_configurator_out.h | 18 + .../TARGET_EFR32MG12/librail_efr32xg12.a | Bin 0 -> 193280 bytes targets/TARGET_Silicon_Labs/mbed_rtx.h | 13 + targets/targets.json | 47 + 78 files changed, 52988 insertions(+), 6 deletions(-) create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralNames.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/PinNames.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg1p.s create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.c create mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12.a diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index e4a7dfb4cd..925895bac5 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -67,6 +67,8 @@ static const RAIL_CsmaConfig_t csma_config = RAIL_CSMA_CONFIG_802_15_4_2003_2p4_ #if defined(TARGET_EFR32MG1) #include "ieee802154_subg_efr32xg1_configurator_out.h" #include "ieee802154_efr32xg1_configurator_out.h" +#elif defined(TARGET_EFR32MG12) +#include "ieee802154_efr32xg12_configurator_out.h" #else #error "Not a valid target." #endif @@ -724,7 +726,7 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { /* Save the pending bit */ last_ack_pending_bit = (rxPacketInfo->dataPtr[1] & (1 << 4)) != 0; /* Tell the stack we got an ACK */ - tr_debug("rACK\n"); + //tr_debug("rACK\n"); device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, PHY_LINK_TX_DONE, @@ -745,7 +747,7 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { RAIL_AutoAckCancelAck(); } - tr_debug("rPKT %d\n", rxPacketInfo->dataLength); + //tr_debug("rPKT %d\n", rxPacketInfo->dataLength); /* Feed the received packet into the stack */ device_driver.phy_rx_cb(rxPacketInfo->dataPtr + 1, rxPacketInfo->dataLength - 1, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralNames.h new file mode 100644 index 0000000000..2e5170aef5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralNames.h @@ -0,0 +1,69 @@ +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "em_adc.h" +#include "em_usart.h" +#include "em_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_0 = ADC0_BASE +} ADCName; + +typedef enum { + I2C_0 = I2C0_BASE, + I2C_1 = I2C1_BASE, +} I2CName; + +typedef enum { + PWM_CH0 = 0, + PWM_CH1 = 1, + PWM_CH2 = 2, + PWM_CH3 = 3 +} PWMName; + +typedef enum { + USART_0 = USART0_BASE, + USART_1 = USART1_BASE, + USART_2 = USART2_BASE, + USART_3 = USART3_BASE, + LEUART_0 = LEUART0_BASE, +} UARTName; + +typedef enum { + SPI_0 = USART0_BASE, + SPI_1 = USART1_BASE, + SPI_2 = USART2_BASE, + SPI_3 = USART3_BASE, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c new file mode 100644 index 0000000000..95baad0840 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.c @@ -0,0 +1,427 @@ +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "PeripheralPins.h" + +/************ADC***************/ +/* The third "function" value is used to select the correct ADC channel */ +const PinMap PinMap_ADC[] = { + {PA0, ADC_0, adcPosSelAPORT3XCH8}, + {PA1, ADC_0, adcPosSelAPORT4XCH9}, + {PA2, ADC_0, adcPosSelAPORT3XCH10}, + {PA3, ADC_0, adcPosSelAPORT4XCH11}, + {PA4, ADC_0, adcPosSelAPORT3XCH12}, + {PA5, ADC_0, adcPosSelAPORT4XCH13}, + + {PB11, ADC_0, adcPosSelAPORT4XCH27}, + {PB12, ADC_0, adcPosSelAPORT3XCH28}, + {PB14, ADC_0, adcPosSelAPORT3XCH30}, + {PB15, ADC_0, adcPosSelAPORT4XCH31}, + + {PC6, ADC_0, adcPosSelAPORT1XCH6}, + {PC7, ADC_0, adcPosSelAPORT2XCH7}, + {PC8, ADC_0, adcPosSelAPORT1XCH8}, + {PC9, ADC_0, adcPosSelAPORT2XCH9}, + {PC10, ADC_0, adcPosSelAPORT1XCH10}, + {PC11, ADC_0, adcPosSelAPORT2XCH11}, + + {PD9, ADC_0, adcPosSelAPORT4XCH1}, + {PD10, ADC_0, adcPosSelAPORT3XCH2}, + {PD11, ADC_0, adcPosSelAPORT3YCH3}, + {PD12, ADC_0, adcPosSelAPORT3XCH4}, + {PD13, ADC_0, adcPosSelAPORT3YCH5}, + {PD14, ADC_0, adcPosSelAPORT3XCH6}, + {PD15, ADC_0, adcPosSelAPORT4XCH7}, + + {PF0, ADC_0, adcPosSelAPORT1XCH16}, + {PF1, ADC_0, adcPosSelAPORT2XCH17}, + {PF2, ADC_0, adcPosSelAPORT1XCH18}, + {PF3, ADC_0, adcPosSelAPORT2XCH19}, + {PF4, ADC_0, adcPosSelAPORT1XCH20}, + {PF5, ADC_0, adcPosSelAPORT2XCH21}, + {PF6, ADC_0, adcPosSelAPORT1XCH22}, + {PF7, ADC_0, adcPosSelAPORT2XCH23}, + {NC , NC , NC} +}; + +/************I2C SCL***********/ +const PinMap PinMap_I2C_SCL[] = { + /* I2C0 */ + {PA1, I2C_0, 0}, + {PA2, I2C_0, 1}, + {PA3, I2C_0, 2}, + {PA4, I2C_0, 3}, + {PA5, I2C_0, 4}, + {PB11, I2C_0, 5}, + {PB12, I2C_0, 6}, + {PB13, I2C_0, 7}, + {PB14, I2C_0, 8}, + {PB15, I2C_0, 9}, + {PC6, I2C_0, 10}, + {PC7, I2C_0, 11}, + {PC8, I2C_0, 12}, + {PC9, I2C_0, 13}, + {PC10, I2C_0, 14}, + {PC11, I2C_0, 15}, + {PD9, I2C_0, 16}, + {PD10, I2C_0, 17}, + {PD11, I2C_0, 18}, + {PD12, I2C_0, 19}, + {PD13, I2C_0, 20}, + {PD14, I2C_0, 21}, + {PD15, I2C_0, 22}, + {PF0, I2C_0, 23}, + {PF1, I2C_0, 24}, + {PF2, I2C_0, 25}, + {PF3, I2C_0, 26}, + {PF4, I2C_0, 27}, + {PF5, I2C_0, 28}, + {PF6, I2C_0, 29}, + {PF7, I2C_0, 30}, + {PA0, I2C_0, 31}, + + {NC , NC , NC} +}; + +/************I2C SDA***********/ +const PinMap PinMap_I2C_SDA[] = { + /* I2C0 */ + {PA0, I2C_0, 0}, + {PA1, I2C_0, 1}, + {PA2, I2C_0, 2}, + {PA3, I2C_0, 3}, + {PA4, I2C_0, 4}, + {PA5, I2C_0, 5}, + {PB11, I2C_0, 6}, + {PB12, I2C_0, 7}, + {PB13, I2C_0, 8}, + {PB14, I2C_0, 9}, + {PB15, I2C_0, 10}, + {PC6, I2C_0, 11}, + {PC7, I2C_0, 12}, + {PC8, I2C_0, 13}, + {PC9, I2C_0, 14}, + {PC10, I2C_0, 15}, + {PC11, I2C_0, 16}, + {PD9, I2C_0, 17}, + {PD10, I2C_0, 18}, + {PD11, I2C_0, 19}, + {PD12, I2C_0, 20}, + {PD13, I2C_0, 21}, + {PD14, I2C_0, 22}, + {PD15, I2C_0, 23}, + {PF0, I2C_0, 24}, + {PF1, I2C_0, 25}, + {PF2, I2C_0, 26}, + {PF3, I2C_0, 27}, + {PF4, I2C_0, 28}, + {PF5, I2C_0, 29}, + {PF6, I2C_0, 30}, + {PF7, I2C_0, 31}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PA0, PWM_CH0, 0}, + {PA1, PWM_CH1, 0}, + {PA2, PWM_CH2, 0}, + {PA3, PWM_CH3, 0}, + {PA4, PWM_CH2, 2}, + {PA5, PWM_CH3, 2}, + {PB11, PWM_CH1, 5}, + {PB12, PWM_CH2, 5}, + {PB13, PWM_CH3, 5}, + {PB14, PWM_CH0, 9}, + {PB15, PWM_CH0, 10}, + {PC6, PWM_CH0, 11}, + {PC7, PWM_CH1, 11}, + {PC8, PWM_CH2, 11}, + {PC9, PWM_CH3, 11}, + {PC10, PWM_CH2, 13}, + {PC11, PWM_CH3, 13}, + {PD9, PWM_CH3, 14}, + {PD10, PWM_CH0, 18}, + {PD11, PWM_CH1, 18}, + {PD12, PWM_CH2, 18}, + {PD13, PWM_CH3, 18}, + {PD14, PWM_CH0, 22}, + {PD15, PWM_CH1, 22}, + {PF0, PWM_CH0, 24}, + {PF1, PWM_CH1, 24}, + {PF2, PWM_CH2, 24}, + {PF3, PWM_CH3, 24}, + {PF4, PWM_CH0, 28}, + {PF5, PWM_CH1, 28}, + {PF6, PWM_CH2, 28}, + {PF7, PWM_CH3, 28}, + + {NC , NC , NC} +}; + +/*************SPI**************/ +const PinMap PinMap_SPI_MOSI[] = { + + /* USART0 */ + {PA0, SPI_0, 0}, + {PA1, SPI_0, 1}, + {PA2, SPI_0, 2}, + {PA3, SPI_0, 3}, + {PA4, SPI_0, 4}, + {PA5, SPI_0, 5}, + {PB11, SPI_0, 6}, + {PB12, SPI_0, 7}, + {PB13, SPI_0, 8}, + {PB14, SPI_0, 9}, + {PB15, SPI_0, 10}, + {PD9, SPI_0, 17}, + {PD10, SPI_0, 18}, + {PD11, SPI_0, 19}, + {PD12, SPI_0, 20}, + {PD13, SPI_0, 21}, + {PD14, SPI_0, 22}, + {PD15, SPI_0, 23}, + + /* USART1 */ + {PC6, SPI_1, 11}, + {PC7, SPI_1, 12}, + {PC8, SPI_1, 13}, + {PC9, SPI_1, 14}, + {PC10, SPI_1, 15}, + {PC11, SPI_1, 16}, + {PF0, SPI_1, 24}, + {PF1, SPI_1, 25}, + {PF2, SPI_1, 26}, + {PF3, SPI_1, 27}, + {PF4, SPI_1, 28}, + {PF5, SPI_1, 29}, + {PF6, SPI_1, 30}, + {PF7, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_MISO[] = { + + /* USART0 */ + {PA0, SPI_0, 31}, + {PA1, SPI_0, 0}, + {PA2, SPI_0, 1}, + {PA3, SPI_0, 2}, + {PA4, SPI_0, 3}, + {PA5, SPI_0, 4}, + {PB11, SPI_0, 5}, + {PB12, SPI_0, 6}, + {PB13, SPI_0, 7}, + {PB14, SPI_0, 8}, + {PB15, SPI_0, 9}, + {PD9, SPI_0, 16}, + {PD10, SPI_0, 17}, + {PD11, SPI_0, 18}, + {PD12, SPI_0, 19}, + {PD13, SPI_0, 20}, + {PD14, SPI_0, 21}, + {PD15, SPI_0, 22}, + + /* USART1 */ + {PC6, SPI_1, 10}, + {PC7, SPI_1, 11}, + {PC8, SPI_1, 12}, + {PC9, SPI_1, 13}, + {PC10, SPI_1, 14}, + {PC11, SPI_1, 15}, + {PF0, SPI_1, 23}, + {PF1, SPI_1, 24}, + {PF2, SPI_1, 25}, + {PF3, SPI_1, 26}, + {PF4, SPI_1, 27}, + {PF5, SPI_1, 28}, + {PF6, SPI_1, 29}, + {PF7, SPI_1, 30}, + {PA0, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_CLK[] = { + + /* USART0 */ + {PA0, SPI_0, 30}, + {PA1, SPI_0, 31}, + {PA2, SPI_0, 0}, + {PA3, SPI_0, 1}, + {PA4, SPI_0, 2}, + {PA5, SPI_0, 3}, + {PB11, SPI_0, 4}, + {PB12, SPI_0, 5}, + {PB13, SPI_0, 6}, + {PB14, SPI_0, 7}, + {PB15, SPI_0, 8}, + {PD9, SPI_0, 15}, + {PD10, SPI_0, 16}, + {PD11, SPI_0, 17}, + {PD12, SPI_0, 18}, + {PD13, SPI_0, 19}, + {PD14, SPI_0, 20}, + {PD15, SPI_0, 21}, + + /* USART1 */ + {PC6, SPI_1, 9}, + {PC7, SPI_1, 10}, + {PC8, SPI_1, 11}, + {PC9, SPI_1, 12}, + {PC10, SPI_1, 13}, + {PC11, SPI_1, 14}, + {PF0, SPI_1, 22}, + {PF1, SPI_1, 23}, + {PF2, SPI_1, 24}, + {PF3, SPI_1, 25}, + {PF4, SPI_1, 26}, + {PF5, SPI_1, 27}, + {PF6, SPI_1, 28}, + {PF7, SPI_1, 29}, + {PA0, SPI_1, 30}, + {PA1, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_CS[] = { + + /* USART0 */ + {PA0, SPI_0, 29}, + {PA1, SPI_0, 30}, + {PA2, SPI_0, 31}, + {PA3, SPI_0, 0}, + {PA4, SPI_0, 1}, + {PA5, SPI_0, 2}, + {PB11, SPI_0, 3}, + {PB12, SPI_0, 4}, + {PB13, SPI_0, 5}, + {PB14, SPI_0, 6}, + {PB15, SPI_0, 7}, + {PD9, SPI_0, 14}, + {PD10, SPI_0, 15}, + {PD11, SPI_0, 16}, + {PD12, SPI_0, 17}, + {PD13, SPI_0, 18}, + {PD14, SPI_0, 19}, + {PD15, SPI_0, 20}, + + /* USART1 */ + {PC6, SPI_1, 8}, + {PC7, SPI_1, 9}, + {PC8, SPI_1, 10}, + {PC9, SPI_1, 11}, + {PC10, SPI_1, 12}, + {PC11, SPI_1, 13}, + {PF0, SPI_1, 21}, + {PF1, SPI_1, 22}, + {PF2, SPI_1, 23}, + {PF3, SPI_1, 24}, + {PF4, SPI_1, 25}, + {PF5, SPI_1, 26}, + {PF6, SPI_1, 27}, + {PF7, SPI_1, 28}, + + {NC , NC , NC} +}; + +/************UART**************/ +const PinMap PinMap_UART_TX[] = { + {PA0, USART_0, 0}, + {PA1, USART_0, 1}, + {PA2, USART_0, 2}, + {PA3, USART_0, 3}, + {PA4, USART_0, 4}, + {PA5, USART_0, 5}, + {PB11, USART_0, 6}, + {PB12, USART_0, 7}, + {PB13, USART_0, 8}, + {PB14, USART_0, 9}, + {PB15, USART_0, 10}, + {PD9, LEUART_0, 17}, + {PD10, LEUART_0, 18}, + {PD11, LEUART_0, 19}, + {PD12, LEUART_0, 20}, + {PD13, LEUART_0, 21}, + {PD14, LEUART_0, 22}, + {PD15, LEUART_0, 23}, + + {PC6, USART_1, 11}, + {PC7, USART_1, 12}, + {PC8, USART_1, 13}, + {PC9, USART_1, 14}, + {PC10, USART_1, 15}, + {PC11, USART_1, 16}, + {PF0, USART_1, 24}, + {PF1, USART_1, 25}, + {PF2, USART_1, 26}, + {PF3, USART_1, 27}, + {PF4, USART_1, 28}, + {PF5, USART_1, 29}, + {PF6, USART_1, 30}, + {PF7, USART_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_UART_RX[] = { + {PA0, USART_0, 31}, + {PA1, USART_0, 0}, + {PA2, USART_0, 1}, + {PA3, USART_0, 2}, + {PA4, USART_0, 3}, + {PA5, USART_0, 4}, + {PB11, USART_0, 5}, + {PB12, USART_0, 6}, + {PB13, USART_0, 7}, + {PB14, USART_0, 8}, + {PB15, USART_0, 9}, + {PD9, LEUART_0, 16}, + {PD10, LEUART_0, 17}, + {PD11, LEUART_0, 18}, + {PD12, LEUART_0, 19}, + {PD13, LEUART_0, 20}, + {PD14, LEUART_0, 21}, + {PD15, LEUART_0, 22}, + + {PC6, USART_1, 10}, + {PC7, USART_1, 11}, + {PC8, USART_1, 12}, + {PC9, USART_1, 13}, + {PC10, USART_1, 14}, + {PC11, USART_1, 15}, + {PF0, USART_1, 23}, + {PF1, USART_1, 24}, + {PF2, USART_1, 25}, + {PF3, USART_1, 26}, + {PF4, USART_1, 27}, + {PF5, USART_1, 28}, + {PF6, USART_1, 29}, + {PF7, USART_1, 30}, + + {NC , NC , NC} +}; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.h new file mode 100644 index 0000000000..79d6072e83 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/PeripheralPins.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************I2C SCL***********/ +extern const PinMap PinMap_I2C_SCL[]; + +/************I2C SDA***********/ +extern const PinMap PinMap_I2C_SDA[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_CLK[]; +extern const PinMap PinMap_SPI_CS[]; + +/************UART**************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +#endif + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/PinNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/PinNames.h new file mode 100644 index 0000000000..a56373d4d9 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/PinNames.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "CommonPinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + EFM32_STANDARD_PIN_DEFINITIONS, + + /* Starter Kit says LED0 and LED1, but mbed expects 1 and 2. This way using 1 and 2 or 0 and 1 will work. */ + LED0 = PD8, + LED1 = PD9, + LED2 = LED0, + LED3 = LED0, + LED4 = LED1, + + /* Push Buttons */ + SW0 = PD14, + SW1 = PD15, + BTN0 = SW0, + BTN1 = SW1, + + /* Expansion headers */ + EXP3 = PA8, + EXP4 = PC6, + EXP5 = PA9, + EXP6 = PC7, + EXP7 = PF3, + EXP8 = PC8, + EXP9 = PF4, + EXP10 = PC9, + EXP11 = PF5, + EXP12 = PA6, + EXP13 = PF6, + EXP14 = PA7, + EXP15 = PC11, + EXP16 = PC10, + + /* Serial (just some usable pins) */ + SERIAL_TX = PA6, + SERIAL_RX = PA7, + + /* Board Controller UART (USB)*/ + USBTX = PA0, + USBRX = PA1, + + /* Board Controller */ + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h new file mode 100644 index 0000000000..93f2510639 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h @@ -0,0 +1,56 @@ +/***************************************************************************//** + * @file device_peripherals.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_DEVICE_PERIPHERALS_H +#define MBED_DEVICE_PERIPHERALS_H + +/* us ticker */ +#define US_TICKER_TIMER TIMER0 +#define US_TICKER_TIMER_CLOCK cmuClock_TIMER0 +#define US_TICKER_TIMER_IRQ TIMER0_IRQn + +/* PWM */ +#define PWM_TIMER TIMER1 +#define PWM_TIMER_CLOCK cmuClock_TIMER1 +#define PWM_ROUTE TIMER_ROUTE_LOCATION_LOC1 + +/* Crystal calibration */ +#if !defined(CMU_HFXOINIT_WSTK_DEFAULT) +#define CMU_HFXOINIT_WSTK_DEFAULT \ +{ \ + false, /* Low-noise mode for EFR32 */ \ + false, /* Disable auto-start on EM0/1 entry */ \ + false, /* Disable auto-select on EM0/1 entry */ \ + false, /* Disable auto-start and select on RAC wakeup */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + 0x142, /* Steady-state CTUNE for WSTK boards without load caps */ \ + _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ + _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ + 0x7, /* Recommended steady-state XO core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ + 0xA, /* Recommended peak detection timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ +} +#endif +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct new file mode 100644 index 0000000000..974cbb0c37 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000108 0x0003FEF8 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S new file mode 100644 index 0000000000..514135d4d6 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S @@ -0,0 +1,320 @@ +;/**************************************************************************//** +; * @file startup_efr32mg1p.s +; * @brief CMSIS Core Device Startup File for +; * Silicon Labs EFR32MG1P Device Series +; * @version 4.3.0 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00010000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY, ALIGN=8 + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD FRC_IRQHandler ; 4: FRC Interrupt + DCD MODEM_IRQHandler ; 5: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 8: BUFC Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 28: AGC Interrupt + DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved + +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT EMU_IRQHandler [WEAK] + EXPORT FRC_PRI_IRQHandler [WEAK] + EXPORT WDOG0_IRQHandler [WEAK] + EXPORT WDOG1_IRQHandler [WEAK] + EXPORT FRC_IRQHandler [WEAK] + EXPORT MODEM_IRQHandler [WEAK] + EXPORT RAC_SEQ_IRQHandler [WEAK] + EXPORT RAC_RSM_IRQHandler [WEAK] + EXPORT BUFC_IRQHandler [WEAK] + EXPORT LDMA_IRQHandler [WEAK] + EXPORT GPIO_EVEN_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT USART0_RX_IRQHandler [WEAK] + EXPORT USART0_TX_IRQHandler [WEAK] + EXPORT ACMP0_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT IDAC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT GPIO_ODD_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT USART1_RX_IRQHandler [WEAK] + EXPORT USART1_TX_IRQHandler [WEAK] + EXPORT LEUART0_IRQHandler [WEAK] + EXPORT PCNT0_IRQHandler [WEAK] + EXPORT CMU_IRQHandler [WEAK] + EXPORT MSC_IRQHandler [WEAK] + EXPORT CRYPTO0_IRQHandler [WEAK] + EXPORT LETIMER0_IRQHandler [WEAK] + EXPORT AGC_IRQHandler [WEAK] + EXPORT PROTIMER_IRQHandler [WEAK] + EXPORT RTCC_IRQHandler [WEAK] + EXPORT SYNTH_IRQHandler [WEAK] + EXPORT CRYOTIMER_IRQHandler [WEAK] + EXPORT RFSENSE_IRQHandler [WEAK] + EXPORT FPUEH_IRQHandler [WEAK] + EXPORT SMU_IRQHandler [WEAK] + EXPORT WTIMER0_IRQHandler [WEAK] + EXPORT WTIMER1_IRQHandler [WEAK] + EXPORT PCNT1_IRQHandler [WEAK] + EXPORT PCNT2_IRQHandler [WEAK] + EXPORT USART2_RX_IRQHandler [WEAK] + EXPORT USART2_TX_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT USART3_RX_IRQHandler [WEAK] + EXPORT USART3_TX_IRQHandler [WEAK] + EXPORT VDAC0_IRQHandler [WEAK] + EXPORT CSEN_IRQHandler [WEAK] + EXPORT LESENSE_IRQHandler [WEAK] + EXPORT CRYPTO1_IRQHandler [WEAK] + EXPORT TRNG0_IRQHandler [WEAK] + + +EMU_IRQHandler +FRC_PRI_IRQHandler +WDOG0_IRQHandler +WDOG1_IRQHandler +FRC_IRQHandler +MODEM_IRQHandler +RAC_SEQ_IRQHandler +RAC_RSM_IRQHandler +BUFC_IRQHandler +LDMA_IRQHandler +GPIO_EVEN_IRQHandler +TIMER0_IRQHandler +USART0_RX_IRQHandler +USART0_TX_IRQHandler +ACMP0_IRQHandler +ADC0_IRQHandler +IDAC0_IRQHandler +I2C0_IRQHandler +GPIO_ODD_IRQHandler +TIMER1_IRQHandler +USART1_RX_IRQHandler +USART1_TX_IRQHandler +LEUART0_IRQHandler +PCNT0_IRQHandler +CMU_IRQHandler +MSC_IRQHandler +CRYPTO0_IRQHandler +LETIMER0_IRQHandler +AGC_IRQHandler +PROTIMER_IRQHandler +RTCC_IRQHandler +SYNTH_IRQHandler +CRYOTIMER_IRQHandler +RFSENSE_IRQHandler +FPUEH_IRQHandler +SMU_IRQHandler +WTIMER0_IRQHandler +WTIMER1_IRQHandler +PCNT1_IRQHandler +PCNT2_IRQHandler +USART2_RX_IRQHandler +USART2_TX_IRQHandler +I2C1_IRQHandler +USART3_RX_IRQHandler +USART3_TX_IRQHandler +VDAC0_IRQHandler +CSEN_IRQHandler +LESENSE_IRQHandler +CRYPTO1_IRQHandler +TRNG0_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld new file mode 100644 index 0000000000..2d17d8743e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld @@ -0,0 +1,215 @@ +/* Linker script for Silicon Labs EFR32MG1P devices */ +/* */ +/* This file is subject to the license terms as defined in ARM's */ +/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of */ +/* Example Code. */ +/* */ +/* Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com */ +/* */ +/* Version 4.3.0 */ +/* */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 262144 +} + +/* MBED: mbed needs to be able to dynamically set the interrupt vector table. + * We make room for the table at the very beginning of RAM, i.e. at + * 0x20000000. We need (16+50 * sizeof(uint32_t) = 264 bytes for EFM32PG */ +__vector_size = 0x108; + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + PROVIDE( __start_vector_table__ = .); + . += __vector_size; + PROVIDE( __end_vector_table__ = .); + *(vtable) + *(.data*) + . = ALIGN (4); + *(.ram) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if FLASH usage exceeds FLASH size */ + ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") +} diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S new file mode 100644 index 0000000000..e0a9c7d700 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/startup_efr32mg12p.S @@ -0,0 +1,360 @@ +/* @file startup_efr32mg1p.S + * @brief startup file for Silicon Labs EFR32MG1P devices. + * For use with GCC for ARM Embedded Processors + * @version 4.3.0 + * Date: 12 June 2014 + * + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + .syntax unified + .arch armv7-m + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00004000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00010000 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long Default_Handler /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long EMU_IRQHandler /* 0 - EMU */ + .long FRC_PRI_IRQHandler /* 1 - FRC_PRI */ + .long WDOG0_IRQHandler /* 2 - WDOG0 */ + .long WDOG1_IRQHandler /* 3 - WDOG1 */ + .long FRC_IRQHandler /* 4 - FRC */ + .long MODEM_IRQHandler /* 5 - MODEM */ + .long RAC_SEQ_IRQHandler /* 6 - RAC_SEQ */ + .long RAC_RSM_IRQHandler /* 7 - RAC_RSM */ + .long BUFC_IRQHandler /* 8 - BUFC */ + .long LDMA_IRQHandler /* 9 - LDMA */ + .long GPIO_EVEN_IRQHandler /* 10 - GPIO_EVEN */ + .long TIMER0_IRQHandler /* 11 - TIMER0 */ + .long USART0_RX_IRQHandler /* 12 - USART0_RX */ + .long USART0_TX_IRQHandler /* 13 - USART0_TX */ + .long ACMP0_IRQHandler /* 14 - ACMP0 */ + .long ADC0_IRQHandler /* 15 - ADC0 */ + .long IDAC0_IRQHandler /* 16 - IDAC0 */ + .long I2C0_IRQHandler /* 17 - I2C0 */ + .long GPIO_ODD_IRQHandler /* 18 - GPIO_ODD */ + .long TIMER1_IRQHandler /* 19 - TIMER1 */ + .long USART1_RX_IRQHandler /* 20 - USART1_RX */ + .long USART1_TX_IRQHandler /* 21 - USART1_TX */ + .long LEUART0_IRQHandler /* 22 - LEUART0 */ + .long PCNT0_IRQHandler /* 23 - PCNT0 */ + .long CMU_IRQHandler /* 24 - CMU */ + .long MSC_IRQHandler /* 25 - MSC */ + .long CRYPTO0_IRQHandler /* 26 - CRYPTO0 */ + .long LETIMER0_IRQHandler /* 27 - LETIMER0 */ + .long AGC_IRQHandler /* 28 - AGC */ + .long PROTIMER_IRQHandler /* 29 - PROTIMER */ + .long RTCC_IRQHandler /* 30 - RTCC */ + .long SYNTH_IRQHandler /* 31 - SYNTH */ + .long CRYOTIMER_IRQHandler /* 32 - CRYOTIMER */ + .long RFSENSE_IRQHandler /* 33 - RFSENSE */ + .long FPUEH_IRQHandler /* 34 - FPUEH */ + .long SMU_IRQHandler /* 35 - SMU */ + .long WTIMER0_IRQHandler /* 36 - WTIMER0 */ + .long WTIMER1_IRQHandler /* 37 - WTIMER1 */ + .long PCNT1_IRQHandler /* 38 - PCNT1 */ + .long PCNT2_IRQHandler /* 39 - PCNT2 */ + .long USART2_RX_IRQHandler /* 40 - USART2_RX */ + .long USART2_TX_IRQHandler /* 41 - USART2_TX */ + .long I2C1_IRQHandler /* 42 - I2C1 */ + .long USART3_RX_IRQHandler /* 43 - USART3_RX */ + .long USART3_TX_IRQHandler /* 44 - USART3_TX */ + .long VDAC0_IRQHandler /* 45 - VDAC0 */ + .long CSEN_IRQHandler /* 46 - CSEN */ + .long LESENSE_IRQHandler /* 47 - LESENSE */ + .long CRYPTO1_IRQHandler /* 48 - CRYPTO1 */ + .long TRNG0_IRQHandler /* 49 - TRNG0 */ + .long Default_Handler /* 50 - Reserved */ + + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + + def_irq_handler EMU_IRQHandler + def_irq_handler FRC_PRI_IRQHandler + def_irq_handler WDOG0_IRQHandler + def_irq_handler WDOG1_IRQHandler + def_irq_handler FRC_IRQHandler + def_irq_handler MODEM_IRQHandler + def_irq_handler RAC_SEQ_IRQHandler + def_irq_handler RAC_RSM_IRQHandler + def_irq_handler BUFC_IRQHandler + def_irq_handler LDMA_IRQHandler + def_irq_handler GPIO_EVEN_IRQHandler + def_irq_handler TIMER0_IRQHandler + def_irq_handler USART0_RX_IRQHandler + def_irq_handler USART0_TX_IRQHandler + def_irq_handler ACMP0_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler IDAC0_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler GPIO_ODD_IRQHandler + def_irq_handler TIMER1_IRQHandler + def_irq_handler USART1_RX_IRQHandler + def_irq_handler USART1_TX_IRQHandler + def_irq_handler LEUART0_IRQHandler + def_irq_handler PCNT0_IRQHandler + def_irq_handler CMU_IRQHandler + def_irq_handler MSC_IRQHandler + def_irq_handler CRYPTO0_IRQHandler + def_irq_handler LETIMER0_IRQHandler + def_irq_handler AGC_IRQHandler + def_irq_handler PROTIMER_IRQHandler + def_irq_handler RTCC_IRQHandler + def_irq_handler SYNTH_IRQHandler + def_irq_handler CRYOTIMER_IRQHandler + def_irq_handler RFSENSE_IRQHandler + def_irq_handler FPUEH_IRQHandler + def_irq_handler SMU_IRQHandler + def_irq_handler WTIMER0_IRQHandler + def_irq_handler WTIMER1_IRQHandler + def_irq_handler PCNT1_IRQHandler + def_irq_handler PCNT2_IRQHandler + def_irq_handler USART2_RX_IRQHandler + def_irq_handler USART2_TX_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler USART3_RX_IRQHandler + def_irq_handler USART3_TX_IRQHandler + def_irq_handler VDAC0_IRQHandler + def_irq_handler CSEN_IRQHandler + def_irq_handler LESENSE_IRQHandler + def_irq_handler CRYPTO1_IRQHandler + def_irq_handler TRNG0_IRQHandler + + .end diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf new file mode 100644 index 0000000000..8d652ba1e0 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000107; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000108; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +/*-Sizes-*/ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __ICFEDIT_size_cstack__ = 0x4000; +define symbol __ICFEDIT_size_heap__ = 0x10000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, block CSTACK, block HEAP }; + \ No newline at end of file diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg1p.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg1p.s new file mode 100644 index 0000000000..aca5a91969 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg1p.s @@ -0,0 +1,354 @@ +;/**************************************************************************//** +; * @file startup_efr32mg1p.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFR32MG1P Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD FRC_IRQHandler ; 3: FRC Interrupt + DCD MODEM_IRQHandler ; 4: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 7: BUFC Interrupt + DCD LDMA_IRQHandler ; 8: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 14: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 16: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt + DCD CMU_IRQHandler ; 23: CMU Interrupt + DCD MSC_IRQHandler ; 24: MSC Interrupt + DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 27: AGC Interrupt + DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 29: RTCC Interrupt + DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FRC_PRI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_PRI_IRQHandler + B FRC_PRI_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK FRC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_IRQHandler + B FRC_IRQHandler + + PUBWEAK MODEM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MODEM_IRQHandler + B MODEM_IRQHandler + + PUBWEAK RAC_SEQ_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_SEQ_IRQHandler + B RAC_SEQ_IRQHandler + + PUBWEAK RAC_RSM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_RSM_IRQHandler + B RAC_RSM_IRQHandler + + PUBWEAK BUFC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BUFC_IRQHandler + B BUFC_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO_IRQHandler + B CRYPTO_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK AGC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AGC_IRQHandler + B AGC_IRQHandler + + PUBWEAK PROTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PROTIMER_IRQHandler + B PROTIMER_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK SYNTH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SYNTH_IRQHandler + B SYNTH_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK RFSENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RFSENSE_IRQHandler + B RFSENSE_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h new file mode 100644 index 0000000000..3721367123 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p132f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P132F1024GL125 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P132F1024GL125_H +#define EFR32MG12P132F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125 EFR32MG12P132F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Core EFR32MG12P132F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P132F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P132F1024GL125_Part EFR32MG12P132F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P132F1024GL125) +#define EFR32MG12P132F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P132F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P132F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P132F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Peripheral_TypeDefs EFR32MG12P132F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P132F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Peripheral_Base EFR32MG12P132F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P132F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Peripheral_Declaration EFR32MG12P132F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P132F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Peripheral_Offsets EFR32MG12P132F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P132F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_BitFields EFR32MG12P132F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_WTIMER_BitFields EFR32MG12P132F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P132F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_SYSTICK_BitFields EFR32MG12P132F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P132F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_UNLOCK EFR32MG12P132F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P132F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P132F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GL125_Alternate_Function EFR32MG12P132F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P132F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P132F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P132F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h new file mode 100644 index 0000000000..cddbb780b0 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p132f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P132F1024GM48 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P132F1024GM48_H +#define EFR32MG12P132F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48 EFR32MG12P132F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Core EFR32MG12P132F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P132F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P132F1024GM48_Part EFR32MG12P132F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P132F1024GM48) +#define EFR32MG12P132F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P132F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P132F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P132F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Peripheral_TypeDefs EFR32MG12P132F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P132F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Peripheral_Base EFR32MG12P132F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P132F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Peripheral_Declaration EFR32MG12P132F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P132F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Peripheral_Offsets EFR32MG12P132F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P132F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_BitFields EFR32MG12P132F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_WTIMER_BitFields EFR32MG12P132F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P132F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_SYSTICK_BitFields EFR32MG12P132F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P132F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_UNLOCK EFR32MG12P132F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P132F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P132F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P132F1024GM48_Alternate_Function EFR32MG12P132F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P132F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P132F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P132F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h new file mode 100644 index 0000000000..b51f5e4a2e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p232f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P232F1024GL125 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P232F1024GL125_H +#define EFR32MG12P232F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125 EFR32MG12P232F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Core EFR32MG12P232F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P232F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P232F1024GL125_Part EFR32MG12P232F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P232F1024GL125) +#define EFR32MG12P232F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P232F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P232F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P232F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Peripheral_TypeDefs EFR32MG12P232F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P232F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Peripheral_Base EFR32MG12P232F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P232F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Peripheral_Declaration EFR32MG12P232F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P232F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Peripheral_Offsets EFR32MG12P232F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P232F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_BitFields EFR32MG12P232F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_WTIMER_BitFields EFR32MG12P232F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P232F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_SYSTICK_BitFields EFR32MG12P232F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P232F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_UNLOCK EFR32MG12P232F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P232F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P232F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GL125_Alternate_Function EFR32MG12P232F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P232F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P232F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P232F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h new file mode 100644 index 0000000000..a8912b713b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p232f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P232F1024GM48 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P232F1024GM48_H +#define EFR32MG12P232F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48 EFR32MG12P232F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Core EFR32MG12P232F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P232F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P232F1024GM48_Part EFR32MG12P232F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P232F1024GM48) +#define EFR32MG12P232F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P232F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P232F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P232F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Peripheral_TypeDefs EFR32MG12P232F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P232F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Peripheral_Base EFR32MG12P232F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P232F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Peripheral_Declaration EFR32MG12P232F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P232F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Peripheral_Offsets EFR32MG12P232F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P232F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_BitFields EFR32MG12P232F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_WTIMER_BitFields EFR32MG12P232F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P232F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_SYSTICK_BitFields EFR32MG12P232F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P232F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_UNLOCK EFR32MG12P232F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P232F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P232F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P232F1024GM48_Alternate_Function EFR32MG12P232F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P232F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P232F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P232F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h new file mode 100644 index 0000000000..401fdacadc --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p332f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P332F1024GL125 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P332F1024GL125_H +#define EFR32MG12P332F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125 EFR32MG12P332F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Core EFR32MG12P332F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P332F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P332F1024GL125_Part EFR32MG12P332F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P332F1024GL125) +#define EFR32MG12P332F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P332F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P332F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P332F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Peripheral_TypeDefs EFR32MG12P332F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P332F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Peripheral_Base EFR32MG12P332F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P332F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Peripheral_Declaration EFR32MG12P332F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P332F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Peripheral_Offsets EFR32MG12P332F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P332F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_BitFields EFR32MG12P332F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_WTIMER_BitFields EFR32MG12P332F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P332F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_SYSTICK_BitFields EFR32MG12P332F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P332F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_UNLOCK EFR32MG12P332F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P332F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P332F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GL125_Alternate_Function EFR32MG12P332F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P332F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P332F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P332F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h new file mode 100644 index 0000000000..ece9e5e9f1 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p332f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P332F1024GM48 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P332F1024GM48_H +#define EFR32MG12P332F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48 EFR32MG12P332F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Core EFR32MG12P332F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P332F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P332F1024GM48_Part EFR32MG12P332F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P332F1024GM48) +#define EFR32MG12P332F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P332F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P332F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P332F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Peripheral_TypeDefs EFR32MG12P332F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P332F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Peripheral_Base EFR32MG12P332F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P332F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Peripheral_Declaration EFR32MG12P332F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P332F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Peripheral_Offsets EFR32MG12P332F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P332F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_BitFields EFR32MG12P332F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_WTIMER_BitFields EFR32MG12P332F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P332F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_SYSTICK_BitFields EFR32MG12P332F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P332F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_UNLOCK EFR32MG12P332F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P332F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P332F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P332F1024GM48_Alternate_Function EFR32MG12P332F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P332F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P332F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P332F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h new file mode 100644 index 0000000000..0a7ac374bd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p432f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P432F1024GL125 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P432F1024GL125_H +#define EFR32MG12P432F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125 EFR32MG12P432F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Core EFR32MG12P432F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P432F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P432F1024GL125_Part EFR32MG12P432F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P432F1024GL125) +#define EFR32MG12P432F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P432F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P432F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P432F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Peripheral_TypeDefs EFR32MG12P432F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P432F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Peripheral_Base EFR32MG12P432F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P432F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Peripheral_Declaration EFR32MG12P432F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P432F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Peripheral_Offsets EFR32MG12P432F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P432F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_BitFields EFR32MG12P432F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_WTIMER_BitFields EFR32MG12P432F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P432F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_SYSTICK_BitFields EFR32MG12P432F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P432F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_UNLOCK EFR32MG12P432F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P432F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P432F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GL125_Alternate_Function EFR32MG12P432F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P432F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P432F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P432F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h new file mode 100644 index 0000000000..1c60c74a7d --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p432f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P432F1024GM48 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P432F1024GM48_H +#define EFR32MG12P432F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48 EFR32MG12P432F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Core EFR32MG12P432F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P432F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P432F1024GM48_Part EFR32MG12P432F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P432F1024GM48) +#define EFR32MG12P432F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P432F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P432F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P432F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Peripheral_TypeDefs EFR32MG12P432F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P432F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Peripheral_Base EFR32MG12P432F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P432F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Peripheral_Declaration EFR32MG12P432F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P432F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Peripheral_Offsets EFR32MG12P432F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P432F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_BitFields EFR32MG12P432F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_WTIMER_BitFields EFR32MG12P432F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P432F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_SYSTICK_BitFields EFR32MG12P432F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P432F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_UNLOCK EFR32MG12P432F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P432F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P432F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P432F1024GM48_Alternate_Function EFR32MG12P432F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P432F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P432F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P432F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h new file mode 100644 index 0000000000..3f76f64ad0 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p433f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P433F1024GL125 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P433F1024GL125_H +#define EFR32MG12P433F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125 EFR32MG12P433F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Core EFR32MG12P433F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P433F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P433F1024GL125_Part EFR32MG12P433F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P433F1024GL125) +#define EFR32MG12P433F1024GL125 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P433F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P433F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P433F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Peripheral_TypeDefs EFR32MG12P433F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P433F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Peripheral_Base EFR32MG12P433F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P433F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Peripheral_Declaration EFR32MG12P433F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P433F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Peripheral_Offsets EFR32MG12P433F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P433F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_BitFields EFR32MG12P433F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_WTIMER_BitFields EFR32MG12P433F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P433F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_SYSTICK_BitFields EFR32MG12P433F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P433F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_UNLOCK EFR32MG12P433F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P433F1024GL125_UNLOCK */ + +/** @} End of group EFR32MG12P433F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GL125_Alternate_Function EFR32MG12P433F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P433F1024GL125_Alternate_Function */ + +/** @} End of group EFR32MG12P433F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P433F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h new file mode 100644 index 0000000000..bb037bab7e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h @@ -0,0 +1,2057 @@ +/**************************************************************************//** + * @file efr32mg12p433f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG12P433F1024GM48 + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFR32MG12P433F1024GM48_H +#define EFR32MG12P433F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48 EFR32MG12P433F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFR32MG12P Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFR32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFR32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFR32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFR32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFR32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFR32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFR32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFR32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFR32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFR32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFR32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFR32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFR32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFR32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFR32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFR32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFR32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFR32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFR32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFR32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFR32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFR32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFR32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFR32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFR32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFR32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFR32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFR32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFR32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFR32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFR32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFR32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFR32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFR32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFR32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFR32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Core EFR32MG12P433F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG12P433F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG12P433F1024GM48_Part EFR32MG12P433F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG12P433F1024GM48) +#define EFR32MG12P433F1024GM48 1 /**< MIGHTY Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG12P433F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFR32MG12P433F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efr32mg12p.h" /* System Header File */ + +/** @} End of group EFR32MG12P433F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Peripheral_TypeDefs EFR32MG12P433F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efr32mg12p_msc.h" +#include "efr32mg12p_emu.h" +#include "efr32mg12p_rmu.h" +#include "efr32mg12p_cmu.h" +#include "efr32mg12p_crypto.h" +#include "efr32mg12p_gpio_p.h" +#include "efr32mg12p_gpio.h" +#include "efr32mg12p_prs_ch.h" +#include "efr32mg12p_prs.h" +#include "efr32mg12p_ldma_ch.h" +#include "efr32mg12p_ldma.h" +#include "efr32mg12p_fpueh.h" +#include "efr32mg12p_gpcrc.h" +#include "efr32mg12p_timer_cc.h" +#include "efr32mg12p_timer.h" +#include "efr32mg12p_usart.h" +#include "efr32mg12p_leuart.h" +#include "efr32mg12p_letimer.h" +#include "efr32mg12p_cryotimer.h" +#include "efr32mg12p_pcnt.h" +#include "efr32mg12p_i2c.h" +#include "efr32mg12p_adc.h" +#include "efr32mg12p_acmp.h" +#include "efr32mg12p_idac.h" +#include "efr32mg12p_vdac_opa.h" +#include "efr32mg12p_vdac.h" +#include "efr32mg12p_csen.h" +#include "efr32mg12p_lesense_st.h" +#include "efr32mg12p_lesense_buf.h" +#include "efr32mg12p_lesense_ch.h" +#include "efr32mg12p_lesense.h" +#include "efr32mg12p_rtcc_cc.h" +#include "efr32mg12p_rtcc_ret.h" +#include "efr32mg12p_rtcc.h" +#include "efr32mg12p_wdog_pch.h" +#include "efr32mg12p_wdog.h" +#include "efr32mg12p_etm.h" +#include "efr32mg12p_smu.h" +#include "efr32mg12p_trng.h" +#include "efr32mg12p_dma_descriptor.h" +#include "efr32mg12p_devinfo.h" +#include "efr32mg12p_romtable.h" + +/** @} End of group EFR32MG12P433F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Peripheral_Base EFR32MG12P433F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFR32MG12P433F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Peripheral_Declaration EFR32MG12P433F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFR32MG12P433F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Peripheral_Offsets EFR32MG12P433F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFR32MG12P433F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_BitFields EFR32MG12P433F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efr32mg12p_prs_signals.h" +#include "efr32mg12p_dmareq.h" + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_WTIMER_BitFields EFR32MG12P433F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFR32MG12P433F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_SYSTICK_BitFields EFR32MG12P433F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFR32MG12P433F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_UNLOCK EFR32MG12P433F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFR32MG12P433F1024GM48_UNLOCK */ + +/** @} End of group EFR32MG12P433F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFR32MG12P433F1024GM48_Alternate_Function EFR32MG12P433F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efr32mg12p_af_ports.h" +#include "efr32mg12p_af_pins.h" + +/** @} End of group EFR32MG12P433F1024GM48_Alternate_Function */ + +/** @} End of group EFR32MG12P433F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFR32MG12P433F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h new file mode 100644 index 0000000000..1cccc2ca02 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h @@ -0,0 +1,1420 @@ +/**************************************************************************//** + * @file efr32mg12p_acmp.h + * @brief EFR32MG12P_ACMP register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_ACMP + * @{ + * @brief EFR32MG12P_ACMP Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTSEL; /**< Input Selection Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */ + __IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t EXTIFCTRL; /**< External override interface control */ +} ACMP_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_ACMP_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */ +#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ +#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */ +#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */ +#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus selected by VASEL */ +#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_VREGVDD 0x00000001UL /**< Mode VREGVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_VREGVDD (_ACMP_CTRL_PWRSEL_VREGVDD << 12) /**< Shifted mode VREGVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP accuracy mode */ +#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */ +#define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */ +#define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */ +#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTSEL */ +#define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */ +#define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */ +#define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */ +#define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000000FUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */ +#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */ +#define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External override interface active. */ +#define _ACMP_STATUS_EXTIFACT_SHIFT 3 /**< Shift value for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_MASK 0x8UL /**< Bit mask for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT_DEFAULT (_ACMP_STATUS_EXTIFACT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */ +#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ +#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */ +#define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IFS */ +#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ +#define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */ +#define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */ +#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */ +#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */ + +/* Bit fields for ACMP IFC */ +#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ +#define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */ +#define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */ +#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */ +#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */ +#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */ +#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */ +#define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP APORTREQ */ +#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */ +#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */ +#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */ +#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ + +/* Bit fields for ACMP APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ + +/* Bit fields for ACMP HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ + +/* Bit fields for ACMP HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ + +/* Bit fields for ACMP ROUTEPEN */ +#define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */ +#define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */ +#define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */ + +/* Bit fields for ACMP ROUTELOC0 */ +#define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_MASK 0x0000001FUL /**< Mask for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_MASK 0x1FUL /**< Bit mask for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC8 0x00000008UL /**< Mode LOC8 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC9 0x00000009UL /**< Mode LOC9 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC10 0x0000000AUL /**< Mode LOC10 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC11 0x0000000BUL /**< Mode LOC11 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC12 0x0000000CUL /**< Mode LOC12 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC13 0x0000000DUL /**< Mode LOC13 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC14 0x0000000EUL /**< Mode LOC14 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC15 0x0000000FUL /**< Mode LOC15 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC16 0x00000010UL /**< Mode LOC16 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC17 0x00000011UL /**< Mode LOC17 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC18 0x00000012UL /**< Mode LOC18 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC19 0x00000013UL /**< Mode LOC19 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC20 0x00000014UL /**< Mode LOC20 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC21 0x00000015UL /**< Mode LOC21 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC22 0x00000016UL /**< Mode LOC22 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC23 0x00000017UL /**< Mode LOC23 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC24 0x00000018UL /**< Mode LOC24 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC25 0x00000019UL /**< Mode LOC25 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC26 0x0000001AUL /**< Mode LOC26 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC27 0x0000001BUL /**< Mode LOC27 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC28 0x0000001CUL /**< Mode LOC28 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC29 0x0000001DUL /**< Mode LOC29 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC30 0x0000001EUL /**< Mode LOC30 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC31 0x0000001FUL /**< Mode LOC31 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC8 (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0) /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC9 (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0) /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC10 (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0) /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC11 (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0) /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC12 (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0) /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC13 (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0) /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC14 (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0) /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC15 (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0) /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC16 (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0) /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC17 (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0) /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC18 (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0) /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC19 (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0) /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC20 (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0) /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC21 (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0) /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC22 (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0) /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC23 (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0) /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC24 (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0) /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC25 (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0) /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC26 (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0) /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC27 (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0) /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC28 (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0) /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC29 (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0) /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */ + +/* Bit fields for ACMP EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_MASK 0x000000F1UL /**< Mask for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable external interface. */ +#define _ACMP_EXTIFCTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN_DEFAULT (_ACMP_EXTIFCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_SHIFT 4 /**< Shift value for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_MASK 0xF0UL /**< Bit mask for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0X 0x00000000UL /**< Mode APORT0X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0Y 0x00000001UL /**< Mode APORT0Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1X 0x00000002UL /**< Mode APORT1X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1Y 0x00000003UL /**< Mode APORT1Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1XY 0x00000004UL /**< Mode APORT1XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2X 0x00000005UL /**< Mode APORT2X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2Y 0x00000006UL /**< Mode APORT2Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2YX 0x00000007UL /**< Mode APORT2YX for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3X 0x00000008UL /**< Mode APORT3X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3Y 0x00000009UL /**< Mode APORT3Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3XY 0x0000000AUL /**< Mode APORT3XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4X 0x0000000BUL /**< Mode APORT4X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4Y 0x0000000CUL /**< Mode APORT4Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4YX 0x0000000DUL /**< Mode APORT4YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_DEFAULT (_ACMP_EXTIFCTRL_APORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0X (_ACMP_EXTIFCTRL_APORTSEL_APORT0X << 4) /**< Shifted mode APORT0X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0Y (_ACMP_EXTIFCTRL_APORTSEL_APORT0Y << 4) /**< Shifted mode APORT0Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1X (_ACMP_EXTIFCTRL_APORTSEL_APORT1X << 4) /**< Shifted mode APORT1X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1Y (_ACMP_EXTIFCTRL_APORTSEL_APORT1Y << 4) /**< Shifted mode APORT1Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1XY (_ACMP_EXTIFCTRL_APORTSEL_APORT1XY << 4) /**< Shifted mode APORT1XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2X (_ACMP_EXTIFCTRL_APORTSEL_APORT2X << 4) /**< Shifted mode APORT2X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2Y (_ACMP_EXTIFCTRL_APORTSEL_APORT2Y << 4) /**< Shifted mode APORT2Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2YX (_ACMP_EXTIFCTRL_APORTSEL_APORT2YX << 4) /**< Shifted mode APORT2YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3X (_ACMP_EXTIFCTRL_APORTSEL_APORT3X << 4) /**< Shifted mode APORT3X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3Y (_ACMP_EXTIFCTRL_APORTSEL_APORT3Y << 4) /**< Shifted mode APORT3Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3XY (_ACMP_EXTIFCTRL_APORTSEL_APORT3XY << 4) /**< Shifted mode APORT3XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4X (_ACMP_EXTIFCTRL_APORTSEL_APORT4X << 4) /**< Shifted mode APORT4X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4Y (_ACMP_EXTIFCTRL_APORTSEL_APORT4Y << 4) /**< Shifted mode APORT4Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4YX (_ACMP_EXTIFCTRL_APORTSEL_APORT4YX << 4) /**< Shifted mode APORT4YX for ACMP_EXTIFCTRL */ + +/** @} End of group EFR32MG12P_ACMP */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h new file mode 100644 index 0000000000..15584b14b7 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h @@ -0,0 +1,2371 @@ +/**************************************************************************//** + * @file efr32mg12p_adc.h + * @brief EFR32MG12P_ADC register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_ADC + * @{ + * @brief EFR32MG12P_ADC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */ + __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register continued */ + __IOM uint32_t SCANCTRL; /**< Scan Control Register */ + __IOM uint32_t SCANCTRLX; /**< Scan Control Register continued */ + __IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */ + __IOM uint32_t SCANINPUTSEL; /**< Input Selection register for Scan mode */ + __IOM uint32_t SCANNEGSEL; /**< Negative Input select register for Scan */ + __IOM uint32_t CMPTHR; /**< Compare Threshold Register */ + __IOM uint32_t BIASPROG; /**< Bias Programming Register for various analog blocks used in ADC operation. */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */ + __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */ + __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ + __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */ + __IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */ + + uint32_t RESERVED2[3]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */ + __IM uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */ + __IOM uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */ + __IOM uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */ + __IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */ +} ADC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_ADC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ADC CTRL */ +#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ +#define _ADC_CTRL_MASK 0xFF7F7FDFUL /**< Mask for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */ +#define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */ +#define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */ +#define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */ +#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */ +#define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */ +#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ +#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ +#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ +#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ +#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */ +#define ADC_CTRL_DBGHALT (0x1UL << 28) /**< Debug Mode Halt Enable */ +#define _ADC_CTRL_DBGHALT_SHIFT 28 /**< Shift value for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_MASK 0x10000000UL /**< Bit mask for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_DBGHALT_DEFAULT (_ADC_CTRL_DBGHALT_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */ +#define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_SHIFT 30 /**< Shift value for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_MASK 0xC0000000UL /**< Bit mask for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN 0x00000000UL /**< Mode PREFSCAN for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE 0x00000001UL /**< Mode PREFSINGLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV 0x00000002UL /**< Mode KEEPPREV for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_DEFAULT (_ADC_CTRL_CHCONREFWARMIDLE_DEFAULT << 30) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN (_ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN << 30) /**< Shifted mode PREFSCAN for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE (_ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE << 30) /**< Shifted mode PREFSINGLE for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV (_ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV << 30) /**< Shifted mode KEEPPREV for ADC_CTRL */ + +/* Bit fields for ADC CMD */ +#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ +#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ +#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Channel Conversion Start */ +#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Channel Conversion Stop */ +#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */ +#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */ +#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */ + +/* Bit fields for ADC STATUS */ +#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ +#define _ADC_STATUS_MASK 0x00031F07UL /**< Mask for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Channel Conversion Active */ +#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */ +#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING (0x1UL << 2) /**< Scan Conversion Pending */ +#define _ADC_STATUS_SCANPENDING_SHIFT 2 /**< Shift value for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_MASK 0x4UL /**< Bit mask for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING_DEFAULT (_ADC_STATUS_SCANPENDING_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Channel Reference Warmed Up */ +#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */ +#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */ +#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ +#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ +#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */ +#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */ +#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ + +/* Bit fields for ADC SINGLECTRL */ +#define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */ +#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */ +#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */ +#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_5V (_ADC_SINGLECTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TESTP 0x000000F5UL /**< Mode TESTP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA3 0x000000FAUL /**< Mode OPA3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TESTP (_ADC_SINGLECTRL_POSSEL_TESTP << 8) /**< Shifted mode TESTP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA3 (_ADC_SINGLECTRL_POSSEL_OPA3 << 8) /**< Shifted mode OPA3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */ +#define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */ +#define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ + +/* Bit fields for ADC SINGLECTRLX */ +#define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */ +#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */ +#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */ +#define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_DEFAULT (_ADC_SINGLECTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_NODELAY (_ADC_SINGLECTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_4CYCLES (_ADC_SINGLECTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_8CYCLES (_ADC_SINGLECTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_16CYCLES (_ADC_SINGLECTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_32CYCLES (_ADC_SINGLECTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_64CYCLES (_ADC_SINGLECTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_128CYCLES (_ADC_SINGLECTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_256CYCLES (_ADC_SINGLECTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SINGLECTRLX */ + +/* Bit fields for ADC SCANCTRL */ +#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */ +#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */ +#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */ +#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_5V (_ADC_SCANCTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */ +#define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */ +#define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ + +/* Bit fields for ADC SCANCTRLX */ +#define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */ +#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */ +#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */ +#define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_DEFAULT (_ADC_SCANCTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_NODELAY (_ADC_SCANCTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_4CYCLES (_ADC_SCANCTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_8CYCLES (_ADC_SCANCTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_16CYCLES (_ADC_SCANCTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_32CYCLES (_ADC_SCANCTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_64CYCLES (_ADC_SCANCTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_128CYCLES (_ADC_SCANCTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_256CYCLES (_ADC_SCANCTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SCANCTRLX */ + +/* Bit fields for ADC SCANMASK */ +#define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */ +#define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */ + +/* Bit fields for ADC SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ + +/* Bit fields for ADC SCANNEGSEL */ +#define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ + +/* Bit fields for ADC CMPTHR */ +#define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */ +#define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */ + +/* Bit fields for ADC BIASPROG */ +#define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */ +#define _ADC_BIASPROG_MASK 0x0001100FUL /**< Mask for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF flag */ +#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy setting for the system bias during ADC operation */ +#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_HIGHACC 0x00000000UL /**< Mode HIGHACC for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_LOWACC 0x00000001UL /**< Mode LOWACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_DEFAULT (_ADC_BIASPROG_GPBIASACC_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_HIGHACC (_ADC_BIASPROG_GPBIASACC_HIGHACC << 16) /**< Shifted mode HIGHACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_LOWACC (_ADC_BIASPROG_GPBIASACC_LOWACC << 16) /**< Shifted mode LOWACC for ADC_BIASPROG */ + +/* Bit fields for ADC CAL */ +#define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */ +#define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative single-ended offset calibration is enabled */ +#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration mode is enabled */ +#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */ +#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */ +#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */ + +/* Bit fields for ADC IF */ +#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ +#define _ADC_IF_MASK 0x3F030F03UL /**< Mask for ADC_IF */ +#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */ +#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */ +#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF (0x1UL << 11) /**< Scan FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */ +#define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */ +#define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV (0x1UL << 24) /**< VREF Over Voltage Interrupt Flag */ +#define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */ +#define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND (0x1UL << 26) /**< External Scan Trigger Pending Flag */ +#define _ADC_IF_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND_DEFAULT (_ADC_IF_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND (0x1UL << 27) /**< Scan Trigger Pending Flag */ +#define _ADC_IF_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND_DEFAULT (_ADC_IF_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR (0x1UL << 28) /**< PRS Timed Mode Error Flag */ +#define _ADC_IF_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR_DEFAULT (_ADC_IF_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR (0x1UL << 29) /**< EM23 Entry Error Flag */ +#define _ADC_IF_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR_DEFAULT (_ADC_IF_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IF */ + +/* Bit fields for ADC IFS */ +#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ +#define _ADC_IFS_MASK 0x3F030F00UL /**< Mask for ADC_IFS */ +#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */ +#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */ +#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */ +#define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */ +#define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */ +#define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */ +#define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */ +#define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */ +#define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND (0x1UL << 26) /**< Set SCANEXTPEND Interrupt Flag */ +#define _ADC_IFS_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND_DEFAULT (_ADC_IFS_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND (0x1UL << 27) /**< Set SCANPEND Interrupt Flag */ +#define _ADC_IFS_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND_DEFAULT (_ADC_IFS_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR (0x1UL << 28) /**< Set PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFS_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR_DEFAULT (_ADC_IFS_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR (0x1UL << 29) /**< Set EM23ERR Interrupt Flag */ +#define _ADC_IFS_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR_DEFAULT (_ADC_IFS_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFS */ + +/* Bit fields for ADC IFC */ +#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ +#define _ADC_IFC_MASK 0x3F030F00UL /**< Mask for ADC_IFC */ +#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */ +#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */ +#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */ +#define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */ +#define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */ +#define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */ +#define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */ +#define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */ +#define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND (0x1UL << 26) /**< Clear SCANEXTPEND Interrupt Flag */ +#define _ADC_IFC_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND_DEFAULT (_ADC_IFC_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND (0x1UL << 27) /**< Clear SCANPEND Interrupt Flag */ +#define _ADC_IFC_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND_DEFAULT (_ADC_IFC_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR (0x1UL << 28) /**< Clear PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFC_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR_DEFAULT (_ADC_IFC_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR (0x1UL << 29) /**< Clear EM23ERR Interrupt Flag */ +#define _ADC_IFC_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR_DEFAULT (_ADC_IFC_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFC */ + +/* Bit fields for ADC IEN */ +#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ +#define _ADC_IEN_MASK 0x3F030F03UL /**< Mask for ADC_IEN */ +#define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */ +#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */ +#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */ +#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */ +#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */ +#define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */ +#define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */ +#define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */ +#define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */ +#define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */ +#define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND (0x1UL << 26) /**< SCANEXTPEND Interrupt Enable */ +#define _ADC_IEN_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND_DEFAULT (_ADC_IEN_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND (0x1UL << 27) /**< SCANPEND Interrupt Enable */ +#define _ADC_IEN_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND_DEFAULT (_ADC_IEN_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR (0x1UL << 28) /**< PRSTIMEDERR Interrupt Enable */ +#define _ADC_IEN_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR_DEFAULT (_ADC_IEN_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR (0x1UL << 29) /**< EM23ERR Interrupt Enable */ +#define _ADC_IEN_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR_DEFAULT (_ADC_IEN_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IEN */ + +/* Bit fields for ADC SINGLEDATA */ +#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ +#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ + +/* Bit fields for ADC SCANDATA */ +#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ +#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ +#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ +#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ + +/* Bit fields for ADC SINGLEDATAP */ +#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ +#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ + +/* Bit fields for ADC SCANDATAP */ +#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ +#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ + +/* Bit fields for ADC SCANDATAX */ +#define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ + +/* Bit fields for ADC SCANDATAXP */ +#define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ + +/* Bit fields for ADC APORTREQ */ +#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */ +#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */ +#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */ +#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT1X is requested */ +#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ +#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */ + +/* Bit fields for ADC APORTCONFLICT */ +#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */ +#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ + +/* Bit fields for ADC SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */ +#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */ + +/* Bit fields for ADC SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */ +#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */ + +/* Bit fields for ADC SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO content */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */ + +/* Bit fields for ADC SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO content */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */ + +/* Bit fields for ADC APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ + +/** @} End of group EFR32MG12P_ADC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h new file mode 100644 index 0000000000..a7b7e3d269 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efr32mg12p_af_pins.h + * @brief EFR32MG12P_AF_PINS register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_AF_Pins + * @{ + *****************************************************************************/ + +/** AF pin number for location number i */ +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : -1) +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_TIMER0_CC3_PIN(i) (-1) +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_TIMER0_CDTI3_PIN(i) (-1) +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_TIMER1_CDTI0_PIN(i) (-1) +#define AF_TIMER1_CDTI1_PIN(i) (-1) +#define AF_TIMER1_CDTI2_PIN(i) (-1) +#define AF_TIMER1_CDTI3_PIN(i) (-1) +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER0_CC3_PIN(i) (-1) +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1) +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 8 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CDTI3_PIN(i) (-1) +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 4 : (i) == 9 ? 5 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 5 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 8 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 11 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 12 : (i) == 31 ? 13 : -1) +#define AF_WTIMER1_CDTI0_PIN(i) (-1) +#define AF_WTIMER1_CDTI1_PIN(i) (-1) +#define AF_WTIMER1_CDTI2_PIN(i) (-1) +#define AF_WTIMER1_CDTI3_PIN(i) (-1) +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 9 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 5 : -1) +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? 8 : (i) == 20 ? 9 : (i) == 21 ? 10 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 5 : (i) == 31 ? 6 : -1) +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? 8 : (i) == 18 ? 9 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 8 : -1) +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 2 : (i) == 9 ? 3 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 14 : (i) == 16 ? 15 : (i) == 17 ? 0 : (i) == 18 ? 1 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 4 : (i) == 22 ? 5 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 8 : -1) +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 13 : (i) == 3 ? 14 : (i) == 4 ? 15 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 14 : (i) == 14 ? 15 : (i) == 15 ? 0 : (i) == 16 ? 1 : (i) == 17 ? 2 : (i) == 18 ? 3 : (i) == 19 ? 4 : (i) == 20 ? 5 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 8 : (i) == 30 ? 9 : (i) == 31 ? 10 : -1) +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 14 : (i) == 13 ? 15 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 4 : (i) == 19 ? 5 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 8 : (i) == 28 ? 9 : (i) == 29 ? 10 : (i) == 30 ? 11 : (i) == 31 ? 12 : -1) +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1) +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1) +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1) +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1) +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1) +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1) +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1) +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1) +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 6 : -1) +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 7 : -1) +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 14 : -1) +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 15 : -1) +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 6 : -1) +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 7 : -1) +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 8 : -1) +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 9 : -1) +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 8 : (i) == 3 ? 10 : -1) + +/** @} End of group EFR32MG12P_AF_Pins */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h new file mode 100644 index 0000000000..d10ddbdbbd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efr32mg12p_af_ports.h + * @brief EFR32MG12P_AF_PORTS register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_AF_Ports + * @{ + *****************************************************************************/ + +/** AF port number for location number i */ +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1) +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC3_PORT(i) (-1) +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI3_PORT(i) (-1) +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CDTI0_PORT(i) (-1) +#define AF_TIMER1_CDTI1_PORT(i) (-1) +#define AF_TIMER1_CDTI2_PORT(i) (-1) +#define AF_TIMER1_CDTI3_PORT(i) (-1) +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1) +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CC3_PORT(i) (-1) +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER0_CDTI3_PORT(i) (-1) +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CDTI0_PORT(i) (-1) +#define AF_WTIMER1_CDTI1_PORT(i) (-1) +#define AF_WTIMER1_CDTI2_PORT(i) (-1) +#define AF_WTIMER1_CDTI3_PORT(i) (-1) +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : (i) == 8 ? 8 : (i) == 9 ? 8 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 9 : (i) == 17 ? 9 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 9 : (i) == 16 ? 9 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 3 : -1) +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 9 : (i) == 15 ? 9 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 9 : (i) == 14 ? 9 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 9 : (i) == 13 ? 9 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) + +/** @} End of group EFR32MG12P_AF_Ports */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h new file mode 100644 index 0000000000..9f16ccd842 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h @@ -0,0 +1,2032 @@ +/**************************************************************************//** + * @file efr32mg12p_cmu.h + * @brief EFR32MG12P_CMU register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_CMU + * @{ + * @brief EFR32MG12P_CMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CMU Control Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + + uint32_t RESERVED9[1]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED10[1]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED11[3]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + + uint32_t RESERVED12[7]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[1]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + + uint32_t RESERVED14[1]; /**< Reserved for future use **/ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED15[3]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + + uint32_t RESERVED16[1]; /**< Reserved for future use **/ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED17[1]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + + uint32_t RESERVED18[2]; /**< Reserved for future use **/ + __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED19[1]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED20[1]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */ + + uint32_t RESERVED21[3]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED22[2]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED23[2]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED24[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED25[1]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_CMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x001101EFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low power mode control. PSR performance is reduced to enable low current consumption. */ +#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */ +#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */ +#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off. */ +#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */ +#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */ +#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off. */ +#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */ +#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */ +#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000001FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< automatic recovery ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x000033FFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x07E133FFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */ +#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization ready */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO oscillation amplitude is too high */ +#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */ +#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */ +#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO regulator shunt current too low */ +#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */ +#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */ +#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ +#define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ +#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x8003FF7FUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */ +#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0x8003FF7FUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0x8003FF7FUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x8003FF7FUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0) /**< Advanced Encryption Standard Accelerator 0 Clock Enable */ +#define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0 /**< Alias for CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT /**< Alias for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK /**< Alias for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT*/ +#define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator 1 Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1 /**< Shift value for CMU_CRYPTO1 */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL /**< Bit mask for CMU_CRYPTO1 */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER1 (0x1UL << 3) /**< Wide Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_WTIMER1_SHIFT 3 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN0_WTIMER1_MASK 0x8UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN0_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER1_DEFAULT (_CMU_HFPERCLKEN0_WTIMER1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 4 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x10UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 5) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 5 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x20UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 6) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 6 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x40UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 7 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x80UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 8) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 8 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x100UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 9) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 9 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x200UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 10) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 10 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x400UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 11) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 11 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x800UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CryoTimer Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 12 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x1000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 13) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 13 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x2000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 15) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_VDAC0_SHIFT 15 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN0_VDAC0_MASK 0x8000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CSEN (0x1UL << 16) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN0_CSEN_SHIFT 16 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN0_CSEN_MASK 0x10000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 17) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 17 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x20000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 1) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 1 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 1 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 2) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 2 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x0000003FUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 4 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x0000033FUL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 4 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 8 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x300UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000003UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} End of group EFR32MG12P_CMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h new file mode 100644 index 0000000000..1fbec9324d --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h @@ -0,0 +1,167 @@ +/**************************************************************************//** + * @file efr32mg12p_cryotimer.h + * @brief EFR32MG12P_CRYOTIMER register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_CRYOTIMER + * @{ + * @brief EFR32MG12P_CRYOTIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PERIODSEL; /**< Interrupt Duration */ + __IM uint32_t CNT; /**< Counter Value */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CRYOTIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_CRYOTIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYOTIMER CTRL */ +#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */ +#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */ + +/* Bit fields for CRYOTIMER PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */ +#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */ + +/* Bit fields for CRYOTIMER CNT */ +#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */ +#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */ + +/* Bit fields for CRYOTIMER EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ +#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */ + +/* Bit fields for CRYOTIMER IF */ +#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */ +#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup event/Interrupt */ +#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */ + +/* Bit fields for CRYOTIMER IFS */ +#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */ +#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */ + +/* Bit fields for CRYOTIMER IFC */ +#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */ +#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */ + +/* Bit fields for CRYOTIMER IEN */ +#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */ +#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */ +#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */ + +/** @} End of group EFR32MG12P_CRYOTIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h new file mode 100644 index 0000000000..1f77ca3526 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h @@ -0,0 +1,1216 @@ +/**************************************************************************//** + * @file efr32mg12p_crypto.h + * @brief EFR32MG12P_CRYPTO register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_CRYPTO + * @{ + * @brief EFR32MG12P_CRYPTO Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t DSTATUS; /**< Data Status Register */ + __IM uint32_t CSTATUS; /**< Control Status Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t KEY; /**< KEY Register Access */ + __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */ + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IOM uint32_t SEQCTRL; /**< Sequence Control */ + __IOM uint32_t SEQCTRLB; /**< Sequence Control B */ + uint32_t RESERVED3[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< AES Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t SEQ0; /**< Sequence register 0 */ + __IOM uint32_t SEQ1; /**< Sequence Register 1 */ + __IOM uint32_t SEQ2; /**< Sequence Register 2 */ + __IOM uint32_t SEQ3; /**< Sequence Register 3 */ + __IOM uint32_t SEQ4; /**< Sequence Register 4 */ + uint32_t RESERVED4[7]; /**< Reserved for future use **/ + __IOM uint32_t DATA0; /**< DATA0 Register Access */ + __IOM uint32_t DATA1; /**< DATA1 Register Access */ + __IOM uint32_t DATA2; /**< DATA2 Register Access */ + __IOM uint32_t DATA3; /**< DATA3 Register Access */ + uint32_t RESERVED5[4]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */ + uint32_t RESERVED6[3]; /**< Reserved for future use **/ + __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */ + __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */ + __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */ + __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */ + __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */ + __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */ + uint32_t RESERVED8[12]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0; /**< DDATA0 Register Access */ + __IOM uint32_t DDATA1; /**< DDATA1 Register Access */ + __IOM uint32_t DDATA2; /**< DDATA2 Register Access */ + __IOM uint32_t DDATA3; /**< DDATA3 Register Access */ + __IOM uint32_t DDATA4; /**< DDATA4 Register Access */ + uint32_t RESERVED9[7]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */ + uint32_t RESERVED10[3]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */ + __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */ + __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 access. */ + uint32_t RESERVED11[13]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0; /**< QDATA0 Register Access */ + __IOM uint32_t QDATA1; /**< QDATA1 Register Access */ + uint32_t RESERVED12[7]; /**< Reserved for future use **/ + __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */ + uint32_t RESERVED13[6]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */ + __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */ +} CRYPTO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_CRYPTO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYPTO CTRL */ +#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */ +#define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */ +#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */ +#define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */ +#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ + +/* Bit fields for CRYPTO WAC */ +#define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */ +#define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */ +#define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */ + +/* Bit fields for CRYPTO CMD */ +#define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */ +#define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADD 0x0000000AUL /**< Mode LADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDC 0x0000000BUL /**< Mode LADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUB 0x00000012UL /**< Mode LSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUBC 0x00000013UL /**< Mode LSUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMUL 0x0000001AUL /**< Mode LMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMULO 0x0000001FUL /**< Mode LMULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDO 0x0000002AUL /**< Mode LADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDIC 0x0000002BUL /**< Mode LADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LINC 0x0000003AUL /**< Mode LINC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LDEC 0x0000003BUL /**< Mode LDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TOBUF 0x00000064UL /**< Mode DATA0TOBUF for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR 0x00000065UL /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TOBUF 0x0000006CUL /**< Mode DATA1TOBUF for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR 0x0000006DUL /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA0 0x00000078UL /**< Mode BUFTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA0XOR 0x00000079UL /**< Mode BUFTODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA1 0x0000007AUL /**< Mode BUFTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADD (_CRYPTO_CMD_INSTR_LADD << 0) /**< Shifted mode LADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDC (_CRYPTO_CMD_INSTR_LADDC << 0) /**< Shifted mode LADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUB (_CRYPTO_CMD_INSTR_LSUB << 0) /**< Shifted mode LSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUBC (_CRYPTO_CMD_INSTR_LSUBC << 0) /**< Shifted mode LSUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMUL (_CRYPTO_CMD_INSTR_LMUL << 0) /**< Shifted mode LMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMULO (_CRYPTO_CMD_INSTR_LMULO << 0) /**< Shifted mode LMULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDO (_CRYPTO_CMD_INSTR_LADDO << 0) /**< Shifted mode LADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDIC (_CRYPTO_CMD_INSTR_LADDIC << 0) /**< Shifted mode LADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LINC (_CRYPTO_CMD_INSTR_LINC << 0) /**< Shifted mode LINC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LDEC (_CRYPTO_CMD_INSTR_LDEC << 0) /**< Shifted mode LDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TOBUF (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0) /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TOBUFXOR (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0) /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TOBUF (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0) /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TOBUFXOR (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0) /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA0 (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0) /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA0XOR (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0) /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA1 (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0) /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */ +#define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */ +#define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */ +#define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */ + +/* Bit fields for CRYPTO STATUS */ +#define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */ +#define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */ +#define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is active */ +#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is active */ +#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ + +/* Bit fields for CRYPTO DSTATUS */ +#define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */ +#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */ +#define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ + +/* Bit fields for CRYPTO CSTATUS */ +#define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */ +#define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */ +#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ + +/* Bit fields for CRYPTO KEY */ +#define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */ +#define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */ +#define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */ + +/* Bit fields for CRYPTO KEYBUF */ +#define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */ +#define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */ + +/* Bit fields for CRYPTO SEQCTRL */ +#define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve A */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve A */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */ +#define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ + +/* Bit fields for CRYPTO SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ + +/* Bit fields for CRYPTO IF */ +#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */ +#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction done */ +#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */ +#define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */ + +/* Bit fields for CRYPTO IFS */ +#define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */ +#define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ + +/* Bit fields for CRYPTO IFC */ +#define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */ +#define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ + +/* Bit fields for CRYPTO IEN */ +#define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ +#define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */ +#define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ + +/* Bit fields for CRYPTO SEQ0 */ +#define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ + +/* Bit fields for CRYPTO SEQ1 */ +#define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ + +/* Bit fields for CRYPTO SEQ2 */ +#define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ + +/* Bit fields for CRYPTO SEQ3 */ +#define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ + +/* Bit fields for CRYPTO SEQ4 */ +#define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ + +/* Bit fields for CRYPTO DATA0 */ +#define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */ +#define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */ + +/* Bit fields for CRYPTO DATA1 */ +#define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */ +#define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */ + +/* Bit fields for CRYPTO DATA2 */ +#define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */ +#define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */ + +/* Bit fields for CRYPTO DATA3 */ +#define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */ +#define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */ + +/* Bit fields for CRYPTO DATA0XOR */ +#define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */ +#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */ + +/* Bit fields for CRYPTO DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */ +#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */ + +/* Bit fields for CRYPTO DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */ +#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */ + +/* Bit fields for CRYPTO DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */ +#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */ + +/* Bit fields for CRYPTO DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */ +#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */ + +/* Bit fields for CRYPTO DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */ +#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */ + +/* Bit fields for CRYPTO DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */ +#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */ + +/* Bit fields for CRYPTO DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */ +#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */ + +/* Bit fields for CRYPTO DDATA0 */ +#define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */ +#define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */ + +/* Bit fields for CRYPTO DDATA1 */ +#define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */ +#define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */ + +/* Bit fields for CRYPTO DDATA2 */ +#define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */ +#define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */ + +/* Bit fields for CRYPTO DDATA3 */ +#define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */ +#define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */ + +/* Bit fields for CRYPTO DDATA4 */ +#define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */ +#define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */ + +/* Bit fields for CRYPTO DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */ +#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */ + +/* Bit fields for CRYPTO DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */ +#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */ + +/* Bit fields for CRYPTO DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */ +#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */ + +/* Bit fields for CRYPTO DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */ +#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */ + +/* Bit fields for CRYPTO QDATA0 */ +#define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */ +#define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */ + +/* Bit fields for CRYPTO QDATA1 */ +#define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */ +#define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */ + +/* Bit fields for CRYPTO QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */ +#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */ + +/* Bit fields for CRYPTO QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */ +#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */ + +/* Bit fields for CRYPTO QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */ +#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */ + +/** @} End of group EFR32MG12P_CRYPTO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h new file mode 100644 index 0000000000..b8a1b5bc2f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h @@ -0,0 +1,1003 @@ +/**************************************************************************//** + * @file efr32mg12p_csen.h + * @brief EFR32MG12P_CSEN register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_CSEN + * @{ + * @brief EFR32MG12P_CSEN Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t PRSSEL; /**< Control Register */ + __IOM uint32_t DATA; /**< Control Register */ + __IOM uint32_t SCANMASK0; /**< CSEN Channel Scan Mask */ + __IOM uint32_t SCANINPUTSEL0; /**< Input Channel Configuration register for Scan mode */ + __IOM uint32_t SCANMASK1; /**< CSEN Channel Scan Mask */ + __IOM uint32_t SCANINPUTSEL1; /**< Input Channel Configuration register for Scan mode */ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ + __IOM uint32_t CMPTHR; /**< CSEN Comparator Threshold */ + __IOM uint32_t EMA; /**< Exponential Moving Average */ + __IOM uint32_t EMACTRL; /**< Exponential Moving Average */ + __IOM uint32_t SINGLECTRL; /**< CSEN Single Conversion Control Register */ + __IOM uint32_t DMBASELINE; /**< Control Register */ + __IOM uint32_t DMCFG; /**< Control Register */ + __IOM uint32_t ANACTRL; /**< Analog Control Register */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CSEN_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_CSEN_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CSEN CTRL */ +#define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */ +#define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */ +#define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */ +#define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */ +#define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */ +#define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */ +#define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */ +#define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */ +#define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */ +#define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */ +#define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable. */ +#define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */ +#define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */ +#define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */ +#define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */ +#define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */ +#define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */ +#define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable Bit. */ +#define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift. */ +#define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit. */ +#define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */ +#define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */ +#define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN auto ground enable */ +#define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect. */ +#define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and less than comparison using the exponential moving average (EMA) is enabled. */ +#define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup mode for CSEN */ +#define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Sense local cap connection instead of the external kelvin connection. */ +#define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Sets the accuracy of the charge pump. */ +#define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */ + +/* Bit fields for CSEN TIMCTRL */ +#define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ + +/* Bit fields for CSEN CMD */ +#define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */ +#define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */ +#define CSEN_CMD_START (0x1UL << 0) /**< Start a CSEN conversion. */ +#define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */ +#define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */ +#define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */ +#define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */ + +/* Bit fields for CSEN STATUS */ +#define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */ +#define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< CSEN Busy */ +#define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */ + +/* Bit fields for CSEN PRSSEL */ +#define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_MASK 0x0000000FUL /**< Mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_MASK 0xFUL /**< Bit mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */ + +/* Bit fields for CSEN DATA */ +#define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */ +#define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */ +#define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */ +#define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */ + +/* Bit fields for CSEN SCANMASK0 */ +#define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */ +#define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */ + +/* Bit fields for CSEN SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ + +/* Bit fields for CSEN SCANMASK1 */ +#define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */ +#define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */ + +/* Bit fields for CSEN SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ + +/* Bit fields for CSEN APORTREQ */ +#define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */ +#define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ + +/* Bit fields for CSEN APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ + +/* Bit fields for CSEN CMPTHR */ +#define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */ +#define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */ + +/* Bit fields for CSEN EMA */ +#define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */ +#define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */ +#define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */ +#define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */ + +/* Bit fields for CSEN EMACTRL */ +#define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */ + +/* Bit fields for CSEN SINGLECTRL */ +#define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */ + +/* Bit fields for CSEN DMBASELINE */ +#define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ + +/* Bit fields for CSEN DMCFG */ +#define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */ +#define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Disable delta modulator gain reduction. */ +#define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */ + +/* Bit fields for CSEN ANACTRL */ +#define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_MASK 0x03730771UL /**< Mask for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF (0x1UL << 0) /**< Reference capacitor divide by half. */ +#define _CSEN_ANACTRL_CREFHALF_SHIFT 0 /**< Shift value for CSEN_CREFHALF */ +#define _CSEN_ANACTRL_CREFHALF_MASK 0x1UL /**< Bit mask for CSEN_CREFHALF */ +#define _CSEN_ANACTRL_CREFHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_CREFHALF_FULL 0x00000000UL /**< Mode FULL for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_CREFHALF_HALF 0x00000001UL /**< Mode HALF for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_DEFAULT (_CSEN_ANACTRL_CREFHALF_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_FULL (_CSEN_ANACTRL_CREFHALF_FULL << 0) /**< Shifted mode FULL for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_HALF (_CSEN_ANACTRL_CREFHALF_HALF << 0) /**< Shifted mode HALF for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_SHIFT 16 /**< Shift value for CSEN_DUTYSCALE */ +#define _CSEN_ANACTRL_DUTYSCALE_MASK 0x30000UL /**< Bit mask for CSEN_DUTYSCALE */ +#define _CSEN_ANACTRL_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DEFAULT (_CSEN_ANACTRL_DUTYSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV1 (_CSEN_ANACTRL_DUTYSCALE_DIV1 << 16) /**< Shifted mode DIV1 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV2 (_CSEN_ANACTRL_DUTYSCALE_DIV2 << 16) /**< Shifted mode DIV2 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV4 (_CSEN_ANACTRL_DUTYSCALE_DIV4 << 16) /**< Shifted mode DIV4 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV8 (_CSEN_ANACTRL_DUTYSCALE_DIV8 << 16) /**< Shifted mode DIV8 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_SHIFT 24 /**< Shift value for CSEN_BIASPROG */ +#define _CSEN_ANACTRL_BIASPROG_MASK 0x3000000UL /**< Bit mask for CSEN_BIASPROG */ +#define _CSEN_ANACTRL_BIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_ONEX 0x00000000UL /**< Mode ONEX for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_TWOX 0x00000001UL /**< Mode TWOX for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_ONETENTH 0x00000002UL /**< Mode ONETENTH for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_HALF 0x00000003UL /**< Mode HALF for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_DEFAULT (_CSEN_ANACTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_ONEX (_CSEN_ANACTRL_BIASPROG_ONEX << 24) /**< Shifted mode ONEX for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_TWOX (_CSEN_ANACTRL_BIASPROG_TWOX << 24) /**< Shifted mode TWOX for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_ONETENTH (_CSEN_ANACTRL_BIASPROG_ONETENTH << 24) /**< Shifted mode ONETENTH for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_HALF (_CSEN_ANACTRL_BIASPROG_HALF << 24) /**< Shifted mode HALF for CSEN_ANACTRL */ + +/* Bit fields for CSEN IF */ +#define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */ +#define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */ +#define CSEN_IF_CMP (0x1UL << 0) /**< CSEN Digital Comparator Interrupt Flag */ +#define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV (0x1UL << 1) /**< CSEN Conversion Done Interrupt Flag */ +#define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS (0x1UL << 2) /**< CSEN End of Scan Interrupt Flag. */ +#define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF (0x1UL << 3) /**< CSEN DMA Overflow Interrupt Flag. */ +#define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */ +#define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */ + +/* Bit fields for CSEN IFS */ +#define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */ +#define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */ +#define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */ +#define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */ +#define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */ +#define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */ +#define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */ + +/* Bit fields for CSEN IFC */ +#define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */ +#define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */ +#define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */ +#define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */ +#define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */ +#define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */ +#define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */ + +/* Bit fields for CSEN IEN */ +#define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */ +#define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */ +#define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */ +#define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */ +#define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */ +#define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */ +#define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */ +#define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */ + +/** @} End of group EFR32MG12P_CSEN */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h new file mode 100644 index 0000000000..93450e0bd4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h @@ -0,0 +1,1298 @@ +/**************************************************************************//** + * @file efr32mg12p_devinfo.h + * @brief EFR32MG12P_DEVINFO register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_DEVINFO + * @{ + *****************************************************************************/ + +typedef struct +{ + __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ + uint32_t RESERVED0[7]; /**< Reserved for future use **/ + __IM uint32_t EXTINFO; /**< External Component description */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ + __IM uint32_t EUI48H; /**< OUI */ + __IM uint32_t CUSTOMINFO; /**< Custom information */ + __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ + __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ + __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ + __IM uint32_t PART; /**< Part description */ + __IM uint32_t DEVINFOREV; /**< Device information page revision */ + __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ + uint32_t RESERVED3[2]; /**< Reserved for future use **/ + __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ + __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ + __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ + __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ + uint32_t RESERVED4[4]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED5[2]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED6[2]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ + __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ + __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ + __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ + __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ + uint32_t RESERVED8[11]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED9[2]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED10[2]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ + __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ + __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED11[1]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ + __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ + __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ + uint32_t RESERVED12[11]; /**< Reserved for future use **/ + __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ + __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ + __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ + uint32_t RESERVED13[3]; /**< Reserved for future use **/ + __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ + __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ + uint32_t RESERVED14[2]; /**< Reserved for future use **/ + __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ + __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ + __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ + __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ + __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ + __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */ + __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */ + __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */ + __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */ + uint32_t RESERVED15[3]; /**< Reserved for future use **/ + __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ +} DEVINFO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_DEVINFO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO CAL */ +#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ +#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ +#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ +#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ +#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */ +#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ +#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ + +/* Bit fields for DEVINFO UNIQUEL */ +#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ + +/* Bit fields for DEVINFO UNIQUEH */ +#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ +#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ +#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ + +/* Bit fields for DEVINFO DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ + +/* Bit fields for DEVINFO ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ + +/* Bit fields for DEVINFO ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ + +/* Bit fields for DEVINFO ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ + +/* Bit fields for DEVINFO ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ + +/* Bit fields for DEVINFO HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO VMONCAL0 */ +#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL1 */ +#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL2 */ +#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ + +/* Bit fields for DEVINFO IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ + +/* Bit fields for DEVINFO DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ + +/* Bit fields for DEVINFO VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */ + +/* Bit fields for DEVINFO VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */ + +/* Bit fields for DEVINFO VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */ + +/* Bit fields for DEVINFO OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */ + +/* Bit fields for DEVINFO OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/** @} End of group EFR32MG12P_DEVINFO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h new file mode 100644 index 0000000000..d145021dd3 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h @@ -0,0 +1,52 @@ +/**************************************************************************//** + * @file efr32mg12p_dma_descriptor.h + * @brief EFR32MG12P_DMA_DESCRIPTOR register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_DMA_DESCRIPTOR + * @{ + *****************************************************************************/ +typedef struct +{ + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h new file mode 100644 index 0000000000..611e4b5892 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h @@ -0,0 +1,110 @@ +/**************************************************************************//** + * @file efr32mg12p_dmareq.h + * @brief EFR32MG12P_DMAREQ register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG12P_DMAREQ_BitFields + * @{ + *****************************************************************************/ +#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */ +#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */ +#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ +#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ +#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */ +#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */ +#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ +#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ +#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ +#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ +#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ +#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ +#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */ +#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */ +#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ +#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ +#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ +#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */ +#define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */ +#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */ +#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */ +#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */ +#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ +#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ +#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ +#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ +#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ +#define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */ +#define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */ +#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ +#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ +#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ +#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ +#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ +#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ +#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ +#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ +#define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */ +#define DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */ +#define DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */ +#define DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */ +#define DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */ +#define DMAREQ_WTIMER1_UFOF ((27 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */ +#define DMAREQ_WTIMER1_CC0 ((27 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */ +#define DMAREQ_WTIMER1_CC1 ((27 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */ +#define DMAREQ_WTIMER1_CC2 ((27 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */ +#define DMAREQ_WTIMER1_CC3 ((27 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */ +#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ +#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR /**< Alias for DMAREQ_CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR /**< Alias for DMAREQ_CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD /**< Alias for DMAREQ_CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR /**< Alias for DMAREQ_CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */ +#define DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD /**< Alias for DMAREQ_CRYPTO0_DATA1RD */ +#define DMAREQ_CSEN_DATA ((50 << 16) + 0) /**< DMA channel select for CSEN_DATA */ +#define DMAREQ_CSEN_BSLN ((50 << 16) + 1) /**< DMA channel select for CSEN_BSLN */ +#define DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */ +#define DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) /**< DMA channel select for CRYPTO1_DATA0WR */ +#define DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) /**< DMA channel select for CRYPTO1_DATA0XWR */ +#define DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) /**< DMA channel select for CRYPTO1_DATA0RD */ +#define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */ +#define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */ + +/** @} End of group EFR32MG12P_DMAREQ */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h new file mode 100644 index 0000000000..ea3347b029 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h @@ -0,0 +1,1437 @@ +/**************************************************************************//** + * @file efr32mg12p_emu.h + * @brief EFR32MG12P_EMU register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_EMU + * @{ + * @brief EFR32MG12P_EMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */ + __IM uint32_t TEMP; /**< Value of last temperature measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + __IOM uint32_t PWRCFG; /**< Power Configuration Register */ + __IOM uint32_t PWRCTRL; /**< Power Control Register. */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED5[5]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + + uint32_t RESERVED6[5]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + + uint32_t RESERVED7[12]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration bits for low power mode to be applied during EM01, this field is only relevant if LP mode is used in EM01. */ + + uint32_t RESERVED8[4]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears corresponding bits in EM23PERNORETAINSTATUS unlocking access to peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status indicating if peripherals were powered down in EM23, subsequently locking access to it. */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When set corresponding peripherals may get powered down in EM23 */ +} EMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_EMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically configures Flash, Ram and Frequency to wakeup from EM2 or EM3 at low voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x0417011FUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */ +#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */ +#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */ +#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE31FC0FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */ +#define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */ +#define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE31FC0FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE31FC0FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE31FC0FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCFG */ +#define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */ +#define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_UNCONFIGURED 0x00000000UL /**< Mode UNCONFIGURED for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_UNCONFIGURED (_EMU_PWRCFG_PWRCFG_UNCONFIGURED << 0) /**< Shifted mode UNCONFIGURED for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00001420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This field selects the input for the regulator. */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_DVDDBODDIS (0x1UL << 12) /**< DVDD BOD Disable */ +#define _EMU_PWRCTRL_DVDDBODDIS_SHIFT 12 /**< Shift value for EMU_DVDDBODDIS */ +#define _EMU_PWRCTRL_DVDDBODDIS_MASK 0x1000UL /**< Bit mask for EMU_DVDDBODDIS */ +#define _EMU_PWRCTRL_DVDDBODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_DVDDBODDIS_DEFAULT (_EMU_PWRCTRL_DVDDBODDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP mode hysteresis in the state machine control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator threshold on the high side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC into CCM mode immediately, based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x00000003UL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL /**< Mode BLK1 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0) /**< Shifted mode BLK1 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x00000001UL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL /**< Mode BLK for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0) /**< Shifted mode BLK for EMU_RAM2CTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears status bit of ACMP0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears status bit of ACMP1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears status bit of PCNT0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears status bit of PCNT1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears status bit of PCNT2 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears status bit of I2C0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears status bit of I2C1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears status bit of DAC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears status bit of IDAC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears status bit of ADC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears status bit of LETIMER0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears status bit of WDOG0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears status bit of WDOG1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears status bit of LESENSE0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears status bit of CSEN and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears status bit of LEUART0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates if ACMP0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates if ACMP1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates if PCNT0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates if PCNT1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates if PCNT2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates if I2C0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates if I2C1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates if DAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates if IDAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates if ADC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates if LETIMER0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates if WDOG0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates if WDOG1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates if LESENSE0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates if CSEN powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates if LEUART0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow power down of ACMP0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow power down of ACMP1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow power down of PCNT0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow power down of PCNT1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow power down of PCNT2 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow power down of I2C0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow power down of I2C1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7) /**< Allow power down of DAC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7 /**< Shift value for EMU_DAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL /**< Bit mask for EMU_DAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow power down of IDAC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow power down of ADC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow power down of LETIMER0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow power down of WDOG0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow power down of WDOG1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow power down of LESENSE0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow power down of CSEN during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow power down of LEUART0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} End of group EFR32MG12P_EMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h new file mode 100644 index 0000000000..8b4ca79dc2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h @@ -0,0 +1,781 @@ +/**************************************************************************//** + * @file efr32mg12p_etm.h + * @brief EFR32MG12P_ETM register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_ETM + * @{ + * @brief EFR32MG12P_ETM Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t ETMCR; /**< Main Control Register */ + __IM uint32_t ETMCCR; /**< Configuration Code Register */ + __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMSR; /**< ETM Status Register */ + __IM uint32_t ETMSCR; /**< ETM System Configuration Register */ + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */ + __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */ + uint32_t RESERVED3[68]; /**< Reserved for future use **/ + __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */ + uint32_t RESERVED4[39]; /**< Reserved for future use **/ + __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */ + __IM uint32_t ETMIDR; /**< ID Register */ + __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */ + uint32_t RESERVED5[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */ + uint32_t RESERVED6[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */ + uint32_t RESERVED8[1]; /**< Reserved for future use **/ + __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */ + uint32_t RESERVED9[66]; /**< Reserved for future use **/ + __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */ + uint32_t RESERVED10[754]; /**< Reserved for future use **/ + __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */ + uint32_t RESERVED11[1]; /**< Reserved for future use **/ + __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */ + uint32_t RESERVED12[1]; /**< Reserved for future use **/ + __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */ + uint32_t RESERVED13[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */ + uint32_t RESERVED14[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */ + uint32_t RESERVED15[39]; /**< Reserved for future use **/ + __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */ + __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */ + uint32_t RESERVED16[2]; /**< Reserved for future use **/ + __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */ + __IM uint32_t ETMLSR; /**< Lock Status Register */ + __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */ + uint32_t RESERVED17[4]; /**< Reserved for future use **/ + __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */ + __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */ + __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */ + __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */ + __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */ + __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */ + __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */ + __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */ + __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */ + __IM uint32_t ETMCIDR0; /**< Component ID0 Register */ + __IM uint32_t ETMCIDR1; /**< Component ID1 Register */ + __IM uint32_t ETMCIDR2; /**< Component ID2 Register */ + __IM uint32_t ETMCIDR3; /**< Component ID3 Register */ +} ETM_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_ETM_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ETM ETMCR */ +#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */ +#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */ +#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */ +#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */ +#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */ +#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */ +#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */ +#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */ +#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */ +#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */ +#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */ +#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */ + +/* Bit fields for ETM ETMCCR */ +#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */ +#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */ +#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */ +#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */ +#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */ +#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */ +#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */ +#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */ + +/* Bit fields for ETM ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ + +/* Bit fields for ETM ETMSR */ +#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */ +#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */ +#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */ +#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */ +#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */ +#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */ + +/* Bit fields for ETM ETMSCR */ +#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */ +#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */ +#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */ +#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */ +#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */ +#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */ +#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */ +#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */ + +/* Bit fields for ETM ETMTEEVR */ +#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ + +/* Bit fields for ETM ETMTECR1 */ +#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */ +#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */ +#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */ + +/* Bit fields for ETM ETMFFLR */ +#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */ +#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */ + +/* Bit fields for ETM ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */ +#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */ + +/* Bit fields for ETM ETMSYNCFR */ +#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */ +#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */ + +/* Bit fields for ETM ETMIDR */ +#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */ +#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */ +#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */ +#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */ +#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */ +#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */ +#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */ +#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */ + +/* Bit fields for ETM ETMCCER */ +#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */ +#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */ +#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */ +#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ +#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */ +#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */ +#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */ +#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */ +#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */ +#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */ +#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */ +#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */ + +/* Bit fields for ETM ETMTESSEICR */ +#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ + +/* Bit fields for ETM ETMTSEVR */ +#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ + +/* Bit fields for ETM ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */ +#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */ + +/* Bit fields for ETM ETMIDR2 */ +#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */ +#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */ +#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */ + +/* Bit fields for ETM ETMPDSR */ +#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */ +#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */ +#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */ + +/* Bit fields for ETM ETMISCIN */ +#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */ +#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ + +/* Bit fields for ETM ITTRIGOUT */ +#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */ +#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */ + +/* Bit fields for ETM ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */ +#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */ + +/* Bit fields for ETM ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */ +#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */ + +/* Bit fields for ETM ETMITCTRL */ +#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */ +#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */ +#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */ + +/* Bit fields for ETM ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */ +#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */ + +/* Bit fields for ETM ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */ +#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */ + +/* Bit fields for ETM ETMLAR */ +#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */ +#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */ +#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */ +#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */ +#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */ + +/* Bit fields for ETM ETMLSR */ +#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */ +#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */ +#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */ +#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */ + +/* Bit fields for ETM ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ + +/* Bit fields for ETM ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ + +/* Bit fields for ETM ETMPIDR4 */ +#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ + +/* Bit fields for ETM ETMPIDR5 */ +#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */ +#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */ + +/* Bit fields for ETM ETMPIDR6 */ +#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */ +#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */ + +/* Bit fields for ETM ETMPIDR7 */ +#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */ +#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */ + +/* Bit fields for ETM ETMPIDR0 */ +#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */ +#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */ + +/* Bit fields for ETM ETMPIDR1 */ +#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ + +/* Bit fields for ETM ETMPIDR2 */ +#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */ +#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */ +#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */ +#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ + +/* Bit fields for ETM ETMPIDR3 */ +#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ + +/* Bit fields for ETM ETMCIDR0 */ +#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */ +#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */ + +/* Bit fields for ETM ETMCIDR1 */ +#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */ +#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */ + +/* Bit fields for ETM ETMCIDR2 */ +#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */ +#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */ + +/* Bit fields for ETM ETMCIDR3 */ +#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */ +#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */ + +/** @} End of group EFR32MG12P_ETM */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h new file mode 100644 index 0000000000..649db3065b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file efr32mg12p_fpueh.h + * @brief EFR32MG12P_FPUEH register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_FPUEH + * @{ + * @brief EFR32MG12P_FPUEH Register Declaration + *****************************************************************************/ +typedef struct +{ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} FPUEH_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_FPUEH_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for FPUEH IF */ +#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */ +#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */ +#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */ +#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */ +#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */ +#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */ +#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */ +#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */ +#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */ + +/* Bit fields for FPUEH IFS */ +#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */ +#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */ +#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */ +#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */ +#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */ +#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */ +#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */ +#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */ + +/* Bit fields for FPUEH IFC */ +#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */ +#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */ +#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */ +#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */ +#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */ +#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */ +#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */ +#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */ + +/* Bit fields for FPUEH IEN */ +#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */ +#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */ +#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */ +#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */ +#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */ +#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */ +#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */ +#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */ + +/** @} End of group EFR32MG12P_FPUEH */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h new file mode 100644 index 0000000000..50dc85eaad --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h @@ -0,0 +1,185 @@ +/**************************************************************************//** + * @file efr32mg12p_gpcrc.h + * @brief EFR32MG12P_GPCRC register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_GPCRC + * @{ + * @brief EFR32MG12P_GPCRC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_GPCRC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */ +#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFR32MG12P_GPCRC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h new file mode 100644 index 0000000000..9bb4b2ef1e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h @@ -0,0 +1,1538 @@ +/**************************************************************************//** + * @file efr32mg12p_gpio.h + * @brief EFR32MG12P_GPIO register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_GPIO + * @{ + * @brief EFR32MG12P_GPIO Register Declaration + *****************************************************************************/ +typedef struct +{ + GPIO_P_TypeDef P[12]; /**< Port configuration bits */ + + uint32_t RESERVED0[112]; /**< Reserved for future use **/ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */ + __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */ + __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wake up Enable Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register 1 */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t INSENSE; /**< Input Sense Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} GPIO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_GPIO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for GPIO P_CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive strength for port */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate drive strength for port */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data In Disable */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO P_MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ + +/* Bit fields for GPIO P_MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ + +/* Bit fields for GPIO P_DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */ +#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */ + +/* Bit fields for GPIO P_DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ + +/* Bit fields for GPIO P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */ +#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */ + +/* Bit fields for GPIO P_OVTDIS */ +#define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */ +#define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTI (_GPIO_EXTIPSELL_EXTIPSEL0_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL0_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTK (_GPIO_EXTIPSELL_EXTIPSEL0_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTI (_GPIO_EXTIPSELL_EXTIPSEL1_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL1_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTK (_GPIO_EXTIPSELL_EXTIPSEL1_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTI (_GPIO_EXTIPSELL_EXTIPSEL2_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL2_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTK (_GPIO_EXTIPSELL_EXTIPSEL2_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTI (_GPIO_EXTIPSELL_EXTIPSEL3_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL3_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTK (_GPIO_EXTIPSELL_EXTIPSEL3_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTI (_GPIO_EXTIPSELL_EXTIPSEL4_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL4_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTK (_GPIO_EXTIPSELL_EXTIPSEL4_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTI (_GPIO_EXTIPSELL_EXTIPSEL5_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL5_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTK (_GPIO_EXTIPSELL_EXTIPSEL5_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTI (_GPIO_EXTIPSELL_EXTIPSEL6_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL6_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTK (_GPIO_EXTIPSELL_EXTIPSEL6_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTI (_GPIO_EXTIPSELL_EXTIPSEL7_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL7_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTK (_GPIO_EXTIPSELL_EXTIPSEL7_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTI (_GPIO_EXTIPSELH_EXTIPSEL8_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL8_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTK (_GPIO_EXTIPSELH_EXTIPSEL8_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTI (_GPIO_EXTIPSELH_EXTIPSEL9_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL9_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTK (_GPIO_EXTIPSELH_EXTIPSEL9_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTI (_GPIO_EXTIPSELH_EXTIPSEL10_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL10_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTK (_GPIO_EXTIPSELH_EXTIPSEL10_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTI (_GPIO_EXTIPSELH_EXTIPSEL11_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL11_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTK (_GPIO_EXTIPSELH_EXTIPSEL11_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTI (_GPIO_EXTIPSELH_EXTIPSEL12_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL12_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTK (_GPIO_EXTIPSELH_EXTIPSEL12_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTI (_GPIO_EXTIPSELH_EXTIPSEL13_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL13_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTK (_GPIO_EXTIPSELH_EXTIPSEL13_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTI (_GPIO_EXTIPSELH_EXTIPSEL14_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL14_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTK (_GPIO_EXTIPSELH_EXTIPSEL14_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTI (_GPIO_EXTIPSELH_EXTIPSEL15_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL15_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTK (_GPIO_EXTIPSELH_EXTIPSEL15_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO EXTILEVEL */ +#define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */ +#define _GPIO_EXTILEVEL_MASK 0x13130000UL /**< Mask for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */ +#define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */ +#define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */ +#define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */ +#define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */ +#define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU12 (0x1UL << 28) /**< EM4 Wake Up Level for EM4WU12 Pin */ +#define _GPIO_EXTILEVEL_EM4WU12_SHIFT 28 /**< Shift value for GPIO_EM4WU12 */ +#define _GPIO_EXTILEVEL_EM4WU12_MASK 0x10000000UL /**< Bit mask for GPIO_EM4WU12 */ +#define _GPIO_EXTILEVEL_EM4WU12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU12_DEFAULT (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */ +#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IFS */ +#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */ +#define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */ +#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */ +#define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */ + +/* Bit fields for GPIO IFC */ +#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */ +#define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */ +#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */ +#define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */ +#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO ROUTEPEN */ +#define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */ +#define _GPIO_ROUTEPEN_MASK 0x001F001FUL /**< Mask for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN (0x1UL << 16) /**< ETM Trace Clock Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_SHIFT 16 /**< Shift value for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_MASK 0x10000UL /**< Bit mask for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT (_GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN (0x1UL << 17) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_SHIFT 17 /**< Shift value for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_MASK 0x20000UL /**< Bit mask for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN (0x1UL << 18) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_SHIFT 18 /**< Shift value for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_MASK 0x40000UL /**< Bit mask for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN (0x1UL << 19) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_SHIFT 19 /**< Shift value for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_MASK 0x80000UL /**< Bit mask for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN (0x1UL << 20) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_SHIFT 20 /**< Shift value for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_MASK 0x100000UL /**< Bit mask for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ + +/* Bit fields for GPIO ROUTELOC0 */ +#define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_MASK 0x00000003UL /**< Mask for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */ + +/* Bit fields for GPIO ROUTELOC1 */ +#define _GPIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_MASK 0x0C30C303UL /**< Mask for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_SHIFT 0 /**< Shift value for GPIO_ETMTCLKLOC */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_MASK 0x3UL /**< Bit mask for GPIO_ETMTCLKLOC */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT (_GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_SHIFT 8 /**< Shift value for GPIO_ETMTD0LOC */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_MASK 0x300UL /**< Bit mask for GPIO_ETMTD0LOC */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC0 << 8) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC1 << 8) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC2 << 8) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC3 << 8) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_SHIFT 14 /**< Shift value for GPIO_ETMTD1LOC */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_MASK 0xC000UL /**< Bit mask for GPIO_ETMTD1LOC */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC0 << 14) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC1 << 14) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC2 << 14) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC3 << 14) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_SHIFT 20 /**< Shift value for GPIO_ETMTD2LOC */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_MASK 0x300000UL /**< Bit mask for GPIO_ETMTD2LOC */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC0 << 20) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC1 << 20) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC2 << 20) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC3 << 20) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_SHIFT 26 /**< Shift value for GPIO_ETMTD3LOC */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_MASK 0xC000000UL /**< Bit mask for GPIO_ETMTD3LOC */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC0 << 26) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC1 << 26) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC2 << 26) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC3 << 26) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ + +/* Bit fields for GPIO INSENSE */ +#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */ +#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */ +#define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */ +#define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */ +#define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */ +#define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */ +#define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/** @} End of group EFR32MG12P_GPIO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h new file mode 100644 index 0000000000..3329331344 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file efr32mg12p_gpio_p.h + * @brief EFR32MG12P_GPIO_P register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief GPIO_P EFR32MG12P GPIO P + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Port Control Register */ + __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */ + __IOM uint32_t MODEH; /**< Port Pin Mode High Register */ + __IOM uint32_t DOUT; /**< Port Data Out Register */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */ + __IM uint32_t DIN; /**< Port Data In Register */ + __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t OVTDIS; /**< Over Voltage Disable for all modes */ + uint32_t RESERVED2[1]; /**< Reserved future */ +} GPIO_P_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h new file mode 100644 index 0000000000..3642c7f8dd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h @@ -0,0 +1,921 @@ +/**************************************************************************//** + * @file efr32mg12p_i2c.h + * @brief EFR32MG12P_I2C register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_I2C + * @{ + * @brief EFR32MG12P_I2C Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Slave Address Register */ + __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ +} I2C_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_I2C_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ +#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IFS */ +#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ +#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */ +#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ +#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */ +#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */ +#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */ +#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */ +#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */ +#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ +#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */ +#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */ +#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */ +#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */ +#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */ +#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */ +#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */ +#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ +#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */ +#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */ +#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */ + +/* Bit fields for I2C IFC */ +#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ +#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */ +#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ +#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */ +#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */ +#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */ +#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */ +#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */ +#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ +#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */ +#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */ +#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */ +#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */ +#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */ +#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */ +#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */ +#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ +#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */ +#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */ +#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ + +/* Bit fields for I2C ROUTEPEN */ +#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */ +#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ +#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ +#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ + +/* Bit fields for I2C ROUTELOC0 */ +#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ + +/** @} End of group EFR32MG12P_I2C */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h new file mode 100644 index 0000000000..8f15a6fad9 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h @@ -0,0 +1,352 @@ +/**************************************************************************//** + * @file efr32mg12p_idac.h + * @brief EFR32MG12P_IDAC register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_IDAC + * @{ + * @brief EFR32MG12P_IDAC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CURPROG; /**< Current Programming Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ +} IDAC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_IDAC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for IDAC CTRL */ +#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */ +#define _IDAC_CTRL_MASK 0x00FD7FFFUL /**< Mask for IDAC_CTRL */ +#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */ +#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */ +#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */ +#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */ +#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */ +#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */ +#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */ +#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */ +#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */ +#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */ +#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */ + +/* Bit fields for IDAC CURPROG */ +#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */ +#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */ +#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */ + +/* Bit fields for IDAC DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */ + +/* Bit fields for IDAC STATUS */ +#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */ +#define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */ +#define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */ +#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */ + +/* Bit fields for IDAC IF */ +#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */ +#define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */ +#define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */ +#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */ + +/* Bit fields for IDAC IFS */ +#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ +#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */ + +/* Bit fields for IDAC IFC */ +#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ +#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */ + +/* Bit fields for IDAC IEN */ +#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ +#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ +#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */ + +/* Bit fields for IDAC APORTREQ */ +#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */ +#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */ +#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ +#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ + +/* Bit fields for IDAC APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ + +/** @} End of group EFR32MG12P_IDAC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h new file mode 100644 index 0000000000..59b3632e39 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h @@ -0,0 +1,643 @@ +/**************************************************************************//** + * @file efr32mg12p_ldma.h + * @brief EFR32MG12P_LDMA register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_LDMA + * @{ + * @brief EFR32MG12P_LDMA Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */ + uint32_t RESERVED0[5]; /**< Reserved for future use **/ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + uint32_t RESERVED1[7]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + + uint32_t RESERVED2[4]; /**< Reserved registers */ + LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */ +} LDMA_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_LDMA_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNC */ +#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */ +#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */ +#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */ +#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IFS */ +#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */ +#define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */ +#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */ +#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */ + +/* Bit fields for LDMA IFC */ +#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */ +#define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */ +#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */ +#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_REQSEL */ +#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR /**< Alias for mode CRYPTO0DATA0WR */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR 0x00000000UL /**< Mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR /**< Alias for mode CRYPTO0DATA0XWR */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR 0x00000001UL /**< Mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD /**< Alias for mode CRYPTO0DATA0RD */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD 0x00000002UL /**< Mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR /**< Alias for mode CRYPTO0DATA1WR */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR 0x00000003UL /**< Mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD /**< Alias for mode CRYPTO0DATA1RD */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD 0x00000004UL /**< Mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR << 0) /**< Shifted mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR << 0) /**< Shifted mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD << 0) /**< Shifted mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR << 0) /**< Shifted mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD << 0) /**< Shifted mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x0000001AUL /**< Mode WTIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x0000001BUL /**< Mode WTIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 /**< Alias for mode CRYPTO0 */ +#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x00000032UL /**< Mode CSEN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x00000033UL /**< Mode LESENSE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 0x00000034UL /**< Mode CRYPTO1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 << 16) /**< Shifted mode CRYPTO1 for LDMA_CH_REQSEL */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */ +#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFR32MG12P_LDMA */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h new file mode 100644 index 0000000000..3809e6f62c --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h @@ -0,0 +1,53 @@ +/**************************************************************************//** + * @file efr32mg12p_ldma_ch.h + * @brief EFR32MG12P_LDMA_CH register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LDMA_CH EFR32MG12P LDMA CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */ + uint32_t RESERVED0[5]; /**< Reserved future */ +} LDMA_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h new file mode 100644 index 0000000000..45defeab7c --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h @@ -0,0 +1,1867 @@ +/**************************************************************************//** + * @file efr32mg12p_lesense.h + * @brief EFR32MG12P_LESENSE register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_LESENSE + * @{ + * @brief EFR32MG12P_LESENSE Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t PERCTRL; /**< Peripheral Control Register */ + __IOM uint32_t DECCTRL; /**< Decoder control Register */ + __IOM uint32_t BIASCTRL; /**< Bias Control Register */ + __IOM uint32_t EVALCTRL; /**< LESENSE evaluation control */ + __IOM uint32_t PRSCTRL; /**< PRS control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t CHEN; /**< Channel enable Register */ + __IOM uint32_t SCANRES; /**< Scan result register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t PTR; /**< Result buffer pointers */ + __IM uint32_t BUFDATA; /**< Result buffer data register */ + __IM uint32_t CURCH; /**< Current channel index */ + __IOM uint32_t DECSTATE; /**< Current decoder state */ + __IOM uint32_t SENSORSTATE; /**< Decoder input register */ + __IOM uint32_t IDLECONF; /**< GPIO Idle phase configuration */ + __IOM uint32_t ALTEXCONF; /**< Alternative excite pin configuration */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */ + + uint32_t RESERVED1[38]; /**< Reserved registers */ + LESENSE_ST_TypeDef ST[32]; /**< Decoding states */ + + LESENSE_BUF_TypeDef BUF[16]; /**< Scanresult */ + + LESENSE_CH_TypeDef CH[16]; /**< Scanconfig */ +} LESENSE_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_LESENSE_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LESENSE CTRL */ +#define _LESENSE_CTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CTRL */ +#define _LESENSE_CTRL_MASK 0x007B29BFUL /**< Mask for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_DEFAULT (_LESENSE_CTRL_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PERIODIC (_LESENSE_CTRL_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_ONESHOT (_LESENSE_CTRL_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PRS (_LESENSE_CTRL_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_SHIFT 2 /**< Shift value for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_MASK 0x3CUL /**< Bit mask for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_DEFAULT (_LESENSE_CTRL_PRSSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH0 (_LESENSE_CTRL_PRSSEL_PRSCH0 << 2) /**< Shifted mode PRSCH0 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH1 (_LESENSE_CTRL_PRSSEL_PRSCH1 << 2) /**< Shifted mode PRSCH1 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH2 (_LESENSE_CTRL_PRSSEL_PRSCH2 << 2) /**< Shifted mode PRSCH2 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH3 (_LESENSE_CTRL_PRSSEL_PRSCH3 << 2) /**< Shifted mode PRSCH3 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH4 (_LESENSE_CTRL_PRSSEL_PRSCH4 << 2) /**< Shifted mode PRSCH4 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH5 (_LESENSE_CTRL_PRSSEL_PRSCH5 << 2) /**< Shifted mode PRSCH5 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH6 (_LESENSE_CTRL_PRSSEL_PRSCH6 << 2) /**< Shifted mode PRSCH6 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH7 (_LESENSE_CTRL_PRSSEL_PRSCH7 << 2) /**< Shifted mode PRSCH7 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH8 (_LESENSE_CTRL_PRSSEL_PRSCH8 << 2) /**< Shifted mode PRSCH8 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH9 (_LESENSE_CTRL_PRSSEL_PRSCH9 << 2) /**< Shifted mode PRSCH9 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH10 (_LESENSE_CTRL_PRSSEL_PRSCH10 << 2) /**< Shifted mode PRSCH10 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH11 (_LESENSE_CTRL_PRSSEL_PRSCH11 << 2) /**< Shifted mode PRSCH11 for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_SHIFT 7 /**< Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_MASK 0x180UL /**< Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DEFAULT (_LESENSE_CTRL_SCANCONF_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DIRMAP (_LESENSE_CTRL_SCANCONF_DIRMAP << 7) /**< Shifted mode DIRMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 7) /**< Shifted mode INVMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 7) /**< Shifted mode TOGGLE for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 7) /**< Shifted mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative excitation map */ +#define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /**< Shift value for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /**< Bit mask for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_ALTEX 0x00000000UL /**< Mode ALTEX for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_CH 0x00000001UL /**< Mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /**< Shifted mode ALTEX for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_CH (_LESENSE_CTRL_ALTEXMAP_CH << 11) /**< Shifted mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable dual sample mode */ +#define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /**< Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /**< Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result buffer overwrite */ +#define _LESENSE_CTRL_BUFOW_SHIFT 16 /**< Shift value for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /**< Bit mask for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable storing of SCANRES */ +#define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /**< Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /**< Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result buffer interrupt and DMA trigger level */ +#define _LESENSE_CTRL_BUFIDL_SHIFT 19 /**< Shift value for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_MASK 0x80000UL /**< Bit mask for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_HALFFULL 0x00000000UL /**< Mode HALFFULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_FULL 0x00000001UL /**< Mode FULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_DEFAULT (_LESENSE_CTRL_BUFIDL_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_HALFFULL (_LESENSE_CTRL_BUFIDL_HALFFULL << 19) /**< Shifted mode HALFFULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_FULL (_LESENSE_CTRL_BUFIDL_FULL << 19) /**< Shifted mode FULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_SHIFT 20 /**< Shift value for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_MASK 0x300000UL /**< Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFDATAV 0x00000001UL /**< Mode BUFDATAV for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFLEVEL 0x00000002UL /**< Mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DEFAULT (_LESENSE_CTRL_DMAWU_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DISABLE (_LESENSE_CTRL_DMAWU_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFDATAV (_LESENSE_CTRL_DMAWU_BUFDATAV << 20) /**< Shifted mode BUFDATAV for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFLEVEL (_LESENSE_CTRL_DMAWU_BUFLEVEL << 20) /**< Shifted mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN (0x1UL << 22) /**< Debug Mode Run Enable */ +#define _LESENSE_CTRL_DEBUGRUN_SHIFT 22 /**< Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_MASK 0x400000UL /**< Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN_DEFAULT (_LESENSE_CTRL_DEBUGRUN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_CTRL */ + +/* Bit fields for LESENSE TIMCTRL */ +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO startup configuration */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ + +/* Bit fields for LESENSE PERCTRL */ +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x3FF0014FUL /**< Mask for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 enable. */ +#define _LESENSE_PERCTRL_DACCH0EN_SHIFT 0 /**< Shift value for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_MASK 0x1UL /**< Bit mask for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN_DEFAULT (_LESENSE_PERCTRL_DACCH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 enable. */ +#define _LESENSE_PERCTRL_DACCH1EN_SHIFT 1 /**< Shift value for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_MASK 0x2UL /**< Bit mask for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN_DEFAULT (_LESENSE_PERCTRL_DACCH1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 data selection. */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 data selection. */ +#define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 3 /**< Shift value for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x8UL /**< Bit mask for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 3) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_THRES (_LESENSE_PERCTRL_DACCH1DATA_THRES << 3) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC startup configuration */ +#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC conversion trigger configuration */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x300000UL /**< Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DISABLE (_LESENSE_PERCTRL_ACMP0MODE_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0xC00000UL /**< Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ +#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ +#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 hysteresis enable */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_SHIFT 26 /**< Shift value for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_MASK 0x4000000UL /**< Bit mask for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 hysteresis enable */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_SHIFT 27 /**< Shift value for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_MASK 0x8000000UL /**< Bit mask for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT << 27) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_SHIFT 28 /**< Shift value for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_MASK 0x30000000UL /**< Bit mask for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM 0x00000001UL /**< Mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM 0x00000002UL /**< Mode KEEPDACWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM 0x00000003UL /**< Mode KEEPACMPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_DEFAULT (_LESENSE_PERCTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_NORMAL (_LESENSE_PERCTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM << 28) /**< Shifted mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM << 28) /**< Shifted mode KEEPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM << 28) /**< Shifted mode KEEPACMPDACWARM for LESENSE_PERCTRL */ + +/* Bit fields for LESENSE DECCTRL */ +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x1EF7BDFFUL /**< Mask for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the decoder */ +#define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /**< Shift value for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /**< Bit mask for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable check of current state */ +#define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /**< Shift value for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /**< Bit mask for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt mapping */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt requests */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channels 0 and 1 */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE decoder input configuration */ +#define _LESENSE_DECCTRL_INPUT_SHIFT 8 /**< Shift value for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /**< Bit mask for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_SENSORSTATE 0x00000000UL /**< Mode SENSORSTATE for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_PRS 0x00000001UL /**< Mode PRS for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_DEFAULT (_LESENSE_DECCTRL_INPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_SENSORSTATE (_LESENSE_DECCTRL_INPUT_SENSORSTATE << 8) /**< Shifted mode SENSORSTATE for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_PRS (_LESENSE_DECCTRL_INPUT_PRS << 8) /**< Shifted mode PRS for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_SHIFT 10 /**< Shift value for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_MASK 0x3C00UL /**< Bit mask for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_DEFAULT (_LESENSE_DECCTRL_PRSSEL0_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH0 (_LESENSE_DECCTRL_PRSSEL0_PRSCH0 << 10) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH1 (_LESENSE_DECCTRL_PRSSEL0_PRSCH1 << 10) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH2 (_LESENSE_DECCTRL_PRSSEL0_PRSCH2 << 10) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH3 (_LESENSE_DECCTRL_PRSSEL0_PRSCH3 << 10) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH4 (_LESENSE_DECCTRL_PRSSEL0_PRSCH4 << 10) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH5 (_LESENSE_DECCTRL_PRSSEL0_PRSCH5 << 10) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH6 (_LESENSE_DECCTRL_PRSSEL0_PRSCH6 << 10) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH7 (_LESENSE_DECCTRL_PRSSEL0_PRSCH7 << 10) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH8 (_LESENSE_DECCTRL_PRSSEL0_PRSCH8 << 10) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH9 (_LESENSE_DECCTRL_PRSSEL0_PRSCH9 << 10) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH10 (_LESENSE_DECCTRL_PRSSEL0_PRSCH10 << 10) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH11 (_LESENSE_DECCTRL_PRSSEL0_PRSCH11 << 10) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_SHIFT 15 /**< Shift value for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_MASK 0x78000UL /**< Bit mask for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_DEFAULT (_LESENSE_DECCTRL_PRSSEL1_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH0 (_LESENSE_DECCTRL_PRSSEL1_PRSCH0 << 15) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH1 (_LESENSE_DECCTRL_PRSSEL1_PRSCH1 << 15) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH2 (_LESENSE_DECCTRL_PRSSEL1_PRSCH2 << 15) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH3 (_LESENSE_DECCTRL_PRSSEL1_PRSCH3 << 15) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH4 (_LESENSE_DECCTRL_PRSSEL1_PRSCH4 << 15) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH5 (_LESENSE_DECCTRL_PRSSEL1_PRSCH5 << 15) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH6 (_LESENSE_DECCTRL_PRSSEL1_PRSCH6 << 15) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH7 (_LESENSE_DECCTRL_PRSSEL1_PRSCH7 << 15) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH8 (_LESENSE_DECCTRL_PRSSEL1_PRSCH8 << 15) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH9 (_LESENSE_DECCTRL_PRSSEL1_PRSCH9 << 15) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH10 (_LESENSE_DECCTRL_PRSSEL1_PRSCH10 << 15) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH11 (_LESENSE_DECCTRL_PRSSEL1_PRSCH11 << 15) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_SHIFT 20 /**< Shift value for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_MASK 0xF00000UL /**< Bit mask for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_DEFAULT (_LESENSE_DECCTRL_PRSSEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH0 (_LESENSE_DECCTRL_PRSSEL2_PRSCH0 << 20) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH1 (_LESENSE_DECCTRL_PRSSEL2_PRSCH1 << 20) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH2 (_LESENSE_DECCTRL_PRSSEL2_PRSCH2 << 20) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH3 (_LESENSE_DECCTRL_PRSSEL2_PRSCH3 << 20) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH4 (_LESENSE_DECCTRL_PRSSEL2_PRSCH4 << 20) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH5 (_LESENSE_DECCTRL_PRSSEL2_PRSCH5 << 20) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH6 (_LESENSE_DECCTRL_PRSSEL2_PRSCH6 << 20) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH7 (_LESENSE_DECCTRL_PRSSEL2_PRSCH7 << 20) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH8 (_LESENSE_DECCTRL_PRSSEL2_PRSCH8 << 20) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH9 (_LESENSE_DECCTRL_PRSSEL2_PRSCH9 << 20) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH10 (_LESENSE_DECCTRL_PRSSEL2_PRSCH10 << 20) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH11 (_LESENSE_DECCTRL_PRSSEL2_PRSCH11 << 20) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_SHIFT 25 /**< Shift value for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_MASK 0x1E000000UL /**< Bit mask for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_DEFAULT (_LESENSE_DECCTRL_PRSSEL3_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH0 (_LESENSE_DECCTRL_PRSSEL3_PRSCH0 << 25) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH1 (_LESENSE_DECCTRL_PRSSEL3_PRSCH1 << 25) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH2 (_LESENSE_DECCTRL_PRSSEL3_PRSCH2 << 25) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH3 (_LESENSE_DECCTRL_PRSSEL3_PRSCH3 << 25) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH4 (_LESENSE_DECCTRL_PRSSEL3_PRSCH4 << 25) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH5 (_LESENSE_DECCTRL_PRSSEL3_PRSCH5 << 25) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH6 (_LESENSE_DECCTRL_PRSSEL3_PRSCH6 << 25) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH7 (_LESENSE_DECCTRL_PRSSEL3_PRSCH7 << 25) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH8 (_LESENSE_DECCTRL_PRSSEL3_PRSCH8 << 25) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH9 (_LESENSE_DECCTRL_PRSSEL3_PRSCH9 << 25) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH10 (_LESENSE_DECCTRL_PRSSEL3_PRSCH10 << 25) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH11 (_LESENSE_DECCTRL_PRSSEL3_PRSCH11 << 25) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ + +/* Bit fields for LESENSE BIASCTRL */ +#define _LESENSE_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_MASK 0x00000003UL /**< Mask for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_SHIFT 0 /**< Shift value for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_MASK 0x3UL /**< Bit mask for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DONTTOUCH 0x00000000UL /**< Mode DONTTOUCH for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE 0x00000001UL /**< Mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_HIGHACC 0x00000002UL /**< Mode HIGHACC for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DEFAULT (_LESENSE_BIASCTRL_BIASMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DONTTOUCH (_LESENSE_BIASCTRL_BIASMODE_DONTTOUCH << 0) /**< Shifted mode DONTTOUCH for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE (_LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE << 0) /**< Shifted mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_HIGHACC (_LESENSE_BIASCTRL_BIASMODE_HIGHACC << 0) /**< Shifted mode HIGHACC for LESENSE_BIASCTRL */ + +/* Bit fields for LESENSE EVALCTRL */ +#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ +#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ + +/* Bit fields for LESENSE PRSCTRL */ +#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ +#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ + +/* Bit fields for LESENSE CMD */ +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ +#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ +#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ + +/* Bit fields for LESENSE CHEN */ +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ + +/* Bit fields for LESENSE SCANRES */ +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ + +/* Bit fields for LESENSE STATUS */ +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000003FUL /**< Mask for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result data valid */ +#define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result buffer half full */ +#define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /**< Shift value for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /**< Bit mask for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result buffer full */ +#define _LESENSE_STATUS_BUFFULL_SHIFT 2 /**< Shift value for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /**< Bit mask for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE periodic counter running */ +#define _LESENSE_STATUS_RUNNING_SHIFT 3 /**< Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x8UL /**< Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE scan active */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /**< Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /**< Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC interface is active */ +#define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /**< Shift value for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /**< Bit mask for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE_DEFAULT (_LESENSE_STATUS_DACACTIVE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ + +/* Bit fields for LESENSE PTR */ +#define _LESENSE_PTR_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PTR */ +#define _LESENSE_PTR_MASK 0x000000FFUL /**< Mask for LESENSE_PTR */ +#define _LESENSE_PTR_RD_SHIFT 0 /**< Shift value for LESENSE_RD */ +#define _LESENSE_PTR_RD_MASK 0xFUL /**< Bit mask for LESENSE_RD */ +#define _LESENSE_PTR_RD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_RD_DEFAULT (_LESENSE_PTR_RD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PTR */ +#define _LESENSE_PTR_WR_SHIFT 4 /**< Shift value for LESENSE_WR */ +#define _LESENSE_PTR_WR_MASK 0xF0UL /**< Bit mask for LESENSE_WR */ +#define _LESENSE_PTR_WR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_WR_DEFAULT (_LESENSE_PTR_WR_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_PTR */ + +/* Bit fields for LESENSE BUFDATA */ +#define _LESENSE_BUFDATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_SHIFT 0 /**< Shift value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATA_DEFAULT (_LESENSE_BUFDATA_BUFDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATASRC_SHIFT 16 /**< Shift value for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATASRC_DEFAULT (_LESENSE_BUFDATA_BUFDATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ + +/* Bit fields for LESENSE CURCH */ +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ + +/* Bit fields for LESENSE DECSTATE */ +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ + +/* Bit fields for LESENSE SENSORSTATE */ +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE */ + +/* Bit fields for LESENSE IDLECONF */ +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_MASK 0x3UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DEFAULT (_LESENSE_IDLECONF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DISABLE (_LESENSE_IDLECONF_CH0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_HIGH (_LESENSE_IDLECONF_CH0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_LOW (_LESENSE_IDLECONF_CH0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DAC (_LESENSE_IDLECONF_CH0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_SHIFT 2 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_MASK 0xCUL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DEFAULT (_LESENSE_IDLECONF_CH1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DISABLE (_LESENSE_IDLECONF_CH1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_HIGH (_LESENSE_IDLECONF_CH1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_LOW (_LESENSE_IDLECONF_CH1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DAC (_LESENSE_IDLECONF_CH1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_SHIFT 4 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_MASK 0x30UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DEFAULT (_LESENSE_IDLECONF_CH2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DISABLE (_LESENSE_IDLECONF_CH2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_HIGH (_LESENSE_IDLECONF_CH2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_LOW (_LESENSE_IDLECONF_CH2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DAC (_LESENSE_IDLECONF_CH2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_SHIFT 6 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_MASK 0xC0UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DEFAULT (_LESENSE_IDLECONF_CH3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DISABLE (_LESENSE_IDLECONF_CH3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_HIGH (_LESENSE_IDLECONF_CH3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_LOW (_LESENSE_IDLECONF_CH3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DAC (_LESENSE_IDLECONF_CH3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_SHIFT 8 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_MASK 0x300UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DEFAULT (_LESENSE_IDLECONF_CH4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DISABLE (_LESENSE_IDLECONF_CH4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_HIGH (_LESENSE_IDLECONF_CH4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_LOW (_LESENSE_IDLECONF_CH4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DAC (_LESENSE_IDLECONF_CH4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_SHIFT 10 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_MASK 0xC00UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DEFAULT (_LESENSE_IDLECONF_CH5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DISABLE (_LESENSE_IDLECONF_CH5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_HIGH (_LESENSE_IDLECONF_CH5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_LOW (_LESENSE_IDLECONF_CH5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DAC (_LESENSE_IDLECONF_CH5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_SHIFT 12 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_MASK 0x3000UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DEFAULT (_LESENSE_IDLECONF_CH6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DISABLE (_LESENSE_IDLECONF_CH6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_HIGH (_LESENSE_IDLECONF_CH6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_LOW (_LESENSE_IDLECONF_CH6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DAC (_LESENSE_IDLECONF_CH6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_SHIFT 14 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_MASK 0xC000UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DEFAULT (_LESENSE_IDLECONF_CH7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DISABLE (_LESENSE_IDLECONF_CH7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_HIGH (_LESENSE_IDLECONF_CH7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_LOW (_LESENSE_IDLECONF_CH7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DAC (_LESENSE_IDLECONF_CH7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_SHIFT 16 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_MASK 0x30000UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DEFAULT (_LESENSE_IDLECONF_CH8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DISABLE (_LESENSE_IDLECONF_CH8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_HIGH (_LESENSE_IDLECONF_CH8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_LOW (_LESENSE_IDLECONF_CH8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DAC (_LESENSE_IDLECONF_CH8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_SHIFT 18 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_MASK 0xC0000UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DEFAULT (_LESENSE_IDLECONF_CH9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DISABLE (_LESENSE_IDLECONF_CH9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_HIGH (_LESENSE_IDLECONF_CH9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_LOW (_LESENSE_IDLECONF_CH9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DAC (_LESENSE_IDLECONF_CH9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_SHIFT 20 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_MASK 0x300000UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DEFAULT (_LESENSE_IDLECONF_CH10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DISABLE (_LESENSE_IDLECONF_CH10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_HIGH (_LESENSE_IDLECONF_CH10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_LOW (_LESENSE_IDLECONF_CH10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DAC (_LESENSE_IDLECONF_CH10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_SHIFT 22 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_MASK 0xC00000UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DEFAULT (_LESENSE_IDLECONF_CH11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DISABLE (_LESENSE_IDLECONF_CH11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_HIGH (_LESENSE_IDLECONF_CH11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_LOW (_LESENSE_IDLECONF_CH11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DAC (_LESENSE_IDLECONF_CH11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_SHIFT 24 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_MASK 0x3000000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DEFAULT (_LESENSE_IDLECONF_CH12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DISABLE (_LESENSE_IDLECONF_CH12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_HIGH (_LESENSE_IDLECONF_CH12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_LOW (_LESENSE_IDLECONF_CH12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DAC (_LESENSE_IDLECONF_CH12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_SHIFT 26 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_MASK 0xC000000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DEFAULT (_LESENSE_IDLECONF_CH13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DISABLE (_LESENSE_IDLECONF_CH13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_HIGH (_LESENSE_IDLECONF_CH13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_LOW (_LESENSE_IDLECONF_CH13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DAC (_LESENSE_IDLECONF_CH13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_SHIFT 28 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_MASK 0x30000000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DEFAULT (_LESENSE_IDLECONF_CH14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DISABLE (_LESENSE_IDLECONF_CH14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_HIGH (_LESENSE_IDLECONF_CH14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_LOW (_LESENSE_IDLECONF_CH14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DAC (_LESENSE_IDLECONF_CH14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_SHIFT 30 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DEFAULT (_LESENSE_IDLECONF_CH15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DISABLE (_LESENSE_IDLECONF_CH15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_HIGH (_LESENSE_IDLECONF_CH15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_LOW (_LESENSE_IDLECONF_CH15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DAC (_LESENSE_IDLECONF_CH15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ + +/* Bit fields for LESENSE ALTEXCONF */ +#define _LESENSE_ALTEXCONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_SHIFT 0 /**< Shift value for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_MASK 0x3UL /**< Bit mask for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DISABLE (_LESENSE_ALTEXCONF_IDLECONF0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_HIGH (_LESENSE_ALTEXCONF_IDLECONF0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_LOW (_LESENSE_ALTEXCONF_IDLECONF0_LOW << 0) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_SHIFT 2 /**< Shift value for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_MASK 0xCUL /**< Bit mask for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DISABLE (_LESENSE_ALTEXCONF_IDLECONF1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_HIGH (_LESENSE_ALTEXCONF_IDLECONF1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_LOW (_LESENSE_ALTEXCONF_IDLECONF1_LOW << 2) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_SHIFT 4 /**< Shift value for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_MASK 0x30UL /**< Bit mask for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DISABLE (_LESENSE_ALTEXCONF_IDLECONF2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_HIGH (_LESENSE_ALTEXCONF_IDLECONF2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_LOW (_LESENSE_ALTEXCONF_IDLECONF2_LOW << 4) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_SHIFT 6 /**< Shift value for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_MASK 0xC0UL /**< Bit mask for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DISABLE (_LESENSE_ALTEXCONF_IDLECONF3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_HIGH (_LESENSE_ALTEXCONF_IDLECONF3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_LOW (_LESENSE_ALTEXCONF_IDLECONF3_LOW << 6) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_SHIFT 8 /**< Shift value for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_MASK 0x300UL /**< Bit mask for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DISABLE (_LESENSE_ALTEXCONF_IDLECONF4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_HIGH (_LESENSE_ALTEXCONF_IDLECONF4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_LOW (_LESENSE_ALTEXCONF_IDLECONF4_LOW << 8) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_SHIFT 10 /**< Shift value for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_MASK 0xC00UL /**< Bit mask for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DISABLE (_LESENSE_ALTEXCONF_IDLECONF5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_HIGH (_LESENSE_ALTEXCONF_IDLECONF5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_LOW (_LESENSE_ALTEXCONF_IDLECONF5_LOW << 10) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_SHIFT 12 /**< Shift value for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_MASK 0x3000UL /**< Bit mask for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DISABLE (_LESENSE_ALTEXCONF_IDLECONF6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_HIGH (_LESENSE_ALTEXCONF_IDLECONF6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_LOW (_LESENSE_ALTEXCONF_IDLECONF6_LOW << 12) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_SHIFT 14 /**< Shift value for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_MASK 0xC000UL /**< Bit mask for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /**< Shift value for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /**< Bit mask for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /**< Shift value for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /**< Bit mask for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /**< Shift value for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /**< Bit mask for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /**< Shift value for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /**< Bit mask for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /**< Shift value for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /**< Bit mask for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /**< Shift value for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /**< Bit mask for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /**< Shift value for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /**< Bit mask for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /**< Shift value for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /**< Bit mask for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7_DEFAULT (_LESENSE_ALTEXCONF_AEX7_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ + +/* Bit fields for LESENSE IF */ +#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x007FFFFFUL /**< Mask for LESENSE_IF */ +#define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 interrupt flag */ +#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 interrupt flag */ +#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 interrupt flag */ +#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 interrupt flag */ +#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 interrupt flag */ +#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 interrupt flag */ +#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 interrupt flag */ +#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 interrupt flag */ +#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 interrupt flag */ +#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 interrupt flag */ +#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 interrupt flag */ +#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 interrupt flag */ +#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 interrupt flag */ +#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 interrupt flag */ +#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 interrupt flag */ +#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 interrupt flag */ +#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE interrupt flag */ +#define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /**< DEC interrupt flag */ +#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR interrupt flag */ +#define _LESENSE_IF_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV interrupt flag */ +#define _LESENSE_IF_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL interrupt flag */ +#define _LESENSE_IF_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF interrupt flag */ +#define _LESENSE_IF_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF interrupt flag */ +#define _LESENSE_IF_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IF */ + +/* Bit fields for LESENSE IFS */ +#define _LESENSE_IFS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFS */ +#define _LESENSE_IFS_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFS */ +#define LESENSE_IFS_CH0 (0x1UL << 0) /**< Set CH0 Interrupt Flag */ +#define _LESENSE_IFS_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH0_DEFAULT (_LESENSE_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1 (0x1UL << 1) /**< Set CH1 Interrupt Flag */ +#define _LESENSE_IFS_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1_DEFAULT (_LESENSE_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2 (0x1UL << 2) /**< Set CH2 Interrupt Flag */ +#define _LESENSE_IFS_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2_DEFAULT (_LESENSE_IFS_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3 (0x1UL << 3) /**< Set CH3 Interrupt Flag */ +#define _LESENSE_IFS_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3_DEFAULT (_LESENSE_IFS_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4 (0x1UL << 4) /**< Set CH4 Interrupt Flag */ +#define _LESENSE_IFS_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4_DEFAULT (_LESENSE_IFS_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5 (0x1UL << 5) /**< Set CH5 Interrupt Flag */ +#define _LESENSE_IFS_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5_DEFAULT (_LESENSE_IFS_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6 (0x1UL << 6) /**< Set CH6 Interrupt Flag */ +#define _LESENSE_IFS_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6_DEFAULT (_LESENSE_IFS_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7 (0x1UL << 7) /**< Set CH7 Interrupt Flag */ +#define _LESENSE_IFS_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7_DEFAULT (_LESENSE_IFS_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8 (0x1UL << 8) /**< Set CH8 Interrupt Flag */ +#define _LESENSE_IFS_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8_DEFAULT (_LESENSE_IFS_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9 (0x1UL << 9) /**< Set CH9 Interrupt Flag */ +#define _LESENSE_IFS_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9_DEFAULT (_LESENSE_IFS_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10 (0x1UL << 10) /**< Set CH10 Interrupt Flag */ +#define _LESENSE_IFS_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10_DEFAULT (_LESENSE_IFS_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11 (0x1UL << 11) /**< Set CH11 Interrupt Flag */ +#define _LESENSE_IFS_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11_DEFAULT (_LESENSE_IFS_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12 (0x1UL << 12) /**< Set CH12 Interrupt Flag */ +#define _LESENSE_IFS_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12_DEFAULT (_LESENSE_IFS_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13 (0x1UL << 13) /**< Set CH13 Interrupt Flag */ +#define _LESENSE_IFS_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13_DEFAULT (_LESENSE_IFS_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14 (0x1UL << 14) /**< Set CH14 Interrupt Flag */ +#define _LESENSE_IFS_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14_DEFAULT (_LESENSE_IFS_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15 (0x1UL << 15) /**< Set CH15 Interrupt Flag */ +#define _LESENSE_IFS_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15_DEFAULT (_LESENSE_IFS_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE (0x1UL << 16) /**< Set SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFS_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE_DEFAULT (_LESENSE_IFS_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC (0x1UL << 17) /**< Set DEC Interrupt Flag */ +#define _LESENSE_IFS_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC_DEFAULT (_LESENSE_IFS_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR (0x1UL << 18) /**< Set DECERR Interrupt Flag */ +#define _LESENSE_IFS_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR_DEFAULT (_LESENSE_IFS_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV (0x1UL << 19) /**< Set BUFDATAV Interrupt Flag */ +#define _LESENSE_IFS_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV_DEFAULT (_LESENSE_IFS_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL (0x1UL << 20) /**< Set BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFS_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL_DEFAULT (_LESENSE_IFS_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF (0x1UL << 21) /**< Set BUFOF Interrupt Flag */ +#define _LESENSE_IFS_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF_DEFAULT (_LESENSE_IFS_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF (0x1UL << 22) /**< Set CNTOF Interrupt Flag */ +#define _LESENSE_IFS_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF_DEFAULT (_LESENSE_IFS_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFS */ + +/* Bit fields for LESENSE IFC */ +#define _LESENSE_IFC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFC */ +#define _LESENSE_IFC_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFC */ +#define LESENSE_IFC_CH0 (0x1UL << 0) /**< Clear CH0 Interrupt Flag */ +#define _LESENSE_IFC_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH0_DEFAULT (_LESENSE_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1 (0x1UL << 1) /**< Clear CH1 Interrupt Flag */ +#define _LESENSE_IFC_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1_DEFAULT (_LESENSE_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2 (0x1UL << 2) /**< Clear CH2 Interrupt Flag */ +#define _LESENSE_IFC_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2_DEFAULT (_LESENSE_IFC_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3 (0x1UL << 3) /**< Clear CH3 Interrupt Flag */ +#define _LESENSE_IFC_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3_DEFAULT (_LESENSE_IFC_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4 (0x1UL << 4) /**< Clear CH4 Interrupt Flag */ +#define _LESENSE_IFC_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4_DEFAULT (_LESENSE_IFC_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5 (0x1UL << 5) /**< Clear CH5 Interrupt Flag */ +#define _LESENSE_IFC_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5_DEFAULT (_LESENSE_IFC_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6 (0x1UL << 6) /**< Clear CH6 Interrupt Flag */ +#define _LESENSE_IFC_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6_DEFAULT (_LESENSE_IFC_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7 (0x1UL << 7) /**< Clear CH7 Interrupt Flag */ +#define _LESENSE_IFC_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7_DEFAULT (_LESENSE_IFC_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8 (0x1UL << 8) /**< Clear CH8 Interrupt Flag */ +#define _LESENSE_IFC_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8_DEFAULT (_LESENSE_IFC_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9 (0x1UL << 9) /**< Clear CH9 Interrupt Flag */ +#define _LESENSE_IFC_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9_DEFAULT (_LESENSE_IFC_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10 (0x1UL << 10) /**< Clear CH10 Interrupt Flag */ +#define _LESENSE_IFC_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10_DEFAULT (_LESENSE_IFC_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11 (0x1UL << 11) /**< Clear CH11 Interrupt Flag */ +#define _LESENSE_IFC_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11_DEFAULT (_LESENSE_IFC_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12 (0x1UL << 12) /**< Clear CH12 Interrupt Flag */ +#define _LESENSE_IFC_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12_DEFAULT (_LESENSE_IFC_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13 (0x1UL << 13) /**< Clear CH13 Interrupt Flag */ +#define _LESENSE_IFC_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13_DEFAULT (_LESENSE_IFC_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14 (0x1UL << 14) /**< Clear CH14 Interrupt Flag */ +#define _LESENSE_IFC_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14_DEFAULT (_LESENSE_IFC_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15 (0x1UL << 15) /**< Clear CH15 Interrupt Flag */ +#define _LESENSE_IFC_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15_DEFAULT (_LESENSE_IFC_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE (0x1UL << 16) /**< Clear SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFC_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE_DEFAULT (_LESENSE_IFC_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC (0x1UL << 17) /**< Clear DEC Interrupt Flag */ +#define _LESENSE_IFC_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC_DEFAULT (_LESENSE_IFC_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR (0x1UL << 18) /**< Clear DECERR Interrupt Flag */ +#define _LESENSE_IFC_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR_DEFAULT (_LESENSE_IFC_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV (0x1UL << 19) /**< Clear BUFDATAV Interrupt Flag */ +#define _LESENSE_IFC_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV_DEFAULT (_LESENSE_IFC_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL (0x1UL << 20) /**< Clear BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFC_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL_DEFAULT (_LESENSE_IFC_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF (0x1UL << 21) /**< Clear BUFOF Interrupt Flag */ +#define _LESENSE_IFC_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF_DEFAULT (_LESENSE_IFC_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF (0x1UL << 22) /**< Clear CNTOF Interrupt Flag */ +#define _LESENSE_IFC_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF_DEFAULT (_LESENSE_IFC_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFC */ + +/* Bit fields for LESENSE IEN */ +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x007FFFFFUL /**< Mask for LESENSE_IEN */ +#define LESENSE_IEN_CH0 (0x1UL << 0) /**< CH0 Interrupt Enable */ +#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /**< CH1 Interrupt Enable */ +#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /**< CH2 Interrupt Enable */ +#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /**< CH3 Interrupt Enable */ +#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /**< CH4 Interrupt Enable */ +#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /**< CH5 Interrupt Enable */ +#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /**< CH6 Interrupt Enable */ +#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /**< CH7 Interrupt Enable */ +#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /**< CH8 Interrupt Enable */ +#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /**< CH9 Interrupt Enable */ +#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /**< CH10 Interrupt Enable */ +#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /**< CH11 Interrupt Enable */ +#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /**< CH12 Interrupt Enable */ +#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /**< CH13 Interrupt Enable */ +#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /**< CH14 Interrupt Enable */ +#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /**< CH15 Interrupt Enable */ +#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Enable */ +#define _LESENSE_IEN_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE_DEFAULT (_LESENSE_IEN_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /**< DEC Interrupt Enable */ +#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR (0x1UL << 18) /**< DECERR Interrupt Enable */ +#define _LESENSE_IEN_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR_DEFAULT (_LESENSE_IEN_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Enable */ +#define _LESENSE_IEN_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV_DEFAULT (_LESENSE_IEN_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Enable */ +#define _LESENSE_IEN_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL_DEFAULT (_LESENSE_IEN_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Enable */ +#define _LESENSE_IEN_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF_DEFAULT (_LESENSE_IEN_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Enable */ +#define _LESENSE_IEN_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IEN */ + +/* Bit fields for LESENSE SYNCBUSY */ +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x00000080UL /**< Mask for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 7) /**< CMD Register Busy */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 7 /**< Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x80UL /**< Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ + +/* Bit fields for LESENSE ROUTEPEN */ +#define _LESENSE_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ROUTEPEN */ +#define _LESENSE_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN_DEFAULT (_LESENSE_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN_DEFAULT (_LESENSE_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN_DEFAULT (_LESENSE_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN_DEFAULT (_LESENSE_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN_DEFAULT (_LESENSE_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN_DEFAULT (_LESENSE_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN_DEFAULT (_LESENSE_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN_DEFAULT (_LESENSE_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN_DEFAULT (_LESENSE_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN_DEFAULT (_LESENSE_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN_DEFAULT (_LESENSE_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN_DEFAULT (_LESENSE_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN_DEFAULT (_LESENSE_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN_DEFAULT (_LESENSE_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN_DEFAULT (_LESENSE_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN_DEFAULT (_LESENSE_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN (0x1UL << 16) /**< ALTEX0 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_SHIFT 16 /**< Shift value for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_MASK 0x10000UL /**< Bit mask for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN (0x1UL << 17) /**< ALTEX1 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_SHIFT 17 /**< Shift value for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_MASK 0x20000UL /**< Bit mask for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN (0x1UL << 18) /**< ALTEX2 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_SHIFT 18 /**< Shift value for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN (0x1UL << 19) /**< ALTEX3 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_SHIFT 19 /**< Shift value for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_MASK 0x80000UL /**< Bit mask for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN (0x1UL << 20) /**< ALTEX4 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_SHIFT 20 /**< Shift value for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_MASK 0x100000UL /**< Bit mask for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN (0x1UL << 21) /**< ALTEX5 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_SHIFT 21 /**< Shift value for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN (0x1UL << 22) /**< ALTEX6 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_SHIFT 22 /**< Shift value for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_MASK 0x400000UL /**< Bit mask for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN (0x1UL << 23) /**< ALTEX7 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_SHIFT 23 /**< Shift value for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_MASK 0x800000UL /**< Bit mask for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ + +/* Bit fields for LESENSE ST_TCONFA */ +#define _LESENSE_ST_TCONFA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK 0x0007DFFFUL /**< Mask for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_COMP_DEFAULT (_LESENSE_ST_TCONFA_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_MASK_DEFAULT (_LESENSE_ST_TCONFA_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable state descriptor chaining */ +#define _LESENSE_ST_TCONFA_CHAIN_SHIFT 14 /**< Shift value for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_MASK 0x4000UL /**< Bit mask for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set interrupt flag enable */ +#define _LESENSE_ST_TCONFA_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF_DEFAULT (_LESENSE_ST_TCONFA_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */ + +/* Bit fields for LESENSE ST_TCONFB */ +#define _LESENSE_ST_TCONFB_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK 0x00079FFFUL /**< Mask for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_COMP_DEFAULT (_LESENSE_ST_TCONFB_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_MASK_DEFAULT (_LESENSE_ST_TCONFB_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set interrupt flag */ +#define _LESENSE_ST_TCONFB_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF_DEFAULT (_LESENSE_ST_TCONFB_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */ + +/* Bit fields for LESENSE BUF_DATA */ +#define _LESENSE_BUF_DATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATA_SHIFT 0 /**< Shift value for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATA_DEFAULT (_LESENSE_BUF_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATASRC_SHIFT 16 /**< Shift value for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATASRC_DEFAULT (_LESENSE_BUF_DATA_DATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ + +/* Bit fields for LESENSE CH_TIMING */ +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ + +/* Bit fields for LESENSE CH_INTERACT */ +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x003FFFFFUL /**< Mask for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 12 /**< Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x3000UL /**< Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 12) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 12) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 12) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 12) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 14 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0x1C000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 14) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 14) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 14) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 14) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 14) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 17 /**< Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x60000UL /**< Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 17) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 17) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 17) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 17) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select clock used for excitation timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 19 /**< Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x80000UL /**< Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select clock used for timing of sample delay */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 20 /**< Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x100000UL /**< Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use alternative excite pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 21 /**< Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ + +/* Bit fields for LESENSE CH_EVAL */ +#define _LESENSE_CH_EVAL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MASK 0x007FFFFFUL /**< Mask for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMPTHRES_SHIFT 0 /**< Shift value for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select mode for threshold comparison */ +#define _LESENSE_CH_EVAL_COMP_SHIFT 16 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /**< Shifted mode LESS for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /**< Shifted mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send result to decoder */ +#define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE_DEFAULT (_LESENSE_CH_EVAL_DECODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_SHIFT 18 /**< Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_MASK 0xC0000UL /**< Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DEFAULT (_LESENSE_CH_EVAL_STRSAMPLE_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DISABLE (_LESENSE_CH_EVAL_STRSAMPLE_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATA (_LESENSE_CH_EVAL_STRSAMPLE_DATA << 18) /**< Shifted mode DATA for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATASRC (_LESENSE_CH_EVAL_STRSAMPLE_DATASRC << 18) /**< Shifted mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable inversion of result */ +#define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 20 /**< Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x100000UL /**< Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SHIFT 21 /**< Shift value for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_MASK 0x600000UL /**< Bit mask for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_DEFAULT (_LESENSE_CH_EVAL_MODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_THRES (_LESENSE_CH_EVAL_MODE_THRES << 21) /**< Shifted mode THRES for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_SLIDINGWIN (_LESENSE_CH_EVAL_MODE_SLIDINGWIN << 21) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_STEPDET (_LESENSE_CH_EVAL_MODE_STEPDET << 21) /**< Shifted mode STEPDET for LESENSE_CH_EVAL */ + +/** @} End of group EFR32MG12P_LESENSE */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h new file mode 100644 index 0000000000..668922bbe8 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efr32mg12p_lesense_buf.h + * @brief EFR32MG12P_LESENSE_BUF register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_BUF EFR32MG12P LESENSE BUF + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t DATA; /**< Scan results */ +} LESENSE_BUF_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h new file mode 100644 index 0000000000..3567289be9 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efr32mg12p_lesense_ch.h + * @brief EFR32MG12P_LESENSE_CH register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_CH EFR32MG12P LESENSE CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t TIMING; /**< Scan configuration */ + __IOM uint32_t INTERACT; /**< Scan configuration */ + __IOM uint32_t EVAL; /**< Scan configuration */ + uint32_t RESERVED0[1]; /**< Reserved future */ +} LESENSE_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h new file mode 100644 index 0000000000..0796466298 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h @@ -0,0 +1,47 @@ +/**************************************************************************//** + * @file efr32mg12p_lesense_st.h + * @brief EFR32MG12P_LESENSE_ST register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_ST EFR32MG12P LESENSE ST + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t TCONFA; /**< State transition configuration A */ + __IOM uint32_t TCONFB; /**< State transition configuration B */ +} LESENSE_ST_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h new file mode 100644 index 0000000000..6069c66530 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h @@ -0,0 +1,620 @@ +/**************************************************************************//** + * @file efr32mg12p_letimer.h + * @brief EFR32MG12P_LETIMER register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_LETIMER + * @{ + * @brief EFR32MG12P_LETIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IOM uint32_t PRSSEL; /**< PRS Input Select Register */ +} LETIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_LETIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IFS */ +#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */ +#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */ +#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */ +#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */ +#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */ +#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */ +#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */ +#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */ + +/* Bit fields for LETIMER IFC */ +#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */ +#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */ +#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */ +#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */ +#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */ +#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */ +#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */ +#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER ROUTEPEN */ +#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */ +#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ + +/* Bit fields for LETIMER ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ + +/* Bit fields for LETIMER PRSSEL */ +#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */ + +/** @} End of group EFR32MG12P_LETIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h new file mode 100644 index 0000000000..e93be21f97 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h @@ -0,0 +1,835 @@ +/**************************************************************************//** + * @file efr32mg12p_leuart.h + * @brief EFR32MG12P_LEUART register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_LEUART + * @{ + * @brief EFR32MG12P_LEUART Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IOM uint32_t STARTFRAME; /**< Start Frame Register */ + __IOM uint32_t SIGFRAME; /**< Signal Frame Register */ + __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PULSECTRL; /**< Pulse Control Register */ + + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< LEUART Input Register */ +} LEUART_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_LEUART_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LEUART CTRL */ +#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ +#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */ +#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */ +#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */ +#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */ +#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ +#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ +#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */ +#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */ +#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */ +#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */ +#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ +#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ +#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */ +#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */ +#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */ +#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */ +#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ + +/* Bit fields for LEUART CMD */ +#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ +#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ +#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */ +#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ + +/* Bit fields for LEUART STATUS */ +#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */ +#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */ +#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */ +#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */ +#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ +#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */ +#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */ +#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */ +#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */ + +/* Bit fields for LEUART CLKDIV */ +#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ +#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ + +/* Bit fields for LEUART STARTFRAME */ +#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ +#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ + +/* Bit fields for LEUART SIGFRAME */ +#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ +#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ + +/* Bit fields for LEUART RXDATAX */ +#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */ +#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */ +#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ + +/* Bit fields for LEUART RXDATA */ +#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ +#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ +#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ + +/* Bit fields for LEUART RXDATAXP */ +#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */ +#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */ +#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ + +/* Bit fields for LEUART TXDATAX */ +#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */ +#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ + +/* Bit fields for LEUART TXDATA */ +#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ +#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ +#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ + +/* Bit fields for LEUART IF */ +#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ +#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ +#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */ +#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */ +#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */ +#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */ +#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */ +#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */ +#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */ +#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */ + +/* Bit fields for LEUART IFS */ +#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ +#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ +#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */ +#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */ +#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */ +#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */ +#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */ +#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */ +#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */ +#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */ +#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ + +/* Bit fields for LEUART IFC */ +#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ +#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ +#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */ +#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */ +#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */ +#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */ +#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */ +#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */ +#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */ +#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */ +#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ + +/* Bit fields for LEUART IEN */ +#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ +#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ +#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */ +#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */ +#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */ +#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */ +#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */ +#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */ +#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */ +#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */ +#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ + +/* Bit fields for LEUART PULSECTRL */ +#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */ +#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */ +#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ + +/* Bit fields for LEUART FREEZE */ +#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ +#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ + +/* Bit fields for LEUART SYNCBUSY */ +#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */ +#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */ +#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */ +#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */ +#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */ +#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */ +#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ + +/* Bit fields for LEUART ROUTEPEN */ +#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */ +#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ + +/* Bit fields for LEUART ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ + +/* Bit fields for LEUART INPUT */ +#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */ +#define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */ +#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */ + +/** @} End of group EFR32MG12P_LEUART */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h new file mode 100644 index 0000000000..e85bf5727e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h @@ -0,0 +1,664 @@ +/**************************************************************************//** + * @file efr32mg12p_msc.h + * @brief EFR32MG12P_MSC register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_MSC + * @{ + * @brief EFR32MG12P_MSC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader read and write enable, write once register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control enable Register */ +} MSC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_MSC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000001FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x0000017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash controller write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x0000017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x0000017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x0000017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Enable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Eanble */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software unlock AAP command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00090101UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */ +#define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */ +#define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */ +#define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */ +#define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */ +#define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */ +#define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMSEQCACHEEN (0x1UL << 19) /**< RAMSEQ CACHE Enable */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_SHIFT 19 /**< Shift value for MSC_RAMSEQCACHEEN */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_MASK 0x80000UL /**< Bit mask for MSC_RAMSEQCACHEEN */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/** @} End of group EFR32MG12P_MSC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h new file mode 100644 index 0000000000..af539fc315 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h @@ -0,0 +1,706 @@ +/**************************************************************************//** + * @file efr32mg12p_pcnt.h + * @brief EFR32MG12P_PCNT register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_PCNT + * @{ + * @brief EFR32MG12P_PCNT Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Top Value Buffer Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED2[7]; /**< Reserved for future use **/ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t INPUT; /**< PCNT Input Register */ + __IOM uint32_t OVSCFG; /**< Oversampling Config Register */ +} PCNT_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_PCNT_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */ +#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */ +#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */ +#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */ +#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */ +#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */ +#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */ +#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */ +#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */ +#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS gate enable */ +#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS polarity select */ +#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High frequency value select */ +#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */ +#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered compare Interrupt Read Flag */ +#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */ +#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IFS */ +#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */ +#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */ +#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */ +#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */ +#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */ +#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */ +#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */ +#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */ +#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */ + +/* Bit fields for PCNT IFC */ +#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */ +#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */ +#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */ +#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */ +#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */ +#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */ +#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */ +#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */ +#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */ +#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */ +#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT ROUTELOC0 */ +#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ + +/* Bit fields for PCNT FREEZE */ +#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */ +#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */ +#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT INPUT */ +#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */ +#define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */ +#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */ +#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */ + +/* Bit fields for PCNT OVSCFG */ +#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ + +/** @} End of group EFR32MG12P_PCNT */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h new file mode 100644 index 0000000000..2af6abec9d --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h @@ -0,0 +1,1089 @@ +/**************************************************************************//** + * @file efr32mg12p_prs.h + * @brief EFR32MG12P_PRS register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_PRS + * @{ + * @brief EFR32MG12P_PRS Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[5]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3]; /**< Reserved registers */ + PRS_CH_TypeDef CH[12]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_PRS_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00000FFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x0F07070FUL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0xFUL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC4 (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC5 (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC6 (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC7 (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC8 (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC9 (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC10 (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC11 (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC12 (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC13 (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x700UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC4 (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC5 (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC6 (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC7 (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x70000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC4 (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC5 (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC6 (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC7 (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC4 (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC5 (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC6 (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC7 (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC8 (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC9 (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC10 (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC11 (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC12 (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC13 (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC14 (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24) /**< Shifted mode LOC14 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x0F1F0707UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x7UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC3 (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC4 (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC5 (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC6 (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x700UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC3 (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC4 (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC5 (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC6 (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x1F0000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC17 0x00000011UL /**< Mode LOC17 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC3 (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC4 (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC5 (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC6 (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC7 (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC8 (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC9 (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC10 (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC11 (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16) /**< Shifted mode LOC11 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC12 (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16) /**< Shifted mode LOC12 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC13 (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16) /**< Shifted mode LOC13 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC14 (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16) /**< Shifted mode LOC14 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC15 (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16) /**< Shifted mode LOC15 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC16 (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16) /**< Shifted mode LOC16 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC17 (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16) /**< Shifted mode LOC17 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC3 (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC4 (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC5 (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC6 (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC7 (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC8 (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC9 (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC10 (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x07071F0FUL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0xFUL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC3 (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC4 (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC5 (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC6 (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC7 (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC8 (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC9 (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC10 (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x1F00UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC3 (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC4 (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC5 (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC6 (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC7 (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC8 (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC9 (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC10 (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC11 (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8) /**< Shifted mode LOC11 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC12 (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8) /**< Shifted mode LOC12 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC13 (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8) /**< Shifted mode LOC13 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC14 (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8) /**< Shifted mode LOC14 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC15 (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8) /**< Shifted mode LOC15 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC16 (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8) /**< Shifted mode LOC16 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x70000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC3 (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC4 (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC5 (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x7000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC3 (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC4 (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC5 (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000002UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000003UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000004UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000005UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000007UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000008UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x00000009UL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000000AUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x0000000BUL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x0000000CUL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000DUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000EUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000FUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x00000010UL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x00000011UL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000012UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000018UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000001AUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x0000003EUL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x0000003FUL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} End of group EFR32MG12P_PRS */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h new file mode 100644 index 0000000000..230aa69208 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efr32mg12p_prs_ch.h + * @brief EFR32MG12P_PRS_CH register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief PRS_CH EFR32MG12P PRS CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Channel Control Register */ +} PRS_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h new file mode 100644 index 0000000000..7ecf6a8714 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efr32mg12p_prs_signals.h + * @brief EFR32MG12P_PRS_SIGNALS register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @addtogroup EFR32MG12P_PRS_Signals + * @{ + * @brief PRS Signal names + *****************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_ACMP0_OUT ((3 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((5 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((5 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_LESENSE_SCANRES0 ((7 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((7 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((7 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((7 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((7 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((7 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((7 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((7 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((8 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((8 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((8 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((8 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((8 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((8 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((8 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((8 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((9 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((9 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((9 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((9 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((10 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_RTCC_CCV0 ((11 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((11 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((11 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((12 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((12 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((12 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((12 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((12 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((12 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((12 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((12 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((13 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((13 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((13 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((13 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((13 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((13 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((13 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((13 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((14 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((14 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((15 << 8) + 0) /**< PRS PCNT0 Triggered compare match */ +#define PRS_PCNT0_UFOF ((15 << 8) + 1) /**< PRS PCNT0 Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((15 << 8) + 2) /**< PRS PCNT0 Counter direction */ +#define PRS_PCNT1_TCC ((16 << 8) + 0) /**< PRS PCNT1 Triggered compare match */ +#define PRS_PCNT1_UFOF ((16 << 8) + 1) /**< PRS PCNT1 Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((16 << 8) + 2) /**< PRS PCNT1 Counter direction */ +#define PRS_PCNT2_TCC ((17 << 8) + 0) /**< PRS PCNT2 Triggered compare match */ +#define PRS_PCNT2_UFOF ((17 << 8) + 1) /**< PRS PCNT2 Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((17 << 8) + 2) /**< PRS PCNT2 Counter direction */ +#define PRS_CMU_CLKOUT0 ((18 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((18 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_VDAC0_CH0 ((24 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((24 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((24 << 8) + 2) /**< PRS OPA0 warmedup or outputvalid based on OPA0PRSOUTMODE mode in OPACTRL. */ +#define PRS_VDAC0_OPA1 ((24 << 8) + 3) /**< PRS OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL. */ +#define PRS_VDAC0_OPA2 ((24 << 8) + 4) /**< PRS OPA2 warmedup or outputvalid based on OPA2PRSOUTMODE mode in OPACTRL. */ +#define PRS_CRYOTIMER_PERIOD ((26 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS USART 0 IRDA out */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS USART 0 TX complete */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS USART 0 RX Data Valid */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS USART 0 RTS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS USART 0 TX */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS USART 0 CS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS USART 1 TX complete */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS USART 1 RX Data Valid */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS USART 1 RTS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS USART 1 TX */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS USART 1 CS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS USART 2 TX complete */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS USART 2 RX Data Valid */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS USART 2 RTS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS USART 2 TX */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS USART 2 CS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS USART 3 TX complete */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS USART 3 RX Data Valid */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS USART 3 RTS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS USART 3 TX */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS USART 3 CS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS Timer 0 Underflow */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS Timer 0 Overflow */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS Timer 1 Underflow */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS Timer 1 Overflow */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */ +#define PRS_WTIMER0_UF ((62 << 8) + 0) /**< PRS Timer 2 Underflow */ +#define PRS_WTIMER0_OF ((62 << 8) + 1) /**< PRS Timer 2 Overflow */ +#define PRS_WTIMER0_CC0 ((62 << 8) + 2) /**< PRS Timer 2 Compare/Capture 0 */ +#define PRS_WTIMER0_CC1 ((62 << 8) + 3) /**< PRS Timer 2 Compare/Capture 1 */ +#define PRS_WTIMER0_CC2 ((62 << 8) + 4) /**< PRS Timer 2 Compare/Capture 2 */ +#define PRS_WTIMER1_UF ((63 << 8) + 0) /**< PRS Timer 3 Underflow */ +#define PRS_WTIMER1_OF ((63 << 8) + 1) /**< PRS Timer 3 Overflow */ +#define PRS_WTIMER1_CC0 ((63 << 8) + 2) /**< PRS Timer 3 Compare/Capture 0 */ +#define PRS_WTIMER1_CC1 ((63 << 8) + 3) /**< PRS Timer 3 Compare/Capture 1 */ +#define PRS_WTIMER1_CC2 ((63 << 8) + 4) /**< PRS Timer 3 Compare/Capture 2 */ +#define PRS_WTIMER1_CC3 ((63 << 8) + 5) /**< PRS Timer 3 Compare/Capture 3 */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ + +/** @} End of group EFR32MG12P_PRS */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h new file mode 100644 index 0000000000..fb4355e5b7 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file efr32mg12p_rmu.h + * @brief EFR32MG12P_RMU register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_RMU + * @{ + * @brief EFR32MG12P_RMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t RSTCAUSE; /**< Reset Cause Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t RST; /**< Reset Control Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} RMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_RMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for RMU CTRL */ +#define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */ +#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */ + +/* Bit fields for RMU RSTCAUSE */ +#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */ +#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */ +#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */ +#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */ +#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */ +#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */ +#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */ +#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */ +#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */ +#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ + +/* Bit fields for RMU CMD */ +#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ +#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ +#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ +#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ +#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ + +/* Bit fields for RMU RST */ +#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */ +#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */ + +/* Bit fields for RMU LOCK */ +#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */ +#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */ + +/** @} End of group EFR32MG12P_RMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h new file mode 100644 index 0000000000..4f3684b93a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file efr32mg12p_romtable.h + * @brief EFR32MG12P_ROMTABLE register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_ROMTABLE + * @{ + * @brief Chip Information, Revision numbers + *****************************************************************************/ +typedef struct +{ + __IM uint32_t PID4; /**< JEP_106_BANK */ + __IM uint32_t PID5; /**< Unused */ + __IM uint32_t PID6; /**< Unused */ + __IM uint32_t PID7; /**< Unused */ + __IM uint32_t PID0; /**< Chip family LSB, chip major revision */ + __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */ + __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */ + __IM uint32_t PID3; /**< Chip minor rev LSB */ + __IM uint32_t CID0; /**< Unused */ +} ROMTABLE_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_ROMTABLE_BitFields + * @{ + *****************************************************************************/ +/* Bit fields for EFR32MG12P_ROMTABLE */ +#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */ +#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */ +#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */ + +/** @} End of group EFR32MG12P_ROMTABLE */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h new file mode 100644 index 0000000000..2895e69f92 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h @@ -0,0 +1,695 @@ +/**************************************************************************//** + * @file efr32mg12p_rtcc.h + * @brief EFR32MG12P_RTCC register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_RTCC + * @{ + * @brief EFR32MG12P_RTCC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */ + __IOM uint32_t TIME; /**< Time of day register */ + __IOM uint32_t DATE; /**< Date register */ + __IM uint32_t IF; /**< RTCC Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + + RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */ + + uint32_t RESERVED0[37]; /**< Reserved registers */ + RTCC_RET_TypeDef RET[32]; /**< RetentionReg */ +} RTCC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_RTCC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for RTCC CTRL */ +#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */ +#define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */ +#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ +#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */ +#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */ +#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */ +#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */ +#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */ +#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */ +#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */ + +/* Bit fields for RTCC PRECNT */ +#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ +#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ +#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ + +/* Bit fields for RTCC CNT */ +#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ +#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ +#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ +#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ + +/* Bit fields for RTCC COMBCNT */ +#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ + +/* Bit fields for RTCC TIME */ +#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */ +#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */ +#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */ +#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */ +#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */ +#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */ +#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */ +#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */ +#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */ +#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */ +#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */ + +/* Bit fields for RTCC DATE */ +#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */ +#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */ +#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ +#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */ +#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */ +#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */ + +/* Bit fields for RTCC IF */ +#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ +#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */ +#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */ +#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */ +#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */ +#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */ +#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */ +#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */ +#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */ +#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */ +#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */ +#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */ +#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */ + +/* Bit fields for RTCC IFS */ +#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */ +#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */ +#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */ +#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */ +#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */ +#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */ +#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */ +#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */ +#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */ +#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */ +#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */ +#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */ +#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */ + +/* Bit fields for RTCC IFC */ +#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */ +#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */ +#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */ +#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */ +#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */ +#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */ +#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */ +#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */ +#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */ +#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */ +#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */ +#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */ +#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */ + +/* Bit fields for RTCC IEN */ +#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ +#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */ +#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */ +#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */ +#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */ +#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */ +#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */ +#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */ +#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */ +#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */ +#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */ +#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */ +#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */ + +/* Bit fields for RTCC STATUS */ +#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ +#define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */ + +/* Bit fields for RTCC CMD */ +#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ +#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */ +#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ + +/* Bit fields for RTCC SYNCBUSY */ +#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ +#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */ +#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ + +/* Bit fields for RTCC POWERDOWN */ +#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */ +#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */ +#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */ + +/* Bit fields for RTCC LOCK */ +#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ +#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ + +/* Bit fields for RTCC EM4WUEN */ +#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */ +#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ +#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */ + +/* Bit fields for RTCC CC_CTRL */ +#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */ +#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */ +#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */ + +/* Bit fields for RTCC CC_CCV */ +#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */ +#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */ +#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */ +#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */ + +/* Bit fields for RTCC CC_TIME */ +#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */ +#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */ +#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */ +#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */ +#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */ +#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */ +#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */ +#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */ +#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ + +/* Bit fields for RTCC CC_DATE */ +#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ +#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ + +/* Bit fields for RTCC RET_REG */ +#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */ +#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */ +#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */ +#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */ +#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */ +#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */ + +/** @} End of group EFR32MG12P_RTCC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h new file mode 100644 index 0000000000..0ca6692db6 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efr32mg12p_rtcc_cc.h + * @brief EFR32MG12P_RTCC_CC register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief RTCC_CC EFR32MG12P RTCC CC + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< Capture/Compare Value Register */ + __IOM uint32_t TIME; /**< Capture/Compare Time Register */ + __IOM uint32_t DATE; /**< Capture/Compare Date Register */ +} RTCC_CC_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h new file mode 100644 index 0000000000..530a6c2668 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efr32mg12p_rtcc_ret.h + * @brief EFR32MG12P_RTCC_RET register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief RTCC_RET EFR32MG12P RTCC RET + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t REG; /**< Retention register */ +} RTCC_RET_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h new file mode 100644 index 0000000000..41559ea3da --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h @@ -0,0 +1,400 @@ +/**************************************************************************//** + * @file efr32mg12p_smu.h + * @brief EFR32MG12P_SMU register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_SMU + * @{ + * @brief EFR32MG12P_SMU Register Declaration + *****************************************************************************/ +typedef struct +{ + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + + uint32_t RESERVED3[14]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_SMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0x3BFF7FA7UL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 2) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 2 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x4UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 5) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 5 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) /**< Advanced Encryption Standard Accelerator 0 access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator 1 access control bit */ +#define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 /**< Shift value for SMU_CRYPTO1 */ +#define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL /**< Bit mask for SMU_CRYPTO1 */ +#define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 13) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 13 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 14) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 14 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 22) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 22 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x400000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 23) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 23 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 24 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 25) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 25 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT0 (0x1UL << 27) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD0_PCNT0_SHIFT 27 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT1 (0x1UL << 28) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD0_PCNT1_SHIFT 28 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD0_PCNT1_MASK 0x10000000UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD0_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT1_DEFAULT (_SMU_PPUPATD0_PCNT1_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT2 (0x1UL << 29) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD0_PCNT2_SHIFT 29 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD0_PCNT2_MASK 0x20000000UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD0_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT2_DEFAULT (_SMU_PPUPATD0_PCNT2_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x0000FFEEUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 1) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 1 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x2UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 2) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 2 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x4UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 5) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 5 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x20UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 6) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 6 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x40UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 7) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 7 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x80UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 8 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x100UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 9 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x200UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 10 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x400UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 11 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x800UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 12) /**< Watchdog 0 access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 12 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x1000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 13) /**< Watchdog 1 access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 13 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x2000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 14) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 14 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x4000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 15) /**< Wide Timer 1 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 15 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x8000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL /**< Mode CRYPTO1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x0000001CUL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x0000001DUL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000021UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000022UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000023UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000025UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x00000026UL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000028UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000029UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x0000002AUL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x0000002BUL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002CUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002DUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002EUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000002FUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) /**< Shifted mode CRYPTO1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ + +/** @} End of group EFR32MG12P_SMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h new file mode 100644 index 0000000000..eb458aba92 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h @@ -0,0 +1,1575 @@ +/**************************************************************************//** + * @file efr32mg12p_timer.h + * @brief EFR32MG12P_TIMER register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_TIMER + * @{ + * @brief EFR32MG12P_TIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[8]; /**< Reserved registers */ + TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */ + + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTTIME; /**< DTI Time Control Register */ + __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_TIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IFS */ +#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */ +#define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */ +#define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */ + +/* Bit fields for TIMER IFC */ +#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */ +#define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */ +#define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER ROUTEPEN */ +#define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */ +#define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ + +/* Bit fields for TIMER ROUTELOC0 */ +#define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ + +/* Bit fields for TIMER ROUTELOC2 */ +#define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_CCV */ +#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */ +#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */ + +/* Bit fields for TIMER CC_CCVP */ +#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */ +#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */ + +/* Bit fields for TIMER CC_CCVB */ +#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */ +#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTTIME */ +#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */ +#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */ + +/* Bit fields for TIMER DTFC */ +#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */ +#define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFR32MG12P_TIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h new file mode 100644 index 0000000000..1eb750e4eb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efr32mg12p_timer_cc.h + * @brief EFR32MG12P_TIMER_CC register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief TIMER_CC EFR32MG12P TIMER CC + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< CC Channel Value Register */ + __IM uint32_t CCVP; /**< CC Channel Value Peek Register */ + __IOM uint32_t CCVB; /**< CC Channel Buffer Register */ +} TIMER_CC_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h new file mode 100644 index 0000000000..aaea21f258 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h @@ -0,0 +1,279 @@ +/**************************************************************************//** + * @file efr32mg12p_trng.h + * @brief EFR32MG12P_TRNG register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_TRNG + * @{ + * @brief EFR32MG12P_TRNG Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CONTROL; /**< Main Control Register */ + __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ + __IOM uint32_t KEY0; /**< Key Register 0 */ + __IOM uint32_t KEY1; /**< Key Register 1 */ + __IOM uint32_t KEY2; /**< Key Register 2 */ + __IOM uint32_t KEY3; /**< Key Register 3 */ + __IOM uint32_t TESTDATA; /**< Test Data Register */ + + uint32_t RESERVED1[3]; /**< Reserved for future use **/ + __IOM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ + uint32_t RESERVED2[50]; /**< Reserved for future use **/ + __IM uint32_t FIFO; /**< FIFO Data */ +} TRNG_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_TRNG_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for TRNG CONTROL */ +#define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */ +#define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ +#define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */ +#define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ +#define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */ +#define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */ +#define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */ +#define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */ +#define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */ +#define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */ +#define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */ +#define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ +#define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */ + +/* Bit fields for TRNG FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */ +#define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */ + +/* Bit fields for TRNG FIFODEPTH */ +#define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */ +#define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */ + +/* Bit fields for TRNG KEY0 */ +#define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */ +#define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */ +#define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */ +#define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */ + +/* Bit fields for TRNG KEY1 */ +#define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */ +#define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */ +#define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */ +#define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */ + +/* Bit fields for TRNG KEY2 */ +#define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */ +#define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */ +#define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */ +#define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */ + +/* Bit fields for TRNG KEY3 */ +#define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */ +#define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */ +#define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */ +#define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */ + +/* Bit fields for TRNG TESTDATA */ +#define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */ +#define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */ + +/* Bit fields for TRNG STATUS */ +#define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */ +#define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ +#define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */ +#define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */ +#define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */ +#define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */ +#define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */ +#define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ +#define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */ + +/* Bit fields for TRNG INITWAITVAL */ +#define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */ +#define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */ + +/* Bit fields for TRNG FIFO */ +#define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */ +#define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */ +#define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */ +#define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */ + +/** @} End of group EFR32MG12P_TRNG */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h new file mode 100644 index 0000000000..cdfb85dfbb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h @@ -0,0 +1,1972 @@ +/**************************************************************************//** + * @file efr32mg12p_usart.h + * @brief EFR32MG12P_USART register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_USART + * @{ + * @brief EFR32MG12P_USART Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< USART Input Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */ + __IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */ + __IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ +} USART_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_USART_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IFS */ +#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ +#define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */ +#define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ +#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ +#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ +#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ +#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ +#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ +#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ +#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ +#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ +#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ +#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ +#define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ +#define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ +#define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ +#define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */ + +/* Bit fields for USART IFC */ +#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ +#define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */ +#define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ +#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ +#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ +#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ +#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ +#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ +#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ +#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ +#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ +#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ +#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ +#define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ +#define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ +#define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ +#define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ +#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */ + +/* Bit fields for USART INPUT */ +#define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ +#define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ +#define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ +#define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ + +/* Bit fields for USART ROUTEPEN */ +#define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */ +#define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ +#define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ +#define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ +#define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ +#define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ + +/* Bit fields for USART ROUTELOC0 */ +#define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ + +/* Bit fields for USART ROUTELOC1 */ +#define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ + +/** @} End of group EFR32MG12P_USART */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h new file mode 100644 index 0000000000..002edb3e09 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h @@ -0,0 +1,1539 @@ +/**************************************************************************//** + * @file efr32mg12p_vdac.h + * @brief EFR32MG12P_VDAC register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_VDAC + * @{ + * @brief EFR32MG12P_VDAC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */ + __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */ + __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */ + __IOM uint32_t COMBDATA; /**< Combined Data Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + + uint32_t RESERVED0[27]; /**< Reserved registers */ + VDAC_OPA_TypeDef OPA[3]; /**< OPA Registers */ +} VDAC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_VDAC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for VDAC CTRL */ +#define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */ +#define _VDAC_CTRL_MASK 0x937F0771UL /**< Mask for VDAC_CTRL */ +#define VDAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CTRL_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DIFF_DEFAULT (_VDAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE (0x1UL << 4) /**< Sine Mode */ +#define _VDAC_CTRL_SINEMODE_SHIFT 4 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_MASK 0x10UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE_DEFAULT (_VDAC_CTRL_SINEMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS (0x1UL << 5) /**< PRS Controlled Output Enable */ +#define _VDAC_CTRL_OUTENPRS_SHIFT 5 /**< Shift value for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_MASK 0x20UL /**< Bit mask for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS_DEFAULT (_VDAC_CTRL_OUTENPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST (0x1UL << 6) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CTRL_CH0PRESCRST_SHIFT 6 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_MASK 0x40UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST_DEFAULT (_VDAC_CTRL_CH0PRESCRST_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_MASK 0x700UL /**< Bit mask for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25LN 0x00000000UL /**< Mode 1V25LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5LN 0x00000001UL /**< Mode 2V5LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25 0x00000002UL /**< Mode 1V25 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5 0x00000003UL /**< Mode 2V5 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_VDD 0x00000004UL /**< Mode VDD for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_EXT 0x00000006UL /**< Mode EXT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_DEFAULT (_VDAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25LN (_VDAC_CTRL_REFSEL_1V25LN << 8) /**< Shifted mode 1V25LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5LN (_VDAC_CTRL_REFSEL_2V5LN << 8) /**< Shifted mode 2V5LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25 (_VDAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5 (_VDAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_VDD (_VDAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_EXT (_VDAC_CTRL_REFSEL_EXT << 8) /**< Shifted mode EXT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_SHIFT 16 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_MASK 0x7F0000UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_DEFAULT (_VDAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_NODIVISION (_VDAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_SHIFT 24 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL /**< Mode 8CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL /**< Mode 16CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL /**< Mode 32CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL /**< Mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_DEFAULT (_VDAC_CTRL_REFRESHPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_8CYCLES (_VDAC_CTRL_REFRESHPERIOD_8CYCLES << 24) /**< Shifted mode 8CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_16CYCLES (_VDAC_CTRL_REFRESHPERIOD_16CYCLES << 24) /**< Shifted mode 16CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_32CYCLES (_VDAC_CTRL_REFRESHPERIOD_32CYCLES << 24) /**< Shifted mode 32CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_64CYCLES (_VDAC_CTRL_REFRESHPERIOD_64CYCLES << 24) /**< Shifted mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE (0x1UL << 28) /**< Warm-up Mode */ +#define _VDAC_CTRL_WARMUPMODE_SHIFT 28 /**< Shift value for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL /**< Bit mask for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_DEFAULT (_VDAC_CTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_NORMAL (_VDAC_CTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY (_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY << 28) /**< Shifted mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE (0x1UL << 31) /**< Clock Mode */ +#define _VDAC_CTRL_DACCLKMODE_SHIFT 31 /**< Shift value for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL /**< Bit mask for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_DEFAULT (_VDAC_CTRL_DACCLKMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_SYNC (_VDAC_CTRL_DACCLKMODE_SYNC << 31) /**< Shifted mode SYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_ASYNC (_VDAC_CTRL_DACCLKMODE_ASYNC << 31) /**< Shifted mode ASYNC for VDAC_CTRL */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x0000000CUL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0x7777003FUL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL (0x1UL << 2) /**< Channel 0 Buffer Level */ +#define _VDAC_STATUS_CH0BL_SHIFT 2 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_MASK 0x4UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL_DEFAULT (_VDAC_STATUS_CH0BL_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL (0x1UL << 3) /**< Channel 1 Buffer Level */ +#define _VDAC_STATUS_CH1BL_SHIFT 3 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_MASK 0x8UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL_DEFAULT (_VDAC_STATUS_CH1BL_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warm */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warm */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS (0x1UL << 20) /**< OPA0 Enabled Status */ +#define _VDAC_STATUS_OPA0ENS_SHIFT 20 /**< Shift value for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_MASK 0x100000UL /**< Bit mask for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS_DEFAULT (_VDAC_STATUS_OPA0ENS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS (0x1UL << 21) /**< OPA1 Enabled Status */ +#define _VDAC_STATUS_OPA1ENS_SHIFT 21 /**< Shift value for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_MASK 0x200000UL /**< Bit mask for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS_DEFAULT (_VDAC_STATUS_OPA1ENS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS (0x1UL << 22) /**< OPA2 Enabled Status */ +#define _VDAC_STATUS_OPA2ENS_SHIFT 22 /**< Shift value for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_MASK 0x400000UL /**< Bit mask for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS_DEFAULT (_VDAC_STATUS_OPA2ENS_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM (0x1UL << 24) /**< OPA0 Warm Status */ +#define _VDAC_STATUS_OPA0WARM_SHIFT 24 /**< Shift value for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_MASK 0x1000000UL /**< Bit mask for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM_DEFAULT (_VDAC_STATUS_OPA0WARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM (0x1UL << 25) /**< OPA1 Warm Status */ +#define _VDAC_STATUS_OPA1WARM_SHIFT 25 /**< Shift value for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_MASK 0x2000000UL /**< Bit mask for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM_DEFAULT (_VDAC_STATUS_OPA1WARM_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM (0x1UL << 26) /**< OPA2 Warm Status */ +#define _VDAC_STATUS_OPA2WARM_SHIFT 26 /**< Shift value for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_MASK 0x4000000UL /**< Bit mask for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM_DEFAULT (_VDAC_STATUS_OPA2WARM_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Status */ +#define _VDAC_STATUS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID_DEFAULT (_VDAC_STATUS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Status */ +#define _VDAC_STATUS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID_DEFAULT (_VDAC_STATUS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID (0x1UL << 30) /**< OPA2 Output Valid Status */ +#define _VDAC_STATUS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID_DEFAULT (_VDAC_STATUS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CTRL */ +#define _VDAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH0CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_DEFAULT (_VDAC_CH0CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_CONTINUOUS (_VDAC_CH0CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_DEFAULT (_VDAC_CH0CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SW (_VDAC_CH0CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_PRS (_VDAC_CH0CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_REFRESH (_VDAC_CH0CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWPRS (_VDAC_CH0CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWREFRESH (_VDAC_CH0CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_LESENSE (_VDAC_CH0CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC (0x1UL << 8) /**< Channel 0 PRS Asynchronous Enable */ +#define _VDAC_CH0CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC_DEFAULT (_VDAC_CH0CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_DEFAULT (_VDAC_CH0CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH0 (_VDAC_CH0CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH1 (_VDAC_CH0CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH2 (_VDAC_CH0CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH3 (_VDAC_CH0CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH4 (_VDAC_CH0CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH5 (_VDAC_CH0CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH6 (_VDAC_CH0CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH7 (_VDAC_CH0CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH8 (_VDAC_CH0CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH9 (_VDAC_CH0CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH10 (_VDAC_CH0CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH11 (_VDAC_CH0CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH0CTRL */ + +/* Bit fields for VDAC CH1CTRL */ +#define _VDAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH1CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_DEFAULT (_VDAC_CH1CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_CONTINUOUS (_VDAC_CH1CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_DEFAULT (_VDAC_CH1CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SW (_VDAC_CH1CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_PRS (_VDAC_CH1CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_REFRESH (_VDAC_CH1CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWPRS (_VDAC_CH1CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWREFRESH (_VDAC_CH1CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_LESENSE (_VDAC_CH1CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC (0x1UL << 8) /**< Channel 1 PRS Asynchronous Enable */ +#define _VDAC_CH1CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC_DEFAULT (_VDAC_CH1CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_DEFAULT (_VDAC_CH1CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH0 (_VDAC_CH1CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH1 (_VDAC_CH1CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH2 (_VDAC_CH1CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH3 (_VDAC_CH1CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH4 (_VDAC_CH1CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH5 (_VDAC_CH1CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH6 (_VDAC_CH1CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH7 (_VDAC_CH1CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH8 (_VDAC_CH1CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH9 (_VDAC_CH1CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH10 (_VDAC_CH1CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH11 (_VDAC_CH1CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH1CTRL */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x003F000FUL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 2) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 2 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x4UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 3) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 3 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x8UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN (0x1UL << 16) /**< OPA0 Enable */ +#define _VDAC_CMD_OPA0EN_SHIFT 16 /**< Shift value for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_MASK 0x10000UL /**< Bit mask for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN_DEFAULT (_VDAC_CMD_OPA0EN_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS (0x1UL << 17) /**< OPA0 Disable */ +#define _VDAC_CMD_OPA0DIS_SHIFT 17 /**< Shift value for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_MASK 0x20000UL /**< Bit mask for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS_DEFAULT (_VDAC_CMD_OPA0DIS_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN (0x1UL << 18) /**< OPA1 Enable */ +#define _VDAC_CMD_OPA1EN_SHIFT 18 /**< Shift value for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_MASK 0x40000UL /**< Bit mask for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN_DEFAULT (_VDAC_CMD_OPA1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS (0x1UL << 19) /**< OPA1 Disable */ +#define _VDAC_CMD_OPA1DIS_SHIFT 19 /**< Shift value for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_MASK 0x80000UL /**< Bit mask for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS_DEFAULT (_VDAC_CMD_OPA1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN (0x1UL << 20) /**< OPA2 Enable */ +#define _VDAC_CMD_OPA2EN_SHIFT 20 /**< Shift value for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_MASK 0x100000UL /**< Bit mask for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN_DEFAULT (_VDAC_CMD_OPA2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS (0x1UL << 21) /**< OPA2 Disable */ +#define _VDAC_CMD_OPA2DIS_SHIFT 21 /**< Shift value for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_MASK 0x200000UL /**< Bit mask for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS_DEFAULT (_VDAC_CMD_OPA2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x000000C0UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x707780FFUL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< Channel 0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< Channel 1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 2) /**< Channel 0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 3) /**< Channel 1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL (0x1UL << 6) /**< Channel 0 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL_DEFAULT (_VDAC_IF_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL (0x1UL << 7) /**< Channel 1 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL_DEFAULT (_VDAC_IF_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR (0x1UL << 15) /**< EM2/3 Entry Error Flag */ +#define _VDAC_IF_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR_DEFAULT (_VDAC_IF_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT_DEFAULT (_VDAC_IF_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT_DEFAULT (_VDAC_IF_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT_DEFAULT (_VDAC_IF_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID_DEFAULT (_VDAC_IF_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID_DEFAULT (_VDAC_IF_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID (0x1UL << 30) /**< OPA3 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID_DEFAULT (_VDAC_IF_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IFS */ +#define _VDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFS */ +#define _VDAC_IFS_MASK 0x7077803FUL /**< Mask for VDAC_IFS */ +#define VDAC_IFS_CH0CD (0x1UL << 0) /**< Set CH0CD Interrupt Flag */ +#define _VDAC_IFS_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0CD_DEFAULT (_VDAC_IFS_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD (0x1UL << 1) /**< Set CH1CD Interrupt Flag */ +#define _VDAC_IFS_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD_DEFAULT (_VDAC_IFS_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF (0x1UL << 2) /**< Set CH0OF Interrupt Flag */ +#define _VDAC_IFS_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF_DEFAULT (_VDAC_IFS_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF (0x1UL << 3) /**< Set CH1OF Interrupt Flag */ +#define _VDAC_IFS_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF_DEFAULT (_VDAC_IFS_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF (0x1UL << 4) /**< Set CH0UF Interrupt Flag */ +#define _VDAC_IFS_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF_DEFAULT (_VDAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF (0x1UL << 5) /**< Set CH1UF Interrupt Flag */ +#define _VDAC_IFS_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF_DEFAULT (_VDAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR (0x1UL << 15) /**< Set EM23ERR Interrupt Flag */ +#define _VDAC_IFS_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR_DEFAULT (_VDAC_IFS_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT (0x1UL << 16) /**< Set OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT (0x1UL << 17) /**< Set OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT (0x1UL << 18) /**< Set OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR (0x1UL << 20) /**< Set OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR (0x1UL << 21) /**< Set OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR (0x1UL << 22) /**< Set OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID (0x1UL << 28) /**< Set OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID_DEFAULT (_VDAC_IFS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID (0x1UL << 29) /**< Set OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID_DEFAULT (_VDAC_IFS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID (0x1UL << 30) /**< Set OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID_DEFAULT (_VDAC_IFS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFS */ + +/* Bit fields for VDAC IFC */ +#define _VDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFC */ +#define _VDAC_IFC_MASK 0x7077803FUL /**< Mask for VDAC_IFC */ +#define VDAC_IFC_CH0CD (0x1UL << 0) /**< Clear CH0CD Interrupt Flag */ +#define _VDAC_IFC_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0CD_DEFAULT (_VDAC_IFC_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD (0x1UL << 1) /**< Clear CH1CD Interrupt Flag */ +#define _VDAC_IFC_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD_DEFAULT (_VDAC_IFC_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF (0x1UL << 2) /**< Clear CH0OF Interrupt Flag */ +#define _VDAC_IFC_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF_DEFAULT (_VDAC_IFC_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF (0x1UL << 3) /**< Clear CH1OF Interrupt Flag */ +#define _VDAC_IFC_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF_DEFAULT (_VDAC_IFC_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF (0x1UL << 4) /**< Clear CH0UF Interrupt Flag */ +#define _VDAC_IFC_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF_DEFAULT (_VDAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF (0x1UL << 5) /**< Clear CH1UF Interrupt Flag */ +#define _VDAC_IFC_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF_DEFAULT (_VDAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR (0x1UL << 15) /**< Clear EM23ERR Interrupt Flag */ +#define _VDAC_IFC_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR_DEFAULT (_VDAC_IFC_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT (0x1UL << 16) /**< Clear OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT (0x1UL << 17) /**< Clear OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT (0x1UL << 18) /**< Clear OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR (0x1UL << 20) /**< Clear OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR (0x1UL << 21) /**< Clear OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR (0x1UL << 22) /**< Clear OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID (0x1UL << 28) /**< Clear OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID_DEFAULT (_VDAC_IFC_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID (0x1UL << 29) /**< Clear OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID_DEFAULT (_VDAC_IFC_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID (0x1UL << 30) /**< Clear OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID_DEFAULT (_VDAC_IFC_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFC */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x707780FFUL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0CD Interrupt Enable */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1CD Interrupt Enable */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 2) /**< CH0OF Interrupt Enable */ +#define _VDAC_IEN_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 3) /**< CH1OF Interrupt Enable */ +#define _VDAC_IEN_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 4) /**< CH0UF Interrupt Enable */ +#define _VDAC_IEN_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 5) /**< CH1UF Interrupt Enable */ +#define _VDAC_IEN_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL (0x1UL << 6) /**< CH0BL Interrupt Enable */ +#define _VDAC_IEN_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL_DEFAULT (_VDAC_IEN_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL (0x1UL << 7) /**< CH1BL Interrupt Enable */ +#define _VDAC_IEN_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL_DEFAULT (_VDAC_IEN_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR (0x1UL << 15) /**< EM23ERR Interrupt Enable */ +#define _VDAC_IEN_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR_DEFAULT (_VDAC_IEN_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID (0x1UL << 28) /**< OPA0OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID_DEFAULT (_VDAC_IEN_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID (0x1UL << 29) /**< OPA1OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID_DEFAULT (_VDAC_IEN_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID (0x1UL << 30) /**< OPA2OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID_DEFAULT (_VDAC_IEN_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0DATA */ +#define _VDAC_CH0DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH0DATA */ +#define VDAC_CH0DATA_DATA_DEFAULT (_VDAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0DATA */ + +/* Bit fields for VDAC CH1DATA */ +#define _VDAC_CH1DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH1DATA */ +#define VDAC_CH1DATA_DATA_DEFAULT (_VDAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1DATA */ + +/* Bit fields for VDAC COMBDATA */ +#define _VDAC_COMBDATA_RESETVALUE 0x08000800UL /**< Default value for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH0DATA_DEFAULT (_VDAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH1DATA_DEFAULT (_VDAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ + +/* Bit fields for VDAC CAL */ +#define _VDAC_CAL_RESETVALUE 0x00082004UL /**< Default value for VDAC_CAL */ +#define _VDAC_CAL_MASK 0x000F3F07UL /**< Mask for VDAC_CAL */ +#define _VDAC_CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_OFFSETTRIM_DEFAULT (_VDAC_CAL_OFFSETTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIM_SHIFT 8 /**< Shift value for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL /**< Bit mask for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIM_DEFAULT (_VDAC_CAL_GAINERRTRIM_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIMCH1_SHIFT 16 /**< Shift value for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL /**< Bit mask for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIMCH1_DEFAULT (_VDAC_CAL_GAINERRTRIMCH1_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CAL */ + +/* Bit fields for VDAC OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ + +/* Bit fields for VDAC OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ + +/* Bit fields for VDAC OPA_CTRL */ +#define _VDAC_OPA_CTRL_RESETVALUE 0x0000000EUL /**< Default value for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_MASK 0x00313F1FUL /**< Mask for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx unity gain bandwidth scale. */ +#define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable. */ +#define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx output driving strength. */ +#define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_FULL 0x00000000UL /**< Mode FULL for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_HALF 0x00000001UL /**< Mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_DEFAULT (_VDAC_OPA_CTRL_OUTSCALE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_FULL (_VDAC_OPA_CTRL_OUTSCALE_FULL << 4) /**< Shifted mode FULL for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_HALF (_VDAC_OPA_CTRL_OUTSCALE_HALF << 4) /**< Shifted mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN (0x1UL << 8) /**< OPAx PRS Trigger Enable */ +#define _VDAC_OPA_CTRL_PRSEN_SHIFT 8 /**< Shift value for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_MASK 0x100UL /**< Bit mask for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN_DEFAULT (_VDAC_OPA_CTRL_PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE (0x1UL << 9) /**< OPAx PRS Trigger Mode */ +#define _VDAC_OPA_CTRL_PRSMODE_SHIFT 9 /**< Shift value for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_MASK 0x200UL /**< Bit mask for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_DEFAULT (_VDAC_OPA_CTRL_PRSMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_PULSED (_VDAC_OPA_CTRL_PRSMODE_PULSED << 9) /**< Shifted mode PULSED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_TIMED (_VDAC_OPA_CTRL_PRSMODE_TIMED << 9) /**< Shifted mode TIMED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_SHIFT 10 /**< Shift value for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_MASK 0x3C00UL /**< Bit mask for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_DEFAULT (_VDAC_OPA_CTRL_PRSSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH0 (_VDAC_OPA_CTRL_PRSSEL_PRSCH0 << 10) /**< Shifted mode PRSCH0 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH1 (_VDAC_OPA_CTRL_PRSSEL_PRSCH1 << 10) /**< Shifted mode PRSCH1 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH2 (_VDAC_OPA_CTRL_PRSSEL_PRSCH2 << 10) /**< Shifted mode PRSCH2 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH3 (_VDAC_OPA_CTRL_PRSSEL_PRSCH3 << 10) /**< Shifted mode PRSCH3 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH4 (_VDAC_OPA_CTRL_PRSSEL_PRSCH4 << 10) /**< Shifted mode PRSCH4 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH5 (_VDAC_OPA_CTRL_PRSSEL_PRSCH5 << 10) /**< Shifted mode PRSCH5 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH6 (_VDAC_OPA_CTRL_PRSSEL_PRSCH6 << 10) /**< Shifted mode PRSCH6 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH7 (_VDAC_OPA_CTRL_PRSSEL_PRSCH7 << 10) /**< Shifted mode PRSCH7 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH8 (_VDAC_OPA_CTRL_PRSSEL_PRSCH8 << 10) /**< Shifted mode PRSCH8 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select. */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_WARM 0x00000000UL /**< Mode WARM for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID 0x00000001UL /**< Mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT (_VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_WARM (_VDAC_OPA_CTRL_PRSOUTMODE_WARM << 16) /**< Shifted mode WARM for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID (_VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID << 16) /**< Shifted mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS (0x1UL << 20) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_SHIFT 20 /**< Shift value for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_MASK 0x100000UL /**< Bit mask for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS (0x1UL << 21) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_SHIFT 21 /**< Shift value for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_MASK 0x200000UL /**< Bit mask for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ + +/* Bit fields for VDAC OPA_TIMER */ +#define _VDAC_OPA_TIMER_RESETVALUE 0x00010700UL /**< Default value for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_MASK 0x03FF7F3FUL /**< Mask for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_STARTUPDLY_SHIFT 0 /**< Shift value for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_MASK 0x3FUL /**< Bit mask for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_STARTUPDLY_DEFAULT (_VDAC_OPA_TIMER_STARTUPDLY_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_WARMUPTIME_SHIFT 8 /**< Shift value for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_MASK 0x7F00UL /**< Bit mask for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_WARMUPTIME_DEFAULT (_VDAC_OPA_TIMER_WARMUPTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_SETTLETIME_SHIFT 16 /**< Shift value for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_MASK 0x3FF0000UL /**< Bit mask for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_SETTLETIME_DEFAULT (_VDAC_OPA_TIMER_SETTLETIME_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ + +/* Bit fields for VDAC OPA_MUX */ +#define _VDAC_OPA_MUX_RESETVALUE 0x0016F2F1UL /**< Default value for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_MASK 0x0717FFFFUL /**< Mask for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_SHIFT 0 /**< Shift value for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_MASK 0xFFUL /**< Bit mask for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH2 0x00000021UL /**< Mode APORT1XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH4 0x00000022UL /**< Mode APORT1XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH6 0x00000023UL /**< Mode APORT1XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH8 0x00000024UL /**< Mode APORT1XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH10 0x00000025UL /**< Mode APORT1XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH12 0x00000026UL /**< Mode APORT1XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH14 0x00000027UL /**< Mode APORT1XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH16 0x00000028UL /**< Mode APORT1XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH18 0x00000029UL /**< Mode APORT1XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH20 0x0000002AUL /**< Mode APORT1XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH22 0x0000002BUL /**< Mode APORT1XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH24 0x0000002CUL /**< Mode APORT1XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH26 0x0000002DUL /**< Mode APORT1XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH28 0x0000002EUL /**< Mode APORT1XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH30 0x0000002FUL /**< Mode APORT1XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH1 0x00000040UL /**< Mode APORT2XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH3 0x00000041UL /**< Mode APORT2XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH5 0x00000042UL /**< Mode APORT2XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH7 0x00000043UL /**< Mode APORT2XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH9 0x00000044UL /**< Mode APORT2XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH11 0x00000045UL /**< Mode APORT2XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH13 0x00000046UL /**< Mode APORT2XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH15 0x00000047UL /**< Mode APORT2XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH17 0x00000048UL /**< Mode APORT2XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH19 0x00000049UL /**< Mode APORT2XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH21 0x0000004AUL /**< Mode APORT2XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH23 0x0000004BUL /**< Mode APORT2XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH25 0x0000004CUL /**< Mode APORT2XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH27 0x0000004DUL /**< Mode APORT2XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH29 0x0000004EUL /**< Mode APORT2XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH31 0x0000004FUL /**< Mode APORT2XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH2 0x00000061UL /**< Mode APORT3XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH4 0x00000062UL /**< Mode APORT3XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH6 0x00000063UL /**< Mode APORT3XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH8 0x00000064UL /**< Mode APORT3XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH10 0x00000065UL /**< Mode APORT3XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH12 0x00000066UL /**< Mode APORT3XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH14 0x00000067UL /**< Mode APORT3XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH16 0x00000068UL /**< Mode APORT3XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH18 0x00000069UL /**< Mode APORT3XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH20 0x0000006AUL /**< Mode APORT3XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH22 0x0000006BUL /**< Mode APORT3XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH24 0x0000006CUL /**< Mode APORT3XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH26 0x0000006DUL /**< Mode APORT3XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH28 0x0000006EUL /**< Mode APORT3XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH30 0x0000006FUL /**< Mode APORT3XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH1 0x00000080UL /**< Mode APORT4XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH3 0x00000081UL /**< Mode APORT4XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH5 0x00000082UL /**< Mode APORT4XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH7 0x00000083UL /**< Mode APORT4XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH9 0x00000084UL /**< Mode APORT4XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH11 0x00000085UL /**< Mode APORT4XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH13 0x00000086UL /**< Mode APORT4XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH15 0x00000087UL /**< Mode APORT4XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH17 0x00000088UL /**< Mode APORT4XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH19 0x00000089UL /**< Mode APORT4XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH21 0x0000008AUL /**< Mode APORT4XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH23 0x0000008BUL /**< Mode APORT4XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH25 0x0000008CUL /**< Mode APORT4XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH27 0x0000008DUL /**< Mode APORT4XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH29 0x0000008EUL /**< Mode APORT4XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH31 0x0000008FUL /**< Mode APORT4XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DEFAULT 0x000000F1UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DAC 0x000000F1UL /**< Mode DAC for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_POSPAD 0x000000F2UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPANEXT 0x000000F3UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPATAP 0x000000F4UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH0 (_VDAC_OPA_MUX_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH2 (_VDAC_OPA_MUX_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH4 (_VDAC_OPA_MUX_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH6 (_VDAC_OPA_MUX_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH8 (_VDAC_OPA_MUX_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH10 (_VDAC_OPA_MUX_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH12 (_VDAC_OPA_MUX_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH14 (_VDAC_OPA_MUX_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH16 (_VDAC_OPA_MUX_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH18 (_VDAC_OPA_MUX_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH20 (_VDAC_OPA_MUX_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH22 (_VDAC_OPA_MUX_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH24 (_VDAC_OPA_MUX_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH26 (_VDAC_OPA_MUX_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH28 (_VDAC_OPA_MUX_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH30 (_VDAC_OPA_MUX_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH1 (_VDAC_OPA_MUX_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH3 (_VDAC_OPA_MUX_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH5 (_VDAC_OPA_MUX_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH7 (_VDAC_OPA_MUX_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH9 (_VDAC_OPA_MUX_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH11 (_VDAC_OPA_MUX_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH13 (_VDAC_OPA_MUX_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH15 (_VDAC_OPA_MUX_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH17 (_VDAC_OPA_MUX_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH19 (_VDAC_OPA_MUX_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH21 (_VDAC_OPA_MUX_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH23 (_VDAC_OPA_MUX_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH25 (_VDAC_OPA_MUX_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH27 (_VDAC_OPA_MUX_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH29 (_VDAC_OPA_MUX_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH31 (_VDAC_OPA_MUX_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH0 (_VDAC_OPA_MUX_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH2 (_VDAC_OPA_MUX_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH4 (_VDAC_OPA_MUX_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH6 (_VDAC_OPA_MUX_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH8 (_VDAC_OPA_MUX_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH10 (_VDAC_OPA_MUX_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH12 (_VDAC_OPA_MUX_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH14 (_VDAC_OPA_MUX_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH16 (_VDAC_OPA_MUX_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH18 (_VDAC_OPA_MUX_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH20 (_VDAC_OPA_MUX_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH22 (_VDAC_OPA_MUX_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH24 (_VDAC_OPA_MUX_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH26 (_VDAC_OPA_MUX_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH28 (_VDAC_OPA_MUX_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH30 (_VDAC_OPA_MUX_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH1 (_VDAC_OPA_MUX_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH3 (_VDAC_OPA_MUX_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH5 (_VDAC_OPA_MUX_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH7 (_VDAC_OPA_MUX_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH9 (_VDAC_OPA_MUX_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH11 (_VDAC_OPA_MUX_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH13 (_VDAC_OPA_MUX_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH15 (_VDAC_OPA_MUX_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH17 (_VDAC_OPA_MUX_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH19 (_VDAC_OPA_MUX_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH21 (_VDAC_OPA_MUX_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH23 (_VDAC_OPA_MUX_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH25 (_VDAC_OPA_MUX_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH27 (_VDAC_OPA_MUX_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH29 (_VDAC_OPA_MUX_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH31 (_VDAC_OPA_MUX_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DISABLE (_VDAC_OPA_MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DEFAULT (_VDAC_OPA_MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DAC (_VDAC_OPA_MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_POSPAD (_VDAC_OPA_MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPANEXT (_VDAC_OPA_MUX_POSSEL_OPANEXT << 0) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPATAP (_VDAC_OPA_MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_SHIFT 8 /**< Shift value for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_MASK 0xFF00UL /**< Bit mask for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_UG 0x000000F1UL /**< Mode UG for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DEFAULT 0x000000F2UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_OPATAP 0x000000F2UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_NEGPAD 0x000000F3UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DISABLE (_VDAC_OPA_MUX_NEGSEL_DISABLE << 8) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_UG (_VDAC_OPA_MUX_NEGSEL_UG << 8) /**< Shifted mode UG for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DEFAULT (_VDAC_OPA_MUX_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_OPATAP (_VDAC_OPA_MUX_NEGSEL_OPATAP << 8) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_NEGPAD (_VDAC_OPA_MUX_NEGSEL_NEGPAD << 8) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_SHIFT 16 /**< Shift value for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_MASK 0x70000UL /**< Bit mask for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_OPANEXT 0x00000001UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_COMPAD 0x00000004UL /**< Mode COMPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_CENTER 0x00000005UL /**< Mode CENTER for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_DEFAULT 0x00000006UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_VSS 0x00000006UL /**< Mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DISABLE (_VDAC_OPA_MUX_RESINMUX_DISABLE << 16) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_OPANEXT (_VDAC_OPA_MUX_RESINMUX_OPANEXT << 16) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_NEGPAD (_VDAC_OPA_MUX_RESINMUX_NEGPAD << 16) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_POSPAD (_VDAC_OPA_MUX_RESINMUX_POSPAD << 16) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_COMPAD (_VDAC_OPA_MUX_RESINMUX_COMPAD << 16) /**< Shifted mode COMPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x gain resistor ladder. */ +#define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X_DEFAULT (_VDAC_OPA_MUX_GAIN3X_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_SHIFT 24 /**< Shift value for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_MASK 0x7000000UL /**< Bit mask for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_DEFAULT (_VDAC_OPA_MUX_RESSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES0 (_VDAC_OPA_MUX_RESSEL_RES0 << 24) /**< Shifted mode RES0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES1 (_VDAC_OPA_MUX_RESSEL_RES1 << 24) /**< Shifted mode RES1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES2 (_VDAC_OPA_MUX_RESSEL_RES2 << 24) /**< Shifted mode RES2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES3 (_VDAC_OPA_MUX_RESSEL_RES3 << 24) /**< Shifted mode RES3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES4 (_VDAC_OPA_MUX_RESSEL_RES4 << 24) /**< Shifted mode RES4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES5 (_VDAC_OPA_MUX_RESSEL_RES5 << 24) /**< Shifted mode RES5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES6 (_VDAC_OPA_MUX_RESSEL_RES6 << 24) /**< Shifted mode RES6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES7 (_VDAC_OPA_MUX_RESSEL_RES7 << 24) /**< Shifted mode RES7 for VDAC_OPA_MUX */ + +/* Bit fields for VDAC OPA_OUT */ +#define _VDAC_OPA_OUT_RESETVALUE 0x00000001UL /**< Default value for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_MASK 0x00FF01FFUL /**< Mask for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN (0x1UL << 0) /**< OPAx Main Output Enable */ +#define _VDAC_OPA_OUT_MAINOUTEN_SHIFT 0 /**< Shift value for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_MASK 0x1UL /**< Bit mask for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN_DEFAULT (_VDAC_OPA_OUT_MAINOUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN (0x1UL << 1) /**< OPAx Alternative Output Enable */ +#define _VDAC_OPA_OUT_ALTOUTEN_SHIFT 1 /**< Shift value for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_MASK 0x2UL /**< Bit mask for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN (0x1UL << 2) /**< OPAx Aport Output Enable */ +#define _VDAC_OPA_OUT_APORTOUTEN_SHIFT 2 /**< Shift value for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN_DEFAULT (_VDAC_OPA_OUT_APORTOUTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT (0x1UL << 3) /**< OPAx Main and Alternative Output Short */ +#define _VDAC_OPA_OUT_SHORT_SHIFT 3 /**< Shift value for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_MASK 0x8UL /**< Bit mask for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT_DEFAULT (_VDAC_OPA_OUT_SHORT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_SHIFT 4 /**< Shift value for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_MASK 0x1F0UL /**< Bit mask for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT0 0x00000001UL /**< Mode OUT0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT1 0x00000002UL /**< Mode OUT1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT2 0x00000004UL /**< Mode OUT2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT3 0x00000008UL /**< Mode OUT3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT4 0x00000010UL /**< Mode OUT4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT0 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT0 << 4) /**< Shifted mode OUT0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT1 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT1 << 4) /**< Shifted mode OUT1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT2 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT2 << 4) /**< Shifted mode OUT2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT3 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT3 << 4) /**< Shifted mode OUT3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT4 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT4 << 4) /**< Shifted mode OUT4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_SHIFT 16 /**< Shift value for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_MASK 0xFF0000UL /**< Bit mask for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_DEFAULT (_VDAC_OPA_OUT_APORTOUTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for VDAC_OPA_OUT */ + +/* Bit fields for VDAC OPA_CAL */ +#define _VDAC_OPA_CAL_RESETVALUE 0x000080E7UL /**< Default value for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_MASK 0x7DF6EDEFUL /**< Mask for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM1_SHIFT 0 /**< Shift value for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_MASK 0xFUL /**< Bit mask for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM1_DEFAULT (_VDAC_OPA_CAL_CM1_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM2_SHIFT 5 /**< Shift value for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_MASK 0x1E0UL /**< Bit mask for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM2_DEFAULT (_VDAC_OPA_CAL_CM2_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM3_SHIFT 10 /**< Shift value for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_MASK 0xC00UL /**< Bit mask for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM3_DEFAULT (_VDAC_OPA_CAL_CM3_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM_SHIFT 13 /**< Shift value for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_MASK 0xE000UL /**< Bit mask for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM_DEFAULT (_VDAC_OPA_CAL_GM_DEFAULT << 13) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM3_SHIFT 17 /**< Shift value for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_MASK 0x60000UL /**< Bit mask for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM3_DEFAULT (_VDAC_OPA_CAL_GM3_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETP_SHIFT 20 /**< Shift value for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_MASK 0x1F00000UL /**< Bit mask for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETP_DEFAULT (_VDAC_OPA_CAL_OFFSETP_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETN_SHIFT 26 /**< Shift value for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_MASK 0x7C000000UL /**< Bit mask for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ + +/** @} End of group EFR32MG12P_VDAC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h new file mode 100644 index 0000000000..dcb2ed4e12 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h @@ -0,0 +1,53 @@ +/**************************************************************************//** + * @file efr32mg12p_vdac_opa.h + * @brief EFR32MG12P_VDAC_OPA register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief VDAC_OPA EFR32MG12P VDAC OPA + *****************************************************************************/ +typedef struct +{ + __IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */ + __IOM uint32_t CTRL; /**< Operational Amplifier Control Register */ + __IOM uint32_t TIMER; /**< Operational Amplifier Timer Control Register */ + __IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */ + __IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */ + __IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */ + uint32_t RESERVED0[1]; /**< Reserved future */ +} VDAC_OPA_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h new file mode 100644 index 0000000000..818ec145f5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h @@ -0,0 +1,335 @@ +/**************************************************************************//** + * @file efr32mg12p_wdog.h + * @brief EFR32MG12P_WDOG register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG12P_WDOG + * @{ + * @brief EFR32MG12P_WDOG Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + WDOG_PCH_TypeDef PCH[2]; /**< PCH */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Watchdog Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} WDOG_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFR32MG12P_WDOG_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG CTRL */ +#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ +#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */ +#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */ +#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */ +#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */ +#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */ +#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */ +#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */ +#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */ +#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */ +#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */ +#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/* Bit fields for WDOG PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IFS */ +#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */ +#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */ +#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */ +#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */ +#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */ +#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */ +#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */ +#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */ + +/* Bit fields for WDOG IFC */ +#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */ +#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */ +#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */ +#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */ +#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */ +#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */ +#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */ +#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/** @} End of group EFR32MG12P_WDOG */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h new file mode 100644 index 0000000000..1021582031 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efr32mg12p_wdog_pch.h + * @brief EFR32MG12P_WDOG_PCH register and bit field definitions + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief WDOG_PCH EFR32MG12P WDOG PCH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t PRSCTRL; /**< PRS Control Register */ +} WDOG_PCH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h new file mode 100644 index 0000000000..da56047efc --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file em_device.h + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + * + * + * @endverbatim + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H + +#if defined(EFR32MG12P132F1024GL125) +#include "efr32mg12p132f1024gl125.h" + +#elif defined(EFR32MG12P132F1024GM48) +#include "efr32mg12p132f1024gm48.h" + +#elif defined(EFR32MG12P232F1024GL125) +#include "efr32mg12p232f1024gl125.h" + +#elif defined(EFR32MG12P232F1024GM48) +#include "efr32mg12p232f1024gm48.h" + +#elif defined(EFR32MG12P332F1024GL125) +#include "efr32mg12p332f1024gl125.h" + +#elif defined(EFR32MG12P332F1024GM48) +#include "efr32mg12p332f1024gm48.h" + +#elif defined(EFR32MG12P432F1024GL125) +#include "efr32mg12p432f1024gl125.h" + +#elif defined(EFR32MG12P432F1024GM48) +#include "efr32mg12p432f1024gm48.h" + +#elif defined(EFR32MG12P433F1024GL125) +#include "efr32mg12p433f1024gl125.h" + +#elif defined(EFR32MG12P433F1024GM48) +#include "efr32mg12p433f1024gm48.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif +#endif /* EM_DEVICE_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c new file mode 100644 index 0000000000..03ead32d08 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c @@ -0,0 +1,384 @@ +/***************************************************************************//** + * @file system_efr32mg12p.c + * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** LFRCO frequency, tuned to below frequency during manufacturing. */ +#define EFR32_LFRCO_FREQ (32768UL) +#define EFR32_ULFRCO_FREQ (1000UL) + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* System oscillator frequencies. These frequencies are normally constant */ +/* for a target, but they are made configurable in order to allow run-time */ +/* handling of different boards. The crystal oscillator clocks can be set */ +/* compile time to a non-default value by defining respective EFR_nFXO_FREQ */ +/* values according to board design. By defining the EFR_nFXO_FREQ to 0, */ +/* one indicates that the oscillator is not present, in order to save some */ +/* SW footprint. */ + +#ifndef EFR32_HFRCO_MAX_FREQ +#define EFR32_HFRCO_MAX_FREQ (38000000UL) +#endif + +#ifndef EFR32_HFXO_FREQ +#define EFR32_HFXO_FREQ (38400000UL) +#endif + +#ifndef EFR32_HFRCO_STARTUP_FREQ +#define EFR32_HFRCO_STARTUP_FREQ (19000000UL) +#endif + + +/* Do not define variable if HF crystal oscillator not present */ +#if (EFR32_HFXO_FREQ > 0UL) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System HFXO clock. */ +static uint32_t SystemHFXOClock = EFR32_HFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +#ifndef EFR32_LFXO_FREQ +#define EFR32_LFXO_FREQ (EFR32_LFRCO_FREQ) +#endif +/* Do not define variable if LF crystal oscillator not present */ +#if (EFR32_LFXO_FREQ > 0UL) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System LFXO clock. */ +static uint32_t SystemLFXOClock = 32768UL; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock; + + +/** + * @brief + * System HFRCO frequency + * + * @note + * This is an EFR32 proprietary variable, not part of the CMSIS definition. + * + * @details + * Frequency of the system HFRCO oscillator + */ +uint32_t SystemHfrcoFreq = EFR32_HFRCO_STARTUP_FREQ; + + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current core clock frequency. + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is an EFR32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemCoreClockGet(void) +{ + uint32_t ret; + uint32_t presc; + + ret = SystemHFClockGet(); + presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >> + _CMU_HFCOREPRESC_PRESC_SHIFT; + ret /= (presc + 1); + + /* Keep CMSIS system clock variable up-to-date */ + SystemCoreClock = ret; + + return ret; +} + + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is an EFR32 proprietary function, not part of the CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return (EFR32_HFRCO_MAX_FREQ > EFR32_HFXO_FREQ ? \ + EFR32_HFRCO_MAX_FREQ : EFR32_HFXO_FREQ); +} + + +/***************************************************************************//** + * @brief + * Get the current HFCLK frequency. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * The current HFCLK frequency in Hz. + ******************************************************************************/ +uint32_t SystemHFClockGet(void) +{ + uint32_t ret; + + switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) + { + case CMU_HFCLKSTATUS_SELECTED_LFXO: +#if (EFR32_LFXO_FREQ > 0) + ret = SystemLFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + case CMU_HFCLKSTATUS_SELECTED_LFRCO: + ret = EFR32_LFRCO_FREQ; + break; + + case CMU_HFCLKSTATUS_SELECTED_HFXO: +#if (EFR32_HFXO_FREQ > 0) + ret = SystemHFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ + ret = SystemHfrcoFreq; + break; + } + + return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT)); +} + + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * HFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFR32_HFXO_FREQ > 0) + return SystemHFXOClock; +#else + return 0; +#endif +} + + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFR32_HFXO_FREQ > 0) + SystemHFXOClock = freq; + + /* Update core clock frequency if HFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO) + { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} + + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Set floating point coprosessor access mode. */ + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif +} + + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + /* Currently we assume that this frequency is properly tuned during */ + /* manufacturing and is not changed after reset. If future requirements */ + /* for re-tuning by user, we can add support for that. */ + return EFR32_LFRCO_FREQ; +} + + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + /* The ULFRCO frequency is not tuned, and can be very inaccurate */ + return EFR32_ULFRCO_FREQ; +} + + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFR32_LFXO_FREQ > 0) + return SystemLFXOClock; +#else + return 0; +#endif +} + + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFR proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFR_LFXO_FREQ > 0) + SystemLFXOClock = freq; + + /* Update core clock frequency if LFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO) + { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h new file mode 100644 index 0000000000..c41e3a00c9 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h @@ -0,0 +1,154 @@ +/***************************************************************************//** + * @file system_efr32mg12p.h + * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. + * @version 5.1.1 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFR32_H +#define SYSTEM_EFR32_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void EMU_IRQHandler(void); +void FRC_PRI_IRQHandler(void); +void WDOG0_IRQHandler(void); +void WDOG1_IRQHandler(void); +void FRC_IRQHandler(void); +void MODEM_IRQHandler(void); +void RAC_SEQ_IRQHandler(void); +void RAC_RSM_IRQHandler(void); +void BUFC_IRQHandler(void); +void LDMA_IRQHandler(void); +void GPIO_EVEN_IRQHandler(void); +void TIMER0_IRQHandler(void); +void USART0_RX_IRQHandler(void); +void USART0_TX_IRQHandler(void); +void ACMP0_IRQHandler(void); +void ADC0_IRQHandler(void); +void IDAC0_IRQHandler(void); +void I2C0_IRQHandler(void); +void GPIO_ODD_IRQHandler(void); +void TIMER1_IRQHandler(void); +void USART1_RX_IRQHandler(void); +void USART1_TX_IRQHandler(void); +void LEUART0_IRQHandler(void); +void PCNT0_IRQHandler(void); +void CMU_IRQHandler(void); +void MSC_IRQHandler(void); +void CRYPTO0_IRQHandler(void); +void LETIMER0_IRQHandler(void); +void AGC_IRQHandler(void); +void PROTIMER_IRQHandler(void); +void RTCC_IRQHandler(void); +void SYNTH_IRQHandler(void); +void CRYOTIMER_IRQHandler(void); +void RFSENSE_IRQHandler(void); +void FPUEH_IRQHandler(void); +void SMU_IRQHandler(void); +void WTIMER0_IRQHandler(void); +void WTIMER1_IRQHandler(void); +void PCNT1_IRQHandler(void); +void PCNT2_IRQHandler(void); +void USART2_RX_IRQHandler(void); +void USART2_TX_IRQHandler(void); +void I2C1_IRQHandler(void); +void USART3_RX_IRQHandler(void); +void USART3_TX_IRQHandler(void); +void VDAC0_IRQHandler(void); +void CSEN_IRQHandler(void); +void LESENSE_IRQHandler(void); +void CRYPTO1_IRQHandler(void); +void TRNG0_IRQHandler(void); +void SYSCFG_IRQHandler(void); + +uint32_t SystemCoreClockGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EFR CMU + * API, this variable will be kept updated. This function is only provided + * for CMSIS compliance and if a user modifies the the core clock outside + * the CMU API. + *****************************************************************************/ +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemCoreClockGet(); +} + +uint32_t SystemMaxCoreClockGet(void); + +void SystemInit(void); +uint32_t SystemHFClockGet(void); + +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); + +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFR32_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h index dd6847ac57..e03eac196b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h @@ -36,8 +36,11 @@ PD0 = 3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, \ PE0 = 4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, \ PF0 = 5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, \ - PG0 = 5 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \ - PH0 = 5 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \ + PG0 = 6 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \ + PH0 = 7 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \ + PI0 = 7 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \ + PJ0 = 7 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \ + PK0 = 7 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \ NC = (int) 0xFFFFFFFF #ifdef __cplusplus diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c index 78391c9c6f..5a216c000d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c @@ -21,10 +21,10 @@ // Default to a ping-pong buffer pool with a size of 128 (127 MTU + 1 length) bytes per buffer #ifndef BUFFER_POOL_SIZE -#define BUFFER_POOL_SIZE 2 +#define BUFFER_POOL_SIZE 8 #endif #ifndef MAX_BUFFER_SIZE -#define MAX_BUFFER_SIZE 128 +#define MAX_BUFFER_SIZE 150 #endif #define INVALID_BUFFER_OBJ ((void*)0xFFFFFFFF) diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.c b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.c new file mode 100644 index 0000000000..7ad3edf01b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.c @@ -0,0 +1,133 @@ +/***************************************************************************//** + * @brief RAIL Configuration + * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************/ +//============================================================================= +// +// WARNING: Auto-Generated Radio Config - DO NOT EDIT +// +//============================================================================= +#include + +const uint32_t ieee802154_config_base[] = { + 0x01011FF4UL, 0x00000000UL, + 0x00010004UL, 0x00157001UL, + 0x00010008UL, 0x0000007FUL, + 0x00010018UL, 0x00000000UL, + 0x0001001CUL, 0x00000000UL, + 0x00010028UL, 0x00000000UL, + 0x0001002CUL, 0x00000000UL, + 0x00010030UL, 0x00000000UL, + 0x00010034UL, 0x00000000UL, + 0x0001003CUL, 0x00000000UL, + 0x00010040UL, 0x000007A0UL, + 0x00010048UL, 0x00000000UL, + 0x00010054UL, 0x00000000UL, + 0x00010058UL, 0x00000000UL, + 0x000100A0UL, 0x00004000UL, + 0x000100A4UL, 0x00004CFFUL, + 0x000100A8UL, 0x00004100UL, + 0x000100ACUL, 0x00004DFFUL, + 0x00012000UL, 0x00000704UL, + 0x00012010UL, 0x00000000UL, + 0x00012018UL, 0x00008408UL, + 0x00013008UL, 0x0100AC37UL, + 0x0001302CUL, 0x01F50AAAUL, + 0x00013030UL, 0x00104911UL, + 0x00013034UL, 0x00000001UL, + 0x0001303CUL, 0x00010AABUL, + 0x00013040UL, 0x00000000UL, + 0x000140A0UL, 0x0F00277AUL, + 0x000140B8UL, 0x00A3C000UL, + 0x000140F4UL, 0x00001020UL, + 0x00014134UL, 0x00000880UL, + 0x00014138UL, 0x000087E6UL, + 0x00014140UL, 0x0088006DUL, + 0x00014144UL, 0x4D52E6C0UL, + 0x00014160UL, 0x00000000UL, + 0x00014164UL, 0x00000000UL, + 0x00014168UL, 0x00000006UL, + 0x0001416CUL, 0x00000006UL, + 0x00016014UL, 0x00000010UL, + 0x00016018UL, 0x0413F920UL, + 0x0001601CUL, 0x0052C007UL, + 0x00016020UL, 0x000000C8UL, + 0x00016024UL, 0x00000000UL, + 0x00016028UL, 0x03000000UL, + 0x0001602CUL, 0x00000000UL, + 0x00016030UL, 0x00000000UL, + 0x00016050UL, 0x00FF0264UL, + 0x00016054UL, 0x00000841UL, + 0x00016058UL, 0x00000001UL, + 0x0001605CUL, 0x000807B0UL, + 0x00016060UL, 0x000000A7UL, + 0x00016064UL, 0x00000000UL, + 0x00016078UL, 0x08A00141UL, + 0x0001607CUL, 0x744AC39BUL, + 0x00016080UL, 0x000003F0UL, + 0x00016084UL, 0x00000000UL, + 0x00016088UL, 0x00000000UL, + 0x0001608CUL, 0x30100101UL, + 0x00016090UL, 0x7F7F7050UL, + 0x00016094UL, 0x00000000UL, + 0x00016098UL, 0x00000000UL, + 0x0001609CUL, 0x00000000UL, + 0x000160A0UL, 0x00000000UL, + 0x000160A4UL, 0x00000000UL, + 0x000160E4UL, 0x8BD70080UL, + 0x000160E8UL, 0x00000000UL, + 0x000160ECUL, 0x07830464UL, + 0x000160F0UL, 0x3AC81388UL, + 0x000160F4UL, 0x0006209CUL, + 0x000160F8UL, 0x00206100UL, + 0x000160FCUL, 0x208556B7UL, + 0x00016104UL, 0x00124887UL, + 0x00016108UL, 0x00003020UL, + 0x0001610CUL, 0x0000BB88UL, + 0x00016120UL, 0x00001003UL, + 0x00017014UL, 0x000270FAUL, + 0x00017018UL, 0x00001800UL, + 0x0001701CUL, 0x850A0000UL, + 0x00017020UL, 0x00000000UL, + 0x00017024UL, 0x00000082UL, + 0x00017028UL, 0x01800000UL, + 0x00017048UL, 0x00003D3CUL, + 0x0001704CUL, 0x000019BCUL, + 0x00017070UL, 0x00210103UL, + 0x00017074UL, 0x0008300BUL, + 0x00017078UL, 0x0049E006UL, + 0xFFFFFFFFUL, +}; + +const uint32_t ieee802154_config_base_min[] = { + 0x00013030UL, 0x00104911UL, + 0x0001303CUL, 0x00010AABUL, + 0x000140B8UL, 0x00A3C000UL, + 0x00014144UL, 0x4D52E6C0UL, + 0x00016054UL, 0x00000841UL, + 0x00016058UL, 0x00000001UL, + 0x00016078UL, 0x08A00141UL, + 0x000160E4UL, 0x8BD70080UL, + 0x00016104UL, 0x00124887UL, + 0x00016120UL, 0x00001003UL, + 0xFFFFFFFFUL, +}; + +const uint32_t ieee802154_config_2415MHz_min[] = { + 0xFFFFFFFFUL, +}; + +const uint32_t ieee802154_config_2420MHz_min[] = { + 0x00013030UL, 0x00104924UL, + 0x0001303CUL, 0x00003555UL, + 0x000140B8UL, 0x0093C000UL, + 0x00014144UL, 0x4D52E6C1UL, + 0x00016054UL, 0x00000441UL, + 0x00016058UL, 0x00000009UL, + 0x00016078UL, 0x04600141UL, + 0x000160E4UL, 0xCC4D087FUL, + 0x00016104UL, 0x0012491FUL, + 0x00016120UL, 0x00000000UL, + 0xFFFFFFFFUL, +}; + diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.h new file mode 100644 index 0000000000..c6ba7e610f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.h @@ -0,0 +1,18 @@ + +/***************************************************************************//** + * @file ieee802154_config.h + * @brief IEEE802154 Configuration + * @copyright Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************/ + +#ifndef __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__ +#define __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__ + +#include + +extern const uint32_t ieee802154_config_base[]; +extern const uint32_t ieee802154_config_base_min[]; +extern const uint32_t ieee802154_config_2415MHz_min[]; +extern const uint32_t ieee802154_config_2420MHz_min[]; + +#endif // __IEEE802154_EFR32XG12_CONFIGURATOR_OUT_H__ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12.a new file mode 100644 index 0000000000000000000000000000000000000000..57c1427a22d4a3df9b17055128a588c66677b85c GIT binary patch literal 193280 zcmeFa3w%`9c`v&5%;O6j~1|%+O1uPp(#z>9*FHz{5UsC?bEn8w^!J5GJZ7N z|F<4{ue~(FcGLFUoL?4ft^Ix9e|_uyUVBZ=+E_Z?|H+ao{ch8+`kJe*xn^ZU!y3Oo z$VK{JzrSJS)z@Cl`Q0UqS^vV=%GdHgp9nJ6`2K&+)4hkW-q3&D^F_qtf9LZ@6O3Kx zIo!n9g`TILXYALHod(vdHufL>)S)`$dsd%emU5fF|xs zZr_)~XjfxXq$?5|NcN;-*#v8Dk2JP+L77CSa`mVeH#E6wfAyl^ZEw?Tt;% zTe?~|H+IEi1Do4o*?!j6*tKP6HnlU`Hhf1SP0F{o#Y8rdjB~g2^<@xs$iP_{?Clv8 z0Lhuc5Q#Ju$dzpx?oGIycVyGaR3g(j)Y~zTj3+WuD+jkGZchwIhKY*|4-O6wp|Hg5 zfJW29gC7FMwQfmelY`0K335EejZ~_oj10u4*vM37V_Rh1P^@Qw>jKe~%qXfY5!=y} z$R^_1;q->&_Wt&rLp-z^yLI>u$qmP{8m2uqnCeUpCMZu3Mj~D5rsOIG6fHv<>D)P# zkniCb5;rk`P{<+xeZ1PVwQuQc-n6dWphO+Eg}gbispbrVJA`J1*{t?Nh61USts97? zGKpRayu<9=vbB>qX}30wP3?xQ!{+noE6tHe9u+pzr9g6OBI1o}Bno zwF$mk5mEvTb96YpJ(0Zu37n9MIuf_>21JB3(%RxuCySmCqC-w*vWawa`ZhFG1AGt? zZI5)dwIe~=uit>SX&{ki#L~$2#zj+9 z5lVu&f=!I@E{r1@Z;vGhczZ68og?9$eSK)h(B!!}q8U`Y#`un@K%1#!+qVgzNW;$l zbn}o>twb_cTrxDoBeKE?Kij8-OmV3Cx-l;QM=)kd^08QJVrV-?1#WB`#*HWkMmi|n z7fhsSgmyCImA8+GV2D(i1|ozsq9T9{aWowpq|rq-Jv`8q$i&kE)r{UxC4g3J(=xrL zb1ce(?@pk4I=PEVv@V^-P=i-0si-M2INZzgd&^M!NQRFs*CB~^x$5k+D0hR<6vxof z?T|QbQ0K^o;elQZ8(lz~>jr-+K8&~|&^EZx4%-dy9JwKu9;B|($ry*{Bt<(qip~)? zjwS*qAX5bZP5~1SN?abb=keU(>7I)ryy@EEI#}V4BXOdI5iSPi7>|TwJA3&oO4Li6 z-?3}3XLz8U=2wOU-IvCOXYCyw%@PC;BJB~X2Q-gsk9Mx>=)@3M%!q7~Pl*&o^Qu^H za#)o6od^p}E~FGi3!~c$0J!eR9i1b}1!rK;ornz@Or0D~IaFAV8>N>Z*A1q!yHLI3 zr~q42=+P3;n$57DM7nc08ynzNsWs7;B~HhVq^Mhp!6Ce=Xf7~dP$3i%g*TWNI?=?i zfWkrE*v!;$dJ31vPdL^+r;wl{Pa@?LG!5b*liE7gZSGjt)sYy&z!}N~sdZzD)szqo zm_pFxSIJO?+WWR-;xyZ}nKoy`Zr0uziFDk!8T}!5rYMZUItCJnlp}8&&SY7G)HoLA5~9P8~I5#uj0lySL>4(!bIUqCJ#c8;LLVX4IBREb z%IR@_msl}GYpvsz5}E^TNDQPf#?L3#Cova*T|h(yQrFB|UnB65e!C%XK@+z%W`_rp z@m5p>ml9q^n=vzSaWU-?_^m@!bzHK}5mi}rA5dj(PY&Yjv?x!&2riqc9H0T=a0v}C| zBzi9h;3G0x@73LlMyav47cEXEnjFCVkye~^h)nGZV(itQ3!->*FNoj`n(nzBzY98Z z#o_{icZtv#G$#^?w%AZ}Z$3dsKSmtV+kEoY;i2u*i1V>U7@OCvTel{-vf--LE|oHk zr;*yJJB^%1zcgIJx}KhPl8r5fDO{9NlA?#6DqA;_LKSc)30LJTNb33`u_08JWZy2# zH5t}pP=Mm7zUWG}cV%eZ*Udwh*4&CkR(p^u7_#=rTEH<=Dx%;fdUkH7UXypRwBnUc zVuZ(Kq9%z-AT)_-2o-wa?Fb?+N9YIzN&qe13K=Ddi$MAa3Bh!N2BrycsG@MSuCl2| z!6gXqGD72$+M@%6%Oy~a-Bh3KVv#2lysG8lBQ8>V9-+G$P4&>-5(ov9pp=F8IWf%6Uc<8JZcOkxTDPA$S-E4W?UrvZT8` zxMi$V6zOIvnXyVdhamp79+_ z%y(&*#?Aut=V|QoC21l|vq4H41QrVh`Pi5Xy0r2}QA`k3j$!df&NfLEf(w%Jai^x; zHEox$2nP4gUYQIDoD*MWf)l*FU@B0uGF^)(K=8$wHIM^5GZZoG%_HL zEh^dMW3N6BN(_MV2wVf8JaT;ilt+xRKA6nJcVbYk6=zof;dNwqINggSR;+AI30z}5 zo=9bRubDUGT+)Vp8{QN1Ja^Pn;iJ4tVvHw7TwQTKpzd0^dS!6ahTUE0!1GEQu9{xj z6U!u~aY!N=h44UP<))q#-x3ok15U#fj$C1)vI==qA}JP`INiDqGaBA2($e+~NF?4w z^GJqU*WJ*MwJq8lCN8?pu0&sY)yk3W4J*5Dha}yTT)D}K?^SDfm_HELa5WOAVGX6w zO8mKMHT@yp)xi&=z)qYG@Q9~WUQEM>4785>cLmx}aN$6^aYjnZ@+2~z4{Q5GmeM=5 z_WJNa%4w#{yU_MN8Yb|ugb-0D#P@%>SavDvMzE)c!Vd_B1Eh3nhff0ZhUiA7j0H$U zeUzM)^C<#X|EWYegC5oHt$CMB)s&Yq3Xsha!L>=-36MtTOwPb{_sz89)rDcYj5XFs z=xCCnWDCk&YW)=GNDqcUyqTkf*_p9Z${bS3X849=wx7Y!vzuo@bYe`Z`9`|| z#K7!`CkUab!nq)d<$(AIz)mCdPU z%HV3r>n@RtAX+z#`RIz_D@%CusEtw5eO>*r0g`A;r*juw4s8q$r@Jt%wN+4e>bP}x zuG2b-JCiP3QExJ~eF)o9$+*pOLPD&P*v^rz)BuH1L{EI%a@93Ke88fA)zT0QUVSxq zE3djneA?pgF1d4EYt*tVri{hvnL{yFS;Qp;tGQLrDp(mSYaW^IIqvXYQ+e*##G%Sl(Q)J5)u z4(0Bu+@0q=Yc8%oaMaUMc?%}Mg^C%`L?p8xqT&cBdbJz77xr*gwt7V3`!TUIl9zM*Dv^tQ&ce^b+V)>8|t z|67BBi95XuBY&CzA{d$22;Ikm-yA#0o{ww{6g;$Y20ne}2K zRC8lD_`v}D3P2b633>48*C*~mnjjBYusB5NvM73Sv>>{V$N12DKc6Ukk4?s_FFF;8 zUJ<=E8svP>a?fcBMaj5Vz7>q~P)(fY8vRkyYk9n^kQL!;sM$#KIjoA8hy`qYB=RwT z{rb&Y{hhk@CJHQ%bT7FY{?wR(x>!FH8#A3JwmaK&G* zOUjs+d2}&ouR;6ROc%$;)2Q0!`Rq4(@v;H~Utr)141A%1FXVVpCka|;;EN1=5yzL= zC{d{u>18tv{0xD&lWm5Aa@z~EJHBqp%Vx2;(#0jPEzr90a_tVsD@zl3=f_jdd~6MD zhb~}SCB2r*3t3Fk^Eh3^MkQSdN9BmmeV~=0ct4DX^lipdj?f>1tqe~W)riJfU6$4L zvPj1boskVIR;%OvI6a6i>%Z=+0_Oy%I%O$8U=U--j$JrfIJhCYZ42MarlAg6X2v`h z<10njC6_YxS7a|@td#5;#_-h^D_O`G)teGjU#dza3mBs`Euq4?BC~5S8|#6cO$)nU zy`hd}*$O&8$yW4aGHeAgR^<7nLi^%kT8#4*feXS1c`MK)xVRYY(E(Vbzxz9kd_eh) z#T1c9vlZ!KiogmxYgfdvKb*js!xdZP6kl%wd5*S*1XoKYAGMD2i#`8fq%0qIa`|Ag-jB0V(z|e7>p#2I2Tj40qIu6B&mkR||xGxzv zsz>t_2)4p~0q@jmgz%7g7EKz(i`oTheF#VN5j?uTCqPpjRz~UjQ!sRW&qE)TchX0E zrSI?YuIqaR1l4(ERDS#|7`ndKpsyZ0(nqbC(l?HG(x=>Affs7iluEIAV;AT?Ik`h0GZ zMop2(L>op$lNen!HAE&@#|hYFffKn64ZVIEk1)J(% zR4!4Up|^ScsE?{`APha!Ca=ds`baOCXYu4~%i6%#+p>?t(T8cvM&NHZ+$uwUks(_& z5u9XMFplAs${;-yJ{4ZQEn5vos~}TG=}V^RbH5MYmR)nr>JQzP{S@OY7`rXI5~C__ zz5mRQUS|`Yic1z$Y^>OAE%lsk+x7aBsr4Sb-Mi};-n>g^pFXwg0ldv@*|w_<_KcPX zc7F{U6XRX=;cUhl%=CgCg@7{gaXKci7AU*@cXCz|JGyLtPyTW^_vdoXL^Y-1MHyE0? zUa@Iu>kGNEhCufVxm<9`=6H7|`Ed7Rx4zo_*gzom)<8V=*l^vJhhzVk8x6i1`^)5y za`%h|dd}p0!FbOLxypuz@wd9+Rs8ig1mZ8`>Kfws+t%=K{2y~q1YeDRYe%5>v1GjW zA9H(y5BE|Uj`P1P;7|MwcxQ5<;H-@_$3Ka;H~J$JA@3XA<$E4WmU}#tsh+@ODqazJ zEXHTtG~XtZg553OS#hXr%*W@~Gg}ty2(gOE(M9u))>YM2`Z?GCq?%)wJ?)RO8s5YC z%P1c)cb~cO{v`Uuin6i$V}I~AYwzeUZmpO|4Zq80>V+*+Bm!AzFTL8A`_#L$Yf>Y z{+{TWcqddcqTb z>^abLQ!+d`>bWV#0)LI%{8qAaV_Zp~ve(~fln(8L*^fjGjb*0o+HCFQ4acRp{up8G1roNPYsLmcK6&5lso zp&i=tg+oOM@0y3a_uU))dbGg5WrEFI|FiQu5l62tdgh4t!N1S3hZY=eiH5PB<{h`9 z^tOhF@X_!SM+>69b0tWPCyqWG{mpvssq5;0{Gu=V>QBCPuE6(q=hhWMSLU@NKRdz} zd+wiku3+XZ>k9tob<1nd{Pnp|!T)n);dr3%=g&WWSom_?vU`sDv1XUwH_w9)gr7RP zIO@6AT5Wxjbe{Q1eYD^ZTBxsj>VG~q3oC(G4Lr^6Xa0(4Nz~#k&MK?}Vo>&blz!~@ zh_Y%#tA!l#TjP{A-a`{luNfl*J+&>htyTRfwKX^4Z_e-E`1StlV=wmK*E2tPU+;~{ z)4g9$-nV^0^O@xLa-*#B)_t-0o3`EB-~GU?DErnK{H?Yscc4yM+wix}dH{dhtTQ{l zmwSR$4m=d!HgIq3z`*x%d;RkV&kQJEmk!Xn?$X{@(H?}nuXeAI{TT zwMJ3;Q2tTwi+Q-~5BpjwlaXrgsnH|FPg9(zzdUr;_#EW%`r1vt=%dMf(fgtYc)nT7 z3ZrwP-cyy&d6yNwc+oh8L8QstanW{%s|!y(o%09Vqs_833OP@&)sH60#pr_A8$}ii zV2w9TG`sw(;VnP=#qGsMzZhP2v=F5^UhO+2^fjF=Y~rh|zscH)Lq#I3>x)knHUHL^ zzP$Tyzr^nI@Z3`Q@#&oJJ<;F)iY~wMu^y@#H~(4l6dKD4<6|XwDODs!lC&aui$>e8 zc%gX=;T==R@s2(<(iR9WM$K+~F~`$bRT#%5(O#h4_!5qp;#Iq5C-N|Ylnt2XdXN(g-m4LKHVHREM|L+f&u27WQe-)o~5+i&#Z#VV&ey)NhYdK*QnppNmfC4AmT9LiD)w7Uc^ zalm-i_kUrjk~U`rR*SN`rEQ zJ}v1-IX#noR?;UqJ!{JT!#BWJrVKBSD*`sr$MKN=Yw?t$KAwTC49QmH&cEox~TG7yKMmd>F=Klay#82JXL}%6L$TGi5Nqvlub3oX6l0M<=767)lALTZwsjGap z8r(1C+W8U!e%ky4E}IfT#nu@A!bBA0-<^*(drS(XEWpc!2QK zHkE8)Y=rDK(bjm-pdFKPAMrcH{y<45V}7FHp4!9`Y_w8uRdR#at0=jdv1(K_vZ>7= zyH(mZNqa=vkHaSasV!It9QOyCFZHDF(_%fb1fA?^qTA)Z~0w!$f>O?>0<1g(xxT3k{Cm4Anc&Dsj8E|Jl%R_x*(o=h>v(un?UKq zaY#36Q%aI@zqF6>-h^-~iH`=biR>Q6Hj*7@3{l{CKv~Il#_lE?>B;rAFvi2xFVcbH z_3vD-HZGELHaS(vHm;E~0Vuidd*;M8tL>VZ4)_T$lj*){Zi2nhfIli zr@G8e4-B;>rhD*It73}sG$+$Q_#XWVcc1l3Z*Q;#D7vWHydJ^g^_XmBsJxS@!9zGN z5inHWbwe^TG|DT+^FcVO$ELri#hf~D6NVo0kLs1`b;Um3D-#)zS`knw?jYk=! z?;sdD?s?FUDiCaiqxk9Z__pRR%^a1#hw-lK+XLbxc*-b!-vL9{_Z0N`!J~AUg-7Z8 z?|9esHKBm41y32J@9)6S^}V9$qnW4D_pf-@^^H!W@2sKkedwd~rSQ$gqx5;8OxO1m z^wmMGj0)dH25ua3iMKS5}n29=&GhdlvfYr9Qu=@81l4Pe32VLm8ERa}iKL?e_E}aDD}Xt#Gq|)AM%{ z{;KjEkT{~38Twv_J{sF7qx97q`re1W4FFNP&`e#W%N9f59(Y1+tTIYpi=nRxjh{;A z%K=vU;=oZjReS#^2#UWl>iu@kUt zp5`pgwc7dg4?34k^JAET)!eGbibN5^n)k2dsTGx86qWyowO|x`&8Si;SakMQH)^d{ z`cG+vYQYVaKdtE7@9V%PoT|fD<2_#; z#`MrthyM`thpEF~hw|S5RvGe(4B2{kUIG0O9;&nSOjn0#tb-%7wo&?0?keom;Whcs z!>w7fY9*>V%m<%`+aQ*a?K=E%%y=tX7L1gQRklVR8>zqSe_nz;QXlrCyCQ*!&*Fr? zui=N--*)I~(7w6%uPF%J``%k`%~+F9yFD{JZ!&>6=)@YRE6QPA~M$$)m5((T7t3wG-cyI(;>@ zlcDhOoR7XTv31Uw5>7w#&V=4N;Qtl)I)tYV=NY~%-~9+1eQn}*=_x?EdzMy-b znhMV_M0@UItR8#Ke$V*X!*ipH{8sIkL)OQ>hTVD=_e|bdUKJ^AxuQFCwy})TZ1rI} z2SF(qnq;Bi)3uTcK5f+$N5_A{LbF3EEo%^7YiZfooYO`1-ZR1%HeTef-gs%t+0VwJj}+i;kxG7kwt++C@C);IsQhZ;#k$OBi2eQ7&;p+n{k-@qUUFZHwcycH*pdf$FGQ*;G=0rS{< z6B7leygUagk5V{fc?>kkU19%XO8 zn>zfCCx|*QK`tws=Wm?Ze|LQVIa2mGeS0(amFg1Tj<5W@THamqo;znS>9rWhwb9JzS+H(=kjg_jDu{H4YgZd$l`>>XdQvS}%Dr2O=% z{skMWTdP8afz|I+lWi;5u9c15QtX@j#XO{KMIchqP2ro_ zvgYt}IfnXnXZgIy@f>R`9DgoXY15UBI5m-eDMoFND!)FQQNq*h+gNcc+L?GokH~W+ z7jYDrdU#xUn|5X&wGkAZ87<*{@fF$=IOTh1 zPwm7U)UYS;RoW9}p8gVq_6a}7b{B^#nuBAfb5Div1o8M!<3s|UHaum=-zo|`^Hx## zwIe^Q`rcdK8qd4dxvB+!{g$`F^RD-;o9D8LIn4V;tity$o4`S_vLNLTbY{jDZCZ+! z#TWIRvX+(}U3uB#m$C8Ry{z;}D^ST#7T`3(Dmo)@=)E^5nj(+C_p`}f>v7bas>9Z* z_Trn5y!(?mOFgf!rPfRT>nC#p3q1YNt9|T#>vt*TMd_fw;Wx`N@knniX`%Y``snBp z&moi&n6k0iIAh&bXJ-&~$(Sy3e$ew}TavSP$5$g4}2I5%oQB0Lw zSSQ*0zgTqFr894R`n~gqM(-@xxbpn@?C8bbvskmeess*b{0Po7jW%0*{~Bw*qo>)# zam@G77_NSt=6x;f>=^n{=s16#Yh{b>+BUZ}{O`568>*UPO2H!jXEmmFNz4`q44Es0FD_EoM zU@usI^=AkNcJy95N#|U@&F=jhnuiUr!_aX#i?Ar<7@Xlnt?;!~e@L?)dVfjD7z6(ewXw{@nR@&f~NSnP17- zgct*g9Qlu#PpGl3(COpjNE#o~#M6TjC9UuG3L*Z|2-7h%zi_)RTF@t{XZ_;>OQ3@U$Z67%x_c-1t(C5804X`;A`c+dnsc7RS?i zfH1Sv3%BX)i5owMKUX@q26ttGMl)V?18)5_9N%PPYV0?9@v?w{4{*Gb>H!14*uXF5 z_%$|avHeCbbk@Wjp36DjsYRC?_$3B@3CGvls3rCrz0g?`xBe?QzRgBmVZRCdQUkw~ z<40}OQu|HdmmB!y9KY5^(W;$eyjZPrhi3)HJLN~nsm&5b$Q^yO+T|E8X7Fx(K_k3D z2aGo_c1cwUr8d&yyQU7ri{8iaoA|5jHTN<&ut4j^i`^qPel=gGB+P6)ma)6!Wmg&a ztJo)`LTZ^U$aUl8U%@&YFIFEqILlmJa@3RGt3tkAGaUd-;2bSG>&8+5;mp2_#+ zDJ?c|c_~A;jc|xH?Q*o2Ka})-E}z5x#YLC#Zw3iZWvU$iDnSr^HK*sX>m)tE>5J^M zJVM_kY*5OnPL(5f?sU-$*nUY<8(og};TtY`5&JVqQ=3_i`u%;-%22s_LCXDjFGqb= zXL+bh(OH{!q?~$+a@5CSBqpg?#_1(&zNAI^UBQ+}dM}qRWosz$r6K=ly_wvH@RXx8 z+~A^Du!MonO1Vgnplhv`^f4^*@a4W(D(;-=!8hQb#g#w3fXG`%Qgp#kus1xYXzdrR zwhYLh@}l3Z+VbmP7c+j~Eb^cF>tga`le$?SIiUXr*?-25jpg|UAHGiW`(q+__U{0Q zMPc=GWP);jO-PIw?6aS-QTvb*sR?l$2+;izrZX{uKg zerj__UJ9H1osLhqk~<{6Tj~d0EZx(7UCHO zcqiPF`_GHBMJ1mV`=}*5r28~ux08HS#uM&7(lWn&GR4(^IA=4awgxU4zq8EwtwC`@ z1a6EU614g5-yO8sd4GLysz-FGoM`26f<~T=foHf{ZOX3^PIYYmE}=_gx)s;%^XhJg zjz{tXey7l-lsj<$Vxdbu#ZzisTnMcN=25k?3DKSUdxkEj&MzC9Y;{MQi?6pd>X!_s z1<0nzCD(od(Zz4qehbk~N@C{8L4_6Ru18i$Tp4b+Q!Wp+UrcoP?#7DW0s#X}f+h+dC} z#y5p{$UK6F+D~Paz6cn)z9vl{xmEh&c-QqE0-aA^m!Yp!(?{V_`q2Ek^wD^>6OS?~ zd}Jl)j{IJ|3m-9}Ru?Or!5PL*Gv|eYAR_ z^!?1x_Yee>zseAf%$tV3_n}Xf16o~C`siE_pmsffVj6ujfYZ}&9x_4cqtzFsZ?U28 z6a=l1D?>OkHHN-r(5K2(4dhB+)X-O5fHFx6q*409hQ8IBz5uXFU!S3GE%ebGQ5mJL z$I!P{(?_d2O5f)UeIwA9uU*@1=xfsSU9Rc7-_W-g`j)A{NgR>iG;oK2>&$~YVc_W8 z+ul65V@CK|5x#ohs65kZkc#h%hQ58!7lK?Fm45%Pfjc=3?hV7=Ec{jFidKP?zeT9m zdO0n|IDWtKRN{#A0;iYLd!R1}KE;DgPFQAWl0 z69(=O3Nx(@DWlwP1&+$O^7j}BrGv2QJtg%~n8^^1)_jzqAkec5IQ&m3{*{RQHHwfJ zBF*z>Pa$2tqynMgNT&)bx$B3%5d8ia-V=Bzd}VkjjWy@&QF!n*&7n%7l>AvSbqLKq zf3{|tvnvfN#dV<{;_OOJEXozEMp&q{uEDxm`n$BNdwq5FQEO#YcV)lYgY~vl_E#RZ z)>L-0Cwsmt_IcNg&Dk`k)vBrIyWX=~0^Q<`cJ^^XVIt(AU444SXZqQM#W)Z8JhVF*yD4@c1`cS%XvbaQZ@j_0YZ0plD=VXdZv~2<^lW6~o{be; z-+t&ih==)#T9!Q7R{KEwrar5-pv5=-Q0=zfoBC{@q4Qqg9>C*mDSmR>4mMsnz)F?> z5s&xW7bD)cYXh`Px&?P&c(J2wwQTDX{?eTU1<@}Yx-VMFQ%N|ISb@96eId*yB+Xa^$XqsF5{ak6|4|2@^a;`Gy{n~t-K=9npcT^wr9(W+^d9dir z%en5dxo3;#lpeKeXz!QRSl3WEyl)iwe5VVq^qgW#UOrtk-f&oikzC_yGQQ_+`3v~H z1lS{|JiH!vr37*6z^dG)=S5l2n(Vfi=b1DL6O7Td;9~hfZ%)Y_E^5#66}du`A8}wJ5K*i*!wmmGYZXDU>{(E0pGG zG*&#<=hBFHtie9_MLbt#Y&bp?n8@Mgk6eZC+zbzH{#ZpfbR6%y0x4-61Td{OlA@He9MM-NAFOVH?=Xd_SIyVm{u%-*o)#k#8X z(SQ93?gIHdFPFdG|3*LKbB(E}7or_m>SJiEK>Ob`MxKX97}bjkiuS+tF&T|^X)TZ3 zlN%3ca!>u5Flg5`L;K-w_r)9^vN6=7JBIed-S`qCd?gMTZ?qro#?Rz{ctyDmVr0-!)F`#*+%&FkqzmeW8mj-ypx`kTaKaqb9Z>kINonV9GAqR zyB^&5xrTlk-8hE!+uitbj(6ti=6-vHfv@2BQ?|+q`;A^`|J|+sA|pH)TxrIO-9R_~ zVvcvpt9y5m_UqmFOE|vC)=4u~$IyPg8$X}pol;3NQpeC;5pH}H$A@ePeL3S8x+}ts zujcrm4RKPISYFgFH-4cJ9;$tgq5XX~evyHv8Kz_C?g=;E&+*G_h~Ivr7rJ}GjjuK2 z0Ye_(`r2$%z<#3_FZL7N`WAD%Q)(9*_{$9ZWd{B-17C08>kWLpfxp7QU%~NCu3TZ@ zml^nF9PgADCnd?D7yFy;_%1i_Q}_Sf_!UO@X=djbFT2vvf2AYD8}0wQ^*JSvfL_*M z$Q!tSPJL-G^sO@J)i?*|7|O@1@KFEIiihsrh`?5cPa<0ATg0j)9prdFTPkURuVtT7%oCCp;aSH1-bF8G|KxJNg8f|5)RUK^{8nHxOz{zPkX{7cp*yJZt{tO(w(hnj>a3#2XQG@&)l&0n__K$?CUyY-yFl?s! z<#5}fxO7}2afgIWIltd%v&3B*Ho0yfmdfDQE9sX`ZD!||t)2V_Bl%tF`PlR`I8*ub zrMb-_kQsU#9hW$6YKoA3N?rk+ap@uwSN=|S?>9TfchLmEFQIz&IG zJXJ}%l87Cs_WVkem-uPZWX7$C|B#cd#SSFG;7(WUjJX*=h`2j}Y7KWr`uOj=*?Pdj z?;Ew^7yaa2DY``DzuY_PY{m~djnMV;Vpr0oR{W%*+pS($;0=_CA0u<4z@$w*o!Oje zjAxU#YpI#%suA14)=cNHTka@RKRiJ7+A|>953;GA(b)mw)0qLPw{+HkMs_75@?MQB zW8anZUyzMq^fS_?zK-_bY2-!tPr_cfORUWi&Gn6nwPE7ZjDYydB#venCD^m);kZqN zt0W`u{Yc6CMc|&}zBJY5{v*8P|3ZX|`v-m0GnOFS|GvF{y;*U#PPNv>VcMxLZrI>o z3EDhSY~*Hd`{?W#?%+ZI!UtKqqT0=x0JAVxJj`FwFSxHDQcLirTS=EzXz zG)j5gIL(vcYDy!O-?1!rQ!@(gMFTaRyQxJ}Z?L9@hPP$fSp-!g;L2{i3|H}-@`P74X}|Pw16s47F^5{MSdDkxV2Hv^4gL}iLlSOG9LdOBj)&T%55mzH z&GfetJY}fOBSUQ^?GuFXkSRsuO!}|JLl}C9j^fevwSu09M;WCr42G_6o~Dn|K~ z@4CKj(4;62Ra|_`v$HUj`HQlj}4rE8r&}o+#290FO^Z@qdU3q-!6YNhsc+2 z(fbc72u$8_W4BP{t&*Z^%fUoD`0h7wdx6WB zeq#piAaEPtk1{GAhmG*vg7A?(3ZH(~K%H4u_4hUCD^<#1D}CmkKb_TR%7Zia{Ii?zBg9x7=AWCPlRrtPa=zH7|KIiX6I6ToegGP0Dv4;%hI1%Ii$ zk-q_nBl?)(Z#5L;D_4~7db+FzE?+qvH~c-J`Fok>FE!x0z75mpd*9IatfsGC(^qZi zy9N6EkSha{n@ZsH^71_Nsd9e>5QL+2S!L+k13|uWu-U-vn+BIOaQlJFmwr@^^mKU? zI2ykzgXG}mj||+AX>iXPxTk>Ipp?M|$<0aN^mO?t(uL{=l^3iG*y-}B)The24`({4 z?@@-rPR~z)!~c}xXMp=Kd;agk-}m8A8PY|DY!!E+zYTqU1ekOV;GuX>cqtB=bN1|P z^z9l$=}YzR>e`u24rJt}zrE*wZT>y~l~=7gH@BRe)c(q>+m!4|N)duf>_u;o5d-wBi`ImZ5dEW?^;dfD1PW*&!Zx^T%j#7x@ z67i-)tQjlddwafUCI6)j+HDlO#LGCXc45~%of`8r-5Z{Js(3LAV0YE`y|>uKO=lzc zd6jI)`ozme8qfM_-aL&fX+QqPPl}`XrkXP3*L#B~kK!J6UMlz>RqF(Y?%HwhZlQ2% zhV};Ca@G1P_eF+W6hNhd_6FVVsfBY4{jQ~3PPND}v{&es>n#%1w^Bo{x0EEG#fyTY zaTXr~5lt!aVSe{Az;U9E)7?YYNt$+P%8`CsC5`3-bRpZ}qKoWtFZDsRR{jksujTX% zehC7#4b%tF+W2YM%1|+WO%bq(e$${W)v!o;xk394`byBm3gY2Aflh;@u2LQt9!_Pt zQi*iet;xQ=UCg=r7mH~0Q;!=G_$~OxOgx#?W&Mfx4t#T!%<3+}$!sQ(ZO-sTunjkM zZS8Ds?dTF*zV_ERFrXT%$khzpsB`7=>lU*m~L?w&G{e=suFnr|S z^1M(s$l16ZxQLb+rcBS0{4zUZ@{3*BlON*FByFB=hft-q>E4yB;!6gzJpRhA4J<>p zQ{7XoD9tOVoG7El8Joe-aZRA9y-`NtZUsZf^?;^!NEwCuA{aU@3pyX}4-Fi-qoS&e z(svRJUEjAs*D4Tfg_|&N{{WiWIb{^?r(oz~z=P<9sC}A?hgy7UtEuOpxx4Of4m`ps zqx3D7I5qsL2TeMZQSbD7c%)D1SOy~Bn6e3c=t?Q~4}$(MV@mo>)lTw28ud!H3M+}8 z2V)cr$`dsgEyKGxrtCz(qe=NS;3sw1R)r1*hj%4>rk`W$Jg=(6oG2dH|BR<* zZg)}bP1|FiSsL}#lIx|>!f|VP$?1zWUesLx2@CjYYxazPhGetHJ1-v>ph_T;l)UK=4IHNd(WMXT^W^bC^Qs4i|@P@;) zcu1G_vo|^zonE!pFwYEr9&X0Qy2(2u<+xQ1H=ji+>EtP$spAHEpf^W%vcdQ^J~vFL z=eF~knE3fpl+F;z#o4;ldht$YM8&%gH=gYevZYTQ^|s)oE5_RB`a={xI%7z`7MEK8 zK6fwN(EG2)uvG7SxH(fd;YWS~$nhc{ev+{I-x29&CtdhQ`2de5ny08j(1L#>8&? zECcTzano=w z@40BCA2rBoG@Tj3Aez4EW&AB1+u6HexBQikHtaf2e|%wmTl1E#w&V~wrt!10Q?2jZ zPdVScVg+v$Taq8L~*HjArRBeK<6j9oiU@$@Dxa4yA z+YI%L^$`vG5!fC-)>p{JM_9iLdm;E(Mqwpa$nV7=Z-55fh3GyOe83Zzjz!7|YLc(NY>T?3xl{~%m3o@P9{zSlrg zo1u)-w+;+l-$T$xYqzA2(m?6!#=EX>H3(`mlu`Odz|e7RAgF#Qqi_#`q2q3u26xoJ z^#hmB-~Vag_D-WuwPz}S@0|u$1wN&t%D01{RoKC{-#)&6ga(4fS4PaKd7(~;|WBF_Q#Y_uVkw-OR^>qWpGGs)nYspr!qWL26TO$7~juR zN+46O=~!=aSR0Y6@puD9-D2P^{x$@IS6_X#-@h_=)oQWG`@w6xIV#B78t?D0uYIKN zy68KaLirU;(4UIX7b!K-#ZByO%l{`~@2R<1Mg4s29eiUUzQhRzwne<>_Tr1DV-?7!_Ro(9`^J!@xlL=k;`^Va{j1MtQv=bMKeU zY(AblSk{3%PVe+~^mN=BnFzr49^${?87dAP`{$19cVCV{O%P-CRB>o@Fz(HbmAB$v z&8_kN|Fzx1?*oqp=O9ff1b@LAqR!V;Gg<o?-gzxZD z1t|EvcslVk;i%=r#d47Z%!=V{jBSUA354rJ9gOPjxTWPf-|_w3QHbhnOv`L3cDmjF-lB0g)&JzX0m4&of5aPvGxJny~K6Jdd> z==>=Ez2u{G$EugR^TG#lm$0YBS4;QXQh8@(C||gpm2`M3~YoFGQkVD zctuD*`h{`t(lbX2P8BWnp7Ji*7T$($tt>xW@v`N^H+0*&t47NX+g~_Rcfm%Nd+0kZ z`y0^Wu>v41f7K|(&EvWscJam(?$;guxRtxm(u$V_qQ+j z+L0q~Pu#hrsrbb$lM`v?FL--mC+Qlyt6*HD*hTa`Uw5p)dV%;AErHNX{yp2gi5YWz zr^a>Y3mw++lwvI1eiu``f(dLYar(zPiJztLAzL zHK(Pz`osf(h%=&b0>s3-cB*N?ID zHKJV7`_gD_^t?dce^cJ)%8>Ra6$!>p?LX7$VL-iU`w4b7ven?wW z67PaPs`16U;7@9NdZ%`0e=suP$DPglsVzc&2wuR&i`S>d3SW%8c{1=oxE?pmV})?M zw{AwujLp@f6k31P7mm~)p|{}Oe|QcfEB>Ck+fVzoFx2l^EtU4Y;HJI;(zlr0*H`U5 z;^(e?n}c^f;^?}o9=b@+hjV*Kb30+XrL|4+g<=wU^KWYRhxZ??jaEhP4tsw{{Jlp! z;|CE#(OWpN@@+o!c_&^IpQm_~%bQ+hV+e8GUW5#{(eu=SZj=n5xo*|glRx>e4`|^i9-GVC3}4HF!DGc34TRew z4<4b_QhdpbIw|fOFT~gE-ie^ce}(7h@wZOYc2r9QzgNAys{B8W~&}p{hUru|+(f2JW zK3Wwmi((xY<(9^844;qF9R!uJ12mRID^KkXJ*)=Lh0U+e6kz@%?$>q_N_>Azb03-$ z)Az{e=>#uJ7Otu*S!c$BROs&Fm@u zvkd$!`^z~c=$psIOz|#tuV`%-=ji1AQ6JjU6=KAYg13#A?lz3W4@nAic z@}nM)Ff^-n4E=Vz+rJ7n1~K_ZIp?uYTnIPxeXtvU5&NFRQ=WVHFYE~{{iW}N-S~^` z`*;POcGw+5-v_(#m+OfE^LFEF41A4&4;c7>fe#q?#Rh({fu|J` z$IyM=?(kgh2=PY074McWG4w4l@JkK+QUkx#z%MuO%MJW;1AnD~ztX^8Y2X_Se1joh zX~^~63yS|LL%xdp*J*26Wxvr2-Iwi7FZ%k{F?1icTYe4K=eHsH${6Xp*1%tDBk9G< zK5ocA&hh4QalBK1LIyr; z;KLkGZJsb;^}=m0PM5pWyUE@U`Zf?A$jR*kwyP%ljb6O?qQmVz%JFM#RMdVG`1J;U zJ;yuo$JA9bUYxRZ>)*if&ib;`QVIRd2EN(AH*4A{{2LAYMgzamz_%Fq76ad6;9CuR zE5|$e=d{cs{F@B?CPUw5L%x~o8@Ex^yF12<9RPRwwK+n(dD-=b{CY#)VaPiSd8Z+F zYCZwII8o^KpH3J$#>;LnTWmiNduoW!k;woI}H2|j(5t-4g)`E;0F!-pn)GY@WUMM z)N*|Xh|2G62L3jVueY_{X1~#kmt_om#=vI`{7wVEljEKCXQzR`!@%Fc@zpl!4*QK> zycoT^>-R20KaK7k<7K-I{BA@4ZU>AvFWY0__Zav+2L5vf{&O7fw^4Lj!ZBVpYT!pX z-pQ{~2aGo_yW7Cu&G8`{b+`RSFJ7FOcBju?j(7U6y$1dZT<$Qxz;crCz_!>I91-5U z?288ei;V6CCKJMAL9QDwW>1wm1GL)nqcUOf*_8wE;zoWqejmG3>i2W}J_n39FZ(j1 zGuhlAz!qq?`!7qOu)Me}<&&=P{+5CNEdzg#A-~7o0~P6WkAeRR>vrk?isAk%2L87V z`ERqdbT889w+;MP4g6Qx-4ai2qQ$;y;O{l)`}ln;ib-z%n{-b+q8~Tt?}H{*3Qsxa zhyS-Be_P7CxqLqJQo=|>`brF1{VsSvWOREL-PfxO;jacwUI_W6EMmyj{VY_b%Q4?m z_p=DPhN*jV1sz~tk@^I^m^~zEA9sH_d(0(Y!k%%_OWFT$(aYICyXY(J`&w$bz6OS0 zNaf+DF=jbVU)4zZ7EZ6Szflw6xr(iq@;WZRhTS4*%KviAH!?1LA7{VqqSvx-y4-() z{iUR-4K2rN&EHE}_!nY7a>>K&EzrtP`d@^Eq4ZyiryS$$<&vg)RgTkQEs`c|ImXNV zF1ne0!9{Omf9RrH*hxu?@U*fYNxF{f+r&HtGW`&Ua;zTB0<8@Bx!j|$fC22Y@T#jEuIv{D0UY+cSq-kZV9OKC!NSfBW$}xWYCrMwy z=^NQQk`8hDW_B?aZYcc_E#N=RmP%U0w~JlxqPy9Mi;l4`yXYSF`z|`p9&^#X><5w- z>w9vnkeMi!MF292vcgc6L7hUq*>@63)hdoSzm4?DU6BUJ6qWpZ0 zEta$h-zZxv=~iIM(VuRVG`TIOFO0;2lMlE&Nt|U1Z;eK7z(+dt6C>G3q$jzJw9JAQ6zBNWkrhEYAbhabrj4x=me?{$#2>aeFd@XwYRY z3Vs_u$vBu8jHh-nSQ%U9{9KVc2(F`=>RzPAF71~^gzoml_GBiTNF&9OV*@?0_zo6r zk94)QNj!inNalOlt{SlU?h%#GuvS~{bl0gHAQ1XI1 zJk*!mE|Y{9;a%B8rt$Vza)4hqC6Jvm$C1PmsyO1?E`_qQSqIuo9oxQ5ln0Tbo&D)% zTudetPm1KJOqUE_rlBnHJD?+ov>EVHb@-YLf#Z>};b7I6UYBJE#si-M2INZw%(w3q2kqoYQi}$Y^ z%BFX@5@TAFI%zB-+Z2z-2HXyb;|6t(Y#1Ks#cyc2fHv0+{#1MzaY>-jaiJZy8}3|P zM;U|Pj#59TqqTwuCScd!mNsbSb`M0nb z3;Bu0B$~!Mbno2NWM5?QeOdZemg~Djd|6Tgo4bQe-#`+5nY3v<46DYq5VI8;84JgYCgbm#>rkF7E0e z``>Uy1=(JUuiH@izE3ok&3HPlmH7>u(re*$vRs5@xEm~f*1ZILo}OWg)dENK8q$OG zBC`cVdpf?4QA}~3$%+XP(-z$?w3%wIqO-LrjHv@IjFJ9Sgc#hL zd}m-kMIr{mCOh9q-ofM<)4PS*nA;KL8Rxr&#)#h$8e@M)kZ%^?NU4D6!+%FIWoDq~ z054ZES@`{qPGK~LpN>KSQL_W;Z>N)q(fCxUJqph6*cMCoTEOzoDf9>_fE)zLnT3wf z<`-tj)Q~e@u#}8O9@DwYA74siZC zdZ7@`^kgc+n5awzhEVY6pW_Ka#;gf_RD7NcfaCIG?X^DRC2NDOV(#XsB4>Z_2PW2|zj zAM&+VJGn>cVYhL@xbK6`7mso9^>le$OBYPB?R3F3)fGN+ zM|rM{iu-vmbbTkZe47iIN@q;VUHVEvt1>}4Rl3xIuj_kO(^sMCGw&0o``{>ll~MY( z82*y}e7IW;+-lG%r3|);Zy)%2_@39ocZtMNKHg*Kdjxbh_{u1K`wV@rKwmvTR8HsP zQRzqS@!w7}A0pTfS{bG9Aw!=J^WYFbqz_YNTi;(9`Ua-a_ZNn~Cg=-FeRQH*h3^GJ z-}BH{3b`^We5Vb4S?HtmqVUm)Z>8@YL*Mu``shr9o*#QOeKndsy2lt$JNsM(8m|Z_M82a{W`YzY>B@KOa)*)Yh zBn*8AHGNAoeRmuB=1rrI&UEPM_lTwsuXg@EWa#rxqmS;_*7bc`(?=)VReAXfLm&NS zZ@&0`*U1f1T#Dcnr(_3}r*?R$$-23zGd{l>8# z-=`2h)gG*pII1s~8~W%TVm-df-+-a-H7&k$!d|7{Iz!(X&~=b2qr%r{==&-3QF}`D z_ZmD(U$3E$?i{9YE2F~KZRmSn3*WT>D}8qv`g{=R>8!%{2L`Tk8XVp0t>?!w;ObQ1 zq`yR}GdQZRY6Fhe6O{qU&C5nSe9N46?UO(dj^h8G;qL$hdcG-rKR5K1YWhN&zDwXh zj|cr$eZKHjfUlRUdC*7WI?A`Ortd04AKjzG_ zL6?ds^1mv4>MWEhSL49dX*g9sZZq`x-~d}awo&>9fz$Ihi~M*1D9Vq`cnC-Nakrtb z66@=f|H>$TzhmHT0uD>*wo$l0G5jq>qpaG4>w#AOs({M-6=&pf6v!f8M}#PJ^?MUV8p^PlKCp;0C6_tu$~W)8IB6xV_Wh zb{M#Ofy>t)Q90M+@yIl|ZyLBKfNN5jA=8=2KLSoKf43k%{NPi0-i}A*$4Nuq`_shZ zgrRSbmcL0&-#;7riV=u>?f5?#`u1w&Z-=Ij%CDX-P1ES3%Bsirpr&t7(|5U{ZxoK& zAXi3}?SP^0apnefzATZ&C{%ec_?P_kS7s)1g|ElZ zR|kEnT-^<%3g2!+UoZ3#P8p?dKX8=(7^ZTQ1y1!D#8B^llm{2$F2oZS@fb%O5Y=!$f;P9V?q--_f`~R``F3@olXTErK&uC^mlBF3**s?6-(Zfc5 zU?kgsz&u6|k0p)3vg{7Bj#G7z;ZOrZ!CS*mz-gOAMYZ06y z2OJ3lS@PPI04IJxqGYp+W3q{iWipG|)&KWZclA`a#)fRp`QLlbNl88R_`dqpySl2n z>MJr+JKu|k_z3^kV3O1EW#Ac+hmp#j)PJVn^K**!BlzZ`Jgs;lO~fh8i&OCVH7Nco z@cb$G2wy0X-jAi=OI2<=z(?5SIsm1Y`aPkDMo%yJP_|Lwo{r9i=66Dg_|Y1lr~^dn zLq0zUzd{K<(nZ>dRtvmI?B#eA=1dSN9TZDik=4W*CGd`tw zb8Bhw!4{G?bsE24j^(#P5(^`_GHDGPA~}=M?n~n&%Z22$1ZC~Rur&@IsNRNSE!k!?D2< zvAovT63?(rt^0Niw2tjK+3MMu*XF7lOAND3ZDZX7ZDU<0+s3yc&QVGaR7eY(;xIp$ zA7@KejO91n6*-=G$n#iafA~~nJUp-Cc%t8PSI2n!S1*oMpXyj2nzzH-cGr&et&ir(?Hq5J*XeC_)o<#25#c}9IlkRdzkl1Q&hc%K z2_=V*u&1Y;%!_mnL*7^va-4?Cvml8Lvc7x=JBp_!V$~>#gW=P=y3eWA-RH8aPq%;V z;%E(Iv4lbz>OfiBCY`plrRsQ2*WJ$Fp8)y@$#5e-X$`I;8#+r+q8r+%E*Me`K}#GV7vCMe zMrUAo;Kpx}tt65&q^vFpT|KcRl6`c3aDM!yq5RKBWKFLP96C{NA;Ay`UhcFe7vn1^4YT0>Nb0^+J>B@d<;Pr+8eK5ozcKh zDj5y*cq4eAR~7EBPH)&d(mfgSd(b*Y*=NtrVmZABLav4!Q6HpuLJSfuD;vsl#1^y% zvVQo`*(}CoE`cH>mif3uEUgqge&{1iQB+06o;^IO&4x~DiaMY_$wxvTZMR4WvU3^M zls%1jNInvMAE?8lDeVH2$VZdLVg7X8v>wznMz%jm$2yIe#*}vy-$N)tc z+AeHvC3o1lf9|i zF_Z(IhrOfQsZM93KK_Spr<~5lpNqhBMe!+xot&P+la2Znu+UpA_IoXM`gUrEUwY^~ z=|PMA8x}i#%ar;55qA9Z?=ab@ucvjpmfk$}JKat-I~(;a4Fg!>r<#?G`ZQM>&{BF< z=yokW#q4(7PJX=1$JXg~;`P$kPBDn(CmMU(`*ug0x^N_JBL=ptw2gIjw6t`#x8Q2A z=v9CLJ1qL2o&8Ige@%nIqx^`61;wW3Yqe&Z1b@98$^zC+=v?%NQz{E+i zk9+`3^KIGmXx_;u_WJ3WBz7mYw8u7f_k}yT-^TWBeGD!ec6Mlol7s_i;b)9`iLUuT z*@zs|vJq)YW--rwxacR#y637|T!;K%1+PZ}M4sE`y z-ibX8gtHDZpGm(#o4ctvTrfcPCdjcT9gF^hq@&}eHyVWlBc~$@oKF3Zx|%UR>APE ztf|s_R2OJVktMl=yJh0YfL9IFc2Z6UZp5Jo)pp zY|?q-jW@dS%*Nwk^MVBt*95J<+4--cnFFQY%B^d6`RA>hbSlMxb(73ib)G52mv-^S z9NWc{tt4yxh3Zu!x6fzSWR(oQvrqk>)%MrsW2MyZI)i%&Rz`ibSjqGyj`;%6x$-@k zIFgC@UX8mvXE!|3!InU}`ZesDfvE z59)}vMy&FiKPb&aUmg7Y5vACv-!pN|&@J~4I+d|Kk$L>ycjjxGn0?-%YO9Wr`(Jip zEO#;^t6+RjWO?wh>bz5Xs~;W-$U?qsZt*s#MfS<-?CV2ifr8NN33ZV=VPC{1 zT#G0sR4Z2290-&77jM(e43y?U>OiTyQ75!~#xKe~ab)nk%Vt|@58Qgv7c9C{xn=>+ z*#*HYtfCZsUT`w^`MDYL0($AzRvh zW60M|p=Jkj>Xk}X9BS`hO{@G1Lff~wBW%eBV`}mCT`k*`B34}7J`XG3OWKti$p`A- zHOcbxvkM*`SAVAe(W_pq$<2MWX4TDz@1NFp(WhO0eV5*Yw7yI4r{p`2dc>q6`S<4a zIR{_QqW+NlkoE3>%Zjx7K5Kg zdr6gQ{WnP^yqW8_gqO_EWX#B4s`XpqpClqz$&w^%s`Xpqr?hK|MpsEi>$gNtsywz? zw@}Sc_~!kYi{4GI}(J$RSoLix7G zV*jGWPIC#Nh<`{}pp*T3c&L8V;mJmMpU~|TUs@kMtJ^83X+8A!x}DC#(E6txI{81u z>2ugTvOtl4FY*iPh1wwE!z7>uHmtdG!nuYV;$X)-=lNX zw6OMFs{)1fgYL_+D_-n&WGYeDk(-y{#nu$cVn-f}3Zdct3*rrJ| z+f%RA_O+5c7aF#aoDmvJyKm6uYi9{%Y3%eUS)oVA_zlg;>S6^p?ewysS`!~|5^FjGj{HR_K9;Ju;H<6BbeU^0K z{6Xtq#_8HWM6QLULdk12T2<4l)=Yv_$z~GuDln5ERfd^Fy;{s9Xh+PA1d3{eC>Rxk z@%12s(!#VwAmL!}p#pJE(Hj2fg(2#Fs5v|EkV17dDKTXzf-CWfIfa#vXr!*emwG59u&##1q@C)$}4?ScL;F0kfVW)a2l)$TogN)~w@F))i-rX?E zcp=zp@dzdGJ^=?AuMQR;+$eq&FM+okW*P4(*h}#UCGdLSAmc@(_)$9*cz+4AjQ1++ z`|t=Q@aSD3<3(X9gB!(<-b4cL8!*dwn_#Jfn@|Gp@8KZh4Zz}q8{x_8LNCKE;|;@Wu=wFd@uToX{2*@06u+0za1Mbkl)#$}J{ix2LZy07c=Ec?GVoD8h<4NogTNq6 zVZKEV_rv%;Zo#8-UIIhLqi>t|H@*QAU#fMDPB4KKCBLNTJQBKoLlFik`nnI2p?pa1 z{elQrVI*DjHN;HkqbA{z#!=MQP+X}#P~ORSE@aZR0t7T+jPSlBT3;az53 zV`cdb8sn ztaJyT*pxPDOH;0$JFcGZ$9=$QB~5|X6B%B@et(x8v)HuvZ5MK??c@Dx%0~KeN31$g zMynDoWmVd;x5j5p`B#4HBD;M{Fo(={9lhAU_0$g6$iW@Tc}1B$LOaaxalhorOKM5M zNP4DQwM`t{!Ai(|{T*MADEpi0>my$54phdNZ~w&46J<}H#%+(elMefP1`1#(ZbhYN3 zr&U#-uXc?*Tm8@croS89fpgAn>(0$B8@%M$&Mvt=t=)=8{%#6rH)1YpyEb?_!HV)j z%Yr{hunM&pyBd3!wEQ5^R(?7W3H=}u@qZ(ttlZhQq-|lt&d!|BbphLXCG$kWHF`R+ z#p9joe;}{kH9ocG;&=vDl^%IpU3p)dQu>>>?XVG6aGUb@Uv5i3ucrU-9h;gJRBJc4 zsaQ+eyrX(jRX4XBjNIKh`c67~J^#V#>8aj-$OtOFyl6%+FN8bve73{K&QAUnYjXM7 zdORq5+P~+o#$XPL_6`a45OdeieZcGQTp4Fe+2j-bO^t6PGJ3uishRqf?Q5Ysf}3{~ z>mjNuHn)AUvmxlkzD~A}^0J@jBKF`-?Y&(M+%oq4cd#T_GI+_wSEK%J#~TTI)w*-a z;`(!*jWilIyIPN|o2vp2&nqsUX6zf)Op_|m)Q)k|JB5H7AOsefr#QA5sT{{!~% zha`CsnU&a zS`>4|vSLDOC}#c)NXgff#%~Ut_SDtrbc%ukyV*Y$>m@~NDzc(G0h=TTdXI(i5EhxU zk$>_#mfZUB5S`>H(4MGAU>1t#G!7$r8-B9st!TXP_$0h}V@(Yt?bd811D^`hgp{Vk z*uT@-TGJQntPZ#C+#Q9W?rqI|tu+vwOb8^ek598_2+TGR`D|v!%-bM0#o9M?wzo%_ zAx&;gXE=%(HHlhfNw)6ZzE6aAwtpeC%$$$bw8-B^9p@fhe^}S4ei1*7eaZh8 z(rM86hwS4>PV+8X1o}P*LAOp1g}afH(u~reC9{vu2TeuFU6SRhS>?k0qi2np%noD^ zYObbej3z5FmMelI@rf~;m5*qouE8UZcQ40R4nAwRm=dVKl;h2xb{C4lHWRLJ7Qn zILLTo0P(|(@W`F`C>>wXb&=0+!XPj}GR%iRBHu^~J}G)U?u0vzhulROP`GkmMl^b8 z4GE+uG_Hb(+((%&c#ybr!V`262hyeNXAc37_A*d&MVG+SOXWy;B=Q7C_8cng^JLJK zz{6ajFCr!jmeBp+Qn{N21^Mz$pSkipqTCB+7u5IJn=jF`Wx4QzI@Ua(RX0aeY zFn0`Q@8i32aBkzp3pq;Km~FMP^x+YEv8$L(*f4q@yrl3kADitzrk@b=6dzEk4UdoRy2rj74i!2C!ap(L9yQHpk?>v!s%3n}VIbP7#wO2KG6Y2NQiIh&>Zhr+n;oHaF`M83x zF;;%>ymC|3In`Ek?h7TLmfH_czJRecH7_(|Ex#x)xpn?ltfIpCyZ(iw(|lkyZgQuw zxHF)Ak6jU5c_(tcNVzU!qGK8t6yvPT0fgk<_omw}sorYv5alO{@_j|Y(F?dmc&dM%|J*EA-g?%4b!hOCQ`wpByks*t=LIKQ z^W*tPSL{+JZ&&l99=e&{_nKqQiJXS#Fek{5X9w+rPok5bSeFRGr(Lpp@dm%1Y`#r_Tb#Rustt%RZQGfmO84`sV>)``B43p1Tzi>}=ZcL&YNE>8K_#eGpbmFA?a za+L0BCmbl6mkGbbFEIDPjJwQ%gB#i7=|i@LoOYVGlRJ+yFF!hq0|kfCf8N1d86MxC z<{H%Z+Ib($^NIgxa}RoFX-a-e5&z8l$!Rp6K5NF$x8UbX+!X(r_lXmJvV7-T_-EcHZjKL)K9b6Ym0fdu z3N7)WmEWXFb^kcwCv$y4k{KpCzauL;pF{jfRh%@!MCWtN^b!lb)Iv{|Br)1>=Gg3? zzp4xj8@@W4>5B}S=KmVL)<9-z`3fKTlTA}LY1M&T=)Q6)VH&3qZZ>=^HrX9~uR@aU zGVL#>*6>N4zaM%wbK?fnq$2u5c*wsG54Da1x}EYo8*}}yLKlkopT$G`G_I%b>96Yc zT5k7XTaiY8hTD_h)5(+kJ$)Ic&tbTFgX3xG%VXsx`#eVTQvB=b&u3zdo=S%9KeV1d z`YRLv)$H$0_CofLy4}b9FJNa09EvnA%I|`1r}FWlylIamDa~HOt}@w+*+P>YvC;<9 zd?5nM4K*7+v9YFZdBsh*O6$&zbz7UaiM0sLUK8064Y%SNFaEWjv(y_bGZq>&KN^EB zEm;4=Ul))+@pGKU?%IxfB-q{+(N$~l4OO5T`vy2SWIi{CySBI2_u}4_4(uk-qRX!- zYV6pBGd0?|0u!O8bEnDGY>9-sy4pKQ&awtp+p)d58&}4d?mkLI5_=?cn)SLQt21Ij zfvmaXV_WHJrN*x2)^6=WF(YIH!VLXkH#Mc83xIoCyVr(0x|(qBOoHdb!tW`^lMO93MYJ$&$w~t>8kOu=FPfGW$J(f@bgkBynpbL;WJ9yk z^(HsNIobH+n5JxkmuC=_-Na$EB_TQ9SoOP1!%Xcv6?TgDc9}p@a2kM`2y$(&2(?4G z#6@*iiddUA$tQJIURo3Q{hqHBI7klc$5bM zZ#&E~UgKr(S}k~+Bs_|j!265^kH$3pc!VN8Qh$a=j$a6PG*YMZ(u_&qJr1)Rzmu^0 z@CYUF4#Pp_OTeBhn4k;3?_2mh@I-MGiqb;r6+CkM;!^zNeJQ^NpB!!kmRbVPl?eA= zVVCjtN%=?b2jZi!GvHswdj^(g;4YNFbHQE48vtH8m?-~f1}5;9S@8Io4GKV40*}r~ z$#|~gH|&-YpQ_FabW z2@BtsFT-b*3r^>xN<|{{_>q;)(#!c$j&x9YQ97tk5$QN%3D+v8SmcXU-Z#k~PLFj$D@^``qOeFcgMrEk!Er_BvqV_r zAk5o8BHz6qk?*g-M{)SDaKCQB%SD7l+$ny-d{oDS#uf32xRZn6`=QQ9ZHE-?6H4{H zf#kd+Zc&Yku`ht{qkM0uLwWp4L;{{gxTH(YY!rA+=$NT3Q6EonrFuqXB=Q7C=1FJl zddZ`}<5xy+ZQZq7|K?zPZ@}p)Z6lKQTTxzq!wvY-u%f*3Bkxa&r%}ks{YhTTQAaP> zitS50&)EVQ0q0oSl38QQlC-f;ChS34|8zB|6RrlFplNvNf_ zt#!WY&-61qKf>cW!lvRm-@4d;-GZ@MC!ZgpT}3On#ISsP5pY!$PQc~5xntkD=(}z{ zen+n>;nZwUJr!9K2yr?KW>(?l<_wrKDr^%%#?(s}TqO=pae$IrfjE^YE48l^f`{UQ zH03y!rj0q5&KgexXQiS}&^HN>GJ3(~i>~D>y9S>-FdLk6$7d6#w`gj*qG+nW2W#_1 zSU>kh*E-3k#oYsUeSH`>e_GF_x^2gbh^*|q-un$FY6(e2>$zrr2j_ptU=brc&4Jc) z&HOITUuy7+H@@I^Tln3azt-TV(MeL#dakT!y_P<@P`hlzL+eX4t`UmbbQvC^@5MuV zH88a^6w$9WY+4_HDI@16e~>O?I?qe|+jM#zr@Prs=t2=)yHB2X4q^?3%L_5~WatwD zv!k)7!p}g|1&jj_W;X09=xwE`UpJBVxl=kw#}t+o zLhmPiE@M8@v1mv6R7fw~|K9!y5;tN^a&nGmj=o6z<>*GLugE~@|D$Iv|99<;pt2Im zt{av?m&YI>5L|G}!b3dtkX_Vc(L(#-wil030xt*$87~4tCEN&){0h8on5i8JJQ@?1 z!7h}*qxK-<4T2!zN4mh<2eXVv>!x)AOy?u(!+2!8LlT}mcljpx2(KIusW>bYXQ7Bj z&$sc&V~e-p_)*3dhY{}g1elIRR>G8q2+Rk|C>*ITpuUOHOJ+)gJhqsCh2~{K5e_LF zfr_?XFtXsW4d+{$;a2@8(xZR?Kh`onsBF8N3xXq(|oP6G6g?wS8jttnBtQQnGNr#z-d zC{dcX!$IbYz%GwP1Rs`=IiKjK`e9GiPkjpRazFJu*gr}?6+j#B0qjGbz)WUOys2VKi*hbN3#@GHZ>mmcE!3CcdU-w zMKUW^t`3z44|cFePC$-?@(ASjPKKHfh7WdBPqLPS;Zp4Jd8oXM??u7sftqh@!|#Tj zE$eU!N|D^c&fjji1_SZw=X}H*z2oG*snb_ zVqcX0j*G1b9ImC9EO>u!;^%K?2iaq^4+Zie4w58`*$w-{Z)sd1RXM?gjCuD>C z3|}BkJ9&UUH52nTmp`;#%MiRt{UpcM1$oZSBWe*OJut#o%d*CgK}N&6_w2TV)%KBf z@1@zk3Hc57Ah{lFSA1-O;XDK8gO}($gAyFr)&DGdZJ4!vYIQ?tK}W-5yS)7ecclgM z`?<`GD3`MV9x4o>Tt_l!9}Sl_;ST2QRqb^n{gW-Y?(LHQe`>x*9b4Hpt=^HH+Jg!{%5&oTZ_Zy+=cF_N)fiG_k@mGPSrnFxN(~|B%?u8dQj>|HrMGu^ zimIS}^V2Fs(p>S!&x-#~jlD#B6g?aDEz~xJ5Yv@%mw*wk?#vdlU{b-@~v_+Jq8(``{plyG%+4 zxr=aV4lCom0E-`PLJ2(D>m=hfN_f;e3%u81ru1RF$rYWwA$*~P`5icrS>~hmDU>k( z9u6|!f59SX#4F4;xD%g|7a*h>3)6Qxgc&8jq`JZPQO3fZNN)iJpetb{UBrP%Bv-H> z54sP2W|{KEgNO1?q!mV1hN;wPGU!U+ZEx>_$dlHs(a0V?9yaFeD=+sw;D+n90|*~3 zht01oSQ=yDdsy!uB!?}^?|Uc>zPamQSFS%T;7i-GO+8`r(YP^pYA{P3|Aqa!6AOpv zRHrX6e^=RrMzeDc;-Y5`#(X(LS8)kmR|W6pJG&uwYs?$W@5;t5c6H1{fA_AuwKyeU8dqYBiE*yT*XWTocP#6Ar>nsK zZ;ofSxlUBW=i`w9TFsvx9P*U7CPEI+iKShq9BC(Zb{=%9C;TNlw>c+nLb&stwi7pi z{|xy5m(w}63T|(~tpaZI;Wm+W&53fPz&06e{nq)>Zr}JaaGY}3PAn#lj)Ap{kfzrh zo;N78YZ|Vpr&~O(X~@R;a29ioxI+sY@!o4BQS9ncu1L=T1G4wqz`Kie=5Y(=|2+98aJuR^n9kz*_s%f2EzZ&7w5NA451R zDIbvDg;V|4?@*m5+>}b-t&Dhh{;Z5V-dQqq^-x(rO0QHWybYcsuO%3rAYM`6AG9A& zxT>{WoWEmW?UQLXLX6xEa|_H=^B#w}#He>3|Ct?mYjKh!q~#&aC;h>nCtSZMjC}4e zD^mBn0@VfTJD*Kk^nTg}+vI}un}dtqSEow+>;TT7ybpl}`yyBWlqvgi1NLR>#^5$! zd*A*+<2jb`l|&u8rTT_e@S_%^G)| zS6t`cRvusUzHO3CE?~iPEd48qdhWjv{@3pNc_Q8q{~148lW}^J=KuYK|BL6)CjlX2 zJmb8QG5NL~zur0qoQw}LK(o~#o&#y+$|~25%D!*D%^pvGKkecH|J60> ze!KtOa8BMxP9S5b1~LGvopmEMsIzMv&@o>=K5I?GSXUm*Y{P@+nBwy9+jgQW-MwxjWMRrIgPtuZO)m(ra>BfK;A?^YDbdZfbPBH}JT_6CCKO8>yP=4}azyQ$7Ao z+rHf8=Kcn@ZQk}+m%HZRHrwHHI&ktfXjfD3Z_D zU4+z5ZT*1aV0_)hSua;(YvgXHW88_JcK#4imCC`ey&)$;w-V)q&<>f)---H`fycw& zQQCVaPviD^j*%}rBv`)3zdzgfx(vDb0`QGnbX+x%wHa^*t_l?J7^%yP#>^NAjzNB& zNaXnz2J?sVBh{0BRh^)_u>5L%=%&DmfbNH{XsD3psV*zmaVn3_L;UZy+xWY{4%!^Z z!YuIRN0nt6AX>NaiBP$y+!>;wJ?Z-9vhHIC)uHte)GF8 zEs)96V@^xdk{<$VMPRWd1sbO>5IrW&K+$`m@<oOv|we?Od8KPq_&VdKNND1C=~Q6_A`l zan>ZV(pkpOANKJ(t{i~~ryNV*+t_>4y#v*@aaPhAD(TOiP@b;fH07JyLZt~;de)D# zUS1k03DFz)OlSJgz*;t;$t-c`aX>7Nc!u0TrE-AFDlI>Xw>Eflz)RsfjGAue^_JGa z(DtFIyy=~-(5XM9#*O#2yYY3b94f`dp{oOI(TT*~^1E%06N^GBAA>0+C84RedD_u` zxV%)B83D+4Jvxu4>{|V6jBRP!_-l!1g>5nmGEt|-b9p&xyEIC%GJ4wisgV*Mn__+* zZUOvh_r;xiTdQkjLz-?L`%!x4B0V*{Un=m zz4%4kc1FH5oLb(ZZHU1cXZ486`78O|a{Z{6lpfv&kU!%59=VCSOLv+nln=^@5MSDj?H7yo+Cp*>`8MJxOI zy^(v#jYe2JjntmnFiE-|v%iqb4>?E;^ah*N;PxNfhE~!;WxF|iFnkKD;L{cJT2Hs} zZ+&=w{eJp_4X5=!z*_RoQCdqbclp)eyzbN8@Vi~JYpuYE{yr_Z8MVf#ZVqjZZ06q! zMVVI~$qii1Ti@t~bXA$mQnKolTU?9nlUerTVf!g|Z7xno<8<_dQtU^&eK1r5xib&c zl;9L~O=y;_CQ^0IUgWKrS5p;2t>XQI_D;eZqY{{qYs1&EQNJ{IZ!qs@UT9Nj0JkHm z@%(6Yd~=i)ABk@E!=z-Hx+#PY3mWIES}E-m0c^@tv1=bL!K$ zo?Y+cI=P8w-IQNp+!Z4>ujbEq+w*Y(`ZmATzfqf}_zNY*4sQ%)28-hlCTe|Ojk}g8 zrx@Pw4<-V>7PzhP{Ss~$Pd=Df>npzZ!9;`49&CZcXbN8epU4xX%yYzh(zZD3Bs*{4 zV7vGq8G^ygkI;{eJXaHeJNtc_pnTu;2gvns2g+ z{O7CFPkR!!iRF>Z_tpQ(^xt{T;aHQf?^IS|)bE2tsn0O}n{x!KoCnYv1Im6iFfWkD zaW@Uwmi_GreSJZ?JYV%69C1^+eArfSSj&f;BX;hG9Z&;6DAGzp_E&HCt2g;`l_>j_ zB8;fula;t;gqPZ1?~%fQk=u_PNCe8+f!P5!5ET6leA`g@&|;i$SMk+K>sM%mskMoI z-X=yNUx4bn9rb_Rdk@4^KeZHcWxO3|?ILM+2b2J>l_T;m)@*_&ca2`?$L>J1bM!$P z6>D9lWDbKqfyVdz<{zx|yc%UXc`ik23prasB~=hgKkyiq3kQ`Q4m9 zj{@Y%Eeu?zy@6)_49@=}gG*kSrFFeb3x6i(uQT|~Uz6y2ks05^zd=xRC{8Nqlz!S5 zrKx02ke$wQoBd~V{zikJN+YT0EVr3Im-7!AEXk50Cpyb*=EtT!NzvJDGo4C3sp#yr znV!$XD>Yc?V@gtytZOrW0q0+3uoM_3GSFFSGk+oHf7#%o+)FAO^I7>W1%m$&=+&OO$OIu!$bxfPC1zI zmU8}bgKMc_()h2n@Ly}8UuU6T$MNV}iKea-2Cmy!g@wO@^C!!v!ot7O!oQO9C-Z-$ zg@2WWf0czlS#!vvja_fyzutm(qlJDW$4lm~{Dpw#}$e%S9{xzJx(Lh~en8;wm*LE}hTF#&BMb}#R z>n!|r7XCU5f4zmjp7SU3v);nrVBv4z{K@n-Soj+){EeLdkinHqIXT&|o4}mjJ2`)? z!7uMNApRx`f3l=Byk-l%*+A0h8!hyW?BgKN>!%BkYTD^e;eFh~|8X9_WGf}#NoB*y zK683DS@@GJlYH6OW()sj3;*UMIOpGD;ooARf67At6vs=}pHEr%w_5nOa{grbZnf}- zEc_wPpR7M23xC+cAGXk2E%a6kz1>2WcbicDZMV?3TjI0bf)}yyM=bOm7Wxj3m+U`w zSon7uvN)&?DL4sXeuM9{@ON71o$NuK!_NJ8TKIQa_;<0#P5iqo{9VS`O)WlM7XMVs zlgfrK&F1)a)8YYFT70^b%rMzl)WRQSujw2bf7HTHy91KS#$xPWl2$%W{vGTT*XQui zSrd701J&DwMAQ}8Z?@Ri!%j}O;D=lAG&*F6~3X9{TWWrWq0UyszY=aawqIUQT+Z~r_;zc8{^ZjSm@8{ z^m0zmXFs;k&*}6^PA_277WzD!7N0jby^!4iyHFJV9Txj`i~U}U{Vy%{r!DqZV5js` zPoK?v?3Wh$2RfbljBFaeqT&$0kK0Swa;iwWqWF=VMWM*vYO&v^``7Y&A^WO@{&k(c z2!69MUVYg@e^aMZPnr$MJX03B1N$9>qVTV_*sp_~;_t_kjqz)ZZl{?acI>jv7XF<& zo!%kY>^k;23;l0&x>i3c*fSRTF^hd%=hyOcCHr@ieHF7IA{0L@KG(BC-A+AUHg=G# zB7&|cebpBGI*YyCVt>G5KVY%{y~X~##s1G0`@dN1zqi;OPAxrDOxYOE7Q!wR#eb~ow=&v?P5Gzg?``aFbvuQXjT;MJ(Cww%?q{cU`$lfB zV*jPv^SHf+EpTago49=qyG^&}a{F2qHreag=XARkUOoGUZrA#g2KHm!{wnw1$bJU9 zP~_*=7W?}ad+sd3t*u)WTkI7Ud%eZp3OnUbBc5!G=l(*sFX#3q_BGvJ&h5?YySiQL zuRhLxYO-%)zc<-8vpHDeAbgE~3%gdgYx(sl)}Y(9{N2hTx?Rh!5WhE){KFaX3$wo^ zgRY3@h|W*dESt5mADZm#>}}ny;caKM0h#bL{s^0|+kM>s4#wn-P<+p-d>;^`Ns(1Q z|G0L|ookxwYqmDk-L(}*_o~|3aJI2G(9zk4tyEpx?+Ev`MmC0VRXt11SsU&PvuJx4 z_P{pBKhc35v7cVk)yBdyjs())MObY$;m*z$$j?pR&N_DJ*YE@p9V?EbXwS{?2aJaRtVv95N_9j187R882=?wFLrG8y$i%66ujeLkP!qQLUnl z-3HsodN+3C3~g&y-@1En#;ddY(@9zqT!+19mp zM%!aXoV5bAWU#q*H@An|ID^GgE%vu-?y176ifa7>?r!ha!_>FJr{cE6YGVwY0mZhl zy=!}4#8iYLF_g>Zh{`USM~eEL?QtukwZig?=}{TvnAId@UB~OLe-Lk;pIC_^6GcB`3LE=gyA05&JMd@)Xp`Lelxj4zm4?cn5&YG`4z2d z(Y>BuhOQpf%5?w1++Jn64!=OT#ThXFm&D@g}G%{AQrsIBq1 zF|mq}{rlL#3!V7iARYWP=OH_N?^M4DJLx!>(xl@xkiQ=?_LRpz07qCAi!p1(YOh*t*D5e}_=5kHULsCLec(osh4i03lW5ziY)e@i>BMEtd6 zhtBaP^nCh-Ue3SN@uBnlfxD0Rf2HT&zv=EjM;?>=zv%8~b(~-8;r^?hFXuG5eN^5& zU%|)Y3-?v{+^!C5GLJ5_Bjgc)b&1HzhBq;NzYce+-vt-h0AntV*|n?ZQNEPkLX;QRQU3qEbD8pbLh_uXw5*VHlzVXFwJT4cQ?pv9 z*{Qj#v**-YGbh8T`S7;2zQU!Yi`0IMm%kWk^h)x9<+KC*!&p*GuTuw_YFeF|Q_L9k z$@G<(E*Ep_OgS~mj7h3?0@suW+JrQ0xS~4^Q!^!}gsJKBR4O&cjCs_|n2L@- zYdvfxgEU>5Nt`ihn#nSA>XbUJM)S2yqCSLMo=$xjt1+>f8B5cgz*uulksX(tWX*&$ z#^KhU>@t-)^`t9xn)uWyHOa`wj~J{e<(G+?InkG4O7_`&B|3HNOw*_AC`4ntsiU3=cv~!ma?4oQ}=J zFipz1jP#iw7r1lyGG7=tvEBNafxGt3{MMjBiRF6f1x>OYW_)${qors4-zC?O#=t_^ zbpy?F@cE06hq)65k~C(f@h|bvL-qh31rLq0Nj2ih*_+g4;!W)(FJfI1@Ddx7_^1<&r(=F$RC;QiKuR|Y%^ zm-3JDN8ovpAg~(k_ZHy20lQEFZ#MYk^4$cy0Wc9B%{2vHr3H`f9Hl-%D3O1(H%Z2u z1YQ%E2+xN{;N5M(+X6glKSGK4(VeeyIwIin2`1Mf_el%hUf`vw zr%zb$Hc5C3CA`-xc&m{3MJeL@I<~`u;A?lUK#i(pBGDb zVs93zCs)J3^Xq2P1m0EXPe3wgho$%})%lQB>_+g(<&l6Vfeo@z9xE+)uL6(!Q~a*Q zBg$iw1&=!ARiFzc;;Z<4i27ot3K)Mpxw_5NH0j~@^6u;GY zh>z0WX2E+Hg|Q0mLJ7RjS@=f5m#W-oFQ1&=AA!juz@Q7fS1f#Qg0D0M-@jYBfNkGuM>EiID+;g z@Tx6%6B6DUunIh}*HF~qmw}g?0`E~vxF;{e_gxF$Z@`zTJbr88`v83M_&}uN9QfpX zIg4}<9@VP`DINJpfSk{H7<|2&A{}$UC*vi6w^zq&l<=;%;7tIJ=t7D3Rao%)QJJZH zDSmh25&2AeBIWok%hJ~R1s+}pT!k%o1HhwlCp>x&3%tLu;B5w8IY-cb1m5Q?c!LsN zvxN7*EqGr9URMgdr!9DgB)p9h-s={;1n?>)JduC2w^J^U!xG-dCA{}6c;%=Bsqo&l z;0;T7)J{bH`7oZ6%Oi3byaMpa@f(%!HcNQ*7Q8_Vo+yts7Q9!12UcFbG)@rl+h)N# z38q}og%bJq7Z$$XfRE~*P=fE97CyT-b-Vnjg)bL;G|v)Bq~mq)$@y|p%9k*hMLH4| zyh7lihzuq0rYv|95?-r>mxsn6ms{y&@N&T?$M39!*Dm4RY{8>@?5RA268ZN@3*Rl5 z3HL5bxRX-25rB$(`Ev_iE%1CIP@RvgPk;~qI9H*mHtH*pq>OCFM)B;1`MY>1u2e6`t0)T?*^f#we!-YXD1mpK zev^?;S05(p@OoT=q_KXutix4^7nC9EknSgVQI3>|%>SdhI#9{ff!pwGRMmlDJX>Ji zfrs>W@x&E%;88r!;u*zL4xZao$3U}_CHU_vPeG1?W8hgA9=BtlAf3H(h$Mz^s$;;P z?ij$Xac=V*RlnmHm`oEK`?GB;_8ztUtU1=R=QAGl^x!`Ih_qCo_B2?_uAG0#5;+a|at8 zWG=sB;E_zbPsK0A*)ee1X?wFUCgP(Y%>5qMNkLHe3$Ji*B5Rv0Mvxrk& zJr57p#B-zMTYWRT$92XPdoss$2EL9CM{UO(1Dy(`m%Z`~&k+j49I?j$VLSvNk%1K{LPnXwsD!0cOR!&XCKI3tQl#?f84-dD- z9Rp7(?3H02AGu6lfQu;cQJ5)3S}K~5r&=jYRTKwQoEbD%aml?3JS zD!Avuzulv3V#f>CyZoiORa@Bca!Ai8%{g0K>aAK_ag(w*u{&>gcU<9Rff|Wg6nC-F zQk11HuE%3o$=~nEDo1`ESJ9zRZrM*cdbl6G?E23*V(LJP-P!7FRnEA3_8o2AqYgyU zoUQDr`WyCR?;8C6sLE>_wx7Bs=B(JC?K7kvnss)BJU`Em3jMyeW&d`;dqtT zb;{n;68D|5$6DjpRFu5sij9I2ira>(yv_>Lq^n%le+MC##hwK3;U4u=VeChz55*kA z>Y0olb=P|D^r?d}XM5Tmk0M1#!Elk+Uq5>4^F4zVRag11SK8NC*}|^V1u^^SB{5I^ zlUJ$NJ5Wb6VvxVsD&7 z@{hfE_0-RlJdZl?Rl9O#725OvN>k6|^?XoV>hYF&%NzseGTHGwl;yO~mCZ(X@cQ5k zQGSnRDyX-<7d*V=B5CY-_99{DUbQ~k+2U*&E%Gj#UXj`3-@887F%V0us$q{-c|qGj zuItekkgKy3?k`5jpGR3eT$Jmr@JyFy^w`5nHVY}I6Fn8ErR2g47v)q&EN{3kZXc#x z5v{-fOl=Q)#Mbf_FXcJ*C%ww46+P^DC3>OKY`d?_L*;HiHK)h^oxF0SJ@lVGWeK@W z7w6q$f71cX80x=oHXB}xnp?iNY40>jME%WlX(9@~A0vj(uWy<@Y4541b%xkZ&zX07 z>_yYXzlvowvcHBzodzktMJgaq6b)2 zrP53^5J9uo+YK6fK+w>2tVZwIT2a03>90oDJzYDjL^i||!yDp$ANIfRzxC^EKl&_$ zgcR-HpjQGUbr!EGP=-m8?0dzHh^NLKllA#ZNhD#bfm z=NOp4o9Aqr?XBXN{X57l)PLjw`US^#*h>$=Pg#yVo+!b)*QLCbfquFc91G)%;gd^Q{0ayYA;4SMztd7T~o zr`%|h{Xlbhk(NPn^PeJ&O&HG5{YkmmIC}eLX;0k?dJXaT(F&De$3VYp@^nTFHKj-8 zHue(XOb;tQ7q!VX;99dO$5r|P+L%(6m!njd<>0+MjJoz>WjWO&Acl}qk1eE>r$vYd zxul0`ixf3YmMhI=Ubv0=$}^E8c8{lNN~<$|*t3h)JHr_j&JJ&L8S>mQaIYKX4&Y8ybH}oa&H=5hoknCwwC0Y3!@pn5*2v zMqegh9%Y$(Hyd7b$T4u6lZ`&CbCw-uFHTNRPkSpfk9z%Ohx&)vi?xUea&?r3&WjF- zkkT@IzD0;#>+i5e>R)sS_TOl<(zx$8MWEcLQ<9kMMVkE)Zd!)M>jQ5V%maRxKM=2q z4`FoFfL^>2VX_zLY;~SzcIIqc#~Fo--CJIf4{99dh4Iq(-@vDEKZn|+`Eno(kgkeKuOI!fmd8jv8-3Ksqo>e2+>i3%<=Ky*Zz}5NO+qrx+%}|8~A3&Vfh`|3gS;aAHDC+`_|pZ23^Bl@jDNDPUay+SSVt*9m+*I zv$#neIET7HuC?5i&k$Zb3~VZ)Pxmiiw?3;>-}*F__w)zK&9^>Hem_02fRXEZwEI6p zT;Sc05g>Bm%{0eA$U$v(Bi=Q)Ij4r##Am_BmyKK@KcCe6*lG{mc8D3F(G=#^A?2o9 zzwR3D#<)#MZ1gaU8WoO|Hyn+#;VQfj)Pc`qZ1Vy}jZ_jFuUelweLan5sdSW0>&xuB zl}%M;nY$eWuchN15u48XNi=Wx)9}egc@0Mo>+Wg7IP&uu=)qB!b=PvO-{n1|r{6bS zPVN1(84P`gk~1e-;Z=5e@A58HTG@-!SP}59R+h5Sy~r|UQ$?BUp0wfkv9f5wN2XVg z6-M7Y_NLEqk7GDDIsx4|oDn?>-8F2F&O$3-EokX@KP#v6Fg9|bSNeR$qNuBA*`BgJ zTHKrwTZFy13_StLHEVi0H@D~(rMAwi4D;Rq?z!1Tc)wLOudn940q+r4<*=70JT8B2 zHp)e@Gv#KCyGzS*T|xHpCb*Z}e{2=D^TQ?Alc1hxlef$VmpEKpUT4VV z#n_WtDesABq~Y?G?`7!G-gDv&J4(H;-K+9`lKSP+J=8)dH#LgAo@|bRrcCd8>QOMp zB%gY}QFWDatFz77rrbicq-n2X;LjQRYm9>W*3{|cg62U zotg5x{PFl6m>_f;eUAT7;1Jbp>cM|9`;H+t`nRa2-b()v;uQ9foG`hOY8AHo%gwM2$NZkJ$^hBcO zqxKC`UQ(X2e&(sP$3P!cnl_-%yg8H7fp;p8k1MK$UX_zk(tN-FKBeh8^l*FbccUet zwyCb%IAYawziW6G+KDSZD{l8vzk%F8infLlL=WI|^YZZCMdKD;et2&>Lw5YyLMnch zkb++pqIaI%Yr{y)8J_li5c6W(NAEmxRm`vnw10i{VU#@f5(OG-x4nT1>yM0@1<%;*}L_QzjQ!|#WuH;~8~EQgsC#+_Uh;g|TtvXYgLXr!*e zBd_aSj&B+G$dAA$KDji7xz55zo~UdLr3buK=QGL=Z?Pl|<*Fp#I?8<7opVC=Y)Ry<$UsC$vvm!*>Tp{+m%8f;=Es)| zvEp@8{pH&2B_)x(ILVhE{pTHQV!I}D&NZaMhe|$1L^^SgI!W+`40jhvW*?!)b0iJ& zRlQtNE-Us1xO~#-jE0Q5oSl$aTv9T{T60=+cCvFX`|@f$t%|_|3C55L>+$mtw0r;X zVF_|kcaC0oRhMImaTS+*O`*DuX=YZI0U4PjG#rpJeWq zA5r4!;?Et1tYF*RlgiV|feoPpp)XatPS-|$wdIYC4@LfU%Nu#h%D;UsU zm;8@J2ES#1P2}Nj!t!Hk5Hfn1CSTQucNE3?N{>R7B2!JzRA*(XRH0CI?WQ2ie#yp=^h>*>LWFkOgY&}cB+}5q+QAJ*E$5vFY)JC_;Un_>o#_k zg?^QVKG#B@YoX7x(9Lga8{S6d_|CV)7YD5*MY2@Q{PK8DMPCMX|ie#ml{ri$c zm`GNtnO~F%J4By4xwa~LbBs#S;s{KoKJM|1C%Z<+83Ps`VG|@8| z?OPR!=zQ)8y$Me?V))k<`XP(`n2tw&N!HsBbh{Rx9QIQS|5=OOjsX%mY5uQbv=3A$ zax2#9RCBV~Ty}$n-e9qR%3_aM>|cVN!mH(Y^Vm}s`VVxv7N7a-tZvuxvw$gLfC&G@ zQwlrbY4k#Nn}yzDqWjpNTj)=j=*8>>3;ky%dMTrQaYFGpBH(2Bi`WW^h^~m>U=#O@w&6ItCXqrrE}|co!u8;-?e(#ma3@Q0=%+<=mgcJZ#;yD` znc+|ixfO;5RQ-sR1(6{LcE;&2`GDXIqUNQ&W%u?#ti5MjF)ZHh?238+UiL zGeZW*hW1Vr2&Ism*7de_basXzrb#OvEk<-ihCFe2{k%+4!o&;*vqYec-H;T+eNx!S z(4^76HIj&`lN$v`=z;vEVuPbti8To2r z)Z%3IUcJYX`6fSl9?IaFlZh)evR?U3;vLM#$C9V(c>b9%jYCu>|AwoHH+A^@6rIU; z>T`87!$zs-_$Kd?^GrXcY%zH=Q)c=!=ZVRyg~a_*V+gl(bc-8|leg)boT*E9WAaJ; zpNh#Zb!qM@T{c8Dy+>fL(asCFYqh;M?lsywf%xg&rDBT5{okz3_X{x);5hJ4s<1)V z8#TK7P91lhE|UQ|u@=Ie$ER6agK%%q?H|+apU~rlfd!raaNniJ3!CjK$xfT(pbBXL zfb_7gx9U0#K%fe@>w1T-@6`2O(3kh_+0_?rf!-I>^oTI^kqjz+D=?$8XVO_ap5t?I!EwctZuA{xxqey;`e?s2 zbE9$C|KID3q)G?S)y!dkS{yuZ5z%mefOdWW0Xh z5f0(e98uu?Z~gpwU#_#@y$U>0ZnPRB@ER<5t6(n!T_}MUu;7hJ`9iBV0xx30 z+X8#70D~^@+AMgJQv7JON8o+If;R}eoL=H1^$!-l!>|h)(M7o5fV-T}2`OA!6%ygT zX2E;zGI;-F!6PC6BA?}Rl+kD&e(T@Ls+QUf6=?lkjL2Oq9o8S@2%H3?8jZ$muPU@Tgu3 zyzf}>esmeUZ(H!nCA=jP-U%H~EGvuw4^_)huyXY-_^5sezMp|0Xv84QDj3Kt^QFS` z>3rqn8R|Fi)U6r$FJaKL7<~AT3KE^e#Sq<4#6!xu@4XV~y-7p@biqeDAPn^=EE9NP zt%S>McqpH#ol;py-dP_Uo+F~J1RjZl-5T4rH4^Sz-hG|V_hH|&R;*a5Z+!po?^z#c zAJB|_?~md`dFPo>^(wa5_V!Xo?*){O%;-SJPRHBYd7##g^>$`5)v4BY z?u`R&a*Um~X}sr$9v)cnb-$#2wY`+}us29K!8HM!u6^iSn7yMhNt zot1czvt!c-CN&m)`la=!tWRv*JlLOn=Ft9et%v3$${Q2cV-~OZp`o&x#71>q`M#j4 z^$-?lU;ogXV{00&e`qLO^Ml>cPPQJ}lz3=pR88Xg%~zA-L1~pfQbuN3fW#2CF zj^%6QKOG8gb;*H5^=MeYKBfJoqVx-xVeBdzNP&A0_UU0qlOgw+_gAy$TZ!9trgDiF z>KOXSR}#SsbX$|Nw5zIT9)R8N1uL$bc-_IFJ2G`u_tt&u(5J_qv@p0RIkl|)PP`5E zhFbdI?$U$z?1o*@4>Xlesw=uCc(inGFr#GZf9v}7!O;VWsbe6$yW-@!-~)56er#w& zW@6putLMC)oXqP$=MB#8A&syKg!Vi$nA_vLqE3$^Er~HNoT=l-xRv2al7qK2JpP8d zrTkz<+Z7%^@Y6)MpL#H}i1(`MqYc)ouCKz)B)_WD{2ADb|7zdJ`Ez0CJz@Q_?bPOvGo1l`p-C4- z+v93*jH-flWX!!bE6l3);l4q2^1z7a6V-_Wco&nC1Hoi9fD~l@*;fwh-^szQ*2mx2 z-&uVi^Wx)g)ZH@WKoQ*jTe1iE7(} zQr`h(1##E*Zh_miXM`>Xqx9PuweSb9l05!!f9s2F-?FN5a7>k(9@On_S zxn)mZZC_8{`MZJ-Zma*d-Ni3184OB-f$6y&xrbp1J~8lcjy^lLT(E`s{kxO75C7GL zxg*uj?GD}ug5bw>B}1=Xyz5AH(ScPJgJk*K{@ovHd|=&@U#Eh5c7Lw^;squ9 zmi)RXk?s#Fzk<^8K--aO*x5}yaP7PUB~u>GjT)$3IJ0s0kQ!i!yXMV1@XXMPfwBE_ z2F`ALag~By*ZSO9ut`2&r~ZyizJ`;+6EPjB1}3%7xO%Z%sb#!2my zw8d_foi<=fTxOSXjWz3_5*Al=`BBv$K78H(eC^e-jU|(#`x%R_&%XNG>c9H&k;<3y z;_DXNGR$_2Reei=|=9{nn*DZA= zMQ;bm=j(p3`>~;t8q`u*>Sl9XN5E%hZG-Z@5sO)Bk#nc$bjXG4Ah4$6#D&ZI_8+PX zS`N)g!tyKJO>p1EU%#hH#P3=zRcmeTjmU=g1fuMqb#V&Er;ff8`lNP zv&|Wk*X`O6K4+p)4F(EdQk2D8OH_l@J**R2+P7Q%jI6alNOuJW+DZDmTh#bKU+1BD zWe;?fw})1d@x{Qn-k#D)e6GaQqFnMIpH5|GbG68kQiQ1=%qAFy{76`2uFjbiD3f*C zB=p}+h~NI*#;!FH<(`?nXb1GcCU%xjVC-8f1*C8t#%X)hwBkmr+)yR^V5|4uU`J4u zxcknb6KZ(BBHcD19>b&>Kf+X2&3KBBm>AjkpOE``F)S48TKx57`h{$J!zA-0Sy%G@9?rs_*-y$zZZ$)IM z;j7iIQ&2rn*&ICZ(3_<-tC|xJe5JXnCk0E&ypOq8vN5w~+jYdv&fUKoF{vr3n{D6g zr1qlRByGJun7sXx>YTiX0J#Y@xK1N;Z@KT$I21M5l;@p->hc4l^_Q)DS8MyY!LH7s zgXzYr+Q$xdtv=!4$i|BHbM#%S=T6S;-@OxeW+>#+r}5?BHw|?&-(An1QY|@sW8&G+PFQFT+|tdavJCs*C1&Pz~I1xe+@H>nx8o*dlWa?`H2KK%x4 z+uU7~o2v0>zj-9S@8brKjA5Awblx?!P%2lhYbjdUPVmhkF2>e#R@-{6v$me;mqiYz zrDyRocAm)@yU!(i_HWVYf%N1Wrt!!F1-@C?vcn4BtfGT6Hk$8MC2EjlrF^k6{9^4( z*>6@tTWl{u4Qp&pldl?#^QeJ)Vse+)Hrn?qiKB@#YY2%mW6WRQu5{z51#GDv9NLn( zJ$d!Mk_G8ztg8yaf(DxccsE#|M^ zH>HM>sZBV}9_vZw7T z3}-)^V@8G;n~1n3ES`Q@eQw&;P$e5)@nSf8+N(pY%J9nQPx0`lX#Az2)|Bwd=%3-~ zpP}`m^x$Y(MDNzVb`;;K5g4wLYMOWdY5M+6q1LqUiWf<&L5ru~bgj?1T0_iD5hZcL zeO&(>t^Zam6)fas3)kKGTzPq&=dfDr`@CMW|96UhyIc3j*=`&C>CU^6xB9 zKi|H#tMG2@X~)ACwx1oXeEguRj`$b0hrKA&`fzx~i=--S-#RL#b3FZg`_`^PA$!(w zdA|MXxV*6a>8O+}aMcn2M(=%b#xA0yTI|Ue>-QOzr^S&nu99krr@zFLU*^d#(|FPQ zxXjbfw>QliC>v@m3$J*QRLed5<(~X;0d$fL3KlXU~y`Fxrhu`bz-{9%rp!K8g$qk-< zpQqpF#i!5H-{|RY^z=7+`Zs#|H+uRvdipnc`Zsy{H+lLud-^wf`Zs&}pY-%U>FIyc z)BlvG|0%5>rRS$S{eDls-_!5+^f!6>o4ojJ^7J=*`kOuc&7S^kp8jnf{%xNAXS6)> z{EVu%ObTwGEjvZhr24F<|5+t9@(Qj0*+>~zNp-uYe|vboYeMVa?&*InJV&oc%RlGI zKkwmvK8&G>@8>=JJ3Re6)EBLW(Z9pfzf*nP`ml)=s5`yzcY6AFdGfo|<5t7q-{t9l z!Q;28{f-aoo#*i5y;+CTemmEM2vL4m7`Wu4zLVj(HiF^H@rP^rXOOW({RJN1?D0Hf zT8R30dHiD@|BT1K?(qq}XiLN!51uN#<{pErC!cNQ>`#?pHaQpLGwRA14-3RGeuC-* zFT{J?YUSpB-?jLa zq5p>S!ZgpGd>K|k{npbz1sRX}&01co&bBibmY4`XIR-Yp; zwExaCP=%;}x0RRTn)ctn?8#|=p7F_Q`3Kc=mT%Jhht*4-{u@?q-v1nxEQX>b-j8R9 z5|6L7Of{$)Pu>`l&r=`s3A33}4qK%QG3v(BHY%3xBhf z*J%0W>P}Bi`}RVN&v!ij1slE$vNH64{?(Ho_V~<5K{L-od-hTMuTpb8`A4kWyw8uS z^`3lFOn!}ez>_~}$mp8UsFp4IXe^@b-;B4aatCjYjoGc3<_MP=yUT*!=X ziRp7mOn$Ap#*?p)$ve~*PyUdVF9lW^`Zxc>lmD%iU#;cq)Q>#*AuBiEk4_bgvXO(s z_?_tSQ^E83O!{1}J{aR+5!><%Tc&zcM@-(UK56+nEx$qi7w|$1^GGawpV}AWH>ww6 z{Eh1M7?1Wl5}xrh_rF<{$M{dG8q3dxPMP|YS`g#=RdY;#lj^hl#ae%}!kIZC@g5Jx z^lwwjU1X*AqPh0|a8QL~=+Eq0$St3D>GFBp@U?ao_K&HxtHes{ITzNP`yTjTFjKYpHhj8a5}qcH=iPv{<2{Po z&AP?fP*-UH#JWUT>9%)74Zg;})D^=7|vX#T^$7)!$ zQta3-=hAiHE(>vG`;~93T>SG)kS|ySyg6%Oz#DtG7PqbI?B1w%eZjXL#*5cq+1(NP zyBnek*vR7xK(Kl1S05`-0eg8i@UlJ&+}7IGaRV&qT7T@hli2C!&2_Jv*G-G@`j*T3 z^llaI%Gl5|58GO_PH5Y{tGlgb9n4bCZR^FJIe@O=&O2~5=A{4$8|Uy=EL@Wdhb-8t zw|j8c%e7`R9iB40VVm(^t$I4w^nRkHn;YSx+~6je7Ff&bI@&Q!+y9jbElUle15tgOb!@P9&hORL3%lcqMn8?0i;+Q=v`=pVru9Y-eX75fDjVKn1 zS$SReqE)?2n=o63wvu6=%VaB>y`Hn7k4L;L+0fhN8AL8*A~FOEZO!ZF)n?t6Z-m9{ zb@Ov8mNd|;Ja&J?c83{r+kWzxJs`d=HmXQP5Vv}7iZAwHMqZ{+dW(_P^<0dOtwzRdZ>R7p9?dpyjP>bn|yt1LSrJ-kC zOSET{8&?^p@HUtCGm?D>%Sc~z_roLDLi?`gyCd;xu6ae$`t&c9uHh$qtjPF>}_ngapXt27i z-%@O2u@*0FY3Rk?S^fNTRyJ_g7_YTVms>xtiKi63ND~FGwGEkvPpY*DRh`_^5z_~6MG$sY+F-bBs6iY@4%i*n~UR`R$|na zt-)ughxycedQAc4!&(WlqZMgIn>%&-H>`@iDU?RprVTUcs%hThr4870}@K(a7#Kr1TkEFeNpXdpcB*%NqE`uD}+4^9V>$*G~W&HgtC{?fgVr_oB8N zkeipzS!wEe?HAQ_xT2;la5{%@Ge5oY{aoL+)>H=JyE!Us?Bz-=yu7QewPQ_3D;rsD zXj;|Fi>66mBn->6JTwy-6^XqY)4$=$d>wj!BCfW)mu-fEs#X-DhEEnN)AF>eGfY0T zCLfUj+)^5^*TUSftk0&C$yK(lH(N7f!DD%9&W7GjeEnnfq4ksfp(ZlcGy3wxyu(t# zd}>ws)C)^wlP&UW%E?g04t!1y1qv%vqEuz zn}+enw@N;e@c^bmM)c#}SGIKY<~qA0e^iM~-q`!{zCSi~7!>>QZD`YTlP6Hh|RuP#oHF=KTJFmKf)O; z^ann>acQ{h$EML^zln1A&xTt8 z{$q3zFOEN?N80e|K%f1S9%b~>rGehRlRhEP^B?Ka1~2ivv1gU|o*BQa7;9|Lr!mH( zpAUvOIgXGH5d)lL4iK;29i_q&xY(&2M-5$-;^*+A{2i}2sI?oZ$*4w}7DiND9Z0r_WPBZT)m zIWXys@Qimwl}$f9{|fMYZjMjz{pfT%)23Useg0|Ioo?UDE6^n_-Z$SH!)sjN>GV0< z+=uCQ2KC@SlP>Ph_msxQ%@5JF>BI0#!6%S!G%hAF$}JB^Rd7Qn-Se$`L4c8agul?F zf8tavRuvbSd_p{(|8QRnuc-8g3|{)fM!%xYJWs`3`&`)gsqroeO#Ym2{TJHjZ8XnS zvB>h5+ITFr?lSA&WW!xy(*XuSb^83o^DywvH2%yo;UF(0==tqEZni8=u81;$SCrR4bH^8qp=mw z+YUi^zTu#Qb!jn6|I|6LK}R(lvWUWY;}nsg;J`#Ajt@LI{^4Ll zFIdHS}K9Sb6zYF|0lz4nDp&)E^#Zl~@b=XiJ4T4edlnq94WWgu3x{yP|#=wz5rw*tWJD1;)+ke|i$>Xu8n|yOy@ESttk_(}nz{ zKUqi?bss%x)K_HF-xE3=M^7Ss#lqgJeV}+B(FvrJ-Rmv7DUWB3_XRy+yhrE*BQ&~C z`R~Q#TQ&(z$1N{h*roF&NTjGk<_nn>qE47EwH+#_>otsqbh&&n;p2U`0vf}2uJV-K zZdSf9-o+{?_xe_OI$_Chvx767U$)yH2?<_3JY2lj96ZKF@IH!b7q1yS+rL7RE?oWV;tc|i z&%yXHUV_(+YZvck@LYc-B=K7h4;Qawrdh{9Jht}*?{-|fc>LhN~;8U_!;6tVQ%>fo_IEO-?j z-nYRQdcPPZh~eGu;4vQx9=gA=`27%kq4LIVv-^Ix15ffZ`@4dN?rIG0m*5M%4|H>5 zcuzXpL+N0!hNNjpXuE9Ef0@t3)|%(tRC5MNH3^{&znWW3q9`` z=(+i?5BIG`IHn)RC**l+JiI;#>L3@Q9%;IVw;gzrpP9b|uhGMM5(2LG6B4{jJiI4? z*AFGekK-JIx5~rYiNdiKav_K{@jPkwd1vFpD(PGU4Z-X4@VEw!m$y^*iyq2+D#d zYkQ?`d=YqA0ke8!PsDxQe6SUGlFlErdW>(a7r!CkH4(s)q;rjjN4xTM&|yC1jx~wj zA`fp7ZsOJlf;Zp8qy2BmS92V^b`P%|c!B{nCF!@?!=oK(c^?f9-e)|#wZq_T^6=F8 z5#Brp@2ehO*D!cr_V7v^yh|Lsr#-x0;8jB|B+tIr!^;3q(r*Ej<$e6n!-HMJg6Vg_ z!^=AHYjp5_>EUe$o?G4|ey@3W)lU4lqfg>D5*KdycoKN5mxbj07D3O=&sY=}=I13) z7Q87Q-YdY%3YgU+JIB*Y0engUy;YuGHT0zHQC;HqG3dGRTk53Wa_B*<^W!ZZUJU}( z5XchsNH=+SE1c)O9CE>Xz{6_>UYSNPe4{xi3$G#K8;8p6i_ip_DY#6*>czE|ac-J_1V~gU?yA62b zAs3Rko&Y_FRGk%UcksAFQsP(R;q64AtPMj)@TPlsJAfzkbBopE^Dgu74gk;nehA*B z9^QT@eytAPEgs%afX9B8ki3tZJiKRtC-qAkl;wH1d3di6gLl7&_o9P$t%LWJhc`3~ z-jg2QYYtwAgE!#emEdE(R36sqk%e{Q*!vv6E{CU0X()Nh2;H~K@Uk0=D#}NNq*^szu-;t@CJZaC_m5j^bQZB zx6;!q!F(L^fsn+n-_t9HUZMNm3_bTbR^U09&zUa0_{np8$-|otygJB*Z>*Eb%g-dzRs+J>fr!~GF1%~B!2F$2Q!{JUtZcUS!kM*3|Jdj1ZbRHa;kmj~)MRx+HBMnWFly1L#?jR! z`zGNevGk%ePTIY%{?uH_fuc*znXymQCk~kN&ZalxbTN-`cGf=Ff7E9&%E@oWuV_Bc z)k>Majj4qbn|ZF87hH|oQ_>iGZ`63%y8XKoIH8VViud5mM0BHZ zYN86hp-+}QVovoPUJ~TY3A9Ccrp&JT!~HXZflB;kOymqRk*Ne_3TL!MGMDh@LiFKU(Wg2{GN)Gxal` zzWY_9oIAcqoJOQi{Qn zu<#t$KUwQbeXcwU(6lKT*FVL%JMoxXBI0>r%r6mD=yhl0nR5c~G=!u&EmFl*Qf0MG zMDgU?aKF#wdqfDA{M{b^KfyEq@_w|L_#IFFvXwI|&rf*UlXLDxh&mU8kMPopb00#K z-(cm{xaN5U_j_`&!C>U0)eD~d|9JdpeCX)Kbf=BPGh=+2;utjL{7jZ1|E+O8jEv81 zR?cy}GUUG5TJ5YL|-5n>WwI%C6jS7rYyzVP4$lw6?Z&^=d1AvQ;M*TuW%{k!JGT2x6%UZrQPB zW3kk}$St)0^PhgUQ^+N*vt1MmM@Eghd@C%v#pwUZz$ofw;buIl_C(xhw ztEfj9@|T$LgY*J0?`j>bd4Yv03V%IMl#;UODl)XDS8zoNQcj152#Z$UIOzi17Q zSGY7CRo@hkqpHLT%274lGT|Icnr$WulX&`tTaP8vV44&m(Nbs(Q zhl_VV@Tf;T;tJjuaqZ&WVP$YM2_F0LF5V6&ez*+r{tDMF-d6C{_zCg8q`$z=#oGyx z8u&4OtRE$Quj1OpdlGyhyqDqc;&Ggo^(gUJUkVx&hqefARODf zLXs|Qi@SInH4)Elfm|!(s22X~Udc(KhCC|}n@tB86)ax{t`Y-YL zTMIp4b&2Q#@NR!h?(2`cW$_$0Lsv-j=sMo23(R&zstW#SQt0Pper1}-GvHEX(5_hG zcnIFP=g%<1X!h^1#@%MloPFHmZm*ciJREmB0WF@xrv>`fDWp!&bt2L_P`4m{<@OE0 z;yR;?GH=}J)~&H_t#vQ9ZXMk1c((bLZ?f(R>u#r8r_|Tr9$BQ+4)Sx9dX)TP+$f8E zQwX1dODcz3ax3ycO`tA-(sa0wq<<24{ zn|*U!Y7*Sy{mWDq?z7OF0+&>6+~jo2*I0Kc+|}4z)dY7A;;{lQLtG7aXK{&YhWp>a zuZBzNgF7eKUUDypgubvqXTfW zD0HQ8x8UQGg_}e=kM9c9TPO_Wa9Kf3qN~!kWwncRg1ZSm)tc`Q=EJ=hZRbUBpF+jc z1veQ?R=sdX)s(0{xFZG@s3RbG_wvr=9m_lP(^k?@o>k&5aTUxd$WO$)9CM`x^In}V zzJ+|DF;T8p;Q3jW4Q6wSn75QHevX)@Ehy8^53!D?!T74aet#^L^iQW9^H?MM>aiDQAkP;;gYG!}U6mN)VuJ@-bh zCs5CiW$o?^BDAgPK5u5NUC6(Py- zjqq^wUV{$vn2_kLhli_oG3x$8diQyHTcO8xypZ7iB|M0SDq9oRHy3IrJp(C3T~JUKlSZRRJ}-gb@?IqO8OYBC9;#X$$1&g;KYTXw+DW~r0v>?Bkl>wr;moW{$7(0l z)<}S3&rg0EZ9P!fPC5l2Fxcyylgf?M_In0S+rN84^~A+vUJR;eF{`{WS$Edn&57a{ zruR))cv9nt0pljDtEP{~jOO^tXKZqw)u+xX z*>_3qsc??7wi$NeK5gt-jf#!(OKL=JW=~OL(fnY_ByEK;rRO+l3o6nuS0!3cRT`US zMlUEZ7h19>r{_J3^_;2sJEF08Ve$Nl&74b>`BfjEyv)HW*pe)%;|wg`ZR5#nURrl~ zHSGqL?yDaR67_?L#7k{=zxD7NTi@C~`25g2*|HPLik^YXYxK_!cV+8eA3LX{0e;%< z6K#rRo*21kVAbT-vAJoxf+{t+wRK{yBnSJDRjXRda}#s0t=eerSW?HhnEZ04wyD>@ z?W`}n{~b2p;c-lykW%`r38vL{{5Yq1He8Nv7-H#+h~MFO_z_w^>WBK@BTV*p5e~@FhUH!(Bs#6e7_CPH^Di}t(Kp!`O)ez%kz6ri&xKh;mw>M zj=L-{*;l`49>%hTsa<@hEaMGkchIRSI^{rQ8W-q!0vgMWS$Q0`_S*LyV zsb_jhVs2YcYfpooV@7^wos&kv`xsqx*t)FC??nQGxwq1tX3ob-oTbzqryk4OW%#*xKLpSG zDwv$Dx8K2Iyaexd4{r*%pBzh*FQt4Kb#4?)kxn+*__bK;faCwQFia`Ae>%!i+l#P6Tr;p%ap zI^U6y=)D9F_rCLSU#17|EB#sWZ{bH5eQ8av0gw1Xa-G42uP67Su3VpC!^`s%kKu$w zuM+-l{FXZLV_TVe42R>}bbJJF5IoaONbr_hJ?3lDJK#IbrTz<6<6MmkciiAQ03Xk| z0r#D7j!H-_=}O!v`x==2xB)&7I=?c0eBXRlNn>29)yV8GIRORl+!-@w{7&Nrvucie zeq}meyfbdVcA=hkfG5Y8V{+f=|1-BV7sTpJJ`<0n%S&Hv3c!dKAjyBiw z4(#XYv3q1{j@^^4hRb!0oNM{fU*CS$YU|H2{SsuTn=Q||mVL>Ih38sQr4u>Va&B&U z%YAU$SFKoZKiu=PJ6GBdTQm~$=n zjs5QY!*Ks=*37j8EoQFelh^(0f9Kpn+c(GRxt1v?Oq^@E-OjZf`DZiNG9+^?C!;_u5zqge_3-0I z&C~Cp9@cZ-r|q|S8XvGJ$P1*S<>_ZrX3m@Y_E-<&a~~W%PyaCO=IMjUX$A9iDm}iE zd3xrYg-e*HNzBtE=4lf1G>Lhd#5~=PCXibX`*Yq~ZJt&w$2aFa3Jns@dFR)|j|`Ki z3(t8M1(muUF7f8PSr3PKx(;cN=Wz3~o4?;5<7Qhhr7Dp|5lKtd_;9W{F2_WZLmcCd z%cUnL;fp1=*@BIT`+nl#QDPiQVuBz`SI|^mqA@; zc@utw`a+CHdSE2L8L%uosUFv{gPO-XSn2A$tFguiARI$HMuha-d_kRPeDLTav98{` zigW~U^hn3`3cd}!ZexZL8HN%VV)+Pg_>v*_bJAFugGwNAsWA?0gvHR>u>O9@kzsXDlY)^luu zzpHl`0Sf6o;py$bXQ$A8|HIRJ0(z`Bg(QA33lO{Sv(PJa-zAX&Q zQ>wKl>GdkA`t5_6r_HK}QH>|J5AIpqt}08c5(sm%lp8Qs*=|? zT)+AHsk@%JKGm3P&QvA4yDs_G^+9t0SMB@N-+b|v6xPv{HwV)a`;rUQByqI$%EsX3SsLtjMiTi#!0{VkmGuec>HK}-5r;AXD*08 z-qRoN>AN*4^(T1x6SRIdj6weTjd*-c()tnVNnuD{aL;>O|70&dtT7|vp7*#uXW1g+ zp7*%?)JTXc?rCTGM0A?2m&r5dV3ao!;fj0S6VzpvpQQPd zR4aJio4>K@-;Z?1!k?^dD8WnHBI2I+2gq3B{dZaY8eEqlKk)orANVR zLz}}~Io->})2%T(9j&mX0JFPxNrGAFvc@c=@U2ofzUGpy^nsv*2+kPo+r&w+=FJv?u#55tPEwHHeXf#Uif zBM_T)xa$>d-950v2$?xOAT+mW)^|W7^zjtJAkd5(@d%^ndGjfu95?C_Di`v0EwkwM z)eUXk%pEKGtQBD&R8DC90LN=ky`$DY5)gx@Vbs znR0$*$P+iwVAq|996akB?gy`cTahzmN%n`Q=iBuk3m|-V>pqxZ%S@(q)>qhMbaSUC zMHrg6E$B;&xOsvwCwdZ_Uu>R?3k&AXe3b$jGGEEhns&hnpVY~q@o-VbWL6zc#$4*j z^73oGJf0WzDwWn)nKE9nDn@$kVLpA&D^vb(dlXncSlvo1tQOb&?g>eEYC1gFKdQ3= zp6$xIo8yG?ZD1Kf(TL%(yk+qd61;kNxOjCA9^*nx;;qKdjo(`E5?5S?eeq^oyLjy5 zF+Af(SMYAcwTs6}hGkwz;&%f)T)Y)d{8+~b-o3bX@jhc^a5M?t7r?oA?N0nkArrjE zaP8vV0iN$fh_Sg( zDR{PbgycCm7w+D7I~d9LY&pw)xrQ14!@SA$D}~Z!m4~;}c@7zi;B#&A@cO`?A(4YC z`O3G+@T3zzw!|fVU-9t11fFGINbu5A3RRI zSD=Ug;d2qMQ2PDK>Pg&x0>01~(r@99xOFiuB-$)Mb0H*%HE|3`o`D_%cwU|hH)6T`K#Z=In0s@&_nlYrl;~qnrG5f;f9z)u15jdDV&-pBS;)663NnC<}}5+U8*lTasO^tCxD(AKjFy9ioHg2zSf+Yqplf4Nni|x z<0$)gmvFRcA4Xr^KQ|Eh;SWD1f~*%3=ll4LU|z&jHTq zUzQUgxi9l_>|2Qluq=$hkMD**-fupBF5ac!S&oDRZ!SDsycdDTZ!htf27Q{JX}1kk0cJ`=eCKz2%hm{I+7m6uh2Jo zJNyx)E;yQCCi%F&(HY!#rv!q_dy(i$T*>o1obC9z?}XQU2HZC!&d)s`auJ^XM)w~7 zH+trU$AA7x7up4&@Egs2#r$HLy~QWwCge`jvo`JatK6)=wHM`P=FInYa1ON-*i}3D z=|KM-mrLi=Wctb%UB2Y-JHj95WB4UE=L9S4^bMv`H#k6Ftx^5v0rT~D!$kV<-N)ab z=2xBhLnx)*I3m|{lVL70zR6flqTJ0f1xAHUKa#rUZPd)*GqwpD3ZF%#&Ws2u` z3GsgHbJEMm$E#*fZrVJkfXv~r93yi~XPZ`z>tPghBj?JF-u5M3y%_J6J)yr#dq<4G z>h_MuGx{(P6|$yTq@e1p&9=2gXfO3jzZ+z_`QU1h46}@5c zyq4>{^N-)Q$uIe0oi_ey=+Sq7lPi`kn>1-(0DB+N`lKY*DwXdFW|udsy{o=y);~!* zKGis>In}5tIU=V|+}Rhcof4hm#*zi6w5MKACPuZ7YZ#?hTTR?0V|Z9?Wl8jLeov@h z^?D+a)*&+fx~y>hl<5N`5qI_sGCA50AtZYPJ$u++N#!zomkb^`PYop7gL_ZhOTD68 zweH1C%>_HiPuNwuD|oP~IkB@#k0;h?w4z)#T-{ckoBi~kX79q3FG=U$NB@H5Eus`! z(B>Yje|RoW72HV2EzQjPBODn~M(FyD`JQ1C;2EA}#SjXdLp&cZ!ls}^>!Uej$z*Qf zxGpQMpVs=-q7bVM8NX6bzf|i_3H4c9N5uY29DlUdk7B{vI3o6M;`$k_ANfU3&QM&p z70Kws+A|`q(~8UE9M@&Vef<7UxxRmdSgvMRhHoy=UzJG8by$2q5uL2+EMxRp+eMVr zHK5C%67JccFQ4`*{P_Nv#_S)lz9wIz`LwzXt`PPA3_r@JV>&_$E^S&V zXVqgd5LtV+y>8$)w5;`58XeGTi#oAlX1#O}peVr3x**3_ha)CNH{pFLj^t@uZF?7v zTEkkL(UR|NA`$g7oDkLuf|jv&1W^GmwG8l%$9uuD2AXQ%$u72RPc!eE z=dSQwq%qdSa+|1BDogitrO)`PzyN~C`3}?ISzf8fcTPQAs*1BCJ-#dIO|g1fA9^f@ z440rB_hZ|KdMp#fAypuwu~ekt>b}r9rp?9mJ*<6rJ_}1-`Yil;SA8KjYed}$Cx=9y zrjzKTt4_e9$aQWwiri#_qbNif;wVZ^K5(@1GfBSCWS4w@^IWTXdd~5RhhEtte&*@^ zbM>#7r-hi$NzB)7`}RKDzC|}(mj&uEFX!-MbtGTKMYwkBcfqTNzl*oc!DCp#<5;|l z*9?9NenNtGB|KcbuK^?rKgN&o61ppo!TSV!T)b}sk7bs4ETe+=Ag*1! zC%`kUgaq%4@Nn^d>BO%TGQoQa*Dl@wc*=zY?@4&Lc%`U2_?(QN+rRo3@Gjmj!54bJ z{|J8!o{x05hCw^}Kif7!ocqL%?-4kNHNXmM6 zTpu9uWB!u(UF_j~2t4avA;IIAq8qof!eyjue?;s{#pNtv5wY(Smz#_u8tf~@;U{`>x2B_fk|&RPp}Y(2 zD7wTwC0ItG%Q%{tc)FCH`xhO?<%7b&CBNL`J3OA_ltR?M4?pHH<^;}FJpxyV@^9fs z`K9==uk}N?LX^KI3|#W>czgzd8J=&FdqDiYk(||K?q8~SCYKQL+HH6vAFVza<1^|$ zPyf-FyiD!)Zk1`rasE&Dfo&g~^MWLv zEy~)T`m80X{{gzwl&YhPzVTeT(@o!`f)yNyeQWIkSG(v_YZrZL?Mfefw&e*5s<_y? zAAb5h zYqK~cQQIHcKi2Q51~`h2Vtn|`;g9#@_t(W+Wo2+Q$#X0O=k}wPA~3@fk7*!y>v8Sk ztpU$_2npWD;o;(~09ZBrh(}z(`#i2)yeGhq#!pD_J_`>QuOA@9As*`s!Fv?fF5cf* z85~W5w*#Du$Fm&-kF86=`!23syzf{U98H2pe;047gU9C)yr1LR#UnmtLW1|N@Nn_& zcktML5ImUqisAjemHBuhpy%RkcktYPysX*bJ16}Bze4e2f8WL9Sr+)O-^X|xhWsU7 z{C+eHUW13X)4_B5@zSo7_`Ng?-f9o;Ne7SL6-mF(dGY(FVemfV;q7w^apEvb0$O?@!JP$q8EnN_6x*YuRj58d-eP4#IkX+K0yhzy{ z@ZkE{N?cFIkMUzZWFC+@4VUU>j59py1Qfh;XUzJY=9y<)SUWqb>Dc28&oMI2I0Mg` zHS@KO%@uoAh}pT3Xsm3X*eqvo*tuP8-6aZP=63%yd;g|R(5ZqyzmNVu`;!rw1Q(wD z|G0dF9(#*=xl&q92#yED^-Huq>kUK5ln!xxAg<3EKO&9~#CzPOdMyMs7}Fp&^2+>r zLKGNR96y+<^`yU<((8#tiTQlKFmTB?;m5qqvdaGN8n{A~Z^VysrUCoEx5E{p`~mzZ zXZ+Z|<#$Vna?`(C-O+OG`p%x-j@EGR|Ejib(@wl(ZRe_%wPq@;zO9=(7GkRlwVx5& zUDCRx3U3oWwo)+kjp1SOq3uEG$rT3?m+Yl&=!xd{a25KRx+8s}`8HSJsO1 zJmwMNF|6RV;o8M(22VX9!E1qsi}w@YW#LCW#!K)xuI1wOSs5Hn@+sqdlZ*Eb@Q6b^ z=4rv>{1E*i)^s!eN}T8+*V0a{(OSm7RH5(s9>{^!W!2O#aB)1}^%QROw-N|0pOHjY zo{2o$aolUl`3IIg#*fd$XO(BbrQ#kDz2J!qNbt^`A$vZ|*ZNrV2j|Z?-x{ks_IG`S z$#~)X!RcsylNMYsL^o`pGg2zdtno zKpAI2vRH#qb>~nfo7xdPawld)?i>ngM%+_;FSSQ#?Gd}w-r#id1LhfXC0LEdJPW^l zt8wB0|0Uot3ggmsjf+%W>s4O}-}(FdSy3)hUVFsYjAOYmB&FPN!?llUMLnz?ML)lN z6sqFlc-lkp_7Z!v5wX1!m%BAQ@iU%0dNQJLz9b$#f4(FxXU!53=S$-9cGgv%UFep8V?`zu)6u^!Q(Td|08wpZ70E z1mZw#Rd=S7>&hs0D$n*RKA@bj{;SGMNdMU<_R&T}ljFR~j zzIm>#yU6*75$_uCyoHgESN)#+t1b*IuS9iDd^yE6$!ib)X zfSXZqSAr2@?oDzg5MsIo=Y66W#B?L?mC=~Gnd*r|j)eD&1U#9`#<@*)hec8dm$s~5 zAhS6!!SeRbZV75TMlt!K&h^(?r-4q+X)uzrO+#dy=EQxN&Mk zPeBnjmK%o&fOk>fjXlhMO6!5oLQJk;NYnZSL_~L)(4CP2`~g+i zPC^CzH4lFs4}_zB1?IbAe4WSFn|@b%uHDCn1p_)>A2xMtdX8D&l}5*nQ)k$FZRX_= z|Fz^V!4L-B`KE7^UVv```B~NmVipXjqS3fqJNq8`_|DtOuK~TTy`w8u{~~*Ue$MPM zd0@4_U(W$Sc8IEz;qMhz07q4cRRu@YbSs6UDtd+g=(=7tFuZcCKo76xuPXM^*Dp%; zXgQ>|IT_!4?KHggX*H+Q{T|FA{=v>$M-kEAevWI9Sgzd`GRq|iRYYve;WZ32uzgd7 zA9eU+9dI>%Y)c3pid<~`Qt(#5-yOr?!L+O%h{v#k_eos4c>PueM^nPO9OHEHW&@A$ zAs$`9dl=U)-mT!zz)wi<9)gF9R|hFTO~{xo zLW0Nrf-WAKcAP+BY6Ml;cW#k7*Gq}$B#WceyAls^V=$TNhCN_!*E%tEnWb< zq%*cy1^#%(7Bjf-CD0WDye7Jix4Ih4ene^t{HNi^_%T278F1f_CKW67oZ}&QdTlZc zf5;(m;n*T(2F)U5^LIu~&8%5C9d72V<3A&=9QOo;V~ZS-F!O+^#-MUyR}yE+l+?7I9dJON3y+P%?!Mb2>HZh~1=6`>_l6fl? zD`(7kWAL)0I*vIpB970w<&s}R>PMqQ@?|w)IDZ+}FVXr@nT@U(g5z~@{j`Vg)*jR^ z_4G?U{Wu!O^Wr}I8b!qMJl6jtmaPChpD!Yo%7~JBHo)b}^!OITGEF#Mg)MO*G4w?t zXUg~z@YK)Z$MLF_aD}Mfi67;RH^-MYSw5@zwE7}kA?kl!7`Wu0#4o}xRp0mI|7_(K z!_^iDsBDSh$9wz?k2m8ltbF9q^^TtUwQbTH(0xT12shgfP1hA-(~)Hxm#uyGP<8rI zUj|Zi7ZxFe7r8fT!61Zc->8k6N3*f+;p~73O`eAlGofZKUezU?aj0n)64TeU;2XN^ z=#U-;TH4axvQC0PwP9HUpXv%uHJeBmHj5q#uWaw=ZCj6pp}dd&9;A_JSoRY5$TJ^S zoNB&r>C;SpqCeXc;!mC>h-*NZ-@q4l6eAtgyJ?yV8@;vF!QYXQ2O>);}^22uaO79Ug95XiJgFW700A z9`nk4{8+T5249NnEPg_QHy0i*-gXC%VFhm$u3fw?@NV5Jcpvldo&+A_!}!q^yjyVX z;@u2Bi=U9-`SZ{Fo%r$VA$VWHwTrh6d=@_;!FvE6?(@Fr;PH6`?`d4Scu#@97(XF2 z@igtlUl(uC!E^gYuRxE_FU`FnToYeNu73>=Ue{Ow_4v&YqKv;I_yLQrLDRMHJf1de t30~?L0$7quy7EjEZHLEpcwi}u9xq_JWbos&$}`|n)j`0ujzV(z{{TiHfzki~ literal 0 HcmV?d00001 diff --git a/targets/TARGET_Silicon_Labs/mbed_rtx.h b/targets/TARGET_Silicon_Labs/mbed_rtx.h index 1a8c5a2ab9..69e953272e 100644 --- a/targets/TARGET_Silicon_Labs/mbed_rtx.h +++ b/targets/TARGET_Silicon_Labs/mbed_rtx.h @@ -115,6 +115,19 @@ extern uint32_t STACK$$Base; #define OS_MAINSTKSIZE 256 #endif +#elif defined(TARGET_EFR32MG12) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20040000UL) +#endif + +#ifndef OS_TASKCNT +#define OS_TASKCNT 14 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 256 +#endif + #endif #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index 1297e9a507..c55d0e0d47 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2335,6 +2335,53 @@ "macro_name": "HFRCO_FREQUENCY_ENUM" } } + }, + "EFR32MG12P332F1024GL125": { + "inherits": ["EFM32"], + "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL"], + "core": "Cortex-M4F", + "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], + "release_versions": ["2", "5"], + "device_name": "EFR32MG12P332F1024GL125", + "public": false + }, + "THUNDERBOARD_SENSE_12": { + "inherits": ["EFR32MG12P332F1024GL125"], + "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "forced_reset_timeout": 5, + "config": { + "hf_clock_src": { + "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator", + "value": "HFXO", + "macro_name": "CORE_CLOCK_SOURCE" + }, + "hfxo_clock_freq": { + "help": "Value: External crystal frequency in hertz", + "value": "38400000", + "macro_name": "HFXO_FREQUENCY" + }, + "lf_clock_src": { + "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator", + "value": "LFXO", + "macro_name": "LOW_ENERGY_CLOCK_SOURCE" + }, + "lfxo_clock_freq": { + "help": "Value: External crystal frequency in hertz", + "value": "32768", + "macro_name": "LFXO_FREQUENCY" + }, + "hfrco_clock_freq": { + "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select", + "value": "32000000", + "macro_name": "HFRCO_FREQUENCY" + }, + "hfrco_band_select": { + "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!", + "value": "cmuHFRCOFreq_32M0Hz", + "macro_name": "HFRCO_FREQUENCY_ENUM" + } + } }, "WIZWIKI_W7500": { "supported_form_factors": ["ARDUINO"], From 1a8c460378f9e4923081114e8fabcf336d045a05 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Mon, 13 Mar 2017 18:23:37 +0100 Subject: [PATCH 02/10] Update to Gecko SDK 5.1.2 Updating emlib --- .../TARGET_EFM32/emlib/Changes_emlib.txt | 41 + .../TARGET_EFM32/emlib/inc/em_acmp.h | 36 +- .../TARGET_EFM32/emlib/inc/em_adc.h | 23 +- .../TARGET_EFM32/emlib/inc/em_aes.h | 2 +- .../TARGET_EFM32/emlib/inc/em_assert.h | 2 +- .../TARGET_EFM32/emlib/inc/em_burtc.h | 2 +- .../TARGET_EFM32/emlib/inc/em_bus.h | 17 +- .../TARGET_EFM32/emlib/inc/em_chip.h | 57 +- .../TARGET_EFM32/emlib/inc/em_cmu.h | 49 +- .../TARGET_EFM32/emlib/inc/em_common.h | 38 +- .../TARGET_EFM32/emlib/inc/em_core.h | 2 +- .../TARGET_EFM32/emlib/inc/em_cryotimer.h | 2 +- .../TARGET_EFM32/emlib/inc/em_crypto.h | 2 +- .../TARGET_EFM32/emlib/inc/em_csen.h | 778 ++++++++++ .../TARGET_EFM32/emlib/inc/em_dac.h | 2 +- .../TARGET_EFM32/emlib/inc/em_dbg.h | 2 +- .../TARGET_EFM32/emlib/inc/em_dma.h | 12 +- .../TARGET_EFM32/emlib/inc/em_ebi.h | 2 +- .../TARGET_EFM32/emlib/inc/em_emu.h | 367 +++-- .../TARGET_EFM32/emlib/inc/em_gpcrc.h | 2 +- .../TARGET_EFM32/emlib/inc/em_gpio.h | 217 ++- .../TARGET_EFM32/emlib/inc/em_i2c.h | 15 +- .../TARGET_EFM32/emlib/inc/em_idac.h | 2 +- .../TARGET_EFM32/emlib/inc/em_int.h | 2 +- .../TARGET_EFM32/emlib/inc/em_lcd.h | 2 +- .../TARGET_EFM32/emlib/inc/em_ldma.h | 190 ++- .../TARGET_EFM32/emlib/inc/em_lesense.h | 376 +++-- .../TARGET_EFM32/emlib/inc/em_letimer.h | 2 +- .../TARGET_EFM32/emlib/inc/em_leuart.h | 2 +- .../TARGET_EFM32/emlib/inc/em_mpu.h | 2 +- .../TARGET_EFM32/emlib/inc/em_msc.h | 4 +- .../TARGET_EFM32/emlib/inc/em_opamp.h | 811 +++++++++- .../TARGET_EFM32/emlib/inc/em_pcnt.h | 2 +- .../TARGET_EFM32/emlib/inc/em_prs.h | 2 +- .../TARGET_EFM32/emlib/inc/em_ramfunc.h | 2 +- .../TARGET_EFM32/emlib/inc/em_rmu.h | 2 +- .../TARGET_EFM32/emlib/inc/em_rtc.h | 2 +- .../TARGET_EFM32/emlib/inc/em_rtcc.h | 59 +- .../TARGET_EFM32/emlib/inc/em_smu.h | 466 ++++++ .../TARGET_EFM32/emlib/inc/em_system.h | 136 +- .../TARGET_EFM32/emlib/inc/em_timer.h | 92 +- .../TARGET_EFM32/emlib/inc/em_usart.h | 4 +- .../TARGET_EFM32/emlib/inc/em_vcmp.h | 2 +- .../TARGET_EFM32/emlib/inc/em_vdac.h | 420 +++++ .../TARGET_EFM32/emlib/inc/em_version.h | 8 +- .../TARGET_EFM32/emlib/inc/em_wdog.h | 2 +- .../TARGET_EFM32/emlib/src/em_acmp.c | 31 +- .../TARGET_EFM32/emlib/src/em_adc.c | 17 +- .../TARGET_EFM32/emlib/src/em_aes.c | 2 +- .../TARGET_EFM32/emlib/src/em_assert.c | 2 +- .../TARGET_EFM32/emlib/src/em_burtc.c | 2 +- .../TARGET_EFM32/emlib/src/em_cmu.c | 262 +++- .../TARGET_EFM32/emlib/src/em_core.c | 16 +- .../TARGET_EFM32/emlib/src/em_cryotimer.c | 2 +- .../TARGET_EFM32/emlib/src/em_crypto.c | 11 +- .../TARGET_EFM32/emlib/src/em_csen.c | 294 ++++ .../TARGET_EFM32/emlib/src/em_dac.c | 2 +- .../TARGET_EFM32/emlib/src/em_dbg.c | 2 +- .../TARGET_EFM32/emlib/src/em_dma.c | 18 +- .../TARGET_EFM32/emlib/src/em_ebi.c | 2 +- .../TARGET_EFM32/emlib/src/em_emu.c | 1350 ++++++++++------- .../TARGET_EFM32/emlib/src/em_gpcrc.c | 2 +- .../TARGET_EFM32/emlib/src/em_gpio.c | 12 +- .../TARGET_EFM32/emlib/src/em_i2c.c | 18 +- .../TARGET_EFM32/emlib/src/em_idac.c | 5 +- .../TARGET_EFM32/emlib/src/em_int.c | 2 +- .../TARGET_EFM32/emlib/src/em_lcd.c | 2 +- .../TARGET_EFM32/emlib/src/em_ldma.c | 2 +- .../TARGET_EFM32/emlib/src/em_lesense.c | 343 ++++- .../TARGET_EFM32/emlib/src/em_letimer.c | 2 +- .../TARGET_EFM32/emlib/src/em_leuart.c | 2 +- .../TARGET_EFM32/emlib/src/em_mpu.c | 2 +- .../TARGET_EFM32/emlib/src/em_msc.c | 111 +- .../TARGET_EFM32/emlib/src/em_opamp.c | 287 +++- .../TARGET_EFM32/emlib/src/em_pcnt.c | 2 +- .../TARGET_EFM32/emlib/src/em_prs.c | 2 +- .../TARGET_EFM32/emlib/src/em_rmu.c | 8 +- .../TARGET_EFM32/emlib/src/em_rtc.c | 2 +- .../TARGET_EFM32/emlib/src/em_rtcc.c | 2 +- .../TARGET_EFM32/emlib/src/em_system.c | 18 +- .../TARGET_EFM32/emlib/src/em_timer.c | 2 +- .../TARGET_EFM32/emlib/src/em_usart.c | 50 +- .../TARGET_EFM32/emlib/src/em_vcmp.c | 2 +- .../TARGET_EFM32/emlib/src/em_vdac.c | 437 ++++++ .../TARGET_EFM32/emlib/src/em_wdog.c | 2 +- 85 files changed, 6282 insertions(+), 1310 deletions(-) create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt index 2e8ebff97b..c7eda3458e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt @@ -1,4 +1,45 @@ ================ Revision history ============================================ +5.1.2: + Misc. bugfixes and improvements. + +5.1.1: + - Enabled errata CMU_E113 workaround for EFM32GG revE. + +5.1.0: + - em_timer: Added support for WTIMER0 and WTIMER1. Added EFM_ASSERT in + em_timer to check that operations on a 16 bit timer is always <= 0xFFFF. + - em_usart: Updated the baudrate sync calculation in USART_BaudrateSyncSet(). + The calculated baudrate is not using any fractional bits and it is always + lower than or equal to the specified frequency. + - em_emu: added function EMU_DCDCConductionModeSet() to allow switching + between DCDC Low-Noise Continuous Conduction Mode (CCM) and + Discontinuous Conduction Mode (DCM). + - SYSTEM_GetSRAMSize() updated to return size of SRAM excluding RAMH for EFR32xG1. + - em_csen: Added support for CSEN (Capacitive Sense Module). + - em_adc: updated ADC_PosSel_TypeDef enum names. + - em_vdac: Added support for VDAC (voltage DAC). + - em_smu: Added support for SMU (Security Management Unit) module. + SMU is used to restrict access to device peripherals. + - Updated emlib to use the _SILICON_LABS_32B_SERIES_x, + _SILICON_LABS_32B_SERIES_x_CONFIG and _SILICON_LABS_GECKO_INTERNAL_SDID_x + macros instead of the _SILICON_LABS_32B_PLATFORM_x and + _SILICON_LABS_32B_PLATFORM_x_GEN_x macros. + - em_rtcc: added workarounds for errata RTCC_E203 and RTCC_E204 for + EFR32xG12, EFM32xG12, EFR32xG13 and EFM32xG13 devices. + - em_lesense: added LESENSE_DecoderPrsOut() for configuring PRS output + from the LESENSE decoder on EFM32xG12 and EFR32xG12. + - em_lesense: added support for the new evaluation modes for EFM32xG12 and + EFR32xG12. + - em_emu: added EMU_RamPowerDown() function for powering down a memory range + and deprecating EMU_MemPwrDown(). + - em_emu: added support for voltage scaling. + - em_emu: added support for EM2 and 3 peripheral retention control. + - em_chip: added current consumption fixes for EFM32xG12 and EFR32xG12. + - em_emu: added support for DCDC EM01-LP mode. + - em_lesense: Support for Series 1 devices + - em_acmp: Added ACMP_ExternalInputSelect() which is used when the ACMP is + controlled by an external module like LESENSE. + 5.0.0: - em_core: New module, contains API for enabling/disabling interrupts and implementing critical regions. diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h index 19345e9a97..ed9de1b4dd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_acmp.h * @brief Analog Comparator (ACMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -283,7 +283,7 @@ typedef enum } ACMP_VLPInput_Typedef; #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2) +#if defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0) /** ACMP Input Selection */ typedef enum { @@ -447,8 +447,12 @@ typedef enum acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14, acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15, acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31, +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT0) acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0, +#endif +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT1) acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1, +#endif acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP, acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV, acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV, @@ -500,6 +504,31 @@ typedef enum } ACMP_Channel_TypeDef; #endif +#if defined(_ACMP_EXTIFCTRL_MASK) +/** + * ACMP External input select. This type is used to select which APORT that is + * used by an external module like LESENSE when it's taking control over + * the ACMP input. + */ +typedef enum +{ + acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X, + acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y, + acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X, + acmpExternalInputAPORT1Y = _ACMP_EXTIFCTRL_APORTSEL_APORT1Y, + acmpExternalInputAPORT1XY = _ACMP_EXTIFCTRL_APORTSEL_APORT1XY, + acmpExternalInputAPORT2X = _ACMP_EXTIFCTRL_APORTSEL_APORT2X, + acmpExternalInputAPORT2Y = _ACMP_EXTIFCTRL_APORTSEL_APORT2Y, + acmpExternalInputAPORT2YX = _ACMP_EXTIFCTRL_APORTSEL_APORT2YX, + acmpExternalInputAPORT3X = _ACMP_EXTIFCTRL_APORTSEL_APORT3X, + acmpExternalInputAPORT3Y = _ACMP_EXTIFCTRL_APORTSEL_APORT3Y, + acmpExternalInputAPORT3XY = _ACMP_EXTIFCTRL_APORTSEL_APORT3XY, + acmpExternalInputAPORT4X = _ACMP_EXTIFCTRL_APORTSEL_APORT4X, + acmpExternalInputAPORT4Y = _ACMP_EXTIFCTRL_APORTSEL_APORT4Y, + acmpExternalInputAPORT4YX = _ACMP_EXTIFCTRL_APORTSEL_APORT4YX, +} ACMP_ExternalInput_Typedef; +#endif + /******************************************************************************* ****************************** STRUCTS ************************************ ******************************************************************************/ @@ -824,6 +853,9 @@ void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel); void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, ACMP_Channel_TypeDef posSel); void ACMP_Disable(ACMP_TypeDef *acmp); void ACMP_Enable(ACMP_TypeDef *acmp); +#if defined(_ACMP_EXTIFCTRL_MASK) +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport); +#endif void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert); void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init); void ACMP_Reset(ACMP_TypeDef *acmp); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h index 0cd23c792a..08bb52614d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_adc.h * @brief Analog to Digital Converter (ADC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -494,25 +494,26 @@ typedef enum adcPosSelAPORT4YCH30 = _ADC_SINGLECTRL_POSSEL_APORT4YCH30, adcPosSelAPORT4XCH31 = _ADC_SINGLECTRL_POSSEL_APORT4XCH31, adcPosSelAVDD = _ADC_SINGLECTRL_POSSEL_AVDD, - adcPosSelBU = _ADC_SINGLECTRL_POSSEL_BU, - adcPosSelAREG = _ADC_SINGLECTRL_POSSEL_AREG, - adcPosSelVREGOUTPA = _ADC_SINGLECTRL_POSSEL_VREGOUTPA, - adcPosSelPDBU = _ADC_SINGLECTRL_POSSEL_PDBU, - adcPosSelIO0 = _ADC_SINGLECTRL_POSSEL_IO0, - adcPosSelIO1 = _ADC_SINGLECTRL_POSSEL_IO1, - adcPosSelVSP = _ADC_SINGLECTRL_POSSEL_VSP, + adcPosSelDVDD = _ADC_SINGLECTRL_POSSEL_AREG, + adcPosSelPAVDD = _ADC_SINGLECTRL_POSSEL_VREGOUTPA, + adcPosSelDECOUPLE = _ADC_SINGLECTRL_POSSEL_PDBU, + adcPosSelIOVDD = _ADC_SINGLECTRL_POSSEL_IO0, adcPosSelOPA2 = _ADC_SINGLECTRL_POSSEL_OPA2, adcPosSelOPA3 = _ADC_SINGLECTRL_POSSEL_OPA3, adcPosSelTEMP = _ADC_SINGLECTRL_POSSEL_TEMP, adcPosSelDAC0OUT0 = _ADC_SINGLECTRL_POSSEL_DAC0OUT0, - adcPosSelTESTP = _ADC_SINGLECTRL_POSSEL_TESTP, - adcPosSelSP1 = _ADC_SINGLECTRL_POSSEL_SP1, - adcPosSelSP2 = _ADC_SINGLECTRL_POSSEL_SP2, adcPosSelDAC0OUT1 = _ADC_SINGLECTRL_POSSEL_DAC0OUT1, adcPosSelSUBLSB = _ADC_SINGLECTRL_POSSEL_SUBLSB, adcPosSelDEFAULT = _ADC_SINGLECTRL_POSSEL_DEFAULT, adcPosSelVSS = _ADC_SINGLECTRL_POSSEL_VSS } ADC_PosSel_TypeDef; + +/* Map legacy or incorrectly named select enums to correct enums. */ +#define adcPosSelIO0 adcPosSelIOVDD +#define adcPosSelVREGOUTPA adcPosSelPAVDD +#define adcPosSelAREG adcPosSelDVDD +#define adcPosSelPDBU adcPosSelDECOUPLE + #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h index b7aee281d9..63c76353f4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_aes.h * @brief Advanced encryption standard (AES) accelerator peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h index fb4d2f0d93..d0a2a92259 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_assert.h * @brief Emlib peripheral API "assert" implementation. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h index 1303111ef9..5787aa377c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_burtc.h * @brief Backup Real Time Counter (BURTC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h index c775e3437a..fc13eaf9f3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bus.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_bus.h * @brief RAM and peripheral bit-field set and clear API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -30,8 +30,8 @@ * ******************************************************************************/ -#ifndef EM_BUS__ -#define EM_BUS__ +#ifndef EM_BUS_H +#define EM_BUS_H #include "em_device.h" @@ -46,9 +46,9 @@ extern "C" { /***************************************************************************//** * @addtogroup BUS - * @brief BUS RAM and register bit/field read/write API + * @brief BUS register and RAM bit/field read/write API * @details - * API to perform bitbanded and masked accesses to SRAM and peripheral memory. + * API to perform bit-band and field set/clear access to RAM and peripherals. * @{ ******************************************************************************/ @@ -280,7 +280,10 @@ __STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, * @param[in] mask Peripheral register mask * * @param[in] val Peripheral register value. The value must be shifted to the - correct bit position in the register. + correct bit position in the register corresponding to the field + defined by the mask parameter. The register value must be + contained in the field defined by the mask parameter. This + function is not performing masking of val internally. ******************************************************************************/ __STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, @@ -326,4 +329,4 @@ __STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, } #endif -#endif /* EM_BUS__ */ +#endif /* EM_BUS_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h index 41979c626b..75989934b1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_chip.h * @brief Chip Initialization API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -49,7 +49,7 @@ extern "C" { /***************************************************************************//** * @addtogroup CHIP - * @brief Chip Initialization API + * @brief Chip errata workarounds initialization API * @details * API to initialize chip for errata workarounds. * @{ @@ -69,7 +69,7 @@ extern "C" { *****************************************************************************/ __STATIC_INLINE void CHIP_Init(void) { -#if defined(_EFM32_GECKO_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) uint32_t rev; SYSTEM_ChipRevision_TypeDef chipRev; volatile uint32_t *reg; @@ -161,26 +161,31 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_EFM32_GIANT_FAMILY) - uint32_t rev; +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + + /****************************/ + /* Fix for errata CMU_E113. */ + + uint8_t prodRev; SYSTEM_ChipRevision_TypeDef chipRev; - rev = *(volatile uint32_t *)(0x0FE081FC); + prodRev = SYSTEM_GetProdRev(); SYSTEM_ChipRevisionGet(&chipRev); - if (((rev >> 24) > 15) && (chipRev.minor == 3)) + if ((prodRev >= 16) && (chipRev.minor >= 3)) { /* This fixes an issue with the LFXO on high temperatures. */ *(volatile uint32_t*)0x400C80C0 = - ( *(volatile uint32_t*)0x400C80C0 & ~(1<<6) ) | (1<<4); + ( *(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); } #endif -#if defined(_EFM32_HAPPY_FAMILY) - uint32_t rev; - rev = *(volatile uint32_t *)(0x0FE081FC); +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) - if ((rev >> 24) <= 129) + uint8_t prodRev; + prodRev = SYSTEM_GetProdRev(); + + if (prodRev <= 129) { /* This fixes a mistaken internal connection between PC0 and PC4 */ /* This disables an internal pulldown on PC4 */ @@ -190,7 +195,7 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) /**************************** * Fixes for errata GPIO_E201 (slewrate) and @@ -244,11 +249,33 @@ __STATIC_INLINE void CHIP_Init(void) } #endif -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_2) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - /* No fixes required. */ + uint8_t prodRev = SYSTEM_GetProdRev(); + /* EM2 current fixes for early samples */ + if (prodRev == 0) + { + *(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198) |= (0x1 << 2); + *(volatile uint32_t *)(EMU_BASE + 0x190) = 0x0; + } + if (prodRev < 2) + { + *(volatile uint32_t *)(EMU_BASE + 0x164) |= (0x1 << 13); + } + + /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of vref */ + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) + | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES + | CMU_LFRCOCTRL_ENVREF; #endif + +#if defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) + MSC->CTRL |= 0x1 << 8; +#endif + + } /** @} (end addtogroup CHIP) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h index 733ae8c022..b049ff9881 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cmu.h * @brief Clock management unit (CMU) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -130,10 +130,15 @@ extern "C" { #define CMU_LCDPRE_CLK_BRANCH 19 #define CMU_LCD_CLK_BRANCH 20 #define CMU_LESENSE_CLK_BRANCH 21 +#define CMU_CSEN_LF_CLK_BRANCH 22 #define CMU_CLK_BRANCH_POS 17 #define CMU_CLK_BRANCH_MASK 0x1f +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/* Max clock frequency for VSCALE voltages */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000 +#endif /** @endcond */ /******************************************************************************* @@ -161,7 +166,7 @@ extern "C" { /** Clock divider configuration */ typedef uint32_t CMU_ClkDiv_TypeDef; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /** Clockprescaler configuration */ typedef uint32_t CMU_ClkPresc_TypeDef; #endif @@ -853,7 +858,7 @@ typedef enum | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), + | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), #endif #if defined( CMU_LFBCLKEN0_LEUART1 ) @@ -938,7 +943,10 @@ typedef enum cmuOsc_USHFRCO, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO ) - cmuOsc_ULFRCO /**< Ultra low frequency RC oscillator. */ + cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ +#endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */ #endif } CMU_Osc_TypeDef; @@ -953,24 +961,27 @@ typedef enum /** Selectable clock sources. */ typedef enum { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ - cmuSelect_HFXO, /**< High frequency crystal oscillator. */ - cmuSelect_HFRCO, /**< High frequency RC oscillator. */ - cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */ - cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */ - cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on - Tiny Gecko and for USBC (not used on Gecko) */ + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFRCO, /**< High frequency RC oscillator. */ + cmuSelect_HFCLKLE, /**< High frequency LE clock divided by 2 or 4. */ + cmuSelect_AUXHFRCO, /**< Auxilliary clock source can be used for debug clock */ + cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on + Tiny Gecko and for USBC (not used on Gecko) */ #if defined( CMU_STATUS_USHFRCOENS ) - cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */ + cmuSelect_USHFRCO, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 ) - cmuSelect_USHFRCODIV2,/**< USB high frequency RC oscillator */ + cmuSelect_USHFRCODIV2, /**< USB high frequency RC oscillator */ #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO ) - cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ +#endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */ #endif } CMU_Select_TypeDef; @@ -1192,7 +1203,7 @@ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, uint32_t presc); uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); #endif @@ -1441,7 +1452,7 @@ __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2) } -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Convert prescaler dividend to logarithmic value. Only works for even diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h index 03d00b53eb..e22df15fa5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_common.h * @brief General purpose utilities. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -107,6 +107,9 @@ extern "C" { /** MDK-ARM compiler: Macro for handling weak symbols. */ #define SL_WEAK __attribute__ ((weak)) +/** MDK-ARM compiler: Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + /** MDK-ARM compiler: Macro for handling section placement */ #define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) #endif @@ -118,6 +121,9 @@ extern "C" { /** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ #define SL_WEAK __weak +/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ +#define SL_NORETURN __noreturn + /** IAR Embedded Workbench: Macro for handling section placement */ #define SL_ATTRIBUTE_SECTION(X) @ X #endif @@ -164,6 +170,9 @@ extern "C" { /** @brief Macro for defining a weak symbol. */ #define SL_WEAK __attribute__ ((weak)) +/** @brief Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + /** Macro for placing a variable in a section. * @n Use this macro after the variable definition, before the = or ;. * @n X denotes the section to place the variable in. @@ -174,13 +183,13 @@ extern "C" { /***************************************************************************//** * @brief - * Count trailing number of zero's. Use CLZ instruction if available. + * Count trailing number of zeros. Use CLZ instruction if available. * * @param[in] value * Data value to check for number of trailing zero bits. * * @return - * Number of trailing zero's in value. + * Number of trailing zeros in value. ******************************************************************************/ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value) { @@ -194,31 +203,14 @@ __STATIC_INLINE uint32_t SL_CTZ(uint32_t value) #endif } -/***************************************************************************//** - * @brief - * Count trailing number of zero's. Use CLZ instruction if available. - * - * @deprecated - * Deprecated function. New code should use @ref SL_CTZ(). - * @param[in] value - * Data value to check for number of trailing zero bits. - * - * @return - * Number of trailing zero's in value. - ******************************************************************************/ +/* Deprecated function. New code should use @ref SL_CTZ. */ __STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) { -#if (__CORTEX_M >= 3) - return __CLZ(__RBIT(value)); - -#else - uint32_t zeros; - for(zeros=0; (zeros<32) && ((value&0x1) == 0); zeros++, value>>=1); - return zeros; -#endif + return SL_CTZ(value); } + /** @} (end addtogroup COMMON) */ /** @} (end addtogroup emlib) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h index c30af03047..45131f3fba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_core.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_core.h * @brief Core interrupt handling API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h index 4ae47098bd..43403b81e8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cryotimer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cryotimer.h * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h index 3b44aa1585..977f9da95a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_crypto.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_crypto.h * @brief Cryptography accelerator peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h new file mode 100644 index 0000000000..aacf4cbc25 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_csen.h @@ -0,0 +1,778 @@ +/***************************************************************************//** + * @file em_csen.h + * @brief Capacitive Sense Module (CSEN) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_CSEN_H +#define EM_CSEN_H + +#include "em_device.h" +#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 ) + +#include +#include "em_bus.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup CSEN + * @brief Capacitive Sense (CSEN) Peripheral API + * + * @details + * This module provides functions for controlling the capacitive sense + * peripheral of Silicon Labs 32-bit MCUs and SoCs. The CSEN includes a + * capacitance-to-digital circuit that measures capacitance on selected + * inputs. Measurements are performed using either a successive approximation + * register (SAR) or a delta modulator (DM) analog to digital converter. + * + * The CSEN can be configured to measure capacitance on a single port pin + * or to automatically measure multiple port pins in succession using scan + * mode. Also several port pins can be shorted together to measure the + * combined capacitance. + * + * The CSEN includes an accumulator which can be configured to average + * multiple conversions on the selected input. Additionally, an exponential + * moving average (EMA) calculator is included to provide data smoothing. + * A comparator is also included and can be used to terminate a continuous + * conversion when the configured threshold condition is met. + * + * The following example shows how to intialize and start a single + * conversion on one input: + * + * @include em_csen_single.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Comparator Mode. Selects the operation of the digital comparator. */ +typedef enum +{ + /** Comparator is disabled. */ + csenCmpModeDisabled = 0, + + /** Comparator trips when the result is greater than the threshold. */ + csenCmpModeGreater = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_GT, + + /** Comparator trips when the result is less or equal to the threshold. */ + csenCmpModeLessOrEqual = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_LTE, + + /** Comparator trips when the EMA is within the threshold window. */ + csenCmpModeEMAWindow = CSEN_CTRL_EMACMPEN, +} CSEN_CmpMode_TypeDef; + + +/** Converter Select. Determines the converter operational mode. */ +typedef enum +{ + /** Successive Approximation (SAR) converter. */ + csenConvSelSAR = CSEN_CTRL_CONVSEL_SAR, + + /** Successive Approximation (SAR) converter with low freq attenuation. */ + csenConvSelSARChop = CSEN_CTRL_CONVSEL_SAR | CSEN_CTRL_CHOPEN_ENABLE, + + /** Delta Modulation (DM) converter. */ + csenConvSelDM = CSEN_CTRL_CONVSEL_DM, + + /** Delta Modulation (DM) converter with low frequency attenuation. */ + csenConvSelDMChop = CSEN_CTRL_CONVSEL_DM | CSEN_CTRL_CHOPEN_ENABLE, +} CSEN_ConvSel_TypeDef; + + +/** Sample Mode. Determines how inputs are sampled for a conversion. */ +typedef enum +{ + /** Convert multiple inputs shorted together and stop. */ + csenSampleModeBonded = CSEN_CTRL_CM_SGL | CSEN_CTRL_MCEN_ENABLE, + + /** Convert one input and stop. */ + csenSampleModeSingle = CSEN_CTRL_CM_SGL, + + /** Convert multiple inputs one at a time and stop. */ + csenSampleModeScan = CSEN_CTRL_CM_SCAN, + + /** Continuously convert multiple inputs shorted together. */ + csenSampleModeContBonded = CSEN_CTRL_CM_CONTSGL | CSEN_CTRL_MCEN_ENABLE, + + /** Continuously convert one input. */ + csenSampleModeContSingle = CSEN_CTRL_CM_CONTSGL, + + /** Continuously convert multiple inputs one at a time. */ + csenSampleModeContScan = CSEN_CTRL_CM_CONTSCAN, +} CSEN_SampleMode_TypeDef; + + +/** Start Trigger Select. */ +typedef enum +{ + csenTrigSelPRS = _CSEN_CTRL_STM_PRS, /**< PRS system. */ + csenTrigSelTimer = _CSEN_CTRL_STM_TIMER, /**< CSEN PC timer. */ + csenTrigSelStart = _CSEN_CTRL_STM_START, /**< Start bit. */ +} CSEN_TrigSel_TypeDef; + + +/** Accumulator Mode Select. */ +typedef enum +{ + csenAccMode1 = _CSEN_CTRL_ACU_ACC1, /**< Accumulate 1 sample. */ + csenAccMode2 = _CSEN_CTRL_ACU_ACC2, /**< Accumulate 2 samples. */ + csenAccMode4 = _CSEN_CTRL_ACU_ACC4, /**< Accumulate 4 samples. */ + csenAccMode8 = _CSEN_CTRL_ACU_ACC8, /**< Accumulate 8 samples. */ + csenAccMode16 = _CSEN_CTRL_ACU_ACC16, /**< Accumulate 16 samples. */ + csenAccMode32 = _CSEN_CTRL_ACU_ACC32, /**< Accumulate 32 samples. */ + csenAccMode64 = _CSEN_CTRL_ACU_ACC64, /**< Accumulate 64 samples. */ +} CSEN_AccMode_TypeDef; + + +/** Successive Approximation (SAR) Conversion Resolution. */ +typedef enum +{ + csenSARRes10 = _CSEN_CTRL_SARCR_CLK10, /**< 10-bit resolution. */ + csenSARRes12 = _CSEN_CTRL_SARCR_CLK12, /**< 12-bit resolution. */ + csenSARRes14 = _CSEN_CTRL_SARCR_CLK14, /**< 14-bit resolution. */ + csenSARRes16 = _CSEN_CTRL_SARCR_CLK16, /**< 16-bit resolution. */ +} CSEN_SARRes_TypeDef; + + +/** Delta Modulator (DM) Conversion Resolution. */ +typedef enum +{ + csenDMRes10 = _CSEN_DMCFG_CRMODE_DM10, /**< 10-bit resolution. */ + csenDMRes12 = _CSEN_DMCFG_CRMODE_DM12, /**< 12-bit resolution. */ + csenDMRes14 = _CSEN_DMCFG_CRMODE_DM14, /**< 14-bit resolution. */ + csenDMRes16 = _CSEN_DMCFG_CRMODE_DM16, /**< 16-bit resolution. */ +} CSEN_DMRes_TypeDef; + + +/** Period counter clock pre-scaler. See the reference manual for source clock + * information. */ +typedef enum +{ + csenPCPrescaleDiv1 = _CSEN_TIMCTRL_PCPRESC_DIV1, /**< Divide by 1. */ + csenPCPrescaleDiv2 = _CSEN_TIMCTRL_PCPRESC_DIV2, /**< Divide by 2. */ + csenPCPrescaleDiv4 = _CSEN_TIMCTRL_PCPRESC_DIV4, /**< Divide by 4. */ + csenPCPrescaleDiv8 = _CSEN_TIMCTRL_PCPRESC_DIV8, /**< Divide by 8. */ + csenPCPrescaleDiv16 = _CSEN_TIMCTRL_PCPRESC_DIV16, /**< Divide by 16. */ + csenPCPrescaleDiv32 = _CSEN_TIMCTRL_PCPRESC_DIV32, /**< Divide by 32. */ + csenPCPrescaleDiv64 = _CSEN_TIMCTRL_PCPRESC_DIV64, /**< Divide by 64. */ + csenPCPrescaleDiv128 = _CSEN_TIMCTRL_PCPRESC_DIV128, /**< Divide by 128. */ +} CSEN_PCPrescale_TypeDef; + + +/** Exponential Moving Average sample weight. */ +typedef enum +{ + csenEMASampleW1 = _CSEN_EMACTRL_EMASAMPLE_W1, /**< Weight 1. */ + csenEMASampleW2 = _CSEN_EMACTRL_EMASAMPLE_W2, /**< Weight 2. */ + csenEMASampleW4 = _CSEN_EMACTRL_EMASAMPLE_W4, /**< Weight 4. */ + csenEMASampleW8 = _CSEN_EMACTRL_EMASAMPLE_W8, /**< Weight 8. */ + csenEMASampleW16 = _CSEN_EMACTRL_EMASAMPLE_W16, /**< Weight 16. */ + csenEMASampleW32 = _CSEN_EMACTRL_EMASAMPLE_W32, /**< Weight 32. */ + csenEMASampleW64 = _CSEN_EMACTRL_EMASAMPLE_W64, /**< Weight 64. */ +} CSEN_EMASample_TypeDef; + + +/** Reset Phase Timing Select (units are microseconds). */ +typedef enum +{ + csenResetPhaseSel0 = 0, /**< Reset phase time = 0.75 usec. */ + csenResetPhaseSel1 = 1, /**< Reset phase time = 1.00 usec. */ + csenResetPhaseSel2 = 2, /**< Reset phase time = 1.20 usec. */ + csenResetPhaseSel3 = 3, /**< Reset phase time = 1.50 usec. */ + csenResetPhaseSel4 = 4, /**< Reset phase time = 2.00 usec. */ + csenResetPhaseSel5 = 5, /**< Reset phase time = 3.00 usec. */ + csenResetPhaseSel6 = 6, /**< Reset phase time = 6.00 usec. */ + csenResetPhaseSel7 = 7, /**< Reset phase time = 12.0 usec. */ +} CSEN_ResetPhaseSel_TypeDef; + + +/** Drive Strength Select. Scales the output current. */ +typedef enum +{ + csenDriveSelFull = 0, /**< Drive strength = fully on. */ + csenDriveSel1 = 1, /**< Drive strength = 1/8 full scale. */ + csenDriveSel2 = 2, /**< Drive strength = 1/4 full scale. */ + csenDriveSel3 = 3, /**< Drive strength = 3/8 full scale. */ + csenDriveSel4 = 4, /**< Drive strength = 1/2 full scale. */ + csenDriveSel5 = 5, /**< Drive strength = 5/8 full scale. */ + csenDriveSel6 = 6, /**< Drive strength = 3/4 full scale. */ + csenDriveSel7 = 7, /**< Drive strength = 7/8 full scale. */ +} CSEN_DriveSel_TypeDef; + + +/** Gain Select. See reference manual for information on each setting. */ +typedef enum +{ + csenGainSel1X = 0, /**< Gain = 1x. */ + csenGainSel2X = 1, /**< Gain = 2x. */ + csenGainSel3X = 2, /**< Gain = 3x. */ + csenGainSel4X = 3, /**< Gain = 4x. */ + csenGainSel5X = 4, /**< Gain = 5x. */ + csenGainSel6X = 5, /**< Gain = 6x. */ + csenGainSel7X = 6, /**< Gain = 7x. */ + csenGainSel8X = 7, /**< Gain = 8x. */ +} CSEN_GainSel_TypeDef; + + +/** Peripheral Reflex System signal used to trigger conversion. */ +typedef enum +{ + csenPRSSELCh0 = _CSEN_PRSSEL_PRSSEL_PRSCH0, /**< PRS channel 0. */ + csenPRSSELCh1 = _CSEN_PRSSEL_PRSSEL_PRSCH1, /**< PRS channel 1. */ + csenPRSSELCh2 = _CSEN_PRSSEL_PRSSEL_PRSCH2, /**< PRS channel 2. */ + csenPRSSELCh3 = _CSEN_PRSSEL_PRSSEL_PRSCH3, /**< PRS channel 3. */ + csenPRSSELCh4 = _CSEN_PRSSEL_PRSSEL_PRSCH4, /**< PRS channel 4. */ + csenPRSSELCh5 = _CSEN_PRSSEL_PRSSEL_PRSCH5, /**< PRS channel 5. */ + csenPRSSELCh6 = _CSEN_PRSSEL_PRSSEL_PRSCH6, /**< PRS channel 6. */ + csenPRSSELCh7 = _CSEN_PRSSEL_PRSSEL_PRSCH7, /**< PRS channel 7. */ + csenPRSSELCh8 = _CSEN_PRSSEL_PRSSEL_PRSCH8, /**< PRS channel 8. */ + csenPRSSELCh9 = _CSEN_PRSSEL_PRSSEL_PRSCH9, /**< PRS channel 9. */ + csenPRSSELCh10 = _CSEN_PRSSEL_PRSSEL_PRSCH10, /**< PRS channel 10. */ + csenPRSSELCh11 = _CSEN_PRSSEL_PRSSEL_PRSCH11, /**< PRS channel 11. */ +} CSEN_PRSSel_TypeDef; + + +/** APORT channel to CSEN input selection. */ +typedef enum +{ + csenInputSelDefault = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT, + csenInputSelAPORT1CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7, + csenInputSelAPORT1CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15, + csenInputSelAPORT1CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23, + csenInputSelAPORT1CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31, + csenInputSelAPORT3CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7, + csenInputSelAPORT3CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15, + csenInputSelAPORT3CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23, + csenInputSelAPORT3CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31, +} CSEN_InputSel_TypeDef; + + +/** APORT channel to CSEN single input selection. */ +typedef enum +{ + csenSingleSelDefault = _CSEN_SINGLECTRL_SINGLESEL_DEFAULT, + csenSingleSelAPORT1XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0, + csenSingleSelAPORT1YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1, + csenSingleSelAPORT1XCH2 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2, + csenSingleSelAPORT1YCH3 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3, + csenSingleSelAPORT1XCH4 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4, + csenSingleSelAPORT1YCH5 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5, + csenSingleSelAPORT1XCH6 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6, + csenSingleSelAPORT1YCH7 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7, + csenSingleSelAPORT1XCH8 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8, + csenSingleSelAPORT1YCH9 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9, + csenSingleSelAPORT1XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10, + csenSingleSelAPORT1YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11, + csenSingleSelAPORT1XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12, + csenSingleSelAPORT1YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13, + csenSingleSelAPORT1XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14, + csenSingleSelAPORT1YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15, + csenSingleSelAPORT1XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16, + csenSingleSelAPORT1YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17, + csenSingleSelAPORT1XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18, + csenSingleSelAPORT1YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19, + csenSingleSelAPORT1XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20, + csenSingleSelAPORT1YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21, + csenSingleSelAPORT1XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22, + csenSingleSelAPORT1YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23, + csenSingleSelAPORT1XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24, + csenSingleSelAPORT1YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25, + csenSingleSelAPORT1XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26, + csenSingleSelAPORT1YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27, + csenSingleSelAPORT1XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28, + csenSingleSelAPORT1YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29, + csenSingleSelAPORT1XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30, + csenSingleSelAPORT1YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31, + csenSingleSelAPORT3XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0, + csenSingleSelAPORT3YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1, + csenSingleSelAPORT3XCH2 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2, + csenSingleSelAPORT3YCH3 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3, + csenSingleSelAPORT3XCH4 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4, + csenSingleSelAPORT3YCH5 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5, + csenSingleSelAPORT3XCH6 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6, + csenSingleSelAPORT3YCH7 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7, + csenSingleSelAPORT3XCH8 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8, + csenSingleSelAPORT3YCH9 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9, + csenSingleSelAPORT3XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10, + csenSingleSelAPORT3YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11, + csenSingleSelAPORT3XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12, + csenSingleSelAPORT3YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13, + csenSingleSelAPORT3XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14, + csenSingleSelAPORT3YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15, + csenSingleSelAPORT3XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16, + csenSingleSelAPORT3YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17, + csenSingleSelAPORT3XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18, + csenSingleSelAPORT3YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19, + csenSingleSelAPORT3XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20, + csenSingleSelAPORT3YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21, + csenSingleSelAPORT3XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22, + csenSingleSelAPORT3YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23, + csenSingleSelAPORT3XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24, + csenSingleSelAPORT3YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25, + csenSingleSelAPORT3XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26, + csenSingleSelAPORT3YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27, + csenSingleSelAPORT3XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28, + csenSingleSelAPORT3YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29, + csenSingleSelAPORT3XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30, + csenSingleSelAPORT3YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31, +} CSEN_SingleSel_TypeDef; + + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** CSEN init structure, common for all measurement modes. */ +typedef struct +{ + /** Requests system charge pump high accuracy mode. */ + bool cpAccuracyHi; + + /** Disables external kelvin connection and senses capacitor locally. */ + bool localSense; + + /** Keeps the converter warm allowing continuous conversions. */ + bool keepWarm; + + /** Converter warmup time is warmUpCount + 3 converter clock cycles. */ + uint8_t warmUpCount; + + /** Period counter reload value. */ + uint8_t pcReload; + + /** Period counter pre-scaler. */ + CSEN_PCPrescale_TypeDef pcPrescale; + + /** Peripheral reflex system trigger selection. */ + CSEN_PRSSel_TypeDef prsSel; + + /** CSEN input to APORT channel mapping. */ + CSEN_InputSel_TypeDef input0To7; + CSEN_InputSel_TypeDef input8To15; + CSEN_InputSel_TypeDef input16To23; + CSEN_InputSel_TypeDef input24To31; + CSEN_InputSel_TypeDef input32To39; + CSEN_InputSel_TypeDef input40To47; + CSEN_InputSel_TypeDef input48To55; + CSEN_InputSel_TypeDef input56To63; +} CSEN_Init_TypeDef; + +#define CSEN_INIT_DEFAULT \ +{ \ + false, /* Charge pump low accuracy mode. */ \ + false, /* Use external kelvin connection. */ \ + false, /* Disable keep warm. */ \ + 0, /* 0+3 cycle warmup time. */ \ + 0, /* Period counter reload. */ \ + csenPCPrescaleDiv1, /* Period counter prescale. */ \ + csenPRSSELCh0, /* PRS channel 0. */ \ + csenInputSelAPORT1CH0TO7, /* input0To7 -> aport1ch0to7 */ \ + csenInputSelAPORT1CH8TO15, /* input8To15 -> aport1ch8to15 */ \ + csenInputSelAPORT1CH16TO23, /* input16To23 -> aport1ch16to23 */ \ + csenInputSelAPORT1CH24TO31, /* input24To31 -> aport1ch24to31 */ \ + csenInputSelAPORT3CH0TO7, /* input32To39 -> aport3ch0to7 */ \ + csenInputSelAPORT3CH8TO15, /* input40To47 -> aport3ch8to15 */ \ + csenInputSelAPORT3CH16TO23, /* input48To55 -> aport3ch16to23 */ \ + csenInputSelAPORT3CH24TO31, /* input56To63 -> aport3ch24to31 */ \ +} + + +/** Measurement mode init structure. */ +typedef struct +{ + /** Selects the conversion sample mode. */ + CSEN_SampleMode_TypeDef sampleMode; + + /** Selects the conversion trigger source. */ + CSEN_TrigSel_TypeDef trigSel; + + /** Enables DMA operation. */ + bool enableDma; + + /** Disables dividing the accumulated result. */ + bool sumOnly; + + /** Selects the number of samples to accumulate per conversion. */ + CSEN_AccMode_TypeDef accMode; + + /** Selects the Exponential Moving Average sample weighting. */ + CSEN_EMASample_TypeDef emaSample; + + /** Enables the comparator and selects the comparison type. */ + CSEN_CmpMode_TypeDef cmpMode; + + /** Comparator threshold value. Meaning depends on @p cmpMode. */ + uint16_t cmpThr; + + /** Selects an APORT channel for a single conversion. */ + CSEN_SingleSel_TypeDef singleSel; + + /** + * Mask selects inputs 0 to 31. Effect depends on @p sampleMode. If sample + * mode is bonded, then mask selects inputs to short together. If sample + * mode is scan, then mask selects which inputs will be scanned. If sample + * mode is single and auto-ground is on (@p autoGnd is true), mask selects + * which pins are grounded. + */ + uint32_t inputMask0; + + /** Mask selects inputs 32 to 63. See @p inputMask0 for more information. */ + uint32_t inputMask1; + + /** Ground inactive inputs during a conversion. */ + bool autoGnd; + + /** Selects the converter type. */ + CSEN_ConvSel_TypeDef convSel; + + /** Selects the Successive Approximation (SAR) converter resolution. */ + CSEN_SARRes_TypeDef sarRes; + + /** Selects the Delta Modulation (DM) converter resolution. */ + CSEN_DMRes_TypeDef dmRes; + + /** Sets the number of DM iterations (comparisons) per cycle. Only applies + * to the Delta Modulation converter. */ + uint8_t dmIterPerCycle; + + /** Sets number of DM converter cycles. Only applies to the + * Delta Modulation converter. */ + uint8_t dmCycles; + + /** Sets the DM converter initial delta value. Only applies to the + * Delta Modulation converter. */ + uint8_t dmDelta; + + /** Disable DM automatic delta size reduction per cycle. Only applies to the + * Delta Modulation converter. */ + bool dmFixedDelta; + + /** Selects the reset phase timing. Most measurements should use the default + * value. See reference manual for details on when to adjust. */ + CSEN_ResetPhaseSel_TypeDef resetPhase; + + /** Selects the output drive strength. Most measurements should use the + * default value. See reference manual for details on when to adjust. */ + CSEN_DriveSel_TypeDef driveSel; + + /** Selects the converter gain. */ + CSEN_GainSel_TypeDef gainSel; +} CSEN_InitMode_TypeDef; + +#define CSEN_INITMODE_DEFAULT \ +{ \ + csenSampleModeSingle, /* Sample one input and stop. */ \ + csenTrigSelStart, /* Use start bit to trigger. */ \ + false, /* Disable DMA. */ \ + false, /* Average the accumulated result. */ \ + csenAccMode1, /* Accumulate 1 sample. */ \ + csenEMASampleW1, /* Disable the EMA. */ \ + csenCmpModeDisabled, /* Disable the comparator. */ \ + 0, /* Comparator threshold not used. */ \ + csenSingleSelDefault, /* Disconnect the single input. */ \ + 0, /* Disable inputs 0 to 31. */ \ + 0, /* Disable inputs 32 to 63. */ \ + false, /* Do not ground inactive inputs. */ \ + csenConvSelSAR, /* Use the SAR converter. */ \ + csenSARRes10, /* Set SAR resolution to 10 bits. */ \ + csenDMRes10, /* Set DM resolution to 10 bits. */ \ + 0, /* Set DM conv/cycle to default. */ \ + 0, /* Set DM cycles to default. */ \ + 0, /* Set DM initial delta to default. */ \ + false, /* Use DM auto delta reduction. */ \ + csenResetPhaseSel0, /* Use shortest reset phase time. */ \ + csenDriveSelFull, /* Use full output current. */ \ + csenGainSel8X, /* Use highest converter gain. */ \ +} + + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get last conversion result. + * + * @note + * Check conversion busy flag before calling this function. In addition, + * the result width and format depend on the parameters passed to the + * @ref CSEN_InitMode() function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * Result data from last conversion. + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_DataGet(CSEN_TypeDef *csen) +{ + return csen->DATA; +} + +/***************************************************************************//** + * @brief + * Get last exponential moving average. + * + * @note + * Confirm CSEN is idle before calling this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * Exponential moving average from last conversion. + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_EMAGet(CSEN_TypeDef *csen) +{ + return (csen->EMA & _CSEN_EMA_EMA_MASK); +} + +/***************************************************************************//** + * @brief + * Set exponential moving average initial value. + * + * @note + * Call this function before starting a conversion. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] ema + * Initial value for the exponential moving average. + ******************************************************************************/ +__STATIC_INLINE void CSEN_EMASet(CSEN_TypeDef *csen, uint32_t ema) +{ + csen->EMA = ema & _CSEN_EMA_EMA_MASK; +} + +/***************************************************************************//** + * @brief + * Disables the CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Disable(CSEN_TypeDef *csen) +{ + BUS_RegBitWrite(&csen->CTRL, _CSEN_CTRL_EN_SHIFT, 0); +} + +/***************************************************************************//** + * @brief + * Enables the CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Enable(CSEN_TypeDef *csen) +{ + BUS_RegBitWrite(&csen->CTRL, _CSEN_CTRL_EN_SHIFT, 1); +} + +void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down); +void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init); +void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init); +void CSEN_Reset(CSEN_TypeDef *csen); + + +/***************************************************************************//** + * @brief + * Clear one or more pending CSEN interrupts. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * Pending CSEN interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntClear(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IFC = flags; +} + + +/***************************************************************************//** + * @brief + * Disable one or more CSEN interrupts. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntDisable(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IEN &= ~flags; +} + + +/***************************************************************************//** + * @brief + * Enable one or more CSEN interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using CSEN_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntEnable(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IEN |= flags; +} + + +/***************************************************************************//** + * @brief + * Get pending CSEN interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * CSEN interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_IntGet(CSEN_TypeDef *csen) +{ + return csen->IF; +} + + +/***************************************************************************//** + * @brief + * Get enabled and pending CSEN interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled CSEN interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in CSENx_IEN_nnn + * register (CSENx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the CSEN module + * (CSENx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen) +{ + uint32_t ien; + + /* Store CSENx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = csen->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return csen->IF & ien; +} + + +/***************************************************************************//** + * @brief + * Set one or more pending CSEN interrupts from SW. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] flags + * CSEN interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the CSEN module (CSEN_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void CSEN_IntSet(CSEN_TypeDef *csen, uint32_t flags) +{ + csen->IFS = flags; +} + + +/***************************************************************************//** + * @brief + * Return CSEN conversion busy status. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @return + * True if CSEN conversion is in progress. + ******************************************************************************/ +__STATIC_INLINE bool CSEN_IsBusy(CSEN_TypeDef *csen) +{ + return (bool)(csen->STATUS & _CSEN_STATUS_CSENBUSY_MASK); +} + + +/***************************************************************************//** + * @brief + * Start scan sequence and/or single conversion. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void CSEN_Start(CSEN_TypeDef *csen) +{ + csen->CMD = CSEN_CMD_START; +} + + +/** @} (end addtogroup CSEN) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */ +#endif /* EM_CSEN_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h index 4218d61138..e9df3b6051 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dac.h * @brief Digital to Analog Converter (DAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h index 0baca2a731..bc96fc93ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dbg.h * @brief Debug (DBG) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h index 5d557684f8..c79f23fbfc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dma.h * @brief Direct memory access (DMA) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -360,21 +360,21 @@ typedef struct void DMA_ActivateAuto(unsigned int channel, bool primary, void *dst, - void *src, + const void *src, unsigned int nMinus1); void DMA_ActivateBasic(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1); void DMA_ActivatePingPong(unsigned int channel, bool useBurst, void *primDst, - void *primSrc, + const void *primSrc, unsigned int primNMinus1, void *altDst, - void *altSrc, + const void *altSrc, unsigned int altNMinus1); void DMA_ActivateScatterGather(unsigned int channel, bool useBurst, @@ -446,7 +446,7 @@ void DMA_RefreshPingPong(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1, bool last); void DMA_Reset(void); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h index 8515bac98c..86c772a09e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ebi.h * @brief External Bus Iterface (EBI) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h index 0594f3cfd0..49ace57649 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_emu.h * @brief Energy management unit (EMU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -151,15 +151,13 @@ typedef enum } EMU_EM4PinRetention_TypeDef; #endif - -#if defined( _EMU_PWRCFG_MASK ) -/** Power configurations */ +/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ typedef enum { /** DCDC is connected to DVDD */ - emuPowerConfig_DcdcToDvdd = EMU_PWRCFG_PWRCFG_DCDCTODVDD, + emuPowerConfig_DcdcToDvdd, } EMU_PowerConfig_TypeDef; -#endif + #if defined( _EMU_DCDCCTRL_MASK ) /** DCDC operating modes */ @@ -176,6 +174,19 @@ typedef enum } EMU_DcdcMode_TypeDef; #endif +#if defined( _EMU_DCDCCTRL_MASK ) +/** DCDC conduction modes */ +typedef enum +{ + /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization + features are available in this mode. */ + emuDcdcConductionMode_ContinuousLN, + /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or + when the EFR32 radio is not enabled. */ + emuDcdcConductionMode_DiscontinuousLN, +} EMU_DcdcConductionMode_TypeDef; +#endif + #if defined( _EMU_PWRCTRL_MASK ) /** DCDC to DVDD mode analog peripheral power supply select */ typedef enum @@ -194,7 +205,7 @@ typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; /** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ #define emuDcdcLnHighEfficiency -1 -/** Deprecated. Fast transient response mode. Specify a reverse current limit instead. */ +/** Default reverse current for fast transient response mode (low noise). */ #define emuDcdcLnFastTransient 160 #endif @@ -258,7 +269,7 @@ typedef enum } EMU_VmonChannel_TypeDef; #endif /* EMU_STATUS_VMONRDY */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /** Bias mode configurations */ typedef enum { @@ -268,56 +279,184 @@ typedef enum } EMU_BiasMode_TypeDef; #endif +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** Supported EM0/1 Voltage Scaling Levels */ +typedef enum +{ + /** High-performance voltage level. HF clock can be set to any frequency. */ + emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, + /** Low-power optimized voltage level. The HF clock must be limited + to @ref CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. + EM0/1 voltage scaling is applied when the core clock frequency is + changed from @ref CMU or when calling @ref EMU_EM01Init() when the HF + clock is already below the limit. */ + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, +} EMU_VScaleEM01_TypeDef; +#endif + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) +/** Supported EM2/3 Voltage Scaling Levels */ +typedef enum +{ + /** Fast-wakeup voltage level. */ + emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 + adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ + emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, +} EMU_VScaleEM23_TypeDef; +#endif + +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) +/** Supported EM4H Voltage Scaling Levels */ +typedef enum +{ + /** Fast-wakeup voltage level. */ + emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM4H + adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ + emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, +} EMU_VScaleEM4H_TypeDef; +#endif + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/** Peripheral EM2 and 3 retention control */ +typedef enum +{ + emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control */ + emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control */ + emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control */ + emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control */ + emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control */ + emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control */ + emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK, /* Select DAC0 retention control */ + emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control */ + emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control */ + emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control */ + emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control */ +#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK ) + emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /* Select PCNT2 retention control */ + emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /* Select PCNT1 retention control */ +#endif + emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /* Select PCNT0 retention control */ + + emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */ + emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK + | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK +#if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK ) + | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK +#endif + | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select all peripherals in domain 2 */ + emuPeripheralRetention_ALL = emuPeripheralRetention_D1 + | emuPeripheralRetention_D2, /* Select all peripherals with retention control */ +} EMU_PeripheralRetention_TypeDef; +#endif + /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ -/** Energy Mode 2 and 3 initialization structure */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** EM0 and 1 initialization structure. Voltage scaling is applied when + the core clock frequency is changed from @ref CMU. EM0 an 1 emuVScaleEM01_HighPerformance + is always enabled. */ typedef struct { - bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */ + bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status */ +} EMU_EM01Init_TypeDef; +#endif + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/** Default initialization of EM0 and 1 configuration */ +#define EMU_EM01INIT_DEFAULT \ +{ \ + false /** Do not scale down in EM0/1 */ \ +} +#endif + +/** EM2 and 3 initialization structure */ +typedef struct +{ + bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */ +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level */ +#endif } EMU_EM23Init_TypeDef; /** Default initialization of EM2 and 3 configuration */ -#define EMU_EM23INIT_DEFAULT \ -{ false } /* Reduced voltage regulator drive strength in EM2 and EM3 */ - +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) +#define EMU_EM23INIT_DEFAULT \ +{ \ + false, /* Reduced voltage regulator drive strength in EM2/3 */ \ + emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3 */ \ +} +#else +#define EMU_EM23INIT_DEFAULT \ +{ \ + false, /* Reduced voltage regulator drive strength in EM2/3 */ \ +} +#endif #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) -/** Energy Mode 4 initialization structure */ +/** EM4 initialization structure */ typedef struct { #if defined( _EMU_EM4CONF_MASK ) - /* Init parameters for platforms with EMU->EM4CONF register */ - bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */ - bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */ - EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */ - bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */ - bool vreg; /**< Enable EM4 voltage regulator */ - + /* Init parameters for platforms with EMU->EM4CONF register (Series 0) */ + bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */ + bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */ + EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */ + bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */ + bool vreg; /**< Enable EM4 voltage regulator */ #elif defined( _EMU_EM4CTRL_MASK ) - /* Init parameters for platforms with EMU->EM4CTRL register */ + /* Init parameters for platforms with EMU->EM4CTRL register (Series 1) */ bool retainLfxo; /**< Disable the LFXO upon EM4 entry */ bool retainLfrco; /**< Disable the LFRCO upon EM4 entry */ bool retainUlfrco; /**< Disable the ULFRCO upon EM4 entry */ EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state */ EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode */ #endif +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) + EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level */ +#endif } EMU_EM4Init_TypeDef; #endif -/** Default initialization of EM4 configuration */ #if defined( _EMU_EM4CONF_MASK ) +/** Default initialization of EM4 configuration (Series 0) */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Dont't lock configuration after it's been set */ \ - false, /* No reset will be asserted due to Brownout when in EM4 */ \ + false, /* No reset will be asserted due to BOD in EM4 */ \ emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \ true, /* Wake up on EM4 BURTC interrupt */ \ true, /* Enable VREG */ \ } -#endif -#if defined( _EMU_EM4CTRL_MASK ) + +#elif defined( _EMU_CTRL_EM4HVSCALE_MASK ) +/** Default initialization of EM4 configuration (Series 1 with VSCALE) */ +#define EMU_EM4INIT_DEFAULT \ +{ \ + false, /* Retain LFXO configuration upon EM4 entry */ \ + false, /* Retain LFRCO configuration upon EM4 entry */ \ + false, /* Retain ULFRCO configuration upon EM4 entry */ \ + emuEM4Shutoff, /* Use EM4 shutoff state */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4 */ \ + emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H */ \ +} + +#elif defined( _EMU_EM4CTRL_MASK ) +/** Default initialization of EM4 configuration (Series 1 without VSCALE) */ #define EMU_EM4INIT_DEFAULT \ { \ false, /* Retain LFXO configuration upon EM4 entry */ \ @@ -380,7 +519,8 @@ typedef struct /** DCDC initialization structure */ typedef struct { - EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration */ + EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. + @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1 */ uint16_t mVout; /**< Target output voltage (mV) */ uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1 (mA). @@ -407,26 +547,11 @@ typedef struct /** Default DCDC initialization */ #if defined( _EFM_DEVICE ) -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG) && (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ - emuDcdcMode_LowNoise, /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ - 5, /* Nominal EM0/1 load current of less than 5mA */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source) */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ - emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ -} - -#else -#define EMU_DCDCINIT_DEFAULT \ -{ \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ - emuDcdcMode_LowNoise, /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */ \ + emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ 5, /* Nominal EM0/1 load current of less than 5mA */ \ 10, /* Nominal EM2/3/4 load current less than 10uA */ \ @@ -436,25 +561,24 @@ typedef struct emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ } +#else +#define EMU_DCDCINIT_DEFAULT \ +{ \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ + emuDcdcMode_LowPower, /* Low-power mode in EM0 */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ + 5, /* Nominal EM0/1 load current of less than 5mA */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source) */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ +} #endif #else /* EFR32 device */ -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG) && (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) -#define EMU_DCDCINIT_DEFAULT \ -{ \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ - emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ - 15, /* Nominal EM0/1 load current of less than 15mA */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source) */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ - 160, /* Maximum reverse current of 160mA */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ -} - -#else +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) #define EMU_DCDCINIT_DEFAULT \ { \ emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ @@ -468,6 +592,20 @@ typedef struct 160, /* Maximum reverse current of 160mA */ \ emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ } +#else +#define EMU_DCDCINIT_DEFAULT \ +{ \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ + emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ + 15, /* Nominal EM0/1 load current of less than 15mA */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source) */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ + 160, /* Maximum reverse current of 160mA */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ +} #endif #endif #endif @@ -522,6 +660,52 @@ typedef struct ***************************** PROTOTYPES ********************************** ******************************************************************************/ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); +#endif +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); +#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); +#endif +void EMU_EnterEM2(bool restore); +void EMU_EnterEM3(bool restore); +void EMU_Restore(void); +void EMU_EnterEM4(void); +#if defined( _EMU_EM4CTRL_MASK ) +void EMU_EnterEM4H(void); +void EMU_EnterEM4S(void); +#endif +void EMU_MemPwrDown(uint32_t blocks); +void EMU_RamPowerDown(uint32_t start, uint32_t end); +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); +#endif +void EMU_UpdateOscConfig(void); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); +#endif +#if defined( BU_PRESENT ) +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); +void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); +void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); +#endif +#if defined( _EMU_DCDCCTRL_MASK ) +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); +void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); +bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); +void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent); +void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); +bool EMU_DCDCPowerOff(void); +#endif +#if defined( EMU_STATUS_VMONRDY ) +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); +void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); +bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); +#endif + /***************************************************************************//** * @brief * Enter energy mode 1 (EM1). @@ -533,38 +717,35 @@ __STATIC_INLINE void EMU_EnterEM1(void) __WFI(); } -void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init); -#if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) -void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init); -#endif -void EMU_EnterEM2(bool restore); -void EMU_EnterEM3(bool restore); -void EMU_EnterEM4(void); -#if defined( _EMU_EM4CTRL_MASK ) -void EMU_EnterEM4H(void); -void EMU_EnterEM4S(void); -#endif -void EMU_MemPwrDown(uint32_t blocks); -void EMU_UpdateOscConfig(void); -#if defined( BU_PRESENT ) -void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit); -void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); -void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); -#endif -#if defined( _EMU_DCDCCTRL_MASK ) -bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit); -void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); -bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); -void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent); -void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); -bool EMU_DCDCPowerOff(void); -#endif -#if defined( EMU_STATUS_VMONRDY ) -void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit); -void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit); -void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); -bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); +#if defined( _EMU_STATUS_VSCALE_MASK ) +/***************************************************************************//** + * @brief + * Wait for voltage scaling to complete + ******************************************************************************/ +__STATIC_INLINE void EMU_VScaleWait(void) +{ + while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT)); +} +#endif + +#if defined( _EMU_STATUS_VSCALE_MASK ) +/***************************************************************************//** + * @brief + * Get current voltage scaling level + * + * @return + * Current voltage scaling level + ******************************************************************************/ +__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) +{ + EMU_VScaleWait(); + return (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); +} +#endif + +#if defined( _EMU_STATUS_VMONRDY_MASK ) /***************************************************************************//** * @brief * Get the status of the voltage monitor (VMON). @@ -577,7 +758,7 @@ __STATIC_INLINE bool EMU_VmonStatusGet(void) { return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT); } -#endif /* EMU_STATUS_VMONRDY */ +#endif /* _EMU_STATUS_VMONRDY_MASK */ #if defined( _EMU_IF_MASK ) /***************************************************************************//** @@ -805,7 +986,7 @@ __STATIC_INLINE void EMU_UnlatchPinRetention(void) } #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h index f66b4efe9d..5ce0660d4c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpcrc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h index ec09bdf8af..049d811497 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_gpio.h * @brief General Purpose IO (GPIO) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -68,6 +68,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 9 #define _GPIO_PORT_E_PIN_COUNT 12 #define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xF77F #define _GPIO_PORT_B_PIN_MASK 0x79F8 @@ -75,6 +80,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0x01FF #define _GPIO_PORT_E_PIN_MASK 0xFFF0 #define _GPIO_PORT_F_PIN_MASK 0x003F +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_HAPPY_FAMILY ) @@ -84,6 +94,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 4 #define _GPIO_PORT_E_PIN_COUNT 4 #define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x0707 #define _GPIO_PORT_B_PIN_MASK 0x6980 @@ -91,6 +106,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0x00F0 #define _GPIO_PORT_E_PIN_MASK 0x3C00 #define _GPIO_PORT_F_PIN_MASK 0x003F +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_GIANT_FAMILY ) \ || defined( _EFM32_WONDER_FAMILY ) @@ -101,6 +121,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 13 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF @@ -108,6 +133,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x1FFF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #elif defined( _EFM32_GECKO_FAMILY ) @@ -117,6 +147,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 16 #define _GPIO_PORT_E_PIN_COUNT 16 #define _GPIO_PORT_F_PIN_COUNT 10 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0xFFFF #define _GPIO_PORT_B_PIN_MASK 0xFFFF @@ -124,11 +159,13 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFFFF #define _GPIO_PORT_E_PIN_MASK 0xFFFF #define _GPIO_PORT_F_PIN_MASK 0x03FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 -#elif defined( _EFR32_MIGHTY_FAMILY ) \ - || defined( _EFR32_BLUE_FAMILY ) \ - || defined( _EFR32_FLEX_FAMILY ) \ - || defined( _EFR32_ZAPPY_FAMILY ) +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFR_DEVICE ) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 @@ -136,6 +173,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 6 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 @@ -143,9 +185,13 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFC00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 -#elif defined( _EFM32_PEARL_FAMILY ) \ - || defined( _EFM32_JADE_FAMILY ) +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) && defined( _EFM_DEVICE ) #define _GPIO_PORT_A_PIN_COUNT 6 #define _GPIO_PORT_B_PIN_COUNT 5 @@ -153,6 +199,11 @@ extern "C" { #define _GPIO_PORT_D_PIN_COUNT 7 #define _GPIO_PORT_E_PIN_COUNT 0 #define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 #define _GPIO_PORT_A_PIN_MASK 0x003F #define _GPIO_PORT_B_PIN_MASK 0xF800 @@ -160,54 +211,95 @@ extern "C" { #define _GPIO_PORT_D_PIN_MASK 0xFE00 #define _GPIO_PORT_E_PIN_MASK 0x0000 #define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 + +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_84 ) + +#define _GPIO_PORT_A_PIN_COUNT 10 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 8 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 4 +#define _GPIO_PORT_J_PIN_COUNT 2 +#define _GPIO_PORT_K_PIN_COUNT 3 + +#define _GPIO_PORT_A_PIN_MASK 0x03FF +#define _GPIO_PORT_B_PIN_MASK 0xFFC0 +#define _GPIO_PORT_C_PIN_MASK 0x0FFF +#define _GPIO_PORT_D_PIN_MASK 0xFF00 +#define _GPIO_PORT_E_PIN_MASK 0x0000 +#define _GPIO_PORT_F_PIN_MASK 0xFFFF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x000F +#define _GPIO_PORT_J_PIN_MASK 0xC000 +#define _GPIO_PORT_K_PIN_MASK 0x0007 + +#elif defined( _SILICON_LABS_GECKO_INTERNAL_SDID_89 ) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 6 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003F +#define _GPIO_PORT_B_PIN_MASK 0xF800 +#define _GPIO_PORT_C_PIN_MASK 0x0FC0 +#define _GPIO_PORT_D_PIN_MASK 0xFC00 +#define _GPIO_PORT_E_PIN_MASK 0x0000 +#define _GPIO_PORT_F_PIN_MASK 0x00FF +#define _GPIO_PORT_G_PIN_MASK 0x0000 +#define _GPIO_PORT_H_PIN_MASK 0x0000 +#define _GPIO_PORT_I_PIN_MASK 0x0000 +#define _GPIO_PORT_J_PIN_MASK 0x0000 +#define _GPIO_PORT_K_PIN_MASK 0x0000 #else #warning "Port and pin masks are not defined for this family." #endif -#if defined( _GPIO_PORT_G_PIN_COUNT ) && defined( _GPIO_PORT_H_PIN_COUNT ) -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ - (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ - (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ - (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ - (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ - (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ - (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \ - (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \ +#define _GPIO_PORT_SIZE(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ + (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ + (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ + (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ + (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ + (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ + (port) == 6 ? _GPIO_PORT_G_PIN_COUNT : \ + (port) == 7 ? _GPIO_PORT_H_PIN_COUNT : \ + (port) == 8 ? _GPIO_PORT_I_PIN_COUNT : \ + (port) == 9 ? _GPIO_PORT_J_PIN_COUNT : \ + (port) == 10 ? _GPIO_PORT_K_PIN_COUNT : \ 0) -#else -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_COUNT : \ - (port) == 1 ? _GPIO_PORT_B_PIN_COUNT : \ - (port) == 2 ? _GPIO_PORT_C_PIN_COUNT : \ - (port) == 3 ? _GPIO_PORT_D_PIN_COUNT : \ - (port) == 4 ? _GPIO_PORT_E_PIN_COUNT : \ - (port) == 5 ? _GPIO_PORT_F_PIN_COUNT : \ - 0) -#endif -#if defined( _GPIO_PORT_G_PIN_MASK ) && defined( _GPIO_PORT_H_PIN_MASK ) -#define _GPIO_PORT_MASK(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ - (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ - (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ - (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ - (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ - (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ - (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \ - (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \ +#define _GPIO_PORT_MASK(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ + (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ + (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ + (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ + (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ + (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ + (port) == 6 ? _GPIO_PORT_G_PIN_MASK : \ + (port) == 7 ? _GPIO_PORT_H_PIN_MASK : \ + (port) == 8 ? _GPIO_PORT_I_PIN_MASK : \ + (port) == 9 ? _GPIO_PORT_J_PIN_MASK : \ + (port) == 10 ? _GPIO_PORT_K_PIN_MASK : \ 0) -#else -#define _GPIO_PORT_MASK(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_MASK : \ - (port) == 1 ? _GPIO_PORT_B_PIN_MASK : \ - (port) == 2 ? _GPIO_PORT_C_PIN_MASK : \ - (port) == 3 ? _GPIO_PORT_D_PIN_MASK : \ - (port) == 4 ? _GPIO_PORT_E_PIN_MASK : \ - (port) == 5 ? _GPIO_PORT_F_PIN_MASK : \ - 0) -#endif /** Validation of port and pin */ #define GPIO_PORT_VALID(port) ( _GPIO_PORT_MASK(port) ) @@ -224,15 +316,17 @@ extern "C" { #define GPIO_PIN_MAX 15 /** Highest GPIO port number */ -#if defined( _GPIO_PORT_J_PIN_COUNT ) +#if ( _GPIO_PORT_K_PIN_COUNT > 0 ) +#define GPIO_PORT_MAX 10 +#elif ( _GPIO_PORT_J_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 9 -#elif defined( _GPIO_PORT_I_PIN_COUNT ) +#elif ( _GPIO_PORT_I_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 8 -#elif defined( _GPIO_PORT_H_PIN_COUNT ) +#elif ( _GPIO_PORT_H_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 7 -#elif defined( _GPIO_PORT_G_PIN_COUNT ) +#elif ( _GPIO_PORT_G_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 6 -#elif defined( _GPIO_PORT_F_PIN_COUNT ) +#elif ( _GPIO_PORT_F_PIN_COUNT > 0 ) #define GPIO_PORT_MAX 5 #else #error "Max GPIO port number is undefined for this part." @@ -266,13 +360,22 @@ typedef enum gpioPortE = 4, #endif #if ( _GPIO_PORT_F_PIN_COUNT > 0 ) - gpioPortF = 5 + gpioPortF = 5, #endif -#if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 ) - gpioPortG = 6 +#if ( _GPIO_PORT_G_PIN_COUNT > 0 ) + gpioPortG = 6, #endif -#if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 ) - gpioPortH = 7 +#if ( _GPIO_PORT_H_PIN_COUNT > 0 ) + gpioPortH = 7, +#endif +#if ( _GPIO_PORT_I_PIN_COUNT > 0 ) + gpioPortI = 8, +#endif +#if ( _GPIO_PORT_J_PIN_COUNT > 0 ) + gpioPortJ = 9, +#endif +#if ( _GPIO_PORT_K_PIN_COUNT > 0 ) + gpioPortK = 10, #endif } GPIO_Port_TypeDef; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h index 659a218612..356cfb86fe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_i2c.h * @brief Inter-intergrated circuit (I2C) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -68,12 +68,17 @@ extern "C" { * @note * Due to chip characteristics, the max value is somewhat reduced. */ -#if defined(_EFM32_GECKO_FAMILY) || defined(_EFM32_TINY_FAMILY) \ - || defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GECKO_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) \ + || defined(_EFM32_HAPPY_FAMILY)) #define I2C_FREQ_STANDARD_MAX 93000 -#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY)) #define I2C_FREQ_STANDARD_MAX 92000 -#elif defined(_SILICON_LABS_32B_PLATFORM_2) +#elif defined(_SILICON_LABS_32B_SERIES_1) // None of the chips on this platform has been characterized on this parameter. // Use same value as on Wonder until further notice. #define I2C_FREQ_STANDARD_MAX 92000 diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h index 7d253e5550..47c4d18415 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_idac.h * @brief Current Digital to Analog Converter (IDAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h index adbc7c1b1f..c7325001d6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_int.h * @brief Interrupt enable/disable unit API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h index 583a26cfc4..62a54059d3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lcd.h * @brief Liquid Crystal Display (LCD) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h index a40d6f873f..9dfb127e58 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ldma.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ldma.h * @brief Direct memory access (LDMA) API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -239,15 +239,12 @@ typedef enum typedef enum { ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN ) + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE ) + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI ) - ldmaPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI. - #endif #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD ) ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD. #endif @@ -263,107 +260,182 @@ typedef enum #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR ) ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) + ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) + ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) + ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) + ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) + ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) + ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) + ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) + ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) + ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) + ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) + ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_BSLN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) + ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) + ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) + ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY ) + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG ) - ldmaPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA ) + #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF ) - ldmaPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 ) - ldmaPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 ) - ldmaPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 ) - ldmaPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 ) - ldmaPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 ) - ldmaPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF ) - ldmaPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF ) - ldmaPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF. - #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF ) + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT ) + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT. #endif - #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY ) - ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1 ///< Trig on USART1_TXEMPTY. + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) + ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) + ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) + ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) + ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) + ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) + ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) + ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) + ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) + ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) + ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) + ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) + ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) + ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) + ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) + ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) + ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) + ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) + ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) + ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) + ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1 ///< Trig on WTIMER1_UFOF. #endif } LDMA_PeripheralSignal_t; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h index 95bde6dcf1..3f74bf0706 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lesense.h * @brief Low Energy Sensor (LESENSE) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -35,9 +35,7 @@ #include "em_device.h" -/* LESENSE is currently only supported on Platform 1. Full support for Platform 2 LESENSE - will be included in the next release. */ -#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) && defined(_SILICON_LABS_32B_PLATFORM_1) +#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) #include #include @@ -56,11 +54,11 @@ extern "C" { * @{ ******************************************************************************/ -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Number of decoder states supported by current device. */ +#define LESENSE_NUM_DECODER_STATES (_LESENSE_DECSTATE_DECSTATE_MASK + 1) - - -/** @endcond */ +/** Number of LESENSE channels. */ +#define LESENSE_NUM_CHANNELS 16 /******************************************************************************* ******************************** ENUMS ************************************ @@ -139,8 +137,16 @@ typedef enum /** Alternate excitation is mapped to the LES_ALTEX pins. */ lesenseAltExMapALTEX = _LESENSE_CTRL_ALTEXMAP_ALTEX, +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) /** Alternate excitation is mapped to the pins of the other ACMP. */ - lesenseAltExMapACMP = _LESENSE_CTRL_ALTEXMAP_ACMP + lesenseAltExMapACMP = _LESENSE_CTRL_ALTEXMAP_ACMP, +#endif + +#if defined(_LESENSE_CTRL_ALTEXMAP_CH) + /** Alternative excitation is mapped to the pin of LESENSE channel + * (X+8 mod 16), X being the active channel. */ + lesenseAltExMapCH = _LESENSE_CTRL_ALTEXMAP_CH, +#endif } LESENSE_AltExMap_TypeDef; @@ -213,12 +219,20 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACIfData = _LESENSE_PERCTRL_DACCH0DATA_DACDATA, +#if defined(_LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES) /** DAC channel x data is defined by ACMPTHRES in LESENSE_CHx_INTERACT. * Note: this value could be used for both DAC Ch0 and Ch1. */ - lesenseACMPThres = _LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES + lesenseACMPThres = _LESENSE_PERCTRL_DACCH0DATA_ACMPTHRES, +#endif + +#if defined(_LESENSE_PERCTRL_DACCH0DATA_THRES) + /** DAC channel x data is defined by THRES in LESENSE_CHx_INTERACT. + * Note: this value could be used for both DAC Ch0 and Ch1. */ + lesenseThres = _LESENSE_PERCTRL_DACCH0DATA_THRES, +#endif } LESENSE_ControlDACData_TypeDef; - +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) /** DAC channel x conversion mode configuration. */ typedef enum { @@ -238,8 +252,9 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACConvModeSampleOff = _LESENSE_PERCTRL_DACCH0CONV_SAMPLEOFF } LESENSE_ControlDACConv_TypeDef; +#endif - +#if defined(_LESENSE_PERCTRL_DACCH0OUT_MASK) /** DAC channel x output mode configuration. */ typedef enum { @@ -259,8 +274,10 @@ typedef enum * Note: this value could be used for both DAC Ch0 and Ch1. */ lesenseDACOutModePinADCACMP = _LESENSE_PERCTRL_DACCH0OUT_PINADCACMP } LESENSE_ControlDACOut_TypeDef; +#endif +#if defined(_LESENSE_PERCTRL_DACREF_MASK) /** DAC reference configuration. */ typedef enum { @@ -270,6 +287,7 @@ typedef enum /** DAC uses bandgap reference. */ lesenseDACRefBandGap = LESENSE_PERCTRL_DACREF_BANDGAP } LESENSE_DACRef_TypeDef; +#endif /** ACMPx control configuration. */ @@ -321,10 +339,18 @@ typedef enum typedef enum { /** Counter output will be used in comparison. */ - lesenseSampleModeCounter = LESENSE_CH_INTERACT_SAMPLE_COUNTER, + lesenseSampleModeCounter = 0x0 << _LESENSE_CH_INTERACT_SAMPLE_SHIFT, /** ACMP output will be used in comparison. */ - lesenseSampleModeACMP = LESENSE_CH_INTERACT_SAMPLE_ACMP + lesenseSampleModeACMP = LESENSE_CH_INTERACT_SAMPLE_ACMP, + +#if defined(LESENSE_CH_INTERACT_SAMPLE_ADC) + /** ADC output will be used in comparison. */ + lesenseSampleModeADC = LESENSE_CH_INTERACT_SAMPLE_ADC, + + /** Differential ADC output will be used in comparison. */ + lesenseSampleModeADCDiff = LESENSE_CH_INTERACT_SAMPLE_ADCDIFF, +#endif } LESENSE_ChSampleMode_TypeDef; @@ -377,13 +403,19 @@ typedef enum * Note: this value could be used for all channels. */ lesenseChPinIdleLow = _LESENSE_IDLECONF_CH0_LOW, +#if defined(_LESENSE_IDLECONF_CH0_DAC) + /** Channel pin is connected to DAC output in idle phase. + * Note: this value could be used for all channels. */ + lesenseChPinIdleDACC = _LESENSE_IDLECONF_CH0_DAC +#else /** Channel pin is connected to DAC CH0 output in idle phase. * Note: only applies to channel 0, 1, 2, 3. */ lesenseChPinIdleDACCh0 = _LESENSE_IDLECONF_CH0_DACCH0, /** Channel pin is connected to DAC CH1 output in idle phase. * Note: only applies to channel 12, 13, 14, 15. */ - lesenseChPinIdleDACCh1 = _LESENSE_IDLECONF_CH12_DACCH1 + lesenseChPinIdleDACCh1 = _LESENSE_IDLECONF_CH12_DACCH1, +#endif } LESENSE_ChPinIdleMode_TypeDef; @@ -401,16 +433,43 @@ typedef enum /** Compare modes for counter comparison. */ typedef enum { - /** Set interrupt flag if counter value is less than CTRTHRESHOLD, or if the - * ACMP output is 0. */ + /** Comparison evaluates to 1 if the sensor data is less than the counter + * threshold, or if the ACMP output is 0. */ lesenseCompModeLess = LESENSE_CH_EVAL_COMP_LESS, - /** Set interrupt flag if counter value is greater than, or equal to - * CTRTHRESHOLD, or if the ACMP output is 1. */ + /** Comparison evaluates to 1 if the sensor data is greater than, or equal to + * the counter threshold, or if the ACMP output is 1. */ lesenseCompModeGreaterOrEq = LESENSE_CH_EVAL_COMP_GE } LESENSE_ChCompMode_TypeDef; +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +/** Sensor evaluation modes. */ +typedef enum +{ + /** Threshold comparison evaluation mode. In this mode the sensor data + * is compared to the configured threshold value. Two possible comparison + * operators can be used on the sensor data, either >= (GE) or < (LT). + * Which operator to use is given using the + * @ref LESENSE_ChDesc_TypeDef::compMode member. */ + lesenseEvalModeThreshold = _LESENSE_CH_EVAL_MODE_THRES, + + /** Sliding window evaluation mode. In this mode the sensor data is + * evaluated against the upper and lower limits of a window range. The + * windows range is defined by a base value and a window size. */ + lesenseEvalModeSlidingWindow = _LESENSE_CH_EVAL_MODE_SLIDINGWIN, + + /** Step detection evaluation mode. In this mode the sensor data is compared + * to the sensor data from the previous measurement. The sensor evaluation + * will result in a "1" if the difference between the current measurement + * and the previous one is greater than a configurable "step size". If the + * difference is less than the configured step size then the sensor + * evaluation will result in a "0". */ + lesenseEvalModeStepDetection = _LESENSE_CH_EVAL_MODE_STEPDET, +} LESENSE_ChEvalMode_TypeDef; +#endif + + /** Idle phase configuration of alternate excitation channels. */ typedef enum { @@ -533,19 +592,25 @@ typedef struct true /* Keep LESENSE running in debug mode. */ \ } - /** LESENSE timing control descriptor structure. */ typedef struct { /** Set the number of LFACLK cycles to delay sensor interaction on * each channel. Valid range: 0-3 (2 bit). */ uint8_t startDelay; + + /** + * Set to true do delay the startup of AUXHFRCO until the system enters + * the excite phase. This will reduce the time AUXHFRCO is enabled and + * reduce power usage. */ + bool delayAuxStartup; } LESENSE_TimeCtrlDesc_TypeDef; /** Default configuration for LESENSE_TimeCtrlDesc_TypeDef structure. */ -#define LESENSE_TIMECTRL_DESC_DEFAULT \ -{ \ - 0U /* No sensor interaction delay. */ \ +#define LESENSE_TIMECTRL_DESC_DEFAULT \ +{ \ + 0U, /* No sensor interaction delay. */ \ + false /* Don't delay the AUXHFRCO startup. */ \ } @@ -555,28 +620,36 @@ typedef struct /** Configure DAC channel 0 data control. */ LESENSE_ControlDACData_TypeDef dacCh0Data; +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) /** Configure how LESENSE controls conversion on DAC channel 0. */ LESENSE_ControlDACConv_TypeDef dacCh0ConvMode; /** Configure how LESENSE controls output on DAC channel 0. */ LESENSE_ControlDACOut_TypeDef dacCh0OutMode; +#endif /** Configure DAC channel 1 data control. */ LESENSE_ControlDACData_TypeDef dacCh1Data; +#if defined(_LESENSE_PERCTRL_DACCH1CONV_MASK) /** Configure how LESENSE controls conversion on DAC channel 1. */ LESENSE_ControlDACConv_TypeDef dacCh1ConvMode; /** Configure how LESENSE controls output on DAC channel 1. */ LESENSE_ControlDACOut_TypeDef dacCh1OutMode; +#endif +#if defined(_LESENSE_PERCTRL_DACPRESC_MASK) /** Configure the prescaling factor for the LESENSE - DAC interface. * Valid range: 0-31 (5bit). */ uint8_t dacPresc; +#endif +#if defined(_LESENSE_PERCTRL_DACREF_MASK) /** Configure the DAC reference to be used. Set to #lesenseDACRefVdd to use * VDD and set to #lesenseDACRefBandGap to use bandgap as reference. */ LESENSE_DACRef_TypeDef dacRef; +#endif /** Configure how LESENSE controls ACMP 0. */ LESENSE_ControlACMP_TypeDef acmp0Mode; @@ -586,24 +659,41 @@ typedef struct /** Configure how LESENSE controls ACMPs and the DAC in idle mode. */ LESENSE_WarmupMode_TypeDef warmupMode; + +#if defined(_LESENSE_PERCTRL_DACCONVTRIG_MASK) + /** When set to true the DAC is only enabled once for each scan. When + * set to false the DAC is enabled before every channel measurement. */ + bool dacScan; +#endif } LESENSE_PerCtrlDesc_TypeDef; /** Default configuration for LESENSE_PerCtrl_TypeDef structure. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define LESENSE_PERCTRL_DESC_DEFAULT \ { \ - lesenseDACIfData, /**/ \ - lesenseDACConvModeDisable, /**/ \ - lesenseDACOutModeDisable, /**/ \ - lesenseDACIfData, /**/ \ - lesenseDACConvModeDisable, /**/ \ - lesenseDACOutModeDisable, /**/ \ - 0U, /**/ \ - lesenseDACRefVdd, /**/ \ - lesenseACMPModeMuxThres, /**/ \ - lesenseACMPModeMuxThres, /**/ \ - lesenseWarmupModeKeepWarm, /**/ \ + lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register */ \ + lesenseDACConvModeDisable, /* LESENSE does not control DAC CH0. */ \ + lesenseDACOutModeDisable, /* DAC channel 0 output to pin disabled. */ \ + lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register */ \ + lesenseDACConvModeDisable, /* LESENSE does not control DAC CH1. */ \ + lesenseDACOutModeDisable, /* DAC channel 1 output to pin disabled. */ \ + 0U, /* DAC prescaling factor of 1 (0+1). */ \ + lesenseDACRefVdd, /* DAC uses VDD reference. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \ + lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \ } - +#else +#define LESENSE_PERCTRL_DESC_DEFAULT \ +{ \ + lesenseDACIfData, /* DAC channel 0 data is defined by DAC_CH0DATA register. */ \ + lesenseDACIfData, /* DAC channel 1 data is defined by DAC_CH1DATA register. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP0. */ \ + lesenseACMPModeMuxThres, /* LESENSE controls the input mux and the threshold value of ACMP1. */ \ + lesenseWarmupModeKeepWarm, /* Keep both ACMPs and the DAC powered up when LESENSE is idle. */ \ + false, /* DAC is enable for before every channel measurement. */ \ +} +#endif /** LESENSE decoder control descriptor structure. */ typedef struct @@ -615,7 +705,7 @@ typedef struct uint32_t initState; /** Set to enable the decoder to check the present state in addition - * to the states defined in DECCONF. */ + * to the states defined in TCONF. */ bool chkState; /** When set, a transition from state x in the decoder will set interrupt flag @@ -658,19 +748,19 @@ typedef struct /** Default configuration for LESENSE_PerCtrl_TypeDef structure. */ #define LESENSE_DECCTRL_DESC_DEFAULT \ { \ - lesenseDecInputSensorSt, /**/ \ - 0U, /**/ \ - false, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - true, /**/ \ - false, /**/ \ - lesensePRSCh0, /**/ \ - lesensePRSCh1, /**/ \ - lesensePRSCh2, /**/ \ - lesensePRSCh3, /**/ \ + lesenseDecInputSensorSt, /* The SENSORSTATE register is used as input to the decoder. */ \ + 0U, /* State 0 is the initial state of the decoder. */ \ + false, /* Disable check of current state. */ \ + true, /* Enable channel x % 16 interrupt on state x change. */ \ + true, /* Enable decoder hysteresis on PRS0 output. */ \ + true, /* Enable decoder hysteresis on PRS1 output. */ \ + true, /* Enable decoder hysteresis on PRS2 output. */ \ + true, /* Enable decoder hysteresis on PRS3 output. */ \ + false, /* Disable count mode on decoder PRS channels 0 and 1*/ \ + lesensePRSCh0, /* PRS Channel 0 as input for bit 0 of the LESENSE decoder. */ \ + lesensePRSCh1, /* PRS Channel 1 as input for bit 1 of the LESENSE decoder. */ \ + lesensePRSCh2, /* PRS Channel 2 as input for bit 2 of the LESENSE decoder. */ \ + lesensePRSCh3, /* PRS Channel 3 as input for bit 3 of the LESENSE decoder. */ \ } @@ -745,14 +835,16 @@ typedef struct uint8_t exTime; /** Configure sample delay. Sampling will occur after sampleDelay+1 sample - * clock cycles. Valid range: 0-127 (7 bits). */ + * clock cycles. Valid range: 0-127 (7 bits) or 0-255 (8 bits) depending on + * device. */ uint8_t sampleDelay; /** Configure measure delay. Sensor measuring is delayed for measDelay - * excitation clock cycles. Valid range: 0-127 (7 bits). */ - uint8_t measDelay; + * excitation clock cycles. Valid range: 0-127 (7 bits) or 0-1023 (10 bits) + * depending on device. */ + uint16_t measDelay; - /** Configure ACMP threshold. + /** Configure ACMP threshold or DAC data. * If perCtrl.dacCh0Data or perCtrl.dacCh1Data is set to #lesenseDACIfData, * acmpThres defines the 12-bit DAC data in the corresponding data register * of the DAC interface (DACn_CH0DATA and DACn_CH1DATA). @@ -763,29 +855,61 @@ typedef struct * In this case, the valid range is: 0-63 (6 bits). */ uint16_t acmpThres; - /** Select if ACMP output or counter output should be used in comparison. */ + /** Select if ACMP output, ADC output or counter output should be used in + * comparison. */ LESENSE_ChSampleMode_TypeDef sampleMode; /** Configure interrupt generation mode for CHx interrupt flag. */ LESENSE_ChIntMode_TypeDef intMode; - /** Configure decision threshold for counter comparison. + /** Configure decision threshold for sensor data comparison. * Valid range: 0-65535 (16 bits). */ uint16_t cntThres; /** Select mode for counter comparison. */ LESENSE_ChCompMode_TypeDef compMode; + +#if defined(_LESENSE_CH_EVAL_MODE_MASK) + /** Select sensor evaluation mode. */ + LESENSE_ChEvalMode_TypeDef evalMode; +#endif + } LESENSE_ChDesc_TypeDef; /** Configuration structure for all scan channels. */ typedef struct { - /** Channel descriptor for all 16 channels. */ - LESENSE_ChDesc_TypeDef Ch[16]; + /** Channel descriptor for all LESENSE channels. */ + LESENSE_ChDesc_TypeDef Ch[LESENSE_NUM_CHANNELS]; } LESENSE_ChAll_TypeDef; /** Default configuration for scan channel. */ +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +#define LESENSE_CH_CONF_DEFAULT \ +{ \ + true, /* Enable scan channel. */ \ + true, /* Enable the assigned pin on scan channel. */ \ + true, /* Enable interrupts on channel. */ \ + lesenseChPinExHigh, /* Channel pin is high during the excitation period. */ \ + lesenseChPinIdleLow, /* Channel pin is low during the idle period. */ \ + false, /* Don't use alternate excitation pins for excitation. */ \ + false, /* Disabled to shift results from this channel to the decoder register. */ \ + false, /* Disabled to invert the scan result bit. */ \ + false, /* Disabled to store counter value in the result buffer. */ \ + lesenseClkLF, /* Use the LF clock for excitation timing. */ \ + lesenseClkLF, /* Use the LF clock for sample timing. */ \ + 0x03U, /* Excitation time is set to 3(+1) excitation clock cycles. */ \ + 0x09U, /* Sample delay is set to 9(+1) sample clock cycles. */ \ + 0x06U, /* Measure delay is set to 6 excitation clock cycles.*/ \ + 0x00U, /* ACMP threshold has been set to 0. */ \ + lesenseSampleModeACMP, /* ACMP output will be used in comparison. */ \ + lesenseSetIntNone, /* No interrupt is generated by the channel. */ \ + 0xFFU, /* Counter threshold has bee set to 0xFF. */ \ + lesenseCompModeLess, /* Compare mode has been set to trigger interrupt on "less". */ \ + lesenseEvalModeThreshold /* Compare mode has been set to trigger interrupt on "less". */ \ +} +#else #define LESENSE_CH_CONF_DEFAULT \ { \ true, /* Enable scan channel. */ \ @@ -808,6 +932,8 @@ typedef struct 0xFFU, /* Counter threshold has bee set to 0xFF. */ \ lesenseCompModeLess /* Compare mode has been set to trigger interrupt on "less". */ \ } +#endif + /** Default configuration for all sensor channels. */ #define LESENSE_SCAN_CONF_DEFAULT \ @@ -887,6 +1013,7 @@ typedef struct } /** Default configuration for all alternate excitation channels. */ +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) #define LESENSE_ALTEX_CONF_DEFAULT \ { \ lesenseAltExMapACMP, \ @@ -909,7 +1036,30 @@ typedef struct LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \ } \ } - +#else +#define LESENSE_ALTEX_CONF_DEFAULT \ +{ \ + lesenseAltExMapCH, \ + { \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 0. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 1. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 2. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 3. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 4. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 5. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 6. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 7. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 8. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 9. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 10. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 11. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 12. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 13. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT, /* Alternate excitation channel 14. */ \ + LESENSE_ALTEX_CH_CONF_DEFAULT /* Alternate excitation channel 15. */ \ + } \ +} +#endif /** Decoder state condition descriptor structure. */ typedef struct @@ -966,11 +1116,12 @@ typedef struct /** Configuration structure for the decoder. */ typedef struct { - /** Descriptor of the 16 decoder states. */ - LESENSE_DecStDesc_TypeDef St[16]; + /** Descriptor of the 16 or 32 decoder states depending on the device. */ + LESENSE_DecStDesc_TypeDef St[LESENSE_NUM_DECODER_STATES]; } LESENSE_DecStAll_TypeDef; /** Default configuration for all decoder states. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define LESENSE_DECODER_CONF_DEFAULT \ { /* chain | Descriptor A | Descriptor B */ \ { \ @@ -992,44 +1143,93 @@ typedef struct { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 15. */ \ } \ } +#else +#define LESENSE_DECODER_CONF_DEFAULT \ +{ /* chain | Descriptor A | Descriptor B */ \ + { \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 0. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 1. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 2. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 3. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 4. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 5. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 6. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 7. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 8. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 9. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 10. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 11. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 12. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 13. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 14. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 15. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 16. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 17. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 18. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 19. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 20. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 21. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 22. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 23. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 24. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 25. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 26. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 27. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 28. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 29. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT }, /* Decoder state 30. */ \ + { false, LESENSE_ST_CONF_DEFAULT, LESENSE_ST_CONF_DEFAULT } /* Decoder state 31. */ \ + } \ +} +#endif /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ -void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset); +void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset); void LESENSE_Reset(void); -uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq); -void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, - bool const start); +uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq); +void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef scanMode, bool start); +void LESENSE_StartDelaySet(uint8_t startDelay); +void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef clk, + LESENSE_ClkPresc_TypeDef clkDiv); -void LESENSE_StartDelaySet(uint8_t const startDelay); - -void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, - LESENSE_ClkPresc_TypeDef const clkDiv); - -void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll); -void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, - uint32_t const chIdx); -void LESENSE_ChannelEnable(uint8_t const chIdx, - bool const enaScanCh, - bool const enaPin); +void LESENSE_ChannelAllConfig(const LESENSE_ChAll_TypeDef * confChAll); +void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh, + uint32_t chIdx); +void LESENSE_ChannelEnable(uint8_t chIdx, + bool enaScanCh, + bool enaPin); void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask); -void LESENSE_ChannelTimingSet(uint8_t const chIdx, - uint8_t const exTime, - uint8_t const sampleDelay, - uint8_t const measDelay); -void LESENSE_ChannelThresSet(uint8_t const chIdx, - uint16_t const acmpThres, - uint16_t const cntThres); +void LESENSE_ChannelTimingSet(uint8_t chIdx, + uint8_t exTime, + uint8_t sampleDelay, + uint16_t measDelay); +void LESENSE_ChannelThresSet(uint8_t chIdx, + uint16_t acmpThres, + uint16_t cntThres); +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +void LESENSE_ChannelSlidingWindow(uint8_t chIdx, + uint32_t windowSize, + uint32_t initValue); +void LESENSE_ChannelStepDetection(uint8_t chIdx, + uint32_t stepSize, + uint32_t initValue); +void LESENSE_WindowSizeSet(uint32_t windowSize); +void LESENSE_StepSizeSet(uint32_t stepSize); +#endif -void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx); +void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx); -void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll); -void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, - uint32_t const decSt); +void LESENSE_DecoderStateAllConfig(const LESENSE_DecStAll_TypeDef * confDecStAll); +void LESENSE_DecoderStateConfig(const LESENSE_DecStDesc_TypeDef * confDecSt, + uint32_t decSt); void LESENSE_DecoderStateSet(uint32_t decSt); uint32_t LESENSE_DecoderStateGet(void); +#if defined(_LESENSE_PRSCTRL_MASK) +void LESENSE_DecoderPrsOut(bool enable, uint32_t decMask, uint32_t decCmp); +#endif void LESENSE_ScanStart(void); void LESENSE_ScanStop(void); @@ -1126,7 +1326,7 @@ __STATIC_INLINE uint32_t LESENSE_ChannelActiveGet(void) ******************************************************************************/ __STATIC_INLINE uint32_t LESENSE_ScanResultGet(void) { - return LESENSE->SCANRES; + return LESENSE->SCANRES & _LESENSE_SCANRES_SCANRES_MASK; } @@ -1184,6 +1384,7 @@ __STATIC_INLINE uint32_t LESENSE_SensorStateGet(void) } +#if defined(LESENSE_POWERDOWN_RAM) /***************************************************************************//** * @brief * Shut off power to the LESENSE RAM, disables LESENSE. @@ -1201,6 +1402,7 @@ __STATIC_INLINE void LESENSE_RAMPowerDown(void) /* Power down LESENSE RAM */ LESENSE->POWERDOWN = LESENSE_POWERDOWN_RAM; } +#endif /***************************************************************************//** diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h index 782a9b8740..9a3eeb8340 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_letimer.h * @brief Low Energy Timer (LETIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h index ac6f842ced..656c0e4b97 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h @@ -2,7 +2,7 @@ * @file em_leuart.h * @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) * peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h index 3b5c528381..b562694d39 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_mpu.h * @brief Memory protection unit (MPU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h index 895ef37ccc..9a71be990f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_msc.h * @brief Flash controller (MSC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -132,7 +132,7 @@ extern "C" { /** Return codes for writing/erasing the flash */ typedef enum { - mscReturnOk = 0, /**< Flash write/erase successful. */ + mscReturnOk = 0, /**< Flash write/erase successful. */ mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not flash. */ mscReturnLocked = -2, /**< Flash address is locked. */ mscReturnTimeOut = -3, /**< Timeout while writing to flash. */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h index cdb2201986..204bfd1669 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_opamp.h * @brief Operational Amplifier (OPAMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -34,7 +34,8 @@ #define EM_OPAMP_H #include "em_device.h" -#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) #ifdef __cplusplus extern "C" { @@ -42,7 +43,12 @@ extern "C" { #include #include + +#if defined(_SILICON_LABS_32B_SERIES_0) #include "em_dac.h" +#elif defined (_SILICON_LABS_32B_SERIES_1) +#include "em_vdac.h" +#endif /***************************************************************************//** * @addtogroup emlib @@ -57,7 +63,11 @@ extern "C" { /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /** Validation of DAC OPA number for assert statements. */ +#if defined(_SILICON_LABS_32B_SERIES_0) #define DAC_OPA_VALID(opa) ((opa) <= OPA2) +#elif defined(_SILICON_LABS_32B_SERIES_1) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA2) +#endif /** @endcond */ @@ -76,34 +86,249 @@ typedef enum /** OPAMP negative terminal input selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */ opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */ opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */ + opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */ + opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */ + opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */ + opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */ + opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */ + opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */ + opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */ + opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */ + opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */ + opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */ + opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */ + opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */ + opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */ + opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */ + opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */ + opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */ + opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */ + opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */ + opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */ + opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */ + opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */ + opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */ + opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */ + opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */ + opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */ + opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */ + opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */ + opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */ + opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */ + opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */ + opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */ + opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */ + opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */ + opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */ + opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */ + opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */ + opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */ + opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */ + opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */ + opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */ + opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */ + opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */ + opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */ + opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */ + opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */ + opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */ + opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */ + opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */ + opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */ + opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */ + opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */ + opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */ + opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */ + opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */ + opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */ + opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */ + opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */ + opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */ + opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */ + opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */ + opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */ + opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */ + opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */ + opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */ + opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */ + opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ + opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_NegSel_TypeDef; /** OPAMP positive terminal input selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */ opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */ opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */ opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */ + opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */ + opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */ + opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */ + opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */ + opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */ + opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */ + opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */ + opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */ + opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */ + opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */ + opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */ + opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */ + opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */ + opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */ + opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */ + opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */ + opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */ + opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */ + opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */ + opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */ + opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */ + opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */ + opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */ + opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */ + opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */ + opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */ + opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */ + opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */ + opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */ + opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */ + opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */ + opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */ + opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */ + opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */ + opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */ + opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */ + opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */ + opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */ + opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */ + opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */ + opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */ + opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */ + opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */ + opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */ + opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */ + opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */ + opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */ + opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */ + opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */ + opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */ + opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */ + opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */ + opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */ + opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */ + opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */ + opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */ + opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */ + opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */ + opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */ + opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */ + opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */ + opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */ + opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */ + opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */ + opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ + opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */ + opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */ + opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_PosSel_TypeDef; /** OPAMP output terminal selection values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */ opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */ opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */ opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaOutModeDisable = 0, /**< OPA output disabled. */ + opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */ + opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */ + opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */ + opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */ + opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */ + opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */ + opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */ + opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */ + opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */ + opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */ + opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */ + opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */ + opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */ + opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */ + opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */ + opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */ + opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */ + opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */ + opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */ + opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */ + opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */ + opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */ + opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */ + opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */ + opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */ + opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */ + opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */ + opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */ + opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */ + opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */ + opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */ + opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */ + opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */ + opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */ + opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */ + opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */ + opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */ + opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */ + opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */ + opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */ + opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */ + opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */ + opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */ + opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */ + opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */ + opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */ + opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */ + opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */ + opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */ + opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */ + opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */ + opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */ + opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */ + opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */ + opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */ + opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */ + opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */ + opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */ + opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */ + opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */ + opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */ + opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */ + opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */ + opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */ + opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */ + opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */ + opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_OutMode_TypeDef; /** OPAMP gain values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */ @@ -113,18 +338,94 @@ typedef enum opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ + opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ + opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */ + opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ + opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */ + opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ + opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ + opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ + opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_ResSel_TypeDef; /** OPAMP resistor ladder input selector values. */ typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */ opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ + opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */ + opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ + opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ + opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0. + Direct input to support common reference. */ + opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully + differential instrumentation amplifier. */ + opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ } OPAMP_ResInMux_TypeDef; +#if defined(_SILICON_LABS_32B_SERIES_1) +typedef enum +{ + opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP + warmup sequence. The end of the warmup sequence + is controlled by timeout settings in OPAxTIMER. */ + opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the + OPAMP warmup sequence. The end of the warmup + sequence is controlled by the edge of the pulse. */ +} OPAMP_PrsMode_TypeDef; + +typedef enum +{ + opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */ + opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */ + opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */ + opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */ + opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */ + opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */ + opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */ + opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */ + opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */ + opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */ + opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */ + opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */ +} OPAMP_PrsSel_TypeDef; + +typedef enum +{ + opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */ + opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */ + opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */ +} OPAMP_PrsOut_TypeDef; + +typedef enum +{ + opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */ + opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */ + opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */ +} OPAMP_OutScale_Typedef; + +typedef enum +{ + opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */ + opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive stregth. */ + opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive stregth. */ + opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive stregth. */ + opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive stregth. */ +} OPAMP_DrvStr_Typedef; +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ @@ -139,6 +440,7 @@ typedef struct OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */ uint32_t outPen; /**< Alternate output enable bit mask. This value should consist of one or more of the + @if DOXYDOC_P1_DEVICE DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags (defined in \_dac.h) OR'ed together. @n @n @@ -163,7 +465,24 @@ typedef struct E.g: @n init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | DAC_OPA0MUX_OUTPEN_OUT2 | - DAC_OPA0MUX_OUTPEN_OUT4; */ + DAC_OPA0MUX_OUTPEN_OUT4; + + @elseif DOXYDOC_P2_DEVICE + VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + (defined in \_vdac.h) OR'ed together. + @n @n + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + + E.g: @n + init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT2 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + @endif */ +#if defined(_SILICON_LABS_32B_SERIES_0) uint32_t bias; /**< Set OPAMP bias current. */ bool halfBias; /**< Divide OPAMP bias current by 2. */ bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */ @@ -174,9 +493,34 @@ typedef struct bool shortInputs; /**< Short OPAMP input terminals. */ bool hcmDisable; /**< Disable input rail-to-rail capability. */ bool defaultOffset; /**< Use factory calibrated opamp offset value. */ - uint32_t offset; /**< Opamp offset value when @ref defaultOffset is false.*/ + uint32_t offset; /**< Opamp offset value when @ref defaultOffset is + false. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */ + bool gain3xEn; /**< Enable 3x gain resistor ladder. */ + bool halfDrvStr; /**< Half or full output drive strength. */ + bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */ + bool prsEn; /**< Enable PRS as OPAMP trigger. */ + OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */ + OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */ + OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */ + bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */ + bool aportXMasterDisable; /**< Disable bus master request on APORT X. */ + uint32_t settleTime; /**< Number of clock cycles to drive the output. */ + uint32_t startupDly; /**< OPAx startup delay in us. */ + bool hcmDisable; /**< Disable input rail-to-rail capability. */ + bool defaultOffsetN; /**< Use factory calibrated opamp inverting input + offset value. */ + uint32_t offsetN; /**< Opamp inverting input offset value when + @ref defaultOffsetInv is false. */ + bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting + input offset value. */ + uint32_t offsetP; /**< Opamp non-inverting input offset value when + @ref defaultOffsetNon is false. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_1) */ } OPAMP_Init_TypeDef; +#if defined(_SILICON_LABS_32B_SERIES_0) /** Configuration of OPA0/1 in unity gain voltage follower mode. */ #define OPA_INIT_UNITY_GAIN \ { \ @@ -551,12 +895,468 @@ typedef struct 0 /* Opamp offset value (not used). */ \ } +#elif defined(_SILICON_LABS_32B_SERIES_1) +/** Configuration of OPA in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA in inverting amplifier mode. */ +#define OPA_INIT_INVERTING \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Pos input from OPA0 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Pos input from OPA1 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA0 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA2 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA0 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA1 \ +{ \ + opaNegSelResTap, /* Neg input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA0 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA1 \ +{ \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Disable resistor ladder. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA2 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA2 \ +{ \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA0 \ +{ \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Pos input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +/** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA1 \ +{ \ + opaNegSelNegPad, /* Neg input from pad. */ \ + opaPosSelResTap, /* Input from resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ +} + +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_0) void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa); void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#elif defined(_SILICON_LABS_32B_SERIES_1) +void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa); +void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ /** @} (end addtogroup OPAMP) */ /** @} (end addtogroup emlib) */ @@ -565,5 +1365,6 @@ void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_Typ } #endif -#endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */ +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ #endif /* EM_OPAMP_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h index c2a7b95c50..7dabb41427 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_pcnt.h * @brief Pulse Counter (PCNT) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h index 26306b70c4..1d995a7df6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_prs.h * @brief Peripheral Reflex System (PRS) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h index 51dee93b30..5476c265bb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ramfunc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ramfunc.h * @brief RAM code support. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h index 81404cdcda..f8ea76bbe7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rmu.h * @brief Reset Management Unit (RMU) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h index c3cb033095..14b28ed06c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rtc.h * @brief Real Time Counter (RTC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h index 3f6789a1cd..388a69ff48 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtcc.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief Real Time Counter (RTCC) peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -53,6 +53,21 @@ extern "C" { * @{ ******************************************************************************/ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +/* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC + * Registers". */ +#define ERRATA_FIX_RTCC_E203 +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +/* Enable fix for errata "RTCC_E204 - Disabling the RTCC Backup RAM may consume extra + * current". */ +#define ERRATA_FIX_RTCC_E204 +#endif +/** @endcond */ + /******************************************************************************* ********************************* ENUM ************************************ ******************************************************************************/ @@ -588,7 +603,26 @@ __STATIC_INLINE void RTCC_IntSet( uint32_t flags ) ******************************************************************************/ __STATIC_INLINE void RTCC_Lock( void ) { +#if defined(ERRATA_FIX_RTCC_E203) + /* RTCC_E203 - Potential Stability Issue with RTCC Registers + * RTCC_LOCK register must be modified while RTCC clock is disabled. */ + uint32_t lfeReg = CMU->LFECLKEN0; + bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; + } + CMU->LFECLKEN0 = 0x0; +#endif RTCC->LOCK = RTCC_LOCK_LOCKKEY_LOCK; +#if defined(ERRATA_FIX_RTCC_E203) + /* Restore clock state after RTCC_E203 fix. */ + CMU->LFECLKEN0 = lfeReg; + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; + } +#endif } /***************************************************************************//** @@ -626,7 +660,11 @@ void RTCC_Reset( void ); ******************************************************************************/ __STATIC_INLINE void RTCC_RetentionRamPowerDown( void ) { +#if !defined(ERRATA_FIX_RTCC_E204) + /* Devices that are affected by RTCC_E204 should always keep the RTCC + * backup RAM retained. */ RTCC->POWERDOWN = RTCC_POWERDOWN_RAM; +#endif } void RTCC_StatusClear( void ); @@ -682,7 +720,26 @@ __STATIC_INLINE void RTCC_TimeSet( uint32_t time ) ******************************************************************************/ __STATIC_INLINE void RTCC_Unlock( void ) { +#if defined(ERRATA_FIX_RTCC_E203) + /* RTCC_E203 - Potential Stability Issue with RTCC Registers + * RTCC_LOCK register must be modified while RTCC clock is disabled. */ + uint32_t lfeReg = CMU->LFECLKEN0; + bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; + } + CMU->LFECLKEN0 = 0x0; +#endif RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK; +#if defined(ERRATA_FIX_RTCC_E203) + /* Restore clock state after RTCC_E203 fix. */ + CMU->LFECLKEN0 = lfeReg; + if (cmuLocked) + { + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; + } +#endif } /** @} (end addtogroup RTCC) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h new file mode 100644 index 0000000000..140bc825fd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h @@ -0,0 +1,466 @@ +/***************************************************************************//** + * @file em_smu.h + * @brief Security Management Unit (SMU) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_SMU_H +#define EM_SMU_H + +#include "em_device.h" +#if defined(SMU_COUNT) && (SMU_COUNT > 0) + +#include "em_assert.h" +#include "em_bus.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup SMU + * @brief Security Management Unit (SMU) Peripheral API + * + * @details + * The Security Management Unit (SMU) forms the control and status/reporting + * component of bus-level security in EFM32/EFR32 devices. + * + * Peripheral-level protection is provided via the peripheral protection unit + * (PPU). The PPU provides a hardware access barrier to any peripheral that is + * configured to be protected. When an attempt is made to access a peripheral + * without the required privilege/security level, the PPU detects the fault + * and intercepts the access. No write or read of the peripheral register + * space occurs, and an all-zero value is returned if the access is a read. + * + * @subsection Usage example + * @include em_smu_init.c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** SMU peripheral identifiers. */ +typedef enum { + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */ + smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */ + smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */ + +#else +#error "No peripherals defined for SMU for this device configuration." +#endif + smuPeripheralEnd +} SMU_Peripheral_TypeDef; + +/** SMU peripheral privileged access enablers. */ +typedef struct { + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */ + +#else +#error "No peripherals defined for SMU for this device configuration" +#endif +} SMU_PrivilegedAccess_TypeDef; + +/******************************************************************************* + ****************************** STRUCTS ************************************ + ******************************************************************************/ + +/** SMU initialization structure. */ +typedef struct { + union { + uint32_t reg[2]; /**< Periperal access control array.*/ + SMU_PrivilegedAccess_TypeDef access; /**< Periperal access control array.*/ + } ppu; + bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/ +} SMU_Init_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80) +/** Default SMU initialization struct settings. */ +#define SMU_INIT_DEFAULT { \ + {{0}}, /* No peripherals acsess protected. */ \ + true /* Enable SMU.*/ \ +} +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable or disable the Peripheral Protection Unit of the SMU. + * + * @param[in] enable + * True if the PPU should be enabled, false if it should be disabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_EnablePPU(bool enable) +{ + BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable); +} + +/***************************************************************************//** + * @brief + * Initialize the Peripheral Protection Unit of the SMU. + * + * @param[in] init + * Pointer to initialization struct defining which peripherals should only + * be accessed from privileged mode, and whether the PPU should be enabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init) +{ + SMU->PPUPATD0 = init->ppu.reg[0]; + SMU->PPUPATD1 = init->ppu.reg[1]; + + SMU_EnablePPU(init->enable); +} + +/***************************************************************************//** + * @brief + * Change the access settings for a peripheral + * + * @details + * Set whether the peripheral can only be accessed from privileged mode + * + * @param[in] peripheral + * ID of the peripheral to change access settings for + * + * @param[in] privileged + * True if the peripheral should only be allowed to be accessed from + * privileged mode, false if the peripheral can be accessed from unprivileged + * mode. + ******************************************************************************/ +__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, + bool privileged) +{ + EFM_ASSERT(peripheral < smuPeripheralEnd); + + if (peripheral < 32) { + BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged); + } else { + BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged); + } +} + +/***************************************************************************//** + * @brief + * Get the ID of the peripheral that caused an access fault. + * + * @note + * The return value is only valid if the @ref SMU_IF_PPUPRIV interrupt flag + * is set. + * + * @return + * ID of the faulting peripheral. + ******************************************************************************/ +__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void) +{ + return (SMU_Peripheral_TypeDef)SMU->PPUFS; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending SMU interrupts. + * + * @param[in] flags + * Bitwise logic OR of SMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntClear(uint32_t flags) +{ + SMU->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more SMU interrupts. + * + * @param[in] flags + * SMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntDisable(uint32_t flags) +{ + SMU->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more SMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using SMU_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] flags + * SMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntEnable(uint32_t flags) +{ + SMU->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending SMU interrupts. + * + * @return + * SMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGet(void) +{ + return SMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending SMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled SMU interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in SMU_IEN register + * and + * - the OR combination of valid interrupt flags in SMU_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGetEnabled(void) +{ + uint32_t tmp; + + // Store SMU->IEN in temporary variable in order to define explicit order + // of volatile accesses. + tmp = SMU->IEN; + + // Bitwise AND of pending and enabled interrupts + return SMU->IF & tmp; +} + +/************************************************************************Æ**//** + * @brief + * Set one or more pending SMU interrupts from SW. + * + * @param[in] flags + * SMU interrupt sources to set to pending. + *************************************************************************Æ****/ +__STATIC_INLINE void SMU_IntSet(uint32_t flags) +{ + SMU->IFS = flags; +} + +/** @} (end addtogroup SMU) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif // defined(SMU_COUNT) && (SMU_COUNT > 0) +#endif // EM_SMU_H diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h index 34810a81c0..84d2049edd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_system.h * @brief System API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -86,10 +86,22 @@ typedef enum systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) - systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Gen1 Basic Device Family */ + systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) - systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Gen1 Basic Device Family */ + systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Config 1 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) + systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Config 2 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) + systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Config 2 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B) + systemPartFamilyEfm32Pearl13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B, /**< EFM32 Pearl Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B) + systemPartFamilyEfm32Jade13B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B, /**< EFM32 Jade Gecko Series 1 Config 3 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family */ @@ -101,78 +113,89 @@ typedef enum systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) - systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Gen1 Premium Device Family */ + systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) - systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Gen1 Basic Device Family */ + systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) - systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Gen1 Value Device Family */ + systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) - systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Gen1 Premium Device Family */ + systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) - systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Gen1 Basic Device Family */ + systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) - systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Gen1 Value Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P) - systemPartFamilyZappy1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1P, /**< EFR32 Zappy Gecko Gen1 Premium Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B) - systemPartFamilyZappy1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1B, /**< EFR32 Zappy Gecko Gen1 Basic Device Family */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V) - systemPartFamilyZappy1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG1V, /**< EFR32 Zappy Gecko Gen1 Value Device Family */ + systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) - systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Gen1 Premium Device Family */ + systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Config 1 Premium Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) - systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Gen1 Basic Device Family */ + systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Config 1 Basic Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) - systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Gen1 Value Device Family */ + systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Config 1 Value Device Family */ #endif #if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P) - systemPartFamilyMighty2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P, /**< EFR32 Mighty Gecko Gen2 Premium Device Family */ + systemPartFamilyMighty2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P, /**< EFR32 Mighty Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2B) - systemPartFamilyMighty2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2B, /**< EFR32 Mighty Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) + systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2V) - systemPartFamilyMighty2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2V, /**< EFR32 Mighty Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) + systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2P) - systemPartFamilyBlue2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2P, /**< EFR32 Blue Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) + systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2B) - systemPartFamilyBlue2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2B, /**< EFR32 Blue Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) + systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG2V) - systemPartFamilyBlue2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG2V, /**< EFR32 Blue Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) + systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2P) - systemPartFamilyZappy2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2P, /**< EFR32 Zappy Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) + systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2B) - systemPartFamilyZappy2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2B, /**< EFR32 Zappy Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) + systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Config 2 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2V) - systemPartFamilyZappy2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG2V, /**< EFR32 Zappy Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) + systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Config 2 Basic Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2P) - systemPartFamilyFlex2P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2P, /**< EFR32 Flex Gecko Gen2 Premium Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) + systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Config 2 Value Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2B) - systemPartFamilyFlex2B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2B, /**< EFR32 Flex Gecko Gen2 Basic Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) + systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Config 3 Premium Device Family */ #endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG2V) - systemPartFamilyFlex2V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG2V, /**< EFR32 Flex Gecko Gen2 Value Device Family */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) + systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) + systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Config 3 Value Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) + systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Config 3 Premium Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) + systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) + systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Config 3 Value Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) + systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Config 3 Premium Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) + systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Config 3 Basic Device Family */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) + systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Config 3 Value Device Family */ #endif - @@ -290,23 +313,32 @@ __STATIC_INLINE uint8_t SYSTEM_GetProdRev(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define SRAM_SIZE can be used instead. + * @ref SRAM_SIZE can be used instead. * * @return * The size of the internal SRAM (in KB). ******************************************************************************/ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void) { + uint16_t sizekb; + #if defined(_EFM32_GECKO_FAMILY) /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ if (SYSTEM_GetProdRev() < 5) { - return (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) - >> _DEVINFO_MSIZE_FLASH_SHIFT; + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT; } #endif - return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) - >> _DEVINFO_MSIZE_SRAM_SHIFT; + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT; + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + /* Do not include EFR32xG1 RAMH */ + sizekb--; +#endif + + return sizekb; } /***************************************************************************//** @@ -316,7 +348,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetSRAMSize(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define FLASH_SIZE can be used instead. + * @ref FLASH_SIZE can be used instead. * * @return * The size of the internal flash (in KB). @@ -343,7 +375,7 @@ __STATIC_INLINE uint16_t SYSTEM_GetFlashSize(void) * @note * This function retrievs the correct value by reading the chip device * info structure. If your binary is made for one specific device only, - * the \#define FLASH_PAGE_SIZE can be used instead. + * @ref FLASH_PAGE_SIZE can be used instead. * * @return * The page size of the internal flash in bytes. diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h index dce5bbc174..cc5d48bb63 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_timer.h * @brief Timer/counter (TIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -59,32 +59,16 @@ extern "C" { /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - /** Validation of TIMER register block pointer reference for assert statements. */ -#if (TIMER_COUNT == 1) -#define TIMER_REF_VALID(ref) ((ref) == TIMER0) -#elif (TIMER_COUNT == 2) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) || ((ref) == TIMER1)) -#elif (TIMER_COUNT == 3) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \ - || ((ref) == TIMER1) \ - || ((ref) == TIMER2)) -#elif (TIMER_COUNT == 4) -#define TIMER_REF_VALID(ref) (((ref) == TIMER0) \ - || ((ref) == TIMER1) \ - || ((ref) == TIMER2) \ - || ((ref) == TIMER3)) -#else -#error "Undefined number of timers." -#endif +#define TIMER_REF_VALID(ref) TIMER_Valid(ref) /** Validation of TIMER compare/capture channel number */ -#if defined(_SILICON_LABS_32B_PLATFORM_1) +#if defined(_SILICON_LABS_32B_SERIES_0) #define TIMER_CH_VALID(ch) ((ch) < 3) -#elif defined(_SILICON_LABS_32B_PLATFORM_2) +#elif defined(_SILICON_LABS_32B_SERIES_1) #define TIMER_CH_VALID(ch) ((ch) < 4) #else -#error "Unknown platform. Undefined number of channels." +#error "Unknown device. Undefined number of channels." #endif /** @endcond */ @@ -499,6 +483,66 @@ typedef struct ***************************** PROTOTYPES ********************************** ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Validate the TIMER register block pointer + * + * @param[in] ref + * Pointer to TIMER peripheral register block. + * + * @return + * true if ref points to a valid timer, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) +{ + return (ref == TIMER0) +#if defined(TIMER1) + || (ref == TIMER1) +#endif +#if defined(TIMER2) + || (ref == TIMER2) +#endif +#if defined(TIMER3) + || (ref == TIMER3) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Get the Max count of the timer + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + * + * @return + * The max count value of the timer. This is 0xFFFF for 16 bit timers + * and 0xFFFFFFFF for 32 bit timers. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) +{ +#if defined(WTIMER_PRESENT) + if ((ref == WTIMER0) +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif + ) + { + return 0xFFFFFFFFUL; + } +#else + (void) ref; +#endif + return 0xFFFFUL; +} + /***************************************************************************//** * @brief * Get capture value for compare/capture channel when operating in capture @@ -542,6 +586,7 @@ __STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CC[ch].CCVB = val; } @@ -564,6 +609,7 @@ __STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CC[ch].CCV = val; } @@ -596,6 +642,7 @@ __STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) ******************************************************************************/ __STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->CNT = val; } @@ -867,6 +914,7 @@ void TIMER_Reset(TIMER_TypeDef *timer); ******************************************************************************/ __STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->TOPB = val; } @@ -899,6 +947,7 @@ __STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) ******************************************************************************/ __STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) { + EFM_ASSERT(val <= TIMER_MaxCount(timer)); timer->TOP = val; } @@ -919,7 +968,6 @@ __STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) } #endif - /** @} (end addtogroup TIMER) */ /** @} (end addtogroup emlib) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h index b80642c9e4..ac79f8d18c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h @@ -2,7 +2,7 @@ * @file em_usart.h * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) * peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -86,7 +86,7 @@ extern "C" { * @if DOXYDOC_P1_DEVICE * @include em_usart_route_p1.c * @note UART hardware flow control is not directly supported in hardware on - * @ref _SILICON_LABS_32B_PLATFORM_1 parts. + * @ref _SILICON_LABS_32B_SERIES_0 parts. * @endif * @if DOXYDOC_P2_DEVICE * @include em_usart_route_p2.c diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h index 66b55c3c85..fdb3e36a2c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_vcmp.h * @brief Voltage Comparator (VCMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h new file mode 100644 index 0000000000..6997dd2ee3 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vdac.h @@ -0,0 +1,420 @@ +/***************************************************************************//** + * @file em_vdac.h + * @brief Digital to Analog Converter (VDAC) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#ifndef EM_VDAC_H +#define EM_VDAC_H + +#include "em_device.h" + +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) + +#include "em_assert.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup VDAC + * @brief Digital to Analog Voltage Converter (VDAC) Peripheral API + * + * @details + * This module contains functions to control the VDAC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The VDAC converts digital values to analog + * signals at up to 500 ksps with 12-bit accuracy. The VDAC is designed for + * low energy consumption, but can also provide very good performance. + * + * The following steps are necessary for basic operation: + * + * Clock enable: + * @code + CMU_ClockEnable(cmuClock_VDAC0, true);@endcode + * + * Initialize the VDAC with default settings and modify selected fields: + * @code + VDAC_Init_TypeDef vdacInit = VDAC_INIT_DEFAULT; + VDAC_InitChannel_TypeDef vdacChInit = VDAC_INITCHANNEL_DEFAULT; + + // Set prescaler to get 1 MHz VDAC clock frequency. + vdacInit.prescaler = VDAC_PrescaleCalc(1000000, true, 0); + VDAC_Init(VDAC0, &vdacInit); + + vdacChInit.enable = true; + VDAC_InitChannel(VDAC0, &vdacChInit, 0);@endcode + * + * Perform a conversion: + * @code + VDAC_ChannelOutputSet(VDAC0, 0, 250);@endcode + * + * @note The output stage of a VDAC channel consist of an onchip operational + * amplifier in the OPAMP module. This opamp is highly configurable and to + * exploit the VDAC functionality fully, you might need to configure the opamp + * using the OPAMP API. By using the OPAMP API you will also load opamp + * calibration values. The default (reset) settings of the opamp will be + * sufficient for many applications. + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of VDAC register block pointer reference for assert statements.*/ +#define VDAC_REF_VALID(ref) ((ref) == VDAC0) + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Channel refresh period. */ +typedef enum +{ + vdacRefresh8 = _VDAC_CTRL_REFRESHPERIOD_8CYCLES, /**< Refresh every 8 clock cycles. */ + vdacRefresh16 = _VDAC_CTRL_REFRESHPERIOD_16CYCLES, /**< Refresh every 16 clock cycles. */ + vdacRefresh32 = _VDAC_CTRL_REFRESHPERIOD_32CYCLES, /**< Refresh every 32 clock cycles. */ + vdacRefresh64 = _VDAC_CTRL_REFRESHPERIOD_64CYCLES, /**< Refresh every 64 clock cycles. */ +} VDAC_Refresh_TypeDef; + +/** Reference voltage for VDAC. */ +typedef enum +{ + vdacRef1V25Ln = _VDAC_CTRL_REFSEL_1V25LN, /**< Internal low noise 1.25 V bandgap reference. */ + vdacRef2V5Ln = _VDAC_CTRL_REFSEL_2V5LN, /**< Internal low noise 2.5 V bandgap reference. */ + vdacRef1V25 = _VDAC_CTRL_REFSEL_1V25, /**< Internal 1.25 V bandgap reference. */ + vdacRef2V5 = _VDAC_CTRL_REFSEL_2V5, /**< Internal 2.5 V bandgap reference. */ + vdacRefAvdd = _VDAC_CTRL_REFSEL_VDD, /**< AVDD reference. */ + vdacRefExtPin = _VDAC_CTRL_REFSEL_EXT, /**< External pin reference. */ +} VDAC_Ref_TypeDef; + +/** Peripheral Reflex System signal used to trig VDAC channel conversion. */ +typedef enum +{ + vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0 , /**< PRS ch 0 triggers conversion. */ + vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1 , /**< PRS ch 1 triggers conversion. */ + vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2 , /**< PRS ch 2 triggers conversion. */ + vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3 , /**< PRS ch 3 triggers conversion. */ + vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4 , /**< PRS ch 4 triggers conversion. */ + vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5 , /**< PRS ch 5 triggers conversion. */ + vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6 , /**< PRS ch 6 triggers conversion. */ + vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7 , /**< PRS ch 7 triggers conversion. */ + vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8 , /**< PRS ch 8 triggers conversion. */ + vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9 , /**< PRS ch 9 triggers conversion. */ + vdacPrsSelCh10 = _VDAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS ch 10 triggers conversion. */ + vdacPrsSelCh11 = _VDAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS ch 11 triggers conversion. */ +} VDAC_PrsSel_TypeDef; + +/** Channel conversion trigger mode. */ +typedef enum +{ + vdacTrigModeSw = _VDAC_CH0CTRL_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ + vdacTrigModePrs = _VDAC_CH0CTRL_TRIGMODE_PRS, /**< Channel is triggered by PRS input. */ + vdacTrigModeRefresh = _VDAC_CH0CTRL_TRIGMODE_REFRESH, /**< Channel is triggered by Refresh timer. */ + vdacTrigModeSwPrs = _VDAC_CH0CTRL_TRIGMODE_SWPRS, /**< Channel is triggered by CHnDATA/COMBDATA write or PRS input. */ + vdacTrigModeSwRefresh = _VDAC_CH0CTRL_TRIGMODE_SWREFRESH, /**< Channel is triggered by CHnDATA/COMBDATA write or Refresh timer. */ + vdacTrigModeLesense = _VDAC_CH0CTRL_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ +} VDAC_TrigMode_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** VDAC init structure, common for both channels. */ +typedef struct +{ + /** Select between main and alternate output path calibration values. */ + bool mainCalibration; + + /** Selects clock from asynchronous or synchronous (with respect to + peripheral clock) source */ + bool asyncClockMode; + + /** Warmup mode, keep VDAC on (in idle) - or shutdown between conversions.*/ + bool warmupKeepOn; + + /** Channel refresh period. */ + VDAC_Refresh_TypeDef refresh; + + /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ + uint32_t prescaler; + + /** Reference voltage to use. */ + VDAC_Ref_TypeDef reference; + + /** Enable/disable reset of prescaler on CH 0 start. */ + bool ch0ResetPre; + + /** Enable/disable output enable control by CH1 PRS signal. */ + bool outEnablePRS; + + /** Enable/disable sine mode. */ + bool sineEnable; + + /** Select if single ended or differential output mode. */ + bool diff; +} VDAC_Init_TypeDef; + +/** Default config for VDAC init structure. */ +#define VDAC_INIT_DEFAULT \ +{ \ + true, /* Use main output path calibration values. */ \ + false, /* Use synchronous clock mode. */ \ + false, /* Turn off between sample off conversions.*/ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25Ln, /* 1.25V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* VDAC output enable always on. */ \ + false, /* Disable sine mode. */ \ + false /* Single ended mode. */ \ +} + +/** VDAC channel init structure. */ +typedef struct +{ + /** Enable channel. */ + bool enable; + + /** + * Peripheral reflex system trigger selection. Only applicable if @p trigMode + * is set to @p vdacTrigModePrs or @p vdacTrigModeSwPrs. */ + VDAC_PrsSel_TypeDef prsSel; + + /** Treat the PRS signal asynchronously. */ + bool prsAsync; + + /** Channel conversion trigger mode. */ + VDAC_TrigMode_TypeDef trigMode; + + /** Set channel conversion mode to sample/shut-off mode. Default is + * continous.*/ + bool sampleOffMode; +} VDAC_InitChannel_TypeDef; + +/** Default config for VDAC channel init structure. */ +#define VDAC_INITCHANNEL_DEFAULT \ +{ \ + false, /* Leave channel disabled when init done. */ \ + vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \ + false, /* Treat PRS channel as a synchronous signal. */ \ + vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ + false, /* Channel conversion set to continous. */ \ +} + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value); +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable); +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init); +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch); + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 0 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 0 by writing @p value + * to the CH0DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 0 output register CH0DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ + EFM_ASSERT(value<=_VDAC_CH0DATA_MASK); + vdac->CH0DATA = value; +} + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 1 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 1 by writing @p value + * to the CH1DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 1 output register CH1DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel1OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ + EFM_ASSERT(value<=_VDAC_CH1DATA_MASK); + vdac->CH1DATA = value; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * Pending VDAC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntClear(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntDisable(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more VDAC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using VDAC_IntClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntEnable(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending VDAC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @return + * VDAC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGet(VDAC_TypeDef *vdac) +{ + return vdac->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending VDAC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled VDAC interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in VDACx_IEN_nnn + * register (VDACx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the VDAC module + * (VDACx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGetEnabled(VDAC_TypeDef *vdac) +{ + uint32_t ien = vdac->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return vdac->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending VDAC interrupts from SW. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntSet(VDAC_TypeDef *vdac, uint32_t flags) +{ + vdac->IFS = flags; +} + +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq); +void VDAC_Reset(VDAC_TypeDef *vdac); + +/** @} (end addtogroup VDAC) */ +/** @} (end addtogroup emlib) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ +#endif /* EM_VDAC_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h index 2ec5de4443..a4e1ca8599 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_version.h * @brief Assign correct part number for include file - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -53,18 +53,18 @@ extern "C" { ******************************************************************************/ /** Version number of emlib peripheral API. */ -#define _EMLIB_VERSION 5.0.0 +#define _EMLIB_VERSION 5.1.2 /** Major version of emlib. Bumped when incompatible API changes introduced. */ #define _EMLIB_VERSION_MAJOR 5 /** Minor version of emlib. Bumped when functionality is added in a backwards- compatible manner. */ -#define _EMLIB_VERSION_MINOR 0 +#define _EMLIB_VERSION_MINOR 1 /** Patch revision of emlib. Bumped when adding backwards-compatible bug fixes.*/ -#define _EMLIB_VERSION_PATCH 0 +#define _EMLIB_VERSION_PATCH 2 /** Version number of targeted CMSIS package. */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h index a554109410..0e4c4a40f0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_wdog.h * @brief Watchdog (WDOG) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c index 9a2bb69f36..ac0c944044 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_acmp.c * @brief Analog Comparator (ACMP) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -230,6 +230,32 @@ void ACMP_Enable(ACMP_TypeDef *acmp) acmp->CTRL |= ACMP_CTRL_EN; } +#if defined(_ACMP_EXTIFCTRL_MASK) +/***************************************************************************//** + * @brief + * Select and enable an external input. + * + * @details + * This is used when an external module needs to take control of the ACMP + * POSSEL field in order to configure the APORT input for the ACMP. Modules + * like LESENSE use this to change the ACMP input during a scan sequence. + * + * @param[in] acmp + * Pointer to ACMP peripheral register block. + * + * @param[in] aport + * This parameter decides which APORT(s) the ACMP will use when it's being + * controlled by an external module. + ******************************************************************************/ +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport) +{ + acmp->EXTIFCTRL = (aport << _ACMP_EXTIFCTRL_APORTSEL_SHIFT) + | ACMP_EXTIFCTRL_EN; + while (!(acmp->STATUS & ACMP_STATUS_EXTIFACT)) + ; +} +#endif + /***************************************************************************//** * @brief * Reset ACMP to same state as after a HW reset. @@ -351,7 +377,8 @@ void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init) EFM_ASSERT(ACMP_REF_VALID(acmp)); /* Make sure biasprog is within bounds */ - EFM_ASSERT(init->biasProg < 16); + EFM_ASSERT(init->biasProg <= + (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); /* Make sure the ACMP is disable since we might be changing the * ACMP power source */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c index a14f6b821e..612c5fe494 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_adc.c * @brief Analog to Digital Converter (ADC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -62,7 +62,7 @@ #define ADC_REF_VALID(ref) ((ref) == ADC0) /** Max ADC clock */ -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #define ADC_MAX_CLOCK 13000000 #else #define ADC_MAX_CLOCK 16000000 @@ -180,7 +180,7 @@ #define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) #define FIX_ADC_TEMP_BIAS_EN #endif /** @endcond */ @@ -418,8 +418,8 @@ void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init) init->em2ClockConfig); #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - /* Fix for errata ADC_EXXX */ +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) + /* A debugger can trigger the SCANUF interrupt on EFM32xG1 or EFR32xG1 */ ADC_IntClear(adc, ADC_IFC_SCANUF); #endif } @@ -750,9 +750,10 @@ void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init) if (init->rep) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - /* Scan repeat mode does not work on platform 2 as described in errata ADC_EXXX. */ - EFM_ASSERT(false); +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) + /* Scan repeat mode does not work on EFM32JG1, EFM32PG1 or EFR32xG1x devices. + * The errata is called ADC_E211 in the errata document. */ + EFM_ASSERT(false); #endif tmp |= ADC_SCANCTRL_REP; } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c index 10c302527d..715535ceee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_aes.c * @brief Advanced Encryption Standard (AES) accelerator peripheral API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c index 9050c63a81..b9bd09a899 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_assert.c * @brief Assert API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c index 018761e4bf..a81a4446b2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_burtc.c * @brief Backup Real Time Counter (BURTC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c index 5b878b892d..dba72ff21f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cmu.c * @brief Clock management unit (CMU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -37,6 +37,7 @@ #include "em_assert.h" #include "em_bus.h" #include "em_emu.h" +#include "em_cmu.h" #include "em_system.h" #include "em_common.h" @@ -60,12 +61,12 @@ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /** Maximum allowed core frequency when using 0 wait-states on flash access. */ #define CMU_MAX_FREQ_0WS 26000000 /** Maximum allowed core frequency when using 1 wait-states on flash access */ #define CMU_MAX_FREQ_1WS 40000000 -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) /** Maximum allowed core frequency when using 0 wait-states on flash access. */ #define CMU_MAX_FREQ_0WS 16000000 /** Maximum allowed core frequency when using 1 wait-states on flash access */ @@ -76,19 +77,21 @@ /** Maximum frequency for HFLE interface */ #if defined( CMU_CTRL_HFLE ) -/** Maximum HFLE frequency for EFM32 and EZR32 Wonder Gecko. */ -#if defined( _EFM32_WONDER_FAMILY ) \ - || defined( _EZR32_WONDER_FAMILY ) +/** Maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ +#if defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_WONDER_FAMILY ) \ + || defined( _EZR32_WONDER_FAMILY )) #define CMU_MAX_FREQ_HFLE 24000000 -/** Maximum HFLE frequency for other platform 1 parts with maximum core clock +/** Maximum HFLE frequency for other series 0 parts with maximum core clock higher than 32MHz. */ -#elif defined( _EFM32_GIANT_FAMILY ) \ - || defined( _EFM32_LEOPARD_FAMILY ) \ - || defined( _EZR32_LEOPARD_FAMILY ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_GIANT_FAMILY ) \ + || defined( _EFM32_LEOPARD_FAMILY ) \ + || defined( _EZR32_LEOPARD_FAMILY )) #define CMU_MAX_FREQ_HFLE maxFreqHfle() #endif #elif defined( CMU_CTRL_WSHFLE ) -/** Maximum HFLE frequency for platform 2 parts */ +/** Maximum HFLE frequency for series 1 parts */ #define CMU_MAX_FREQ_HFLE 32000000 #endif @@ -112,9 +115,10 @@ static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined( _EFM32_GIANT_FAMILY ) \ - || defined( _EFM32_LEOPARD_FAMILY ) \ - || defined( _EZR32_LEOPARD_FAMILY ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) \ + && (defined( _EFM32_GIANT_FAMILY ) \ + || defined( _EFM32_LEOPARD_FAMILY ) \ + || defined( _EZR32_LEOPARD_FAMILY )) /***************************************************************************//** * @brief * Return max allowed frequency for low energy peripherals. @@ -235,7 +239,7 @@ static uint32_t auxClkGet(void) ret = auxHfrcoFreq; #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK ) - /* All platform 1 families except EFM32G */ + /* All series 0 families except EFM32G */ switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { case CMU_AUXHFRCOCTRL_BAND_1MHZ: @@ -585,6 +589,12 @@ static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) ret = SystemULFRCOClockGet(); break; +#if defined( CMU_LFACLKSEL_LFA_PLFRCO ) + case _CMU_LFACLKSEL_LFA_PLFRCO: + ret = SystemLFRCOClockGet(); + break; +#endif + #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) case _CMU_LFACLKSEL_LFA_HFCLKLE: ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) @@ -1101,10 +1111,10 @@ uint32_t CMU_CalibrateCountGet(void) ******************************************************************************/ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) return 1 + (uint32_t)CMU_ClockPrescGet(clock); -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) uint32_t divReg; CMU_ClkDiv_TypeDef ret; @@ -1233,10 +1243,10 @@ CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) ******************************************************************************/ void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) { -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1)); -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) uint32_t freq; uint32_t divReg; @@ -1560,7 +1570,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #endif break; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) #if defined( CRYPTO_PRESENT ) \ || defined( LDMA_PRESENT ) \ || defined( GPCRC_PRESENT ) \ @@ -1584,7 +1594,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) break; #endif -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #if defined( AES_PRESENT ) \ || defined( DMA_PRESENT ) \ || defined( EBI_PRESENT ) \ @@ -1617,10 +1627,10 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFACLKEN0_LETIMER0_MASK ) case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFA); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >> _CMU_LFAPRESC0_LETIMER0_SHIFT); #endif @@ -1659,10 +1669,10 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFBCLKEN0_LEUART0_MASK ) case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >> _CMU_LFBPRESC0_LEUART0_SHIFT); #endif @@ -1672,17 +1682,25 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #if defined( _CMU_LFBCLKEN0_LEUART1_MASK ) case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFB); -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >> _CMU_LFBPRESC0_LEUART1_SHIFT); #endif break; #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _CMU_LFBCLKEN0_CSEN_MASK ) + case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + ret /= CMU_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4); + break; +#endif + +#if defined( _SILICON_LABS_32B_SERIES_1 ) case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): ret = lfClkGet(cmuClock_LFE); break; @@ -1712,7 +1730,7 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) } -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Get clock prescaler. @@ -1809,6 +1827,15 @@ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( _CMU_LFBPRESC0_CSEN_MASK ) + case cmuClock_CSEN_LF: + ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT)); + /* Convert the exponent to prescaler value. */ + ret = CMU_Log2ToDiv(ret + 4) - 1U; + break; +#endif + default: EFM_ASSERT(0); ret = 0U; @@ -1845,7 +1872,7 @@ uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) #endif -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /***************************************************************************//** * @brief * Set clock prescaler. @@ -2044,6 +2071,22 @@ void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) break; #endif +#if defined( _CMU_LFBPRESC0_CSEN_MASK ) + case cmuClock_CSEN_LF: + EFM_ASSERT((presc <= 127U) && (presc >= 15U)); + + /* Convert prescaler value to DIV exponent scale. + * DIV16 is the lowest supported prescaler. */ + presc = CMU_PrescToLog2(presc) - 4; + + /* LF register about to be modified require sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) + | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); + break; +#endif + default: EFM_ASSERT(0); break; @@ -2089,7 +2132,7 @@ void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) * @li #cmuClock_LFA * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO * @li #cmuClock_LFC - * @endif @if _SILICON_LABS_32B_PLATFORM_2 + * @endif @if _SILICON_LABS_32B_SERIES_1 * @li #cmuClock_LFE * @endif * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT @@ -2217,6 +2260,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( CMU_LFACLKSEL_LFA_PLFRCO ) + case CMU_LFACLKSEL_LFA_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2282,6 +2331,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) ret = cmuSelect_HFCLKLE; break; +#if defined( CMU_LFBCLKSEL_LFB_PLFRCO ) + case CMU_LFBCLKSEL_LFB_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2331,6 +2386,12 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) break; #endif +#if defined( CMU_LFECLKSEL_LFE_PLFRCO ) + case CMU_LFECLKSEL_LFE_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + default: ret = cmuSelect_Disabled; break; @@ -2436,7 +2497,7 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) * @li #cmuClock_LFA * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO * @li #cmuClock_LFC - * @endif @if _SILICON_LABS_32B_PLATFORM_2 + * @endif @if _SILICON_LABS_32B_SERIES_1 * @li #cmuClock_LFE * @endif * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT @@ -2454,20 +2515,43 @@ CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) * @li #cmuSelect_AUXHFRCO * @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY * @li #cmuSelect_ULFRCO + * @li #cmuSelect_PLFRCO * @endif ******************************************************************************/ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) { - uint32_t select = cmuOsc_HFRCO; - CMU_Osc_TypeDef osc = cmuOsc_HFRCO; - uint32_t freq; - uint32_t tmp; - uint32_t selRegId; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) - volatile uint32_t *selReg = NULL; + uint32_t select = cmuOsc_HFRCO; + CMU_Osc_TypeDef osc = cmuOsc_HFRCO; + uint32_t freq; + uint32_t tmp; + uint32_t selRegId; +#if defined( _SILICON_LABS_32B_SERIES_1 ) + volatile uint32_t *selReg = NULL; #endif #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) - uint32_t lfExtended = 0; + uint32_t lfExtended = 0; +#endif + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + uint32_t vScaleFrequency = 0; /* Use default */ + + /* Start voltage upscaling before clock is set. */ + if (clock == cmuClock_HF) + { + if (ref == cmuSelect_HFXO) + { + vScaleFrequency = SystemHFXOClockGet(); + } + else if ((ref == cmuSelect_HFRCO) + && (CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) + { + vScaleFrequency = CMU_HFRCOBandGet(); + } + if (vScaleFrequency != 0) + { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } + } #endif selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; @@ -2478,18 +2562,18 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) switch (ref) { case cmuSelect_LFXO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_LFXO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_LFXO; #endif osc = cmuOsc_LFXO; break; case cmuSelect_LFRCO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_LFRCO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_LFRCO; #endif osc = cmuOsc_LFRCO; @@ -2523,9 +2607,9 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) break; case cmuSelect_HFRCO: -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) select = CMU_HFCLKSEL_HF_HFRCO; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) select = CMU_CMD_HFCLKSEL_HFRCO; #endif osc = cmuOsc_HFRCO; @@ -2561,6 +2645,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) /* Configure worst case wait states for flash access before selecting */ flashWaitStateMax(); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Wait for voltage upscaling to complete before clock is set. */ + if (vScaleFrequency != 0) + { + EMU_VScaleWait(); + } +#endif + /* Switch to selected oscillator */ #if defined( _CMU_HFCLKSEL_MASK ) CMU->HFCLKSEL = select; @@ -2573,18 +2665,24 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE); #endif - /* Keep EMU module informed */ - EMU_UpdateOscConfig(); - /* Update CMSIS core clock variable */ /* (The function will update the global variable) */ freq = SystemCoreClockGet(); /* Optimize flash access wait state setting for currently selected core clk */ flashWaitStateControl(freq); + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Keep EMU module informed on source HF clock frequency. This will apply voltage + downscaling after clock is set if downscaling is configured. */ + if (vScaleFrequency == 0) + { + EMU_VScaleEM01ByClock(0, true); + } +#endif break; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) case CMU_LFACLKSEL_REG: selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg; #if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) @@ -2633,6 +2731,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) tmp = _CMU_LFACLKSEL_LFA_ULFRCO; break; +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + case cmuSelect_PLFRCO: + /* Ensure selected oscillator is enabled, waiting for it to stabilize */ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_PLFRCO; + break; +#endif + default: EFM_ASSERT(0); return; @@ -2640,7 +2746,7 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) *selReg = tmp; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_1 ) +#elif defined( _SILICON_LABS_32B_SERIES_0 ) case CMU_LFACLKSEL_REG: case CMU_LFBCLKSEL_REG: switch (ref) @@ -3154,6 +3260,11 @@ void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) /* Reduce HFLE frequency if possible. */ setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE), CMU_MAX_FREQ_HFLE); + + /* Update voltage scaling */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + EMU_VScaleEM01ByClock(0, true); +#endif } #endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ @@ -3238,15 +3349,17 @@ void CMU_HFXOAutostartEnable(uint32_t userSel, | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0) | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0); - CMU->HFXOCTRL = hfxoCtrl; - /* Set wait-states for HFXO if automatic start and select is configured. */ if (userSel || enEM0EM1StartSel) { hfxoFreq = SystemHFXOClockGet(); flashWaitStateControl(hfxoFreq); - setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE); + setHfLeConfig(hfxoFreq, CMU_MAX_FREQ_HFLE); } + + /* Update HFXOCTRL after wait-states are updated as HF may automatically switch + to HFXO when automatic select is enabled . */ + CMU->HFXOCTRL = hfxoCtrl; } #endif @@ -3268,6 +3381,11 @@ void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) /* Do not disable HFXO if it is currently selected as HF/Core clock */ EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); + /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ +#if defined( _EMU_PWRCTRL_REGPWRSEL_MASK ) + EFM_ASSERT(EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD); +#endif + /* HFXO must be disabled before reconfiguration */ CMU_OscillatorEnable(cmuOsc_HFXO, false, true); @@ -3476,7 +3594,7 @@ void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) { uint32_t rdyBitPos; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) uint32_t ensBitPos; #endif #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK ) @@ -3492,7 +3610,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_HFRCOEN; disBit = CMU_OSCENCMD_HFRCODIS; rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; #endif break; @@ -3501,7 +3619,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_HFXOEN; disBit = CMU_OSCENCMD_HFXODIS; rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; #endif break; @@ -3510,7 +3628,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_AUXHFRCOEN; disBit = CMU_OSCENCMD_AUXHFRCODIS; rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; #endif break; @@ -3519,7 +3637,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_LFRCOEN; disBit = CMU_OSCENCMD_LFRCODIS; rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; #endif break; @@ -3528,7 +3646,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_LFXOEN; disBit = CMU_OSCENCMD_LFXODIS; rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; #endif break; @@ -3538,12 +3656,21 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) enBit = CMU_OSCENCMD_USHFRCOEN; disBit = CMU_OSCENCMD_USHFRCODIS; rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; #endif break; #endif +#if defined( _CMU_STATUS_PLFRCOENS_MASK ) + case cmuOsc_PLFRCO: + enBit = CMU_OSCENCMD_PLFRCOEN; + disBit = CMU_OSCENCMD_PLFRCODIS; + rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT; + ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT; + break; +#endif + default: /* Undefined clock source or cmuOsc_ULFRCO. ULFRCO is always enabled, and cannot be disabled. Ie. the definition of cmuOsc_ULFRCO is primarely @@ -3576,7 +3703,7 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) #endif CMU->OSCENCMD = enBit; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Always wait for ENS to go high */ while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos)) { @@ -3618,16 +3745,13 @@ void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) { CMU->OSCENCMD = disBit; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Always wait for ENS to go low */ while (BUS_RegBitRead(&CMU->STATUS, ensBitPos)) { } #endif } - - /* Keep EMU module informed */ - EMU_UpdateOscConfig(); } @@ -3715,7 +3839,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT)); #endif CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) @@ -3726,7 +3850,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)) { } @@ -3739,7 +3863,7 @@ void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT)) { } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c index 90283edf82..8f1895e844 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_core.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_core.c * @brief Core interrupt handling API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -63,11 +63,13 @@ blocking capabilities. @li CRITICAL section: Inside a critical sections all interrupts are - disabled (except for fault handlers). The PRIMASK register is used for + disabled (except for fault handlers). The PRIMASK register is always used for interrupt disable/enable. - @li ATOMIC section: Interrupts with priority equal to or lower than a - given level are disabled. The interrupt disable priority level is defined - at compile time. The BASEPRI register is used for interrupt disable/enable. + @li ATOMIC section: This type of section is configurable and the default + method is to use PRIMASK. With BASEPRI configuration, interrupts with priority + equal to or lower than a given configurable level are disabled. The interrupt + disable priority level is defined at compile time. The BASEPRI register is not + available for all architectures. @li NVIC mask section: Disable NVIC (external interrupts) on an individual manner. @@ -535,7 +537,7 @@ void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) /***************************************************************************//** * @brief - * Get current NVIC interrupt enable mask. + * Set current NVIC interrupt enable mask. * * @param[out] enable * Mask specifying which NVIC interrupts are currently enabled. @@ -556,7 +558,7 @@ void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) * Mask specifying which NVIC interrupts to briefly enable. * * @note - * Usully used within a NVIC mask section. + * Usually used within a NVIC mask section. ******************************************************************************/ void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c index 7a4b67acdb..871a0b8641 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cryotimer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_cryotimer.c * @brief Ultra Low Energy Timer/Counter (CRYOTIMER) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c index fd6b29a44c..d3c526abc6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_crypto.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_crypto.c * @brief Cryptography accelerator peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -1139,12 +1139,13 @@ void CRYPTO_AES_DecryptKey128(CRYPTO_TypeDef * crypto, uint32_t * _out = (uint32_t *) out; const uint32_t * _in = (const uint32_t *) in; + /* Setup CRYPTO in AES-128 mode. */ + crypto->CTRL = CRYPTO_CTRL_AES_AES128; + /* Load key */ CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]); /* Do dummy encryption to generate decrypt key */ - crypto->CTRL = CRYPTO_CTRL_AES_AES128; - CRYPTO_IntClear(crypto, CRYPTO_IF_INSTRDONE); crypto->CMD = CRYPTO_CMD_INSTR_AESENC; /* Save decryption key */ @@ -1176,12 +1177,14 @@ void CRYPTO_AES_DecryptKey256(CRYPTO_TypeDef * crypto, uint32_t * _out = (uint32_t *) out; const uint32_t * _in = (const uint32_t *) in; + /* Setup CRYPTO in AES-256 mode. */ + crypto->CTRL = CRYPTO_CTRL_AES_AES256; + /* Load key */ CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[0]); CRYPTO_BurstToCrypto(&crypto->KEYBUF, &_in[4]); /* Do dummy encryption to generate decrypt key */ - crypto->CTRL = CRYPTO_CTRL_AES_AES256; crypto->CMD = CRYPTO_CMD_INSTR_AESENC; /* Save decryption key */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c new file mode 100644 index 0000000000..331fa724e5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_csen.c @@ -0,0 +1,294 @@ +/***************************************************************************//** + * @file em_csen.c + * @brief Capacitive Sense Module (CSEN) peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#include "em_csen.h" +#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 ) + +#include "em_assert.h" +#include "em_cmu.h" +#include + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup CSEN + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of CSEN register block pointer reference for assert statements. */ +#define CSEN_REF_VALID(ref) ((ref) == CSEN) + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set the DM integrator initial value. + * + * @details + * Sets the initial value of the integrator(s) for the Delta Modulation (DM) + * converter. The initial value for the ramp-down integrator has no effect + * if low frequency attenuation was not selected by the mode initialization + * function @ref CSEN_InitMode(). + * + * @note + * Confirm CSEN is idle before calling this function. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] up + * Initial value for the ramp-up integrator. + * + * @param[in] down + * Initial value for the ramp-down integrator. Has no effect if low frequency + * attenuation is not configured. + ******************************************************************************/ +void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down) +{ + EFM_ASSERT(up < 0x10000); + EFM_ASSERT(down < 0x10000); + + csen->DMBASELINE = (up << _CSEN_DMBASELINE_BASELINEUP_SHIFT) + | (down << _CSEN_DMBASELINE_BASELINEDN_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Initialize CSEN. + * + * @details + * Initializes common functionality for all measurement types. In addition, + * measurement mode must be configured, please refer to @ref CSEN_InitMode(). + * + * @note + * This function will stop any ongoing conversion and disable CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] init + * Pointer to CSEN initialization structure. + ******************************************************************************/ +void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init) +{ + uint32_t tmp; + + EFM_ASSERT(CSEN_REF_VALID(csen)); + EFM_ASSERT(init->warmUpCount < 4); + + /* Initialize CTRL. This will stop any conversion in progress. */ + tmp = CSEN_CTRL_STM_DEFAULT; + + if (init->cpAccuracyHi) + { + tmp |= CSEN_CTRL_CPACCURACY_HI; + } + + if (init->localSense) + { + tmp |= _CSEN_CTRL_LOCALSENS_MASK; + } + + if (init->keepWarm) + { + tmp |= CSEN_CTRL_WARMUPMODE_KEEPCSENWARM; + } + + csen->CTRL = tmp; + + /* Initialize TIMCTRL. */ + csen->TIMCTRL = (init->warmUpCount << _CSEN_TIMCTRL_WARMUPCNT_SHIFT) + | (init->pcReload << _CSEN_TIMCTRL_PCTOP_SHIFT) + | (init->pcPrescale << _CSEN_TIMCTRL_PCPRESC_SHIFT); + + /* PRSSEL only has one field */ + csen->PRSSEL = init->prsSel << _CSEN_PRSSEL_PRSSEL_SHIFT; + + /* Set input selections for inputs 0 to 31 */ + csen->SCANINPUTSEL0 = (init->input0To7 << _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT) + | (init->input8To15 << _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT) + | (init->input16To23 << _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT) + | (init->input24To31 << _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT); + + /* Set input selections for inputs 32 to 63 */ + csen->SCANINPUTSEL1 = (init->input32To39 << _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT) + | (init->input40To47 << _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT) + | (init->input48To55 << _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT) + | (init->input56To63 << _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Initialize a CSEN measurement mode. + * + * @details + * Used to configure any type of measurement mode. After the measurement + * has been configured, calling @ref CSEN_Enable() will enable CSEN and + * allow it to start a conversion from the selected trigger source. To + * manually start a conversion use @ref CSEN_Start(). To check if a + * conversion is in progress use @ref CSEN_IsBusy(), or alternatively + * use the interrupt flags returned by @ref CSEN_IntGet() to detect when + * a conversion is completed. + * + * @note + * This function will stop any ongoing conversion and disable CSEN. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + * + * @param[in] init + * Pointer to CSEN measurement mode initialization structure. + ******************************************************************************/ +void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init) +{ + uint32_t tmp; + + EFM_ASSERT(CSEN_REF_VALID(csen)); + EFM_ASSERT(init->dmIterPerCycle < 0x10); + EFM_ASSERT(init->dmCycles < 0x10); + + /* Initialize CTRL. This will stop any conversion in progress. + * These composite inputs set multiple fields. They do not need + * to be shifted. */ + tmp = ((uint32_t)init->sampleMode + | (uint32_t)init->convSel + | (uint32_t)init->cmpMode); + + tmp |= (init->trigSel << _CSEN_CTRL_STM_SHIFT) + | (init->accMode << _CSEN_CTRL_ACU_SHIFT) + | (init->sarRes << _CSEN_CTRL_SARCR_SHIFT); + + if (init->enableDma) + { + tmp |= CSEN_CTRL_DMAEN_ENABLE; + } + + if (init->sumOnly) + { + tmp |= CSEN_CTRL_DRSF_ENABLE; + } + + if (init->autoGnd) + { + tmp |= CSEN_CTRL_AUTOGND_ENABLE; + } + + /* Preserve the fields that were initialized by CSEN_Init(). */ + tmp |= csen->CTRL & (_CSEN_CTRL_CPACCURACY_MASK + | _CSEN_CTRL_LOCALSENS_MASK + | _CSEN_CTRL_WARMUPMODE_MASK); + + csen->CTRL = tmp; + + /* EMACTRL only has one field */ + csen->EMACTRL = init->emaSample << _CSEN_EMACTRL_EMASAMPLE_SHIFT; + + /* CMPTHR only has one field */ + csen->CMPTHR = init->cmpThr << _CSEN_CMPTHR_CMPTHR_SHIFT; + + /* SINGLECTRL only has one field */ + csen->SINGLECTRL = init->singleSel << _CSEN_SINGLECTRL_SINGLESEL_SHIFT; + + /* Set all input enables */ + csen->SCANMASK0 = init->inputMask0; + csen->SCANMASK1 = init->inputMask1; + + /* Initialize DMCFG. */ + tmp = (init->dmRes << _CSEN_DMCFG_CRMODE_SHIFT) + | (init->dmCycles << _CSEN_DMCFG_DMCR_SHIFT) + | (init->dmIterPerCycle << _CSEN_DMCFG_DMR_SHIFT) + | (init->dmDelta << _CSEN_DMCFG_DMG_SHIFT); + + if (init->dmFixedDelta) + { + tmp |= CSEN_DMCFG_DMGRDIS; + } + + csen->DMCFG = tmp; + + /* Initialize ANACTRL. */ + csen->ANACTRL = (init->resetPhase << _CSEN_ANACTRL_TRSTPROG_SHIFT) + | (init->driveSel << _CSEN_ANACTRL_IDACIREFS_SHIFT) + | (init->gainSel << _CSEN_ANACTRL_IREFPROG_SHIFT); +} + + +/***************************************************************************//** + * @brief + * Reset CSEN to same state as after a HW reset. + * + * @param[in] csen + * Pointer to CSEN peripheral register block. + ******************************************************************************/ +void CSEN_Reset(CSEN_TypeDef *csen) +{ + EFM_ASSERT(CSEN_REF_VALID(csen)); + + /* Resetting CTRL stops any conversion in progress. */ + csen->CTRL = _CSEN_CTRL_RESETVALUE; + csen->TIMCTRL = _CSEN_TIMCTRL_RESETVALUE; + csen->PRSSEL = _CSEN_PRSSEL_RESETVALUE; + csen->DATA = _CSEN_DATA_RESETVALUE; + csen->SCANMASK0 = _CSEN_SCANMASK0_RESETVALUE; + csen->SCANINPUTSEL0 = _CSEN_SCANINPUTSEL0_RESETVALUE; + csen->SCANMASK1 = _CSEN_SCANMASK1_RESETVALUE; + csen->SCANINPUTSEL1 = _CSEN_SCANINPUTSEL1_RESETVALUE; + csen->CMPTHR = _CSEN_CMPTHR_RESETVALUE; + csen->EMA = _CSEN_EMA_RESETVALUE; + csen->EMACTRL = _CSEN_EMACTRL_RESETVALUE; + csen->SINGLECTRL = _CSEN_SINGLECTRL_RESETVALUE; + csen->DMBASELINE = _CSEN_DMBASELINE_RESETVALUE; + csen->DMCFG = _CSEN_DMCFG_RESETVALUE; + csen->ANACTRL = _CSEN_ANACTRL_RESETVALUE; + csen->IEN = _CSEN_IEN_RESETVALUE; + csen->IFC = _CSEN_IF_MASK; +} + + +/** @} (end addtogroup CSEN) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c index de6694d365..074dc94530 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dac.c * @brief Digital to Analog Converter (DAC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c index 0888225897..c259a967bd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dbg.c * @brief Debug (DBG) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c index 7dae4a395e..4ad4cdb8fa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_dma.c * @brief Direct memory access (DMA) module peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -173,7 +173,7 @@ static void DMA_Prepare(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1) { DMA_DESCRIPTOR_TypeDef *descr; @@ -209,7 +209,7 @@ static void DMA_Prepare(unsigned int channel, inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT; if (inc == _DMA_CTRL_SRC_INC_NONE) { - descr->SRCEND = src; + descr->SRCEND = (volatile void*)src; } else { @@ -386,7 +386,7 @@ void DMA_IRQHandler(void) void DMA_ActivateAuto(unsigned int channel, bool primary, void *dst, - void *src, + const void *src, unsigned int nMinus1) { uint32_t chBit; @@ -450,7 +450,7 @@ void DMA_ActivateBasic(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1) { EFM_ASSERT(channel < DMA_CHAN_COUNT); @@ -521,10 +521,10 @@ void DMA_ActivateBasic(unsigned int channel, void DMA_ActivatePingPong(unsigned int channel, bool useBurst, void *primDst, - void *primSrc, + const void *primSrc, unsigned int primNMinus1, void *altDst, - void *altSrc, + const void *altSrc, unsigned int altNMinus1) { EFM_ASSERT(channel < DMA_CHAN_COUNT); @@ -1136,7 +1136,7 @@ void DMA_RefreshPingPong(unsigned int channel, bool primary, bool useBurst, void *dst, - void *src, + const void *src, unsigned int nMinus1, bool stop) { @@ -1174,7 +1174,7 @@ void DMA_RefreshPingPong(unsigned int channel, inc = (descr->CTRL & _DMA_CTRL_SRC_INC_MASK) >> _DMA_CTRL_SRC_INC_SHIFT; if (inc == _DMA_CTRL_SRC_INC_NONE) { - descr->SRCEND = src; + descr->SRCEND = (volatile void*)src; } else { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c index 6c1c5178c0..fd114788f7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ebi.c * @brief External Bus Interface (EBI) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c index c5d329e6c6..154bae1252 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_emu.c * @brief Energy Management Unit (EMU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -70,9 +70,10 @@ #error Conflict in LFXOENS and LFXOEN bitpositions #endif - /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Fix for errata EMU_E107 - non-WIC interrupt masks. */ +#if defined( _SILICON_LABS_32B_SERIES_0 ) +/* Fix for errata EMU_E107 - non-WIC interrupt masks. + * Zero Gecko and future families are not affected by errata EMU_E107 */ #if defined( _EFM32_GECKO_FAMILY ) #define ERRATA_FIX_EMU_E107_EN #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) @@ -93,41 +94,65 @@ #define NON_WIC_INT_MASK_0 (~(0xff020e63U)) #define NON_WIC_INT_MASK_1 (~(0x00000046U)) -#else -/* Zero Gecko and future families are not affected by errata EMU_E107 */ +#endif #endif /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ -#if defined( _EFM32_HAPPY_FAMILY ) +#if defined(_SILICON_LABS_32B_SERIES_0) && defined( _EFM32_HAPPY_FAMILY ) #define ERRATA_FIX_EMU_E108_EN #endif /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_EMU_E208_EN #endif /* Enable FETCNT tuning errata fix */ -#if defined( _EMU_DCDCCTRL_MASK ) && defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_DCDC_FETCNT_SET_EN #endif /* Enable LN handshake errata fix */ -#if defined( _EMU_DCDCCTRL_MASK ) && ( _SILICON_LABS_32B_PLATFORM_2_GEN < 3 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) #define ERRATA_FIX_DCDC_LNHS_BLOCK_EN +typedef enum +{ + errataFixDcdcHsInit, + errataFixDcdcHsTrimSet, + errataFixDcdcHsBypassLn, + errataFixDcdcHsLnWaitDone +} errataFixDcdcHs_TypeDef; +static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; #endif -/* Enable bypass current limiter enable timing fix */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_2 ) -#define ERRATA_FIX_BYPLIMEN_TIMING_EN +/* Used to figure out if a memory address is inside or outside of a RAM block. + * A memory address is inside a RAM block if the address is greater than the + * RAM block address. */ +#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block)) + +/* RAM Block layout for various device families. Note that some devices + * have special layout in RAM0. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +#define RAM1_BLOCKS 2 +#define RAM1_BLOCK_SIZE 0x10000 // 64 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +#define RAM0_BLOCKS 2 +#define RAM0_BLOCK_SIZE 0x4000 +#define RAM1_BLOCKS 2 +#define RAM1_BLOCK_SIZE 0x4000 // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) +#define RAM0_BLOCKS 4 +#define RAM0_BLOCK_SIZE 0x8000 // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) +#define RAM0_BLOCKS 4 +#define RAM0_BLOCK_SIZE 0x1000 // 4 kB blocks #endif -#define EMU_DCDCCLIMCTRL (uint32_t *)(EMU_BASE + 0x054) -#if !defined(_EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT) -#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 -#endif -#if !defined(_EMU_PWRCTRL_DVDDBODDIS_SHIFT) -#define EMU_PWRCTRL_DVDDBODDIS (1 << 12) +#if defined(_SILICON_LABS_32B_SERIES_0) +/* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE */ +#define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) +#else +#define RAM0_END RAM_MEM_END #endif /** @endcond */ @@ -141,41 +166,23 @@ #if !defined(PWRCFG_DCDCTODVDD_VMAX) #define PWRCFG_DCDCTODVDD_VMAX 3000 #endif - -typedef enum -{ - errataFixDcdcHsInit, - errataFixDcdcHsTrimSet, - errataFixDcdcHsBypassLn, - errataFixDcdcHsLnWaitDone -} errataFixDcdcHs_TypeDef; -errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; #endif /******************************************************************************* - ************************** LOCAL VARIABLES ******************************** + *************************** LOCAL VARIABLES ******************************** ******************************************************************************/ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** - * CMU configured oscillator selection and oscillator enable status. When a - * user configures oscillators, this varaiable shall shadow the configuration. - * It is used by the EMU module in order to be able to restore the oscillator - * config after having been in certain energy modes (since HW may automatically - * alter config when going into an energy mode). It is the responsibility of - * the CMU module to keep it up-to-date (or a user if not using the CMU API - * for oscillator control). - */ -static uint32_t cmuStatus; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) -static uint16_t cmuHfclkStatus; -#endif + +/* Static user configuration */ #if defined( _EMU_DCDCCTRL_MASK ) static uint16_t dcdcMaxCurrent_mA; static uint16_t dcdcEm01LoadCurrent_mA; static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; #endif - +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +static EMU_EM01Init_TypeDef vScaleEM01Config = {false}; +#endif /** @endcond */ @@ -185,147 +192,105 @@ static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/* Convert from level to EM0 and 1 command bit */ +__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) +{ + return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); +} +#endif + /***************************************************************************//** * @brief - * Restore oscillators and core clock after having been in EM2 or EM3. + * Save/restore/update oscillator, core clock and voltage scaling configuration on + * EM2 or EM3 entry/exit. + * + * @details + * Hardware may automatically change oscillator and voltage scaling configuration + * when going into or out of an energy mode. Static data in this function keeps track of + * such configuration bits and is used to restore state if needed. + * ******************************************************************************/ -static void emuRestore(void) +typedef enum +{ + emState_Save, /* Save EMU and CMU state */ + emState_Restore, /* Restore and unlock */ +} emState_TypeDef; + +static void emState(emState_TypeDef action) { uint32_t oscEnCmd; uint32_t cmuLocked; + static uint32_t cmuStatus; + static CMU_Select_TypeDef hfClock; +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + static uint8_t vScaleStatus; +#endif - /* Although we could use the CMU API for most of the below handling, we */ - /* would like this function to be as efficient as possible. */ - /* CMU registers may be locked */ - cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; - CMU_Unlock(); + /* Save or update state */ + if (action == emState_Save) + { + /* Save configuration. */ + cmuStatus = CMU->STATUS; + hfClock = CMU_ClockSelectGet(cmuClock_HF); +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Save vscale */ + EMU_VScaleWait(); + vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); +#endif + } + else if (action == emState_Restore) /* Restore state */ + { + /* Apply saved configuration. */ +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) + /* Restore EM0 and 1 voltage scaling level. EMU_VScaleWait() is called later, + just before HF clock select is set. */ + EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); +#endif - /* AUXHFRCO are automatically disabled (except if using debugger). */ - /* HFRCO, USHFRCO and HFXO are automatically disabled. */ - /* LFRCO/LFXO may be disabled by SW in EM3. */ - /* Restore according to status prior to entering energy mode. */ - oscEnCmd = 0; - oscEnCmd |= ((cmuStatus & CMU_STATUS_HFRCOENS) ? CMU_OSCENCMD_HFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_AUXHFRCOENS) ? CMU_OSCENCMD_AUXHFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_LFRCOENS) ? CMU_OSCENCMD_LFRCOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_HFXOENS) ? CMU_OSCENCMD_HFXOEN : 0); - oscEnCmd |= ((cmuStatus & CMU_STATUS_LFXOENS) ? CMU_OSCENCMD_LFXOEN : 0); + /* CMU registers may be locked */ + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + + /* AUXHFRCO are automatically disabled (except if using debugger). */ + /* HFRCO, USHFRCO and HFXO are automatically disabled. */ + /* LFRCO/LFXO may be disabled by SW in EM3. */ + /* Restore according to status prior to entering energy mode. */ + oscEnCmd = 0; + oscEnCmd |= ((cmuStatus & CMU_STATUS_HFRCOENS) ? CMU_OSCENCMD_HFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_AUXHFRCOENS) ? CMU_OSCENCMD_AUXHFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_LFRCOENS) ? CMU_OSCENCMD_LFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_HFXOENS) ? CMU_OSCENCMD_HFXOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_LFXOENS) ? CMU_OSCENCMD_LFXOEN : 0); #if defined( _CMU_STATUS_USHFRCOENS_MASK ) - oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0); + oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0); #endif - CMU->OSCENCMD = oscEnCmd; + CMU->OSCENCMD = oscEnCmd; - -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - /* Restore oscillator used for clocking core */ - switch (cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) - { - case CMU_HFCLKSTATUS_SELECTED_LFRCO: - /* HFRCO could only be selected if the autostart HFXO feature is not - * enabled, otherwise the HFXO would be started and selected automatically. - * Note: this error hook helps catching erroneous oscillator configurations, - * when the AUTOSTARTSELEM0EM1 is set in CMU_HFXOCTRL. */ - if (!(CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1)) - { - /* Wait for LFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFRCORDY)) - ; - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO; - } - else - { - EFM_ASSERT(0); - } - break; - - case CMU_HFCLKSTATUS_SELECTED_LFXO: - /* Wait for LFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFXORDY)) - ; - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO; - break; - - case CMU_HFCLKSTATUS_SELECTED_HFXO: - /* Wait for HFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_HFXORDY)) - ; -#if defined( _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK ) - if (BUS_RegMaskedRead(&CMU->HFXOCTRL, - _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) - { - while (BUS_RegMaskedRead(&CMU->STATUS, - _CMU_STATUS_HFXOSHUNTOPTRDY_MASK - | _CMU_STATUS_HFXOPEAKDETRDY_MASK) - != (CMU_STATUS_HFXOSHUNTOPTRDY | CMU_STATUS_HFXOPEAKDETRDY)) - ; - } -#endif - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; - break; - - default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ - /* If core clock was HFRCO core clock, it is automatically restored to */ - /* state prior to entering energy mode. No need for further action. */ - break; - } -#else - switch (cmuStatus & (CMU_STATUS_HFRCOSEL - | CMU_STATUS_HFXOSEL - | CMU_STATUS_LFRCOSEL -#if defined( CMU_STATUS_USHFRCODIV2SEL ) - | CMU_STATUS_USHFRCODIV2SEL -#endif - | CMU_STATUS_LFXOSEL)) - { - case CMU_STATUS_LFRCOSEL: - /* Wait for LFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFRCORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO; - break; - - case CMU_STATUS_LFXOSEL: - /* Wait for LFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_LFXORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_LFXO; - break; - - case CMU_STATUS_HFXOSEL: - /* Wait for HFXO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_HFXORDY)) - ; - CMU->CMD = CMU_CMD_HFCLKSEL_HFXO; - break; - -#if defined( CMU_STATUS_USHFRCODIV2SEL ) - case CMU_STATUS_USHFRCODIV2SEL: - /* Wait for USHFRCO to stabilize */ - while (!(CMU->STATUS & CMU_STATUS_USHFRCORDY)) - ; - CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2; - break; +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* Wait for upscale to complete and then restore selected clock */ + EMU_VScaleWait(); #endif - default: /* CMU_STATUS_HFRCOSEL */ - /* If core clock was HFRCO core clock, it is automatically restored to */ - /* state prior to entering energy mode. No need for further action. */ - break; - } + if (hfClock != cmuSelect_HFRCO) + { + CMU_ClockSelectSet(cmuClock_HF, hfClock); + } - /* If HFRCO was disabled before entering Energy Mode, turn it off again */ - /* as it is automatically enabled by wake up */ - if ( ! (cmuStatus & CMU_STATUS_HFRCOENS) ) - { - CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; - } -#endif - /* Restore CMU register locking */ - if (cmuLocked) - { - CMU_Lock(); + /* If HFRCO was disabled before entering Energy Mode, turn it off again */ + /* as it is automatically enabled by wake up */ + if ( ! (cmuStatus & CMU_STATUS_HFRCOENS) ) + { + CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; + } + + /* Restore CMU register locking */ + if (cmuLocked) + { + CMU_Lock(); + } } } @@ -412,7 +377,49 @@ static void dcdcHsFixLnBlock(void) #endif +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) +/* Configure EMU and CMU for EM2 and 3 voltage downscale */ +static void vScaleDownEM23Setup(void) +{ + uint32_t hfSrcClockFrequency; + EMU_VScaleEM23_TypeDef scaleEM23Voltage = + (EMU_VScaleEM23_TypeDef)((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) + >> _EMU_CTRL_EM23VSCALE_SHIFT); + + EMU_VScaleEM01_TypeDef currentEM01Voltage = + (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); + + /* Wait until previous scaling is done. */ + EMU_VScaleWait(); + + /* Inverse coding. */ + if ((uint32_t)scaleEM23Voltage > (uint32_t)currentEM01Voltage) + { + /* Set safe clock and wait-states. */ + if (scaleEM23Voltage == emuVScaleEM23_LowPower) + { + hfSrcClockFrequency = CMU_ClockDivGet(cmuClock_HF) * CMU_ClockFreqGet(cmuClock_HF); + /* Set default low power voltage HFRCO band as HF clock. */ + if (hfSrcClockFrequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX) + { + CMU_HFRCOBandSet(cmuHFRCOFreq_19M0Hz); + } + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + } + else + { + /* Other voltage scaling levels are not currently supported. */ + EFM_ASSERT(false); + } + } + else + { + /* Same voltage or hardware will scale to min(EMU_CTRL_EM23VSCALE, EMU_STATUS_VSCALE) */ + } +} +#endif /** @endcond */ @@ -458,9 +465,13 @@ static void dcdcHsFixLnBlock(void) * the starting and selecting of the core clocks will be identical to the user * independently of the value of the @p restore parameter when waking up on * the wakeup sources corresponding to the autostart and select setting. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM2 level, then the EM0 level is + * also restored. * * @param[in] restore - * @li true - restore oscillators and clocks, see function details. + * @li true - restore oscillators, clocks and voltage scaling, see function details. * @li false - do not restore oscillators and clocks, see function details. * @par * The @p restore option should only be used if all clock control is done @@ -473,11 +484,11 @@ void EMU_EnterEM2(bool restore) uint32_t nonWicIntEn[2]; #endif - /* Auto-update CMU status just in case before entering energy mode. */ - /* This variable is normally kept up-to-date by the CMU API. */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); + /* Save EMU and CMU state requiring restore on EM2 exit. */ + emState(emState_Save); + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + vScaleDownEM23Setup(); #endif /* Enter Cortex deep sleep mode */ @@ -504,9 +515,6 @@ void EMU_EnterEM2(bool restore) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif __WFI(); @@ -525,21 +533,16 @@ void EMU_EnterEM2(bool restore) } #endif - /* Restore oscillators/clocks if specified */ + /* Restore oscillators/clocks and voltage scaling if supported. */ if (restore) { - emuRestore(); + emState(emState_Restore); } - /* If not restoring, and original clock was not HFRCO, we have to */ - /* update CMSIS core clock variable since core clock has changed */ - /* to using HFRCO. */ -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) - != CMU_HFCLKSTATUS_SELECTED_HFRCO) -#else - else if (!(cmuStatus & CMU_STATUS_HFRCOSEL)) -#endif + else { + /* If not restoring, and original clock was not HFRCO, we have to */ + /* update CMSIS core clock variable since HF clock has changed */ + /* to HFRCO. */ SystemCoreClockUpdate(); } } @@ -579,9 +582,13 @@ void EMU_EnterEM2(bool restore) * If a debugger is attached, the AUXHFRCO will not be disabled if enabled * upon entering EM3. It will thus remain enabled when returning to EM0 * regardless of the @p restore parameter. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM3 level, then the EM0 level is + * also restored. * * @param[in] restore - * @li true - restore oscillators and clocks, see function details. + * @li true - restore oscillators, clocks and voltage scaling, see function details. * @li false - do not restore oscillators and clocks, see function details. * @par * The @p restore option should only be used if all clock control is done @@ -596,11 +603,11 @@ void EMU_EnterEM3(bool restore) uint32_t nonWicIntEn[2]; #endif - /* Auto-update CMU status just in case before entering energy mode. */ - /* This variable is normally kept up-to-date by the CMU API. */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); + /* Save EMU and CMU state requiring restore on EM2 exit. */ + emState(emState_Save); + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + vScaleDownEM23Setup(); #endif /* CMU registers may be locked */ @@ -640,9 +647,6 @@ void EMU_EnterEM3(bool restore) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif __WFI(); @@ -661,26 +665,36 @@ void EMU_EnterEM3(bool restore) } #endif - /* Restore oscillators/clocks if specified */ + /* Restore oscillators/clocks and voltage scaling if supported. */ if (restore) { - emuRestore(); + emState(emState_Restore); } - /* If not restoring, and original clock was not HFRCO, we have to */ - /* update CMSIS core clock variable since core clock has changed */ - /* to using HFRCO. */ -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK) - != CMU_HFCLKSTATUS_SELECTED_HFRCO) -#else - else if (!(cmuStatus & CMU_STATUS_HFRCOSEL)) -#endif + else { + /* If not restoring, and original clock was not HFRCO, we have to */ + /* update CMSIS core clock variable since HF clock has changed */ + /* to HFRCO. */ SystemCoreClockUpdate(); } } +/***************************************************************************//** + * @brief + * Restore CMU HF clock select state, oscillator enable and voltage scaling + * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the application to evaluate the + * wakeup reason before restoring state. + ******************************************************************************/ +void EMU_Restore(void) +{ + emState(emState_Restore); +} + + /***************************************************************************//** * @brief * Enter energy mode 4 (EM4). @@ -745,9 +759,6 @@ void EMU_EnterEM4(void) #if defined( ERRATA_FIX_DCDC_LNHS_BLOCK_EN ) dcdcHsFixLnBlock(); #endif -#if defined( ERRATA_FIX_BYPLIMEN_TIMING_EN ) - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif for (i = 0; i < 4; i++) { @@ -805,69 +816,258 @@ void EMU_EnterEM4S(void) * memory blocks for a device. * * @note - * Only a reset can make the specified memory block(s) available for use - * after having been powered down. Function will be void for devices not - * supporting this feature. + * Only a POR reset can power up the specified memory block(s) after powerdown. + * + * @deprecated + * This function is deprecated, use @ref EMU_RamPowerDown() instead which + * maps a user provided memory range into RAM blocks to power down. ******************************************************************************/ void EMU_MemPwrDown(uint32_t blocks) { -#if defined( _EMU_MEMCTRL_POWERDOWN_MASK ) - EFM_ASSERT(blocks <= (_EMU_MEMCTRL_POWERDOWN_MASK - >> _EMU_MEMCTRL_POWERDOWN_SHIFT)); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) \ - && defined( _EMU_MEMCTRL_RAMHPOWERDOWN_MASK ) \ - && defined( _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & (_EMU_MEMCTRL_RAMPOWERDOWN_MASK - | _EMU_MEMCTRL_RAMHPOWERDOWN_MASK - | _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK)) - == blocks); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & _EMU_MEMCTRL_RAMPOWERDOWN_MASK) == blocks); - EMU->MEMCTRL = blocks; - -#elif defined( _EMU_RAM0CTRL_RAMPOWERDOWN_MASK ) - EFM_ASSERT((blocks & _EMU_RAM0CTRL_RAMPOWERDOWN_MASK) == blocks); - EMU->RAM0CTRL = blocks; - +#if defined( _EMU_MEMCTRL_MASK ) + EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; +#elif defined( _EMU_RAM0CTRL_MASK ) + EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; #else (void)blocks; #endif } +/***************************************************************************//** + * @brief + * Power down RAM memory blocks. + * + * @details + * This function will power down all the RAM blocks that are within a given + * range. The RAM block layout is different between device families, so this + * function can be used in a generic way to power down a RAM memory region + * which is known to be unused. + * + * This function will only power down blocks which are completely enclosed + * by the memory range given by [start, end). + * + * Here is an example of how to power down all RAM blocks except the first + * one. The first RAM block is special in that it cannot be powered down + * by the hardware. The size of this first RAM block is device specific + * see the reference manual to find the RAM block sizes. + * + * @code + * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); + * @endcode + * + * @note + * Only a POR reset can power up the specified memory block(s) after powerdown. + * + * @param[in] start + * The start address of the RAM region to power down. This address is + * inclusive. + * + * @param[in] end + * The end address of the RAM region to power down. This address is + * exclusive. If this parameter is 0, then all RAM blocks contained in the + * region from start to the upper RAM address will be powered down. + ******************************************************************************/ +void EMU_RamPowerDown(uint32_t start, uint32_t end) +{ + uint32_t mask = 0; + + if (end == 0) + { + end = SRAM_BASE + SRAM_SIZE; + } + + // Check to see if something in RAM0 can be powered down + if (end > RAM0_END) + { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 + // Block 0 is 16 kB and cannot be powered off + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 0; // Block 1, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000) << 1; // Block 2, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000) << 2; // Block 3, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000) << 3; // Block 4, 64 kB +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 + // Block 0 is 4 kB and cannot be powered off + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000) << 0; // Block 1, 4 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000) << 1; // Block 2, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000) << 2; // Block 3, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000) << 3; // Block 4, 7 kB +#elif defined(RAM0_BLOCKS) + // These platforms have equally sized RAM blocks + for (int i = 1; i < RAM0_BLOCKS; i++) + { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1); + } +#endif + } + + // Power down the selected blocks +#if defined( _EMU_MEMCTRL_MASK ) + EMU->MEMCTRL = EMU->MEMCTRL | mask; +#elif defined( _EMU_RAM0CTRL_MASK ) + EMU->RAM0CTRL = EMU->RAM0CTRL | mask; +#else + // These devices are unable to power down RAM blocks + (void) mask; + (void) start; +#endif + +#if defined(RAM1_MEM_END) + mask = 0; + if (end > RAM1_MEM_END) + { + for (int i = 0; i < RAM1_BLOCKS; i++) + { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; + } + } + EMU->RAM1CTRL |= mask; +#endif +} + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/***************************************************************************//** + * @brief + * Set EM2 3 peripheral retention control. + * + * @param[in] periMask + * Peripheral select mask. Use | operator to select multiple peripheral, for example + * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. + * @param[in] enable + * Peripheral retention enable (true) or disable (false). + * + * + * @note + * Only peripheral retention disable is currently supported. Peripherals are + * enabled by default, and can only be disabled. + ******************************************************************************/ +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) +{ + EFM_ASSERT(!enable); + EMU->EM23PERNORETAINCTRL = periMask & emuPeripheralRetention_ALL; +} +#endif + /***************************************************************************//** * @brief * Update EMU module with CMU oscillator selection/enable status. * - * @details - * When entering EM2 and EM3, the HW may change the core clock oscillator - * used, as well as disabling some oscillators. The user may optionally select - * to restore the oscillators after waking up from EM2 and EM3 through the - * SW API. - * - * However, in order to support this in a safe way, the EMU module must - * be kept up-to-date on the actual selected configuration. The CMU - * module must keep the EMU module up-to-date. - * - * This function is mainly intended for internal use by the CMU module, - * but if the applications changes oscillator configurations without - * using the CMU API, this function can be used to keep the EMU module - * up-to-date. + * @deprecated + * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). ******************************************************************************/ void EMU_UpdateOscConfig(void) { - /* Fetch current configuration */ - cmuStatus = CMU->STATUS; -#if defined( _CMU_HFCLKSTATUS_RESETVALUE ) - cmuHfclkStatus = (uint16_t)(CMU->HFCLKSTATUS); -#endif + emState(emState_Save); } +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Voltage scale in EM0 and 1 by clock frequency. + * + * @param[in] clockFrequency + * Use CMSIS HF clock if 0, or override to custom clock. Providing a + * custom clock frequency is required if using a non-standard HFXO + * frequency. + * @param[in] wait + * Wait for scaling to complate. + * + * @note + * This function is primarely needed by the @ref CMU module. + ******************************************************************************/ +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) +{ + uint32_t hfSrcClockFrequency; + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + + /* VSCALE frequency is HFSRCCLK */ + if (clockFrequency == 0) + { + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; + } + else + { + hfSrcClockFrequency = clockFrequency; + } + + /* Apply EM0 and 1 voltage scaling command. */ + if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable + && (hfSrcClockFrequency < CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) + { + EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_LowPower); + } + else + { + EMU->CMD = vScaleEM01Cmd(emuVScaleEM01_HighPerformance); + } + + if (wait) + { + EMU_VScaleWait(); + } +} +#endif + + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Force voltage scaling in EM0 and 1 to a specific voltage level. + * + * @param[in] voltage + * Target VSCALE voltage level. + * @param[in] wait + * Wait for scaling to complate. + * + * @note + * This function is useful for upscaling before programming Flash from @ref MSC, + * and downscaling after programming is done. Flash programming is only supported + * at @ref emuVScaleEM01_HighPerformance. + * + * @note + * This function ignores @ref vScaleEM01LowPowerVoltageEnable set from @ref + * EMU_EM01Init(). + ******************************************************************************/ +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) +{ + uint32_t hfSrcClockFrequency; + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; + + if (voltage == emuVScaleEM01_LowPower) + { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + } + + EMU->CMD = vScaleEM01Cmd(voltage); + if (wait) + { + EMU_VScaleWait(); + } +} +#endif + + +#if defined( _EMU_CMD_EM01VSCALE0_MASK ) +/***************************************************************************//** + * @brief + * Update EMU module with Energy Mode 0 and 1 configuration + * + * @param[in] em01Init + * Energy Mode 0 and 1 configuration structure + ******************************************************************************/ +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) +{ + vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = + em01Init->vScaleEM01LowPowerVoltageEnable; + EMU_VScaleEM01ByClock(0, true); +} +#endif + + /***************************************************************************//** * @brief * Update EMU module with Energy Mode 2 and 3 configuration @@ -875,7 +1075,7 @@ void EMU_UpdateOscConfig(void) * @param[in] em23Init * Energy Mode 2 and 3 configuration structure ******************************************************************************/ -void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) { #if defined( _EMU_CTRL_EMVREG_MASK ) EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) @@ -886,6 +1086,11 @@ void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) #else (void)em23Init; #endif + +#if defined( _EMU_CTRL_EM23VSCALE_MASK ) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) + | (em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); +#endif } @@ -897,7 +1102,7 @@ void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init) * @param[in] em4Init * Energy Mode 4 configuration structure ******************************************************************************/ -void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) { #if defined( _EMU_EM4CONF_MASK ) /* Init for platforms with EMU->EM4CONF register */ @@ -937,6 +1142,11 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) EMU->EM4CTRL = em4ctrl; #endif + +#if defined( _EMU_CTRL_EM4HVSCALE_MASK ) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) + | (em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); +#endif } #endif @@ -949,7 +1159,7 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init) * @param[in] bupdInit * Backup power domain initialization structure ******************************************************************************/ -void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit) +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) { uint32_t reg; @@ -1055,8 +1265,8 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) #endif +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ #if defined( _EMU_DCDCCTRL_MASK ) - /* Translate fields with different names across platform generations to common names. */ #if defined( _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK ) #define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK @@ -1073,7 +1283,15 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) #define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT #endif -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Internal DCDC trim modes. */ +typedef enum +{ + dcdcTrimMode_EM234H_LP = 0, +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + dcdcTrimMode_EM01_LP, +#endif + dcdcTrimMode_LN, +} dcdcTrimMode_TypeDef; /***************************************************************************//** * @brief @@ -1083,9 +1301,9 @@ void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) * @return * False if calibration registers are locked ******************************************************************************/ -static bool ConstCalibrationLoad(void) +static bool dcdcConstCalibrationLoad(void) { -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) uint32_t val; volatile uint32_t *reg; @@ -1129,10 +1347,7 @@ static bool ConstCalibrationLoad(void) /* Return when assertions are disabled */ return false; -#elif defined( _SILICON_LABS_32B_PLATFORM_2_GEN_2 ) - return true; #else -#error "Undefined platform 2 generation." return true; #endif } @@ -1143,7 +1358,7 @@ static bool ConstCalibrationLoad(void) * Set recommended and validated current optimization and timing settings * ******************************************************************************/ -static void ValidatedConfigSet(void) +static void dcdcValidatedConfigSet(void) { /* Disable LP mode hysterysis in the state machine control */ #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) @@ -1151,14 +1366,13 @@ static void ValidatedConfigSet(void) #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) #define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44)) -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) + uint32_t lnForceCcm; + +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) uint32_t dcdcTiming; - SYSTEM_PartFamily_TypeDef family; SYSTEM_ChipRevision_TypeDef rev; #endif - uint32_t lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); - /* Enable duty cycling of the bias */ EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; @@ -1166,6 +1380,7 @@ static void ValidatedConfigSet(void) * LNFORCECCM is default 1 for EFR32 * LNFORCECCM is default 0 for EFM32 */ + lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); if (lnForceCcm) { /* 7MHz is recommended for LNFORCECCM = 1 */ @@ -1177,18 +1392,14 @@ static void ValidatedConfigSet(void) EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); } -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS | EMU_DCDCMISCCTRL_LPCMPHYSHI; - family = SYSTEM_GetFamily(); SYSTEM_ChipRevisionGet(&rev); - if ((((family >= systemPartFamilyMighty1P) - && (family <= systemPartFamilyFlex1V)) - || (family == systemPartFamilyEfm32Pearl1B) - || (family == systemPartFamilyEfm32Jade1B)) - && ((rev.major == 1) && (rev.minor < 3)) + if ((rev.major == 1) + && (rev.minor < 3) && (errataFixDcdcHsState == errataFixDcdcHsInit)) { /* LPCMPWAITDIS = 1 */ @@ -1315,16 +1526,14 @@ static void userCurrentLimitsSet(uint32_t maxCurrent_mA, ******************************************************************************/ static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) { -#define EMU_DCDCLNCOMPCTRL (*(volatile uint32_t *) (EMU_BASE + 0x58UL)) - switch (comp) { case emuDcdcLnCompCtrl_1u0F: - EMU_DCDCLNCOMPCTRL = 0x57204077UL; + EMU->DCDCLNCOMPCTRL = 0x57204077UL; break; case emuDcdcLnCompCtrl_4u7F: - EMU_DCDCLNCOMPCTRL = 0xB7102137UL; + EMU->DCDCLNCOMPCTRL = 0xB7102137UL; break; default: @@ -1338,21 +1547,29 @@ static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback * attenuation and DEVINFOREV. * - * @param[in] attSet + * @param[in] lpAttenuation * LP feedback attenuation. * @param[in] lpCmpBias - * lpCmpBias selection (unshifted) + * lpCmpBias selection. + * @param[in] trimMode + * DCDC trim mode. ******************************************************************************/ -static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) +static bool lpCmpHystCalibrationLoad(bool lpAttenuation, + uint8_t lpCmpBias, + dcdcTrimMode_TypeDef trimMode) { - uint8_t devinfoRev; uint32_t lpcmpHystSel; /* Get calib data revision */ - devinfoRev = SYSTEM_GetDevinfoRev(); +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); /* Load LPATT indexed calibration data */ if (devinfoRev < 4) +#else + /* Format change not present of newer families. */ + if (false) +#endif { lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; @@ -1378,17 +1595,17 @@ static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; break; - case 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 1: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; break; - case 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 2: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; break; - case 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: + case 3: lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; break; @@ -1399,19 +1616,138 @@ static bool LpCmpHystCalibrationLoad(bool lpAttenuation, uint32_t lpCmpBias) return false; } } - /* Make sure the sel value is within the field range. */ - lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; - if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) + + /* Set trims */ + if (trimMode == dcdcTrimMode_EM234H_LP) { - EFM_ASSERT(false); - /* Return when assertions are disabled */ - return false; + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; + if (lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; } - EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; + +#if defined( _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK ) + if (trimMode == dcdcTrimMode_EM01_LP) + { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; + if (lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; + } +#endif return true; } + +/***************************************************************************//** + * @brief + * Load LPVREF low and high from DEVINFO. + * + * @param[out] vrefL + * LPVREF low from DEVINFO. + * @param[out] vrefH + * LPVREF high from DEVINFO. + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpcmpBias + * lpcmpBias to lookup in DEVINFO. + ******************************************************************************/ +static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, + uint32_t *vrefH, + bool lpAttenuation, + uint8_t lpcmpBias) +{ + uint32_t vrefLow = 0; + uint32_t vrefHigh = 0; + + /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) + and LPATT (lpAttenuation) */ + uint32_t switchVal = (lpcmpBias << 8) | (lpAttenuation ? 1 : 0); + switch (switchVal) + { + case ((0 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; + break; + + case ((0 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + *vrefL = vrefLow; + *vrefH = vrefHigh; +} + /** @endcond */ /***************************************************************************//** @@ -1431,11 +1767,11 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) return; } -#if defined(_SILICON_LABS_32B_PLATFORM_2_GEN_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); /* Configure bypass current limiter */ - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1); + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1); /* Fix for errata DCDC_E203 */ if (((EMU_DcdcMode_TypeDef)currentDcdcMode == emuDcdcMode_Bypass) @@ -1444,8 +1780,9 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) errataFixDcdcHsState = errataFixDcdcHsBypassLn; } -#elif defined(_SILICON_LABS_32B_PLATFORM_2_GEN_2) +#else + /* Fix for errata DCDC_E204 */ if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { @@ -1455,21 +1792,65 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; while(!(EMU_IntGet() & EMU_IF_DCDCLNRUNNING)); } - else if (dcdcMode == emuDcdcMode_Bypass) - { - /* Enable limiter to remove current peak. Disable again in EMU_EnterEM2/3/4 */ - while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); - BUS_RegBitWrite(EMU_DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); - } -#else -#error "DCDC mode handling is undefined for this family." #endif /* Set user requested mode. */ + while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode; } +/***************************************************************************//** + * @brief + * Set DCDC LN regulator conduction mode + * + * @param[in] conductionMode + * DCDC LN conduction mode. + * @param[in] rcoDefaultSet + * The default DCDC RCO band for the conductionMode will be used if true. + * Otherwise the current RCO configuration is used. + ******************************************************************************/ +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet) +{ + EMU_DcdcMode_TypeDef currentDcdcMode + = (EMU_DcdcMode_TypeDef)(EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); + EMU_DcdcLnRcoBand_TypeDef rcoBand + = (EMU_DcdcLnRcoBand_TypeDef)((EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); + + /* Set bypass mode and wait for bypass mode to settle before + EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ + EMU_IntClear(EMU_IFC_DCDCINBYPASS); + EMU_DCDCModeSet(emuDcdcMode_Bypass); + while(EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY); + while(!(EMU_IntGet() & EMU_IF_DCDCINBYPASS)); + if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) + { + EMU->DCDCMISCCTRL &= ~ EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) + { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } + else + { + /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ + EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); + } + } + else + { + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) + { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } + } + EMU_DCDCModeSet(currentDcdcMode); + /* Update slice configuration as it depends on conduction mode and RCO band. */ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} + + /***************************************************************************//** * @brief * Configure DCDC regulator @@ -1485,20 +1866,18 @@ void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) * @return * True if initialization parameters are valid ******************************************************************************/ -bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) { -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - uint32_t lpCmpBiasSelEM01; -#endif uint32_t lpCmpBiasSelEM234H; +#if defined(_EMU_PWRCFG_MASK) /* Set external power configuration. This enables writing to the other DCDC registers. */ - EMU->PWRCFG = dcdcInit->powerConfig; + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; /* EMU->PWRCFG is write-once and POR reset only. Check that we could set the desired power configuration. */ - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != dcdcInit->powerConfig) + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { /* If this assert triggers unexpectedly, please power cycle the kit to reset the power configuration. */ @@ -1506,23 +1885,25 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) /* Return when assertions are disabled */ return false; } +#endif /* Load DCDC calibration data from the DI page */ - ConstCalibrationLoad(); + dcdcConstCalibrationLoad(); /* Check current parameters */ EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200); EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); - /* DCDC low-noise supports max 200mA */ if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { + /* DCDC low-noise supports max 200mA */ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200); } -#if (_SILICON_LABS_32B_PLATFORM_2_GEN > 1) +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { + /* Up to 10mA is supported for EM01-LP mode. */ EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10); } #endif @@ -1530,22 +1911,6 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) /* EM2/3/4 current above 10mA is not supported */ EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000); - /* Decode LP comparator bias for EM0/1 and EM2/3 */ -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; - if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) - { - if (dcdcInit->em01LoadCurrent_mA <= 1) - { - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1; - } - else if (dcdcInit->em01LoadCurrent_mA <= 3) - { - lpCmpBiasSelEM01 = EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2; - } - } -#endif - if (dcdcInit->em234LoadCurrent_uA < 75) { lpCmpBiasSelEM234H = 0; @@ -1575,14 +1940,15 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) | (dcdcInit->reverseCurrentControl >= 0 ? EMU_DCDCMISCCTRL_LNFORCECCM : 0)); #if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Only 10mA EM01-LP current is supported */ EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - | lpCmpBiasSelEM01; + | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; #endif /* 2. Set recommended and validated current optimization settings <= Depends on LNFORCECCM => Updates DCDCLNFREQCTRL_RCOBAND */ - ValidatedConfigSet(); + dcdcValidatedConfigSet(); /* 3. Updated static currents and limits user data. Limiters are updated in EMU_DCDCOptimizeSlice() */ @@ -1611,27 +1977,28 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) return false; } -#if ( _SILICON_LABS_32B_PLATFORM_2_GEN == 1 ) +#if ( _SILICON_LABS_GECKO_INTERNAL_SDID == 80 ) /* Select analog peripheral power supply. This must be done before - DCDC mode is set for GEN_1. */ + DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0); #endif +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + /* Select DVDD as input to the digital regulator. The switch to DVDD will take + effect once the DCDC output is stable. */ + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + /* Set EM0 DCDC operating mode. Output voltage set in EMU_DCDCOutputVoltageSet() above takes effect if mode is changed from bypass/off mode. */ EMU_DCDCModeSet(dcdcInit->dcdcMode); - /* Select DVDD as input to the digital regulator */ -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; -#endif - -#if ( _SILICON_LABS_32B_PLATFORM_2_GEN > 1 ) +#if ( _SILICON_LABS_GECKO_INTERNAL_SDID != 80 ) /* Select analog peripheral power supply. This must be done after - DCDC mode is set for GEN > 1. */ + DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ BUS_RegBitWrite(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0); @@ -1640,7 +2007,6 @@ bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit) return true; } - /***************************************************************************//** * @brief * Set DCDC output voltage @@ -1657,27 +2023,21 @@ bool EMU_DCDCOutputVoltageSet(uint32_t mV, { #if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK ) +#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) bool validOutVoltage; - uint8_t lnMode; - bool attSet; - uint32_t attMask; - uint32_t vrefLow = 0; - uint32_t vrefHigh = 0; - uint32_t vrefVal = 0; + bool attenuationSet; uint32_t mVlow = 0; uint32_t mVhigh = 0; - uint32_t vrefShift; - uint32_t lpcmpBias; - volatile uint32_t* ctrlReg; + uint32_t mVdiff; + uint32_t vrefVal[DCDC_TRIM_MODES] = {0}; + uint32_t vrefLow[DCDC_TRIM_MODES] = {0}; + uint32_t vrefHigh[DCDC_TRIM_MODES] = {0}; + uint8_t lpcmpBias[DCDC_TRIM_MODES] = {0}; /* Check that the set voltage is within valid range. Voltages are obtained from the datasheet. */ - validOutVoltage = false; - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) - { - validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN) - && (mV <= PWRCFG_DCDCTODVDD_VMAX)); - } + validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN) + && (mV <= PWRCFG_DCDCTODVDD_VMAX)); if (!validOutVoltage) { @@ -1686,167 +2046,127 @@ bool EMU_DCDCOutputVoltageSet(uint32_t mV, return false; } - /* Populate both LP and LN registers, set control reg pointer and VREF shift. */ - for (lnMode = 0; lnMode <= 1; lnMode++) + /* Set attenuation to use and low/high range. */ + attenuationSet = (mV > 1800); + if (attenuationSet) { - if (((lnMode == 0) && !setLpVoltage) - || ((lnMode == 1) && !setLnVoltage)) - { - continue; - } + mVlow = 1800; + mVhigh = 3000; + mVdiff = mVhigh - mVlow; + } + else + { + mVlow = 1200; + mVhigh = 1800; + mVdiff = mVhigh - mVlow; + } - ctrlReg = (lnMode ? &EMU->DCDCLNVCTRL : &EMU->DCDCLPVCTRL); - vrefShift = (lnMode ? _EMU_DCDCLNVCTRL_LNVREF_SHIFT - : _EMU_DCDCLPVCTRL_LPVREF_SHIFT); + /* Get 2-point calib data from DEVINFO */ - /* Set attenuation to use */ - attSet = (mV > 1800); - /* Always set mVlow different from mVhigh to avoid division by zero */ - /* further down. */ - if (attSet) + /* LN mode */ + if (attenuationSet) { - mVlow = 1800; - mVhigh = 3000; - attMask = (lnMode ? EMU_DCDCLNVCTRL_LNATT : EMU_DCDCLPVCTRL_LPATT); + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; } else { - mVlow = 1200; - mVhigh = 1800; - attMask = 0; + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; } - /* Get 2-point calib data from DEVINFO, calculate trimming and set voltege */ - if (lnMode) - { - /* Set low-noise DCDC output voltage tuning */ - if (attSet) - { - vrefLow = DEVINFO->DCDCLNVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; - } - else - { - vrefLow = DEVINFO->DCDCLNVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; - } - } - else - { - /* Set low-power DCDC output voltage tuning */ - /* Get LPCMPBIAS and make sure masks are not overlayed */ - lpcmpBias = EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK; - EFM_ASSERT(!(_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK & attMask)); - switch (attMask | lpcmpBias) - { - case EMU_DCDCLPVCTRL_LPATT: - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; - break; + /* LP EM234H mode */ + lpcmpBias[dcdcTrimMode_EM234H_LP] = (EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) + >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], + &vrefHigh[dcdcTrimMode_EM234H_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM234H_LP]); - case EMU_DCDCLPVCTRL_LPATT | 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; - break; - - case EMU_DCDCLPVCTRL_LPATT | 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; - break; - - case EMU_DCDCLPVCTRL_LPATT | 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; - break; - - case 0: - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; - break; - - case 1 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; - break; - - case 2 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; - break; - - case 3 << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT: - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; - break; - - default: - EFM_ASSERT(false); - break; - } - - /* Load LP comparator hysteresis calibration */ - if(!(LpCmpHystCalibrationLoad(attSet, lpcmpBias))) - { - EFM_ASSERT(false); - /* Return when assertions are disabled */ - return false; - } - } /* Low-nise / low-power mode */ +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + /* LP EM01 mode */ + lpcmpBias[dcdcTrimMode_EM01_LP] = (EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT; + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], + &vrefHigh[dcdcTrimMode_EM01_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM01_LP]); +#endif - /* Check for valid 2-point trim values */ - if (mVlow >= mVhigh) + /* Calculate output voltage trims */ + vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) + / mVdiff; + vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; + + vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; + +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; +#endif + + /* Range checks */ + if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) + || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) + || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) +#endif + || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) + || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) + { + EFM_ASSERT(false); + /* Return when assertions are disabled */ + return false; + } + + /* Update output voltage tuning for LN and LP modes. */ + if (setLnVoltage) + { + EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) + | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0); + } + + if (setLpVoltage) + { + /* Load LP EM234H comparator hysteresis calibration */ + if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { EFM_ASSERT(false); /* Return when assertions are disabled */ return false; } - /* Calculate and set voltage trim */ - vrefVal = ((mV - mVlow) * (vrefHigh - vrefLow)) / (mVhigh - mVlow); - vrefVal += vrefLow; - - /* Range check */ - if ((vrefVal > vrefHigh) || (vrefVal < vrefLow)) +#if defined( _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK ) + /* Load LP EM234H comparator hysteresis calibration */ + if(!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { EFM_ASSERT(false); /* Return when assertions are disabled */ return false; } - /* Update DCDCLNVCTRL/DCDCLPVCTRL */ - *ctrlReg = (vrefVal << vrefShift) | attMask; + /* LP VREF is that max of trims for EM01 and EM234H. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); +#endif + + /* Don't exceed max available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); + EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) + | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0); } #endif return true; @@ -1969,11 +2289,15 @@ bool EMU_DCDCPowerOff(void) { bool dcdcModeSet; +#if defined(_EMU_PWRCFG_MASK) /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL */ EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; +#endif /* Select DVDD as input to the digital regulator */ -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) +#if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; +#elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; #endif @@ -2015,7 +2339,7 @@ __STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(int mV, uint32_t coarseThr * @param[in] vmonInit * VMON initialization struct ******************************************************************************/ -void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit) +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) { uint32_t thresholdCoarse, thresholdFine; EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980)); @@ -2073,7 +2397,7 @@ void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit) * @param[in] vmonInit * VMON Hysteresis initialization struct ******************************************************************************/ -void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit) +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) { uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine; /* VMON supports voltages between 1200 mV and 3980 mV (inclusive) in 20 mV increments */ @@ -2181,20 +2505,20 @@ bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) } #endif /* EMU_STATUS_VMONRDY */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) -/** +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) +/***************************************************************************//** * @brief * Adjust the bias refresh rate * * @details * This function is only meant to be used under high-temperature operation on - * the first generation EFR32, Pearl and Jade. Adjusting the bias mode will + * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will * increase the typical current consumption. See application note 1027 * and errata documents for further details. * * @param [in] mode * The new bias refresh rate - */ + ******************************************************************************/ void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) { #define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) @@ -2202,37 +2526,37 @@ void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) #define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) #define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) - uint32_t freq = 0x2; + uint32_t freq = 0x2u; bool emuTestLocked = false; if (mode == emuBiasMode_1KHz) { - freq = 0x0; + freq = 0x0u; } - if (EMU_TESTLOCK == 0x1) + if (EMU_TESTLOCK == 0x1u) { emuTestLocked = true; - EMU_TESTLOCK = 0xADE8; + EMU_TESTLOCK = 0xADE8u; } if (mode == emuBiasMode_Continuous) { - EMU_BIASCONF &= ~0x74; + EMU_BIASCONF &= ~0x74u; } else { - EMU_BIASCONF |= 0x74; + EMU_BIASCONF |= 0x74u; } - EMU_BIASTESTCTRL |= 0x8; - CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00) - | ((freq & 0x3) << 10); - EMU_BIASTESTCTRL &= ~0x8; + EMU_BIASTESTCTRL |= 0x8u; + CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) + | ((freq & 0x3u) << 10u); + EMU_BIASTESTCTRL &= ~0x8u; if (emuTestLocked) { - EMU_TESTLOCK = 0; + EMU_TESTLOCK = 0u; } } #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c index 3914e87adf..bee3af2ea8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpcrc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c index 599cfe414e..15011e06f8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c @@ -2,7 +2,7 @@ * @file em_gpio.c * @brief General Purpose IO (GPIO) peripheral API * devices. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -148,10 +148,10 @@ void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, * by this function. * * @note - * On platform 1 devices the pin number parameter is not used. The + * On series 0 devices the pin number parameter is not used. The * pin number used on these devices is hardwired to the interrupt with the * same number. @n - * On platform 2 devices, pin number can be selected freely within a group. + * On series 1 devices, pin number can be selected freely within a group. * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin * number within the interrupt groups are: * 0: pins 0-3 @@ -185,7 +185,7 @@ void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, bool fallingEdge, bool enable) { - uint32_t tmp; + uint32_t tmp = 0; #if !defined(_GPIO_EXTIPINSELL_MASK) (void)pin; #endif @@ -291,12 +291,12 @@ void GPIO_PinModeSet(GPIO_Port_TypeDef port, * register controls pins 0-7 and MODEH controls pins 8-15. */ if (pin < 8) { - GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xF << (pin * 4))) + GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4))) | (mode << (pin * 4)); } else { - GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xF << ((pin - 8) * 4))) + GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4))) | (mode << ((pin - 8) * 4)); } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c index d28873105a..287e031511 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_i2c.c * @brief Inter-integrated Circuit (I2C) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -77,9 +77,9 @@ #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) /* Max I2C transmission rate constant */ -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) #define I2C_CR_MAX 4 -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) #define I2C_CR_MAX 8 #else #warning "Max I2C transmission rate constant is not defined" @@ -257,21 +257,21 @@ void I2C_BusFreqSet(I2C_TypeDef *i2c, switch(i2cMode) { case i2cClockHLRStandard: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 4200000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 2000000; break; #endif case i2cClockHLRAsymetric: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 11000000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 5000000; break; #endif case i2cClockHLRFast: -#if defined( _SILICON_LABS_32B_PLATFORM_1 ) +#if defined( _SILICON_LABS_32B_SERIES_0 ) minFreq = 24400000; break; -#elif defined( _SILICON_LABS_32B_PLATFORM_2 ) +#elif defined( _SILICON_LABS_32B_SERIES_1 ) minFreq = 14000000; break; #endif } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c index 1dfc2b6d5b..7d6428eac9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_idac.c * @brief Current Digital to Analog Converter (IDAC) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -48,7 +48,8 @@ /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ /* Fix for errata IDAC_E101 - IDAC output current degradation */ -#if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY)) #define ERRATA_FIX_IDAC_E101_EN #endif /** @endcond */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c index ed84185d64..32ef970104 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_int.c * @brief Interrupt enable/disable unit API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c index 99833a8d36..5a8b05893b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lcd.c * @brief Liquid Crystal Display (LCD) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c index 9a1718016e..1a2f8a1f15 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ldma.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_ldma.c * @brief Direct memory access (LDMA) module peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c index 88e7d65c21..aee2ec7597 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_lesense.c * @brief Low Energy Sensor (LESENSE) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -31,9 +31,8 @@ ******************************************************************************/ #include "em_lesense.h" -/* LESENSE is currently only supported on Platform 1. Full support for Platform 2 LESENSE - will be included in the next release. */ -#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) && defined(_SILICON_LABS_32B_PLATFORM_1) + +#if defined(LESENSE_COUNT) && (LESENSE_COUNT > 0) #include "em_assert.h" #include "em_bus.h" #include "em_cmu.h" @@ -60,6 +59,22 @@ * @{ ******************************************************************************/ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_LESENSE_ROUTE_MASK) +#define GENERIC_LESENSE_ROUTE LESENSE->ROUTE +#else +#define GENERIC_LESENSE_ROUTE LESENSE->ROUTEPEN +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +/* DACOUT mode only available on channel 0,1,2,3,12,13,14,15 */ +#define DACOUT_SUPPORT 0xF00F +#else +/* DACOUT mode only available on channel 4,5,7,10,12,13 */ +#define DACOUT_SUPPORT 0x34B0 +#endif +/** @endcond */ + /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ @@ -100,11 +115,13 @@ * Request to call @ref LESENSE_Reset() first in order to initialize all * LESENSE registers with the default value. ******************************************************************************/ -void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) +void LESENSE_Init(const LESENSE_Init_TypeDef * init, bool reqReset) { /* Sanity check of initialization values */ EFM_ASSERT((uint32_t)init->timeCtrl.startDelay < 4U); +#if defined(_LESENSE_PERCTRL_DACPRESC_MASK) EFM_ASSERT((uint32_t)init->perCtrl.dacPresc < 32U); +#endif /* Reset LESENSE registers if requested. */ if (reqReset) @@ -114,6 +131,11 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) /* Set sensor start delay for each channel. */ LESENSE_StartDelaySet((uint32_t)init->timeCtrl.startDelay); +#if defined(_LESENSE_TIMCTRL_AUXSTARTUP_MASK) + /* Configure the AUXHRFCO startup delay. */ + LESENSE->TIMCTRL = (LESENSE->TIMCTRL & (~_LESENSE_TIMCTRL_AUXSTARTUP_MASK)) + | (init->timeCtrl.delayAuxStartup << _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT); +#endif /* LESENSE core control configuration. * Set PRS source, SCANCONF register usage strategy, interrupt and @@ -127,8 +149,10 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) | (uint32_t)init->coreCtrl.scanConfSel | (uint32_t)init->coreCtrl.bufTrigLevel | (uint32_t)init->coreCtrl.wakeupOnDMA +#if defined(_LESENSE_CTRL_ACMP0INV_MASK) | ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_CTRL_ACMP0INV_SHIFT) | ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_CTRL_ACMP1INV_SHIFT) +#endif | ((uint32_t)init->coreCtrl.dualSample << _LESENSE_CTRL_DUALSAMPLE_SHIFT) | ((uint32_t)init->coreCtrl.storeScanRes << _LESENSE_CTRL_STRSCANRES_SHIFT) | ((uint32_t)init->coreCtrl.bufOverWr << _LESENSE_CTRL_BUFOW_SHIFT) @@ -144,15 +168,24 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) * duty cycle (warm up) mode. */ LESENSE->PERCTRL = ((uint32_t)init->perCtrl.dacCh0Data << _LESENSE_PERCTRL_DACCH0DATA_SHIFT) + | ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT) +#if defined(_LESENSE_PERCTRL_DACCH0CONV_MASK) | ((uint32_t)init->perCtrl.dacCh0ConvMode << _LESENSE_PERCTRL_DACCH0CONV_SHIFT) | ((uint32_t)init->perCtrl.dacCh0OutMode << _LESENSE_PERCTRL_DACCH0OUT_SHIFT) - | ((uint32_t)init->perCtrl.dacCh1Data << _LESENSE_PERCTRL_DACCH1DATA_SHIFT) | ((uint32_t)init->perCtrl.dacCh1ConvMode << _LESENSE_PERCTRL_DACCH1CONV_SHIFT) | ((uint32_t)init->perCtrl.dacCh1OutMode << _LESENSE_PERCTRL_DACCH1OUT_SHIFT) | ((uint32_t)init->perCtrl.dacPresc << _LESENSE_PERCTRL_DACPRESC_SHIFT) | (uint32_t)init->perCtrl.dacRef +#endif | ((uint32_t)init->perCtrl.acmp0Mode << _LESENSE_PERCTRL_ACMP0MODE_SHIFT) | ((uint32_t)init->perCtrl.acmp1Mode << _LESENSE_PERCTRL_ACMP1MODE_SHIFT) +#if defined(_LESENSE_PERCTRL_ACMP0INV_MASK) + | ((uint32_t)init->coreCtrl.invACMP0 << _LESENSE_PERCTRL_ACMP0INV_SHIFT) + | ((uint32_t)init->coreCtrl.invACMP1 << _LESENSE_PERCTRL_ACMP1INV_SHIFT) +#endif +#if defined(_LESENSE_PERCTRL_DACCONVTRIG_MASK) + | ((uint32_t)init->perCtrl.dacScan << _LESENSE_PERCTRL_DACCONVTRIG_SHIFT) +#endif | (uint32_t)init->perCtrl.warmupMode; /* LESENSE decoder general control configuration. @@ -211,7 +244,7 @@ void LESENSE_Init(LESENSE_Init_TypeDef const *init, bool const reqReset) * Frequency in Hz calculated and set by this function. Users can use this to * compare the requested and set values. ******************************************************************************/ -uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq) +uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t scanFreq) { uint32_t tmp; uint32_t pcPresc = 0UL; /* Period counter prescaler. */ @@ -293,8 +326,8 @@ uint32_t LESENSE_ScanFreqSet(uint32_t refFreq, uint32_t const scanFreq) * @param[in] start * If true, LESENSE_ScanStart() is immediately issued after configuration. ******************************************************************************/ -void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, - bool const start) +void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef scanMode, + bool start) { uint32_t tmp; /* temporary storage of the CTRL register value */ @@ -335,7 +368,7 @@ void LESENSE_ScanModeSet(LESENSE_ScanMode_TypeDef const scanMode, * @param[in] startDelay * Number of LFACLK cycles to delay. Valid range: 0-3 (2 bit). ******************************************************************************/ -void LESENSE_StartDelaySet(uint8_t const startDelay) +void LESENSE_StartDelaySet(uint8_t startDelay) { uint32_t tmp; /* temporary storage of the TIMCTRL register value */ @@ -378,8 +411,8 @@ void LESENSE_StartDelaySet(uint8_t const startDelay) * @param[in] clkDiv * Clock divisor value. Valid range depends on the @p clk value. ******************************************************************************/ -void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, - LESENSE_ClkPresc_TypeDef const clkDiv) +void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef clk, + LESENSE_ClkPresc_TypeDef clkDiv) { uint32_t tmp; @@ -440,12 +473,12 @@ void LESENSE_ClkDivSet(LESENSE_ChClk_TypeDef const clk, * @param[in] confChAll * Configuration structure for all (16) LESENSE sensor channels. ******************************************************************************/ -void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll) +void LESENSE_ChannelAllConfig(const LESENSE_ChAll_TypeDef * confChAll) { uint32_t i; /* Iterate through all the 16 channels */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) { /* Configure scan channels. */ LESENSE_ChannelConfig(&confChAll->Ch[i], i); @@ -475,26 +508,31 @@ void LESENSE_ChannelAllConfig(LESENSE_ChAll_TypeDef const *confChAll) * @param[in] chIdx * Channel index to configure (0-15). ******************************************************************************/ -void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, - uint32_t const chIdx) +void LESENSE_ChannelConfig(const LESENSE_ChDesc_TypeDef * confCh, + uint32_t chIdx) { uint32_t tmp; /* Service variable. */ /* Sanity check of configuration parameters */ - EFM_ASSERT(chIdx < 16U); - EFM_ASSERT(confCh->exTime < 64U); - EFM_ASSERT(confCh->sampleDelay < 128U); - EFM_ASSERT(confCh->measDelay < 128U); + EFM_ASSERT(chIdx < LESENSE_NUM_CHANNELS); + EFM_ASSERT(confCh->exTime <= (_LESENSE_CH_TIMING_EXTIME_MASK >> _LESENSE_CH_TIMING_EXTIME_SHIFT)); + EFM_ASSERT(confCh->measDelay <= (_LESENSE_CH_TIMING_MEASUREDLY_MASK >> _LESENSE_CH_TIMING_MEASUREDLY_SHIFT)); +#if defined(_SILICON_LABS_32B_SERIES_0) + // Sample delay on other devices are 8 bits which fits perfectly in uint8_t + EFM_ASSERT(confCh->sampleDelay <= (_LESENSE_CH_TIMING_SAMPLEDLY_MASK >> _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)); +#endif + /* Not a complete assert, as the max. value of acmpThres depends on other * configuration parameters, check the parameter description of acmpThres for * for more details! */ EFM_ASSERT(confCh->acmpThres < 4096U); - EFM_ASSERT(!(confCh->chPinExMode == lesenseChPinExDACOut - && (chIdx != 2U) - && (chIdx != 3U) - && (chIdx != 4U) - && (chIdx != 5U))); + if (confCh->chPinExMode == lesenseChPinExDACOut) + { + EFM_ASSERT((0x1 << chIdx) & DACOUT_SUPPORT); + } + +#if defined(_LESENSE_IDLECONF_CH0_DACCH0) EFM_ASSERT(!(confCh->chPinIdleMode == lesenseChPinIdleDACCh1 && ((chIdx != 12U) && (chIdx != 13U) @@ -505,6 +543,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, && (chIdx != 1U) && (chIdx != 2U) && (chIdx != 3U)))); +#endif /* Configure chIdx setup in LESENSE idle phase. * Read-modify-write in order to support reconfiguration during LESENSE @@ -516,9 +555,9 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, /* Channel specific timing configuration on scan channel chIdx. * Set excitation time, sampling delay, measurement delay. */ LESENSE_ChannelTimingSet(chIdx, - (uint32_t)confCh->exTime, - (uint32_t)confCh->sampleDelay, - (uint32_t)confCh->measDelay); + confCh->exTime, + confCh->sampleDelay, + confCh->measDelay); /* Channel specific configuration of clocks, sample mode, excitation pin mode * alternate excitation usage and interrupt mode on scan channel chIdx in @@ -538,22 +577,26 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, (uint32_t)confCh->compMode | ((uint32_t)confCh->shiftRes << _LESENSE_CH_EVAL_DECODE_SHIFT) | ((uint32_t)confCh->storeCntRes << _LESENSE_CH_EVAL_STRSAMPLE_SHIFT) - | ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT); + | ((uint32_t)confCh->invRes << _LESENSE_CH_EVAL_SCANRESINV_SHIFT) +#if defined(_LESENSE_CH_EVAL_MODE_MASK) + | ((uint32_t)confCh->evalMode << _LESENSE_CH_EVAL_MODE_SHIFT) +#endif + ; /* Configure analog comparator (ACMP) threshold and decision threshold for * counter separately with the function provided for that. */ LESENSE_ChannelThresSet(chIdx, - (uint32_t)confCh->acmpThres, - (uint32_t)confCh->cntThres); + confCh->acmpThres, + confCh->cntThres); /* Enable/disable interrupts on channel */ - BUS_RegBitWrite(&(LESENSE->IEN), chIdx, confCh->enaInt); + BUS_RegBitWrite(&LESENSE->IEN, chIdx, confCh->enaInt); /* Enable/disable CHchIdx pin. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), chIdx, confCh->enaPin); + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, confCh->enaPin); /* Enable/disable scan channel chIdx. */ - BUS_RegBitWrite(&(LESENSE->CHEN), chIdx, confCh->enaScanCh); + BUS_RegBitWrite(&LESENSE->CHEN, chIdx, confCh->enaScanCh); } @@ -574,7 +617,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh, * @param[in] confAltEx * Configuration structure for LESENSE alternate excitation pins. ******************************************************************************/ -void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) +void LESENSE_AltExConfig(const LESENSE_ConfAltEx_TypeDef * confAltEx) { uint32_t i; uint32_t tmp; @@ -583,7 +626,7 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) /* Configure alternate excitation mapping. * Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->CTRL), + BUS_RegBitWrite(&LESENSE->CTRL, _LESENSE_CTRL_ALTEXMAP_SHIFT, confAltEx->altExMap); @@ -596,7 +639,7 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) /* Enable/disable alternate excitation pin i. * Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, (16UL + i), confAltEx->AltEx[i].enablePin); @@ -608,20 +651,24 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) LESENSE->ALTEXCONF = tmp; /* Enable/disable always excite on channel i */ - BUS_RegBitWrite(&(LESENSE->ALTEXCONF), + BUS_RegBitWrite(&LESENSE->ALTEXCONF, (16UL + i), confAltEx->AltEx[i].alwaysEx); } break; +#if defined(_LESENSE_CTRL_ALTEXMAP_ACMP) case lesenseAltExMapACMP: +#else + case lesenseAltExMapCH: +#endif /* Iterate through all the 16 alternate excitation channels */ for (i = 0U; i < 16U; ++i) { /* Enable/disable alternate ACMP excitation channel pin i. */ /* Atomic read-modify-write using BUS_RegBitWrite function in order to * support reconfiguration during LESENSE operation. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, i, confAltEx->AltEx[i].enablePin); } @@ -658,18 +705,18 @@ void LESENSE_AltExConfig(LESENSE_ConfAltEx_TypeDef const *confAltEx) * @param[in] enaPin * Enable/disable the pin assigned to the channel selected by @p chIdx. ******************************************************************************/ -void LESENSE_ChannelEnable(uint8_t const chIdx, - bool const enaScanCh, - bool const enaPin) +void LESENSE_ChannelEnable(uint8_t chIdx, + bool enaScanCh, + bool enaPin) { /* Enable/disable the assigned pin of scan channel chIdx. * Note: BUS_RegBitWrite() function is used for setting/clearing single * bit peripheral register bitfields. Read the function description in * em_bus.h for more details. */ - BUS_RegBitWrite(&(LESENSE->ROUTE), chIdx, enaPin); + BUS_RegBitWrite(&GENERIC_LESENSE_ROUTE, chIdx, enaPin); /* Enable/disable scan channel chIdx. */ - BUS_RegBitWrite(&(LESENSE->CHEN), chIdx, enaScanCh); + BUS_RegBitWrite(&LESENSE->CHEN, chIdx, enaScanCh); } @@ -700,7 +747,7 @@ void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask) /* Enable/disable all channels at once according to the mask. */ LESENSE->CHEN = chMask; /* Enable/disable all channel pins at once according to the mask. */ - LESENSE->ROUTE = pinMask; + GENERIC_LESENSE_ROUTE = pinMask; } @@ -732,15 +779,18 @@ void LESENSE_ChannelEnableMask(uint16_t chMask, uint16_t pinMask) * Measure delay on chIdx. Sensor measuring is delayed for measDelay+1 * excitation clock cycles. Valid range: 0-127 (7 bits). ******************************************************************************/ -void LESENSE_ChannelTimingSet(uint8_t const chIdx, - uint8_t const exTime, - uint8_t const sampleDelay, - uint8_t const measDelay) +void LESENSE_ChannelTimingSet(uint8_t chIdx, + uint8_t exTime, + uint8_t sampleDelay, + uint16_t measDelay) { /* Sanity check of parameters. */ - EFM_ASSERT(exTime < 64U); - EFM_ASSERT(sampleDelay < 128U); - EFM_ASSERT(measDelay < 128U); + EFM_ASSERT(exTime <= (_LESENSE_CH_TIMING_EXTIME_MASK >> _LESENSE_CH_TIMING_EXTIME_SHIFT)); + EFM_ASSERT(measDelay <= (_LESENSE_CH_TIMING_MEASUREDLY_MASK >> _LESENSE_CH_TIMING_MEASUREDLY_SHIFT)); +#if defined(_SILICON_LABS_32B_SERIES_0) + // Sample delay on other devices are 8 bits which fits perfectly in uint8_t + EFM_ASSERT(sampleDelay <= (_LESENSE_CH_TIMING_SAMPLEDLY_MASK >> _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT)); +#endif /* Channel specific timing configuration on scan channel chIdx. * Setting excitation time, sampling delay, measurement delay. */ @@ -784,9 +834,9 @@ void LESENSE_ChannelTimingSet(uint8_t const chIdx, * Decision threshold for counter comparison. * Valid range: 0-65535 (16 bits). ******************************************************************************/ -void LESENSE_ChannelThresSet(uint8_t const chIdx, - uint16_t const acmpThres, - uint16_t const cntThres) +void LESENSE_ChannelThresSet(uint8_t chIdx, + uint16_t acmpThres, + uint16_t cntThres) { uint32_t tmp; /* temporary storage */ @@ -794,13 +844,13 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, /* Sanity check for acmpThres only, cntThres is 16bit value. */ EFM_ASSERT(acmpThres < 4096U); /* Sanity check for LESENSE channel id. */ - EFM_ASSERT(chIdx < 16); + EFM_ASSERT(chIdx < LESENSE_NUM_CHANNELS); /* Save the INTERACT register value of channel chIdx to tmp. * Please be aware the effects of the non-atomic Read-Modify-Write cycle! */ - tmp = LESENSE->CH[chIdx].INTERACT & ~(_LESENSE_CH_INTERACT_ACMPTHRES_MASK); + tmp = LESENSE->CH[chIdx].INTERACT & ~(0xFFF); /* Set the ACMP threshold value to the INTERACT register of channel chIdx. */ - tmp |= (uint32_t)acmpThres << _LESENSE_CH_INTERACT_ACMPTHRES_SHIFT; + tmp |= (uint32_t)acmpThres; /* Write the new value to the INTERACT register. */ LESENSE->CH[chIdx].INTERACT = tmp; @@ -813,6 +863,122 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, LESENSE->CH[chIdx].EVAL = tmp; } +#if defined(_LESENSE_CH_EVAL_MODE_MASK) +/***************************************************************************//** + * @brief + * Configure Sliding Window evaluation mode for a specific channel + * + * @details + * This function will configure the evaluation mode, the initial + * sensor measurement (COMPTHRES) and the window size. For other channel + * related configuration see the @ref LESENSE_ChannelConfig() function. + * + * @warning + * Beware that the step size and window size configuration are global to all + * LESENSE channels and use the same register field in the hardware. This + * means that any windowSize configuration passed to this function will + * apply for all channels and override all other stepSize/windowSize + * configurations. + * + * @param[in] chIdx + * Identifier of the scan channel. Valid range: 0-15. + * + * @param[in] windowSize + * Window size to be used on all channels. + * + * @param[in] initValue + * The initial sensor value for the channel. + ******************************************************************************/ +void LESENSE_ChannelSlidingWindow(uint8_t chIdx, + uint32_t windowSize, + uint32_t initValue) +{ + LESENSE_CH_TypeDef * ch = &LESENSE->CH[chIdx]; + + LESENSE_WindowSizeSet(windowSize); + ch->EVAL = (ch->EVAL & ~(_LESENSE_CH_EVAL_COMPTHRES_MASK | _LESENSE_CH_EVAL_MODE_MASK)) + | (initValue << _LESENSE_CH_EVAL_COMPTHRES_SHIFT) + | LESENSE_CH_EVAL_MODE_SLIDINGWIN; +} + +/***************************************************************************//** + * @brief + * Configure step detection evaluation mode for a specific channel + * + * @details + * This function will configure the evaluation mode, the initial + * sensor measurement (COMPTHRES) and the window size. For other channel + * related configuration see the @ref LESENSE_ChannelConfig() function. + * + * @warning + * Beware that the step size and window size configuration are global to all + * LESENSE channels and use the same register field in the hardware. This + * means that any stepSize configuration passed to this function will + * apply for all channels and override all other stepSize/windowSize + * configurations. + * + * @param[in] chIdx + * Identifier of the scan channel. Valid range: 0-15. + * + * @param[in] stepSize + * Step size to be used on all channels. + * + * @param[in] initValue + * The initial sensor value for the channel. + ******************************************************************************/ +void LESENSE_ChannelStepDetection(uint8_t chIdx, + uint32_t stepSize, + uint32_t initValue) +{ + LESENSE_CH_TypeDef * ch = &LESENSE->CH[chIdx]; + + LESENSE_StepSizeSet(stepSize); + ch->EVAL = (ch->EVAL & ~(_LESENSE_CH_EVAL_COMPTHRES_MASK | _LESENSE_CH_EVAL_MODE_MASK)) + | (initValue << _LESENSE_CH_EVAL_COMPTHRES_SHIFT) + | LESENSE_CH_EVAL_MODE_STEPDET; +} + +/***************************************************************************//** + * @brief + * Set the window size for all LESENSE channels. + * + * @details + * The window size is used by all channels that are configured as + * @ref lesenseEvalModeSlidingWindow. + * + * @warning + * The window size configuration is using the same register field as the + * step detection size. So the window size configuration will have an + * effect on channels configured with the @ref lesenseEvalModeStepDetection + * evaluation mode as well. + * + * @param[in] windowSize + * The window size to use for all channels. + ******************************************************************************/ +void LESENSE_WindowSizeSet(uint32_t windowSize) +{ + LESENSE->EVALCTRL = (LESENSE->EVALCTRL & ~_LESENSE_EVALCTRL_WINSIZE_MASK) + | windowSize; +} + +/***************************************************************************//** + * @brief + * Set the step size for all LESENSE channels. + * + * @details + * The step size is configured using the same register field as use to + * configure window size. So calling this function will overwrite any + * previously configured window size as done by the + * @ref LESENSE_WindowSizeSet() function. + * + * @param[in] stepSize + * The step size to use for all channels. + ******************************************************************************/ +void LESENSE_StepSizeSet(uint32_t stepSize) +{ + LESENSE_WindowSizeSet(stepSize); +} +#endif /***************************************************************************//** * @brief @@ -828,14 +994,14 @@ void LESENSE_ChannelThresSet(uint8_t const chIdx, * LESENSE_DecoderStateConfig() function. * * @param[in] confDecStAll - * Configuration structure for all (16) LESENSE decoder states. + * Configuration structure for all (16 or 32) LESENSE decoder states. ******************************************************************************/ -void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll) +void LESENSE_DecoderStateAllConfig(const LESENSE_DecStAll_TypeDef * confDecStAll) { uint32_t i; - /* Iterate through all the 16 decoder states. */ - for (i = 0U; i < 16U; ++i) + /* Iterate through all the 16 or 32 decoder states. */ + for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) { /* Configure decoder state i. */ LESENSE_DecoderStateConfig(&confDecStAll->St[i], i); @@ -856,19 +1022,19 @@ void LESENSE_DecoderStateAllConfig(LESENSE_DecStAll_TypeDef const *confDecStAll) * Configuration structure for a single LESENSE decoder state. * * @param[in] decSt - * Decoder state index to configure (0-15). + * Decoder state index to configure (0-15) or (0-31) depending on device. ******************************************************************************/ -void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, - uint32_t const decSt) +void LESENSE_DecoderStateConfig(const LESENSE_DecStDesc_TypeDef * confDecSt, + uint32_t decSt) { /* Sanity check of configuration parameters */ - EFM_ASSERT(decSt < 16U); + EFM_ASSERT(decSt < LESENSE_NUM_DECODER_STATES); EFM_ASSERT((uint32_t)confDecSt->confA.compMask < 16U); EFM_ASSERT((uint32_t)confDecSt->confA.compVal < 16U); - EFM_ASSERT((uint32_t)confDecSt->confA.nextState < 16U); + EFM_ASSERT((uint32_t)confDecSt->confA.nextState < LESENSE_NUM_DECODER_STATES); EFM_ASSERT((uint32_t)confDecSt->confB.compMask < 16U); EFM_ASSERT((uint32_t)confDecSt->confB.compVal < 16U); - EFM_ASSERT((uint32_t)confDecSt->confB.nextState < 16U); + EFM_ASSERT((uint32_t)confDecSt->confB.nextState < LESENSE_NUM_DECODER_STATES); /* Configure state descriptor A (LESENSE_STi_TCONFA) for decoder state i. * Setting sensor compare value, sensor mask, next state index, @@ -907,11 +1073,12 @@ void LESENSE_DecoderStateConfig(LESENSE_DecStDesc_TypeDef const *confDecSt, * enabling the decoder! * * @param[in] decSt - * Decoder state to set as current state. Valid range: 0-15 + * Decoder state to set as current state. Valid range: 0-15 or 0-31 + * depending on device. ******************************************************************************/ void LESENSE_DecoderStateSet(uint32_t decSt) { - EFM_ASSERT(decSt < 16U); + EFM_ASSERT(decSt <= _LESENSE_DECSTATE_DECSTATE_MASK); LESENSE->DECSTATE = decSt & _LESENSE_DECSTATE_DECSTATE_MASK; } @@ -930,6 +1097,28 @@ uint32_t LESENSE_DecoderStateGet(void) return LESENSE->DECSTATE & _LESENSE_DECSTATE_DECSTATE_MASK; } +#if defined(_LESENSE_PRSCTRL_MASK) +/***************************************************************************//** + * @brief + * Enable or disable PRS output from the LESENSE decoder. + * + * @param[in] enable + * enable/disable the PRS output from the LESENSE decoder. true to enable and + * false to disable. + * + * @param[in] decMask + * Decoder state compare value mask + * + * @param[in] decVal + * Decoder state compare value. + ******************************************************************************/ +void LESENSE_DecoderPrsOut(bool enable, uint32_t decMask, uint32_t decVal) +{ + LESENSE->PRSCTRL = (enable << _LESENSE_PRSCTRL_DECCMPEN_SHIFT) + | (decMask << _LESENSE_PRSCTRL_DECCMPMASK_SHIFT) + | (decVal << _LESENSE_PRSCTRL_DECCMPVAL_SHIFT); +} +#endif /***************************************************************************//** * @brief @@ -1092,15 +1281,23 @@ void LESENSE_Reset(void) LESENSE->PERCTRL = _LESENSE_PERCTRL_RESETVALUE; LESENSE->DECCTRL = _LESENSE_DECCTRL_RESETVALUE; LESENSE->BIASCTRL = _LESENSE_BIASCTRL_RESETVALUE; +#if defined(_LESENSE_EVALCTRL_MASK) + LESENSE->EVALCTRL = _LESENSE_EVALCTRL_RESETVALUE; + LESENSE->PRSCTRL = _LESENSE_PRSCTRL_RESETVALUE; +#endif LESENSE->CHEN = _LESENSE_CHEN_RESETVALUE; LESENSE->IDLECONF = _LESENSE_IDLECONF_RESETVALUE; LESENSE->ALTEXCONF = _LESENSE_ALTEXCONF_RESETVALUE; /* Disable LESENSE to control GPIO pins */ - LESENSE->ROUTE = _LESENSE_ROUTE_RESETVALUE; +#if defined(_LESENSE_ROUTE_MASK) + LESENSE->ROUTE = _LESENSE_ROUTE_RESETVALUE; +#else + LESENSE->ROUTEPEN = _LESENSE_ROUTEPEN_RESETVALUE; +#endif /* Reset all channel configuration registers */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_CHANNELS; ++i) { LESENSE->CH[i].TIMING = _LESENSE_CH_TIMING_RESETVALUE; LESENSE->CH[i].INTERACT = _LESENSE_CH_INTERACT_RESETVALUE; @@ -1108,7 +1305,7 @@ void LESENSE_Reset(void) } /* Reset all decoder state configuration registers */ - for (i = 0U; i < 16U; ++i) + for (i = 0U; i < LESENSE_NUM_DECODER_STATES; ++i) { LESENSE->ST[i].TCONFA = _LESENSE_ST_TCONFA_RESETVALUE; LESENSE->ST[i].TCONFB = _LESENSE_ST_TCONFB_RESETVALUE; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c index 666aa4a19b..7281084139 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_letimer.c * @brief Low Energy Timer (LETIMER) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c index 30e6e68565..b96dee3060 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c @@ -2,7 +2,7 @@ * @file em_leuart.c * @brief Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) * Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c index acaad77aae..066de51082 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_mpu.c * @brief Memory Protection Unit (MPU) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c index 30c14dc971..6bc3975f04 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_msc.c * @brief Flash controller (MSC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -57,8 +57,8 @@ #define WORDS_PER_DATA_PHASE (1) #endif +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /* Fix for errata FLASH_E201 - Potential program failure after Power On */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) #define ERRATA_FIX_FLASH_E201_EN #endif @@ -159,6 +159,13 @@ void MSC_Init(void) #if defined( _MSC_TIMEBASE_MASK ) uint32_t freq, cycles; #endif + +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash erase and write requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + /* Unlock the MSC */ MSC->LOCK = MSC_UNLOCK_CODE; /* Disable writing to the flash */ @@ -382,7 +389,7 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, { uint32_t timeOut; uint32_t wordIndex; - uint32_t wordsPerDataPhase; + bool useWDouble = false; MSC_Status_TypeDef retval = mscReturnOk; #if !defined( _EFM32_GECKO_FAMILY ) uint32_t irqState; @@ -392,6 +399,7 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, /* If LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word) */ if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { +#if defined(_SILICON_LABS_32B_SERIES_0) /* If the number of words to be written are odd, we need to align by writing a single word first, before setting the WDOUBLE bit. */ if (numWords & 0x1) @@ -431,14 +439,11 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, } /* Now we can set the double word option in order to write two words per data phase. */ +#endif MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; - wordsPerDataPhase = 2; + useWDouble = true; } - else #endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ - { - wordsPerDataPhase = 1; - } /* Write the rest as double word write if wordsPerDataPhase == 2 */ if (numWords > 0) @@ -451,34 +456,34 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, wordIndex = 0; while(wordIndex < numWords) { - MSC->WDATA = *data++; - wordIndex++; - if (wordsPerDataPhase == 1) + if (!useWDouble) { - MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; - } - else if (wordsPerDataPhase == 2) - { - while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)); MSC->WDATA = *data++; wordIndex++; - - /* Trigger double write. Platform 1 and 2 - have different trigger behavior for - double word write as described in the - reference manual for MSC_WRITECMD_WRITEONCE - and WRITETRIG. */ -#if defined(_SILICON_LABS_32B_PLATFORM_1) MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; -#else + } + + else // useWDouble == true + { + /* Trigger double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + MSC->WDATA = *data++; + while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)); + MSC->WDATA = *data++; + wordIndex += 2; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; + +#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) + while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)); + do + { + MSC->WDATA = *data++; + wordIndex++; + } while ((MSC->STATUS & MSC_STATUS_WDATAREADY) + && (wordIndex < numWords)); MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; #endif } - else - { - /* Not supported. */ - EFM_ASSERT(false); - } /* Wait for the transaction to finish. */ timeOut = MSC_PROGRAM_TIMEOUT; @@ -539,14 +544,37 @@ MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; } } - MSC->WDATA = *data; - if ((wordsPerDataPhase == 1) - || ((wordsPerDataPhase == 2) && (wordIndex & 0x1))) + + if (!useWDouble) { + MSC->WDATA = *data; MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + data++; + wordIndex++; + } + + else // useWDouble == true + { + /* Trigger double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + MSC->WDATA = *data; + if (wordIndex & 0x1) + { + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + } + data++; + wordIndex++; + +#elif (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) + do + { + MSC->WDATA = *data++; + wordIndex++; + } while ((MSC->STATUS & MSC_STATUS_WDATAREADY) + && (wordIndex < numWords)); + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; +#endif } - data++; - wordIndex++; } if (irqState == 0) @@ -587,8 +615,8 @@ MSC_RAMFUNC_DEFINITION_END * Write address * @param[in] data * Pointer to the first data word to load. - * @param[in] numWords - * Number of data words (32-bit) to load. + * @param[in] numBytes + * Number of data bytes to load, must be a multiple of 4 bytes. * @param[in] writeStrategy * Write strategy to apply. * @return @@ -612,6 +640,12 @@ MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, /* Check number of bytes. Must be divisable by four */ EFM_ASSERT((numBytes & 0x3) == 0); +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash write requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + /* Enable writing to the MSC */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; @@ -717,6 +751,11 @@ MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) /* Address must be aligned to pages */ EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); +#if defined( _EMU_STATUS_VSCALE_MASK ) + /* VSCALE must be done and flash erase requires VSCALE2 */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif /* Enable writing to the MSC */ MSC->WRITECTRL |= MSC_WRITECTRL_WREN; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c index 6963ab69f1..a342cd7bbd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c @@ -1,7 +1,7 @@ /**************************************************************************//** * @file em_opamp.c * @brief Operational Amplifier (OPAMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -31,7 +31,8 @@ ******************************************************************************/ #include "em_opamp.h" -#if defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) #include "em_system.h" #include "em_assert.h" @@ -50,8 +51,13 @@ * @li OPAMP_Enable() Configure and enable an opamp. * @li OPAMP_Disable() Disable an opamp. * + * @if DOXYDOC_P1_DEVICE * All OPAMP functions assume that the DAC clock is running. If the DAC is not * used, the clock can be turned off when the opamp's are configured. + * @elseif DOXYDOC_P2_DEVICE + * All OPAMP functions assume that the VDAC clock is running. If the VDAC is not + * used, the clock can be turned off when the opamp's are configured. + * @endif * * If the available gain values dont suit the application at hand, the resistor * ladders can be disabled and external gain programming resistors used. @@ -64,8 +70,12 @@ * pads should be connected to a suitable signal ground. * * \nUnity gain voltage follower.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_UNITY_GAIN and * @ref OPA_INIT_UNITY_GAIN_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_UNITY_GAIN. + * @endif * @verbatim |\ @@ -78,8 +88,12 @@ @endverbatim * * \nNon-inverting amplifier.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_NON_INVERTING and * @ref OPA_INIT_NON_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_NON_INVERTING. + * @endif * @verbatim |\ @@ -95,8 +109,12 @@ NEGPAD @endverbatim * * \nInverting amplifier.\n + * @if DOXYDOC_P1_DEVICE * Use predefined macros @ref OPA_INIT_INVERTING and * @ref OPA_INIT_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_INVERTING. + * @endif * @verbatim _____R2____ @@ -185,6 +203,36 @@ |___________| @endverbatim * + * @if DOXYDOC_P2_DEVICE + * \nInstrumentation amplifier.\n + * Use predefined macros @ref OPA_INIT_INSTR_AMP_OPA0 and + * @ref OPA_INIT_INSTR_AMP_OPA0. + * @verbatim + + |\ + __________|+\ OPA1 + | \______________ + ___|_ / | + | | / | + | |/ R2 + |____________| + | + R1 + | + R1 + ____________| + | | + | R2 + | |\ | + |___|+\ OPA0 | + | \_____|________ + __________|_ / + | / + |/ + + @endverbatim + * @endif + * * @{ ******************************************************************************/ @@ -196,14 +244,27 @@ * @brief * Disable an Operational Amplifier. * + * @if DOXYDOC_P1_DEVICE * @param[in] dac * Pointer to DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @param[in] dac + * Pointer to VDAC peripheral register block. + * @endif + * * * @param[in] opa * Selects an OPA, valid vaules are @ref OPA0, @ref OPA1 and @ref OPA2. ******************************************************************************/ -void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) +void OPAMP_Disable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa) { +#if defined(_SILICON_LABS_32B_SERIES_0) EFM_ASSERT(DAC_REF_VALID(dac)); EFM_ASSERT(DAC_OPA_VALID(opa)); @@ -221,6 +282,33 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) { dac->OPACTRL &= ~DAC_OPACTRL_OPA2EN; } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + + if (opa == OPA0) + { + dac->CMD |= VDAC_CMD_OPA0DIS; + while (dac->STATUS & VDAC_STATUS_OPA0ENS) + { + } + } + else if (opa == OPA1) + { + dac->CMD |= VDAC_CMD_OPA1DIS; + while (dac->STATUS & VDAC_STATUS_OPA1ENS) + { + } + } + else /* OPA2 */ + { + dac->CMD |= VDAC_CMD_OPA2DIS; + while (dac->STATUS & VDAC_STATUS_OPA2ENS) + { + } + } +#endif } @@ -228,6 +316,7 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * @brief * Configure and enable an Operational Amplifier. * + * @if DOXYDOC_P1_DEVICE * @note * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef * structure should consist of one or more of the @@ -256,6 +345,23 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * * @param[in] dac * Pointer to DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @note + * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef + * structure should consist of one or more of the + * VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + * (defined in \_vdac.h) OR'ed together. @n @n + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + * + * E.g: @n + * init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + * @param[in] dac + * Pointer to VDAC peripheral register block. + * @endif * * @param[in] opa * Selects an OPA, valid vaules are @ref OPA0, @ref OPA1 and @ref OPA2. @@ -263,8 +369,16 @@ void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa) * @param[in] init * Pointer to a structure containing OPAMP init information. ******************************************************************************/ -void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init) +void OPAMP_Enable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa, + const OPAMP_Init_TypeDef *init) { +#if defined(_SILICON_LABS_32B_SERIES_0) uint32_t offset; EFM_ASSERT(DAC_REF_VALID(dac)); @@ -421,9 +535,172 @@ void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef | (init->hcmDisable ? DAC_OPACTRL_OPA2HCMDIS : 0) | DAC_OPACTRL_OPA2EN; } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + uint32_t calData = 0; + uint32_t warmupTime; + + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + EFM_ASSERT(init->settleTime <= (_VDAC_OPA_TIMER_SETTLETIME_MASK + >> _VDAC_OPA_TIMER_SETTLETIME_SHIFT)); + EFM_ASSERT(init->startupDly <= (_VDAC_OPA_TIMER_STARTUPDLY_MASK + >> _VDAC_OPA_TIMER_STARTUPDLY_SHIFT)); + EFM_ASSERT((init->outPen & ~_VDAC_OPA_OUT_ALTOUTPADEN_MASK) == 0); + EFM_ASSERT(!((init->gain3xEn == true) + && ((init->negSel == opaNegSelResTap) + || (init->posSel == opaPosSelResTap)))); + EFM_ASSERT((init->drvStr == opaDrvStrLowerAccLowStr) + || (init->drvStr == opaDrvStrLowAccLowStr) + || (init->drvStr == opaDrvStrHighAccHighStr) + || (init->drvStr == opaDrvStrHigherAccHighStr)); + + /* Disable OPAMP before writing to registers. */ + OPAMP_Disable(dac, opa); + + /* Get the calibration value based on OPAMP, Drive Strength, and INCBW. */ + switch (opa) + { + case OPA0: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL0 : DEVINFO->OPA0CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL1 : DEVINFO->OPA0CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL2 : DEVINFO->OPA0CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL3 : DEVINFO->OPA0CAL7); + break; + } + break; + + case OPA1: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL0 : DEVINFO->OPA1CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL1 : DEVINFO->OPA1CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL2 : DEVINFO->OPA1CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL3 : DEVINFO->OPA1CAL7); + break; + } + break; + + case OPA2: + switch (init->drvStr) + { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL0 : DEVINFO->OPA2CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL1 : DEVINFO->OPA2CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL2 : DEVINFO->OPA2CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL3 : DEVINFO->OPA2CAL7); + break; + } + break; + } + if (!init->defaultOffsetN) + { + EFM_ASSERT(init->offsetN <= (_VDAC_OPA_CAL_OFFSETN_MASK + >> _VDAC_OPA_CAL_OFFSETN_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETN_MASK) + | (init->offsetN << _VDAC_OPA_CAL_OFFSETN_SHIFT); + } + if (!init->defaultOffsetP) + { + EFM_ASSERT(init->offsetP <= (_VDAC_OPA_CAL_OFFSETP_MASK + >> _VDAC_OPA_CAL_OFFSETP_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETP_MASK) + | (init->offsetP << _VDAC_OPA_CAL_OFFSETP_SHIFT); + } + + dac->OPA[opa].CAL = (calData & _VDAC_OPA_CAL_MASK); + + dac->OPA[opa].MUX = (uint32_t)init->resSel + | (init->gain3xEn ? VDAC_OPA_MUX_GAIN3X : 0) + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel; + + dac->OPA[opa].OUT = (uint32_t)init->outMode + | (uint32_t)init->outPen; + + switch (init->drvStr) + { + case opaDrvStrHigherAccHighStr: + warmupTime = 6; + break; + + case opaDrvStrHighAccHighStr: + warmupTime = 8; + break; + + case opaDrvStrLowAccLowStr: + warmupTime = 85; + break; + + case opaDrvStrLowerAccLowStr: + default: + warmupTime = 100; + break; + } + + dac->OPA[opa].TIMER = (uint32_t)(init->settleTime + << _VDAC_OPA_TIMER_SETTLETIME_SHIFT) + | (uint32_t)(warmupTime + << _VDAC_OPA_TIMER_WARMUPTIME_SHIFT) + | (uint32_t)(init->startupDly + << _VDAC_OPA_TIMER_STARTUPDLY_SHIFT); + + dac->OPA[opa].CTRL = (init->aportYMasterDisable + ? VDAC_OPA_CTRL_APORTYMASTERDIS : 0) + | (init->aportXMasterDisable + ? VDAC_OPA_CTRL_APORTXMASTERDIS : 0) + | (uint32_t)init->prsOutSel + | (uint32_t)init->prsSel + | (uint32_t)init->prsMode + | (init->prsEn ? VDAC_OPA_CTRL_PRSEN : 0) + | (init->halfDrvStr + ? VDAC_OPA_CTRL_OUTSCALE_HALF + : VDAC_OPA_CTRL_OUTSCALE_FULL) + | (init->hcmDisable ? VDAC_OPA_CTRL_HCMDIS : 0) + | (init->ugBwScale ? VDAC_OPA_CTRL_INCBW : 0) + | (uint32_t)init->drvStr; + + if (opa == OPA0) + { + dac->CMD |= VDAC_CMD_OPA0EN; + } + else if (opa == OPA1) + { + dac->CMD |= VDAC_CMD_OPA1EN; + } + else /* OPA2 */ + { + dac->CMD |= VDAC_CMD_OPA2EN; + } + +#endif } /** @} (end addtogroup OPAMP) */ /** @} (end addtogroup emlib) */ -#endif /* defined( OPAMP_PRESENT ) && ( OPAMP_COUNT == 1 ) */ +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c index 44035ebf14..a71999b7d1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_pcnt.c * @brief Pulse Counter (PCNT) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c index 3b1813423a..244d07c1d6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_prs.c * @brief Peripheral Reflex System (PRS) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c index 9f467e7214..a8cd720863 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c @@ -2,7 +2,7 @@ * @file em_rmu.c * @brief Reset Management Unit (RMU) peripheral module peripheral API * - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -111,7 +111,7 @@ #define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ #define NUM_RSTCAUSES 16 -/* EFM32XG1X */ +/* EFM32xG1, EFM32xG12, EFM32xG13 */ #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ @@ -128,8 +128,8 @@ #error "RMU_RSTCAUSE XMASKs are not defined for this family." #endif +#if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */ -#if defined( _SILICON_LABS_32B_PLATFORM_2_GEN_1 ) #define ERRATA_FIX_EMU_E208_EN #endif @@ -303,7 +303,7 @@ uint32_t RMU_ResetCauseGet(void) for (i = 0; i < NUM_RSTCAUSES; i++) { zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; -#if defined( _SILICON_LABS_32B_PLATFORM_2 ) +#if defined( _SILICON_LABS_32B_SERIES_1 ) /* Handle soft/hard pin reset */ if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c index c5ee6e79b7..0356bf2964 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_rtc.c * @brief Real Time Counter (RTC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c index 76e91979b2..3b5d3a1012 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtcc.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file * @brief Real Time Counter with Calendar (RTCC) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c index dcedb24629..cac903b062 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_system.c * @brief System Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -33,7 +33,6 @@ #include "em_system.h" #include "em_assert.h" #include -#include "core_cmSecureAccess.h" /***************************************************************************//** * @addtogroup emlib @@ -62,24 +61,19 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) EFM_ASSERT(rev); - uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0)); - uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1)); - uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2)); - uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3)); - /* CHIP FAMILY bit [5:2] */ - tmp = (((pid1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); + tmp = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); /* CHIP FAMILY bit [1:0] */ - tmp |= ((pid0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); + tmp |= ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); rev->family = tmp; /* CHIP MAJOR bit [3:0] */ - rev->major = (pid0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; + rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; /* CHIP MINOR bit [7:4] */ - tmp = (((pid2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + tmp = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); /* CHIP MINOR bit [3:0] */ - tmp |= ((pid3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + tmp |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); rev->minor = tmp; } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c index 1182d7310b..5c21e8d4e9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_timer.c * @brief Timer/counter (TIMER) Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c index 1e9bb63262..134519ca9c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c @@ -2,7 +2,7 @@ * @file em_usart.c * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) * Peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com @@ -110,14 +110,18 @@ #define USART_IRDA_VALID(ref) (0) #endif -#if defined(_EZR32_HAPPY_FAMILY) -#define USART_I2S_VALID(ref) ((ref) == USART0) -#elif defined(_EFM32_HAPPY_FAMILY) -#define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) -#elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) || defined(_SILICON_LABS_32B_PLATFORM_2) -#define USART_I2S_VALID(ref) ((ref) == USART1) -#elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) -#define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) +#if defined(_SILICON_LABS_32B_SERIES_1) + #define USART_I2S_VALID(ref) ((ref) == USART1) +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART1) + #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) +#endif #endif #if (UART_COUNT == 1) @@ -475,11 +479,7 @@ uint32_t USART_BaudrateGet(USART_TypeDef *usart) ******************************************************************************/ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) { -#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL) - uint64_t clkdiv; -#else uint32_t clkdiv; -#endif /* Inhibit divide by 0 */ EFM_ASSERT(baudrate); @@ -496,28 +496,8 @@ void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baud refFreq = CMU_ClockFreqGet(cmuClock_HFPER); } -#if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL) - /* Calculate CLKDIV with fractional bits */ - clkdiv = (128ULL*refFreq)/baudrate - 256; - - /* - * Make sure we dont use fractional bits, do normal integer rounding when - * discarding fractional bits. - */ - clkdiv = ((clkdiv + 128)/256) << 8; -#else - /* Calculate and set CLKDIV with fractional bits */ - clkdiv = 2 * refFreq; - clkdiv += baudrate - 1; - clkdiv /= baudrate; - clkdiv -= 4; - clkdiv *= 64; - /* Make sure we don't use fractional bits by rounding CLKDIV */ - /* up (and thus reducing baudrate, not increasing baudrate above */ - /* specified value). */ - clkdiv += 0xc0; - clkdiv &= 0xffffff00; -#endif + clkdiv = (refFreq - 1) / (2 * baudrate); + clkdiv = clkdiv << 8; /* Verify that resulting clock divider is within limits */ EFM_ASSERT(!(clkdiv & ~_USART_CLKDIV_DIV_MASK)); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c index 6198550c36..03cf953c66 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file em_vcmp.c * @brief Voltage Comparator (VCMP) peripheral API - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c new file mode 100644 index 0000000000..634a6513d2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vdac.c @@ -0,0 +1,437 @@ +/***************************************************************************//** + * @file em_vdac.c + * @brief Digital to Analog Converter (VDAC) Peripheral API + * @version 5.1.2 + ******************************************************************************* + * @section License + * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + ******************************************************************************* + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + +#include "em_vdac.h" +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) +#include "em_cmu.h" + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup VDAC + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of VDAC channel for assert statements. */ +#define VDAC_CH_VALID(ch) ((ch) <= 1) + +/** Max VDAC clock */ +#define VDAC_MAX_CLOCK 1000000 + +/** Max clock frequency of internal clock oscillator, 10 MHz + 20%. */ +#define VDAC_INTERNAL_CLOCK_FREQ 12000000 + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable/disable VDAC channel. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] ch + * Channel to enable/disable. + * + * @param[in] enable + * true to enable VDAC channel, false to disable. + ******************************************************************************/ +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + + if (ch == 0) + { + if (enable) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + else + { + vdac->CMD = VDAC_CMD_CH0DIS; + while (vdac->STATUS & VDAC_STATUS_CH0ENS); + } + } + else + { + if (enable) + { + vdac->CMD = VDAC_CMD_CH1EN; + } + else + { + vdac->CMD = VDAC_CMD_CH1DIS; + while (vdac->STATUS & VDAC_STATUS_CH1ENS); + } + } +} + +/***************************************************************************//** + * @brief + * Initialize VDAC. + * + * @details + * Initializes common parts for both channels. This function will also load + * calibration values from the Device Information (DI) page into the VDAC + * calibration register. + * To complete a VDAC setup, channel control configuration must also be done, + * please refer to VDAC_InitChannel(). + * + * @note + * This function will disable both channels prior to configuration. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] init + * Pointer to VDAC initialization structure. + ******************************************************************************/ +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init) +{ + uint32_t cal, tmp = 0; + uint32_t const volatile *calData; + + EFM_ASSERT(VDAC_REF_VALID(vdac)); + + /* Make sure both channels are disabled. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + + /* Get OFFSETTRIM calibration value. */ + cal = ((DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK) + >> _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT) + << _VDAC_CAL_OFFSETTRIM_SHIFT; + + if (init->mainCalibration) + { + calData = &DEVINFO->VDAC0MAINCAL; + } + else + { + calData = &DEVINFO->VDAC0ALTCAL; + } + + /* Get correct GAINERRTRIM calibration value. */ + switch (init->reference) + { + case vdacRef1V25Ln: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT; + break; + + case vdacRef2V5Ln: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT; + break; + + case vdacRef1V25: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT; + break; + + case vdacRef2V5: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT; + break; + + case vdacRefAvdd: + case vdacRefExtPin: + tmp = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT; + break; + } + + /* Set GAINERRTRIM calibration value. */ + cal |= tmp << _VDAC_CAL_GAINERRTRIM_SHIFT; + + /* Get GAINERRTRIMCH1 calibration value. */ + switch (init->reference) + { + case vdacRef1V25Ln: + case vdacRef1V25: + case vdacRefAvdd: + case vdacRefExtPin: + tmp = (DEVINFO->VDAC0CH1CAL && _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT; + break; + + case vdacRef2V5Ln: + case vdacRef2V5: + tmp = (DEVINFO->VDAC0CH1CAL && _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT; + break; + } + + /* Set GAINERRTRIM calibration value. */ + cal |= tmp << _VDAC_CAL_GAINERRTRIMCH1_SHIFT; + + tmp = ((uint32_t)init->asyncClockMode << _VDAC_CTRL_DACCLKMODE_SHIFT) + | ((uint32_t)init->warmupKeepOn << _VDAC_CTRL_WARMUPMODE_SHIFT) + | ((uint32_t)init->refresh << _VDAC_CTRL_REFRESHPERIOD_SHIFT) + | (((uint32_t)init->prescaler << _VDAC_CTRL_PRESC_SHIFT) + & _VDAC_CTRL_PRESC_MASK) + | ((uint32_t)init->reference << _VDAC_CTRL_REFSEL_SHIFT) + | ((uint32_t)init->ch0ResetPre << _VDAC_CTRL_CH0PRESCRST_SHIFT) + | ((uint32_t)init->outEnablePRS << _VDAC_CTRL_OUTENPRS_SHIFT) + | ((uint32_t)init->sineEnable << _VDAC_CTRL_SINEMODE_SHIFT) + | ((uint32_t)init->diff << _VDAC_CTRL_DIFF_SHIFT); + + /* Write to VDAC registers. */ + vdac->CAL = cal; + vdac->CTRL = tmp; +} + +/***************************************************************************//** + * @brief + * Initialize a VDAC channel. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] init + * Pointer to VDAC channel initialization structure. + * + * @param[in] ch + * Channel number to initialize. + ******************************************************************************/ +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch) +{ + uint32_t vdacChCtrl, vdacStatus; + + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + + /* Make sure both channels are disabled. */ + vdacStatus = vdac->STATUS; + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + + vdacChCtrl = ((uint32_t)init->prsSel << _VDAC_CH0CTRL_PRSSEL_SHIFT) + | ((uint32_t)init->prsAsync << _VDAC_CH0CTRL_PRSASYNC_SHIFT) + | ((uint32_t)init->trigMode << _VDAC_CH0CTRL_TRIGMODE_SHIFT) + | ((uint32_t)init->sampleOffMode << _VDAC_CH0CTRL_CONVMODE_SHIFT); + + if (ch == 0) + { + vdac->CH0CTRL = vdacChCtrl; + } + else + { + vdac->CH1CTRL = vdacChCtrl; + } + + /* Check if the channel must be enabled. */ + if (init->enable) + { + if (ch == 0) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + else + { + vdac->CMD = VDAC_CMD_CH1EN; + } + } + + /* Check if the other channel had to be turned off above + * and needs to be turned on again. */ + if (ch == 0) + { + if (vdacStatus & VDAC_STATUS_CH1ENS) + { + vdac->CMD = VDAC_CMD_CH1EN; + } + } + else + { + if (vdacStatus & VDAC_STATUS_CH0ENS) + { + vdac->CMD = VDAC_CMD_CH0EN; + } + } +} + +/***************************************************************************//** + * @brief + * Set the output signal of a VDAC channel to a given value. + * + * @details + * This function sets the output signal of a VDAC channel by writing @p value + * to the corresponding CHnDATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] channel + * Channel number to set output of. + * + * @param[in] value + * Value to write to the channel output register CHnDATA. + ******************************************************************************/ +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value) +{ + switch(channel) + { + case 0: + VDAC_Channel0OutputSet(vdac, value); + break; + case 1: + VDAC_Channel1OutputSet(vdac, value); + break; + default: + EFM_ASSERT(0); + break; + } +} + +/***************************************************************************//** + * @brief + * Calculate prescaler value used to determine VDAC clock. + * + * @details + * The VDAC clock is given by input clock divided by prescaler+1. + * + * VDAC_CLK = IN_CLK / (prescale + 1) + * + * Maximum VDAC clock is 1 MHz. Input clock is HFPERCLK when VDAC synchronous + * mode is selected, or an internal oscillator of 10 MHz +/- 20% when + * asynchronous mode is selected. + * + * @note + * If the requested VDAC frequency is low and the max prescaler value can not + * adjust the actual VDAC frequency lower than requested, the max prescaler + * value is returned, resulting in a higher VDAC frequency than requested. + * + * @param[in] vdacFreq VDAC frequency target. The frequency will automatically + * be adjusted to be below max allowed VDAC clock. + * + * @param[in] syncMode Set to true if you intend to use VDAC in synchronous + * mode. + * + * @param[in] hfperFreq Frequency in Hz of HFPERCLK oscillator. Set to 0 to + * use currently defined HFPERCLK clock setting. This parameter is only used + * when syncMode is set to true. + * + * @return + * Prescaler value to use for VDAC in order to achieve a clock value less than + * or equal to @p vdacFreq. + ******************************************************************************/ +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq) +{ + uint32_t ret, refFreq; + + /* Make sure selected VDAC clock is below max value */ + if (vdacFreq > VDAC_MAX_CLOCK) + { + vdacFreq = VDAC_MAX_CLOCK; + } + + if (!syncMode) + { + refFreq = VDAC_INTERNAL_CLOCK_FREQ; + } + else + { + if (hfperFreq) + { + refFreq = hfperFreq; + } + else + { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } + } + + /* Iterate in order to determine best prescale value. Start with lowest */ + /* prescaler value in order to get the first equal or less VDAC */ + /* frequency value. */ + for (ret = 0; ret <= _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; ret++) + { + if ((refFreq / (ret + 1)) <= vdacFreq) + { + break; + } + } + + /* If ret is higher than the max prescaler value, make sure to return + the max value. */ + if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT)) + { + ret = _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Reset VDAC to same state as after a HW reset. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + ******************************************************************************/ +void VDAC_Reset(VDAC_TypeDef *vdac) +{ + /* Disable channels, before resetting other registers. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)); + vdac->CH0CTRL = _VDAC_CH0CTRL_RESETVALUE; + vdac->CH1CTRL = _VDAC_CH1CTRL_RESETVALUE; + vdac->CH0DATA = _VDAC_CH0DATA_RESETVALUE; + vdac->CH1DATA = _VDAC_CH1DATA_RESETVALUE; + vdac->CTRL = _VDAC_CTRL_RESETVALUE; + vdac->IEN = _VDAC_IEN_RESETVALUE; + vdac->IFC = _VDAC_IFC_MASK; + vdac->CAL = _VDAC_CAL_RESETVALUE; +} + +/** @} (end addtogroup VDAC) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c index 3e1024d35e..55a66e44d2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c @@ -2,7 +2,7 @@ * @file em_wdog.c * @brief Watchdog (WDOG) peripheral API * devices. - * @version 5.0.0 + * @version 5.1.2 ******************************************************************************* * @section License * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com From ca91e7c2d5b6e936de17a08065cd842dd8cffb63 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Mon, 13 Mar 2017 18:24:40 +0100 Subject: [PATCH 03/10] Update to Gecko SDK 5.1.2 Updating CMSIS device headers --- .../TARGET_EFM32GG/device/efm32gg230f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg230f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg232f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg232f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg280f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg280f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg290f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg290f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg295f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg295f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg330f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg330f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg332f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg332f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg380f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg380f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg390f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg390f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg395f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg395f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg840f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg840f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg842f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg842f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg880f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg880f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg890f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg890f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg895f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg895f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg900f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg900f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg940f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg940f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg942f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg942f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg980f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg980f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg990f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg990f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg995f1024.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg995f512.h | 18 ++- .../TARGET_EFM32GG/device/efm32gg_acmp.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_adc.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_aes.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_af_pins.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_af_ports.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_burtc.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_burtc_ret.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_calibrate.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_cmu.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_dac.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_devinfo.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_dma.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_dma_ch.h | 4 +- .../device/efm32gg_dma_descriptor.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_dmactrl.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_dmareq.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_ebi.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_emu.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_etm.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_gpio.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_gpio_p.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_i2c.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_lcd.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_lesense.h | 4 +- .../device/efm32gg_lesense_buf.h | 4 +- .../device/efm32gg_lesense_ch.h | 4 +- .../device/efm32gg_lesense_st.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_letimer.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_leuart.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_msc.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_pcnt.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_prs.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_prs_ch.h | 4 +- .../device/efm32gg_prs_signals.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_rmu.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_romtable.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_rtc.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_timer.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_timer_cc.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_uart.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_usart.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_usb.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_usb_diep.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_usb_doep.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_usb_hc.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_vcmp.h | 4 +- .../TARGET_EFM32GG/device/efm32gg_wdog.h | 4 +- .../TARGET_EFM32GG/device/em_device.h | 4 +- .../TARGET_EFM32GG/device/system_efm32gg.c | 4 +- .../TARGET_EFM32GG/device/system_efm32gg.h | 4 +- .../TARGET_EFM32HG/device/efm32hg108f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg108f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg110f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg110f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg210f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg210f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg222f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg222f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg308f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg308f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg309f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg309f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg310f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg310f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg321f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg321f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg322f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg322f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg350f32.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg350f64.h | 18 ++- .../TARGET_EFM32HG/device/efm32hg_acmp.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_adc.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_aes.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_af_pins.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_af_ports.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_calibrate.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_cmu.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_devinfo.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_dma.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_dma_ch.h | 4 +- .../device/efm32hg_dma_descriptor.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_dmactrl.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_dmareq.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_emu.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_gpio.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_gpio_p.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_i2c.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_idac.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_leuart.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_msc.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_mtb.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_pcnt.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_prs.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_prs_ch.h | 4 +- .../device/efm32hg_prs_signals.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_rmu.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_romtable.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_rtc.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_timer.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_timer_cc.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_usart.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_usb.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_usb_diep.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_usb_doep.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_vcmp.h | 4 +- .../TARGET_EFM32HG/device/efm32hg_wdog.h | 4 +- .../TARGET_EFM32HG/device/em_device.h | 4 +- .../TARGET_EFM32HG/device/system_efm32hg.c | 4 +- .../TARGET_EFM32HG/device/system_efm32hg.h | 4 +- .../TARGET_EFM32LG/device/efm32lg230f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg230f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg230f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg232f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg232f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg232f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg280f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg280f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg280f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg290f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg290f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg290f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg295f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg295f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg295f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg330f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg330f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg330f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg332f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg332f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg332f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg360f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg360f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg360f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg380f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg380f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg380f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg390f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg390f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg390f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg395f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg395f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg395f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg840f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg840f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg840f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg842f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg842f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg842f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg880f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg880f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg880f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg890f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg890f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg890f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg895f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg895f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg895f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg900f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg940f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg940f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg940f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg942f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg942f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg942f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg980f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg980f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg980f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg990f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg990f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg990f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg995f128.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg995f256.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg995f64.h | 18 ++- .../TARGET_EFM32LG/device/efm32lg_acmp.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_adc.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_aes.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_af_pins.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_af_ports.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_burtc.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_burtc_ret.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_calibrate.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_cmu.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_dac.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_devinfo.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_dma.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_dma_ch.h | 4 +- .../device/efm32lg_dma_descriptor.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_dmactrl.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_dmareq.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_ebi.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_emu.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_etm.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_gpio.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_gpio_p.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_i2c.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_lcd.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_lesense.h | 4 +- .../device/efm32lg_lesense_buf.h | 4 +- .../device/efm32lg_lesense_ch.h | 4 +- .../device/efm32lg_lesense_st.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_letimer.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_leuart.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_msc.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_pcnt.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_prs.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_prs_ch.h | 4 +- .../device/efm32lg_prs_signals.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_rmu.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_romtable.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_rtc.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_timer.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_timer_cc.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_uart.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_usart.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_usb.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_usb_diep.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_usb_doep.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_usb_hc.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_vcmp.h | 4 +- .../TARGET_EFM32LG/device/efm32lg_wdog.h | 4 +- .../TARGET_EFM32LG/device/em_device.h | 4 +- .../TARGET_EFM32LG/device/system_efm32lg.c | 4 +- .../TARGET_EFM32LG/device/system_efm32lg.h | 4 +- .../device/efm32pg1b100f128gm32.h | 44 +++--- .../device/efm32pg1b100f128im32.h | 44 +++--- .../device/efm32pg1b100f256gm32.h | 44 +++--- .../device/efm32pg1b100f256im32.h | 44 +++--- .../device/efm32pg1b200f128gm32.h | 44 +++--- .../device/efm32pg1b200f128gm48.h | 44 +++--- .../device/efm32pg1b200f128im32.h | 44 +++--- .../device/efm32pg1b200f256gm32.h | 44 +++--- .../device/efm32pg1b200f256gm48.h | 44 +++--- .../device/efm32pg1b200f256im32.h | 44 +++--- .../device/efm32pg1b200f256im48.h | 44 +++--- .../TARGET_EFM32PG/device/efm32pg1b_acmp.h | 12 +- .../TARGET_EFM32PG/device/efm32pg1b_adc.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_af_pins.h | 4 +- .../device/efm32pg1b_af_ports.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_cmu.h | 38 ++++- .../device/efm32pg1b_cryotimer.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_crypto.h | 40 +---- .../TARGET_EFM32PG/device/efm32pg1b_devinfo.h | 4 +- .../device/efm32pg1b_dma_descriptor.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_dmareq.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_emu.h | 145 +++++++++++++----- .../TARGET_EFM32PG/device/efm32pg1b_fpueh.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_gpcrc.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_gpio.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_gpio_p.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_i2c.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_idac.h | 27 +--- .../TARGET_EFM32PG/device/efm32pg1b_ldma.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_letimer.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_leuart.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_msc.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_pcnt.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_prs.h | 8 +- .../TARGET_EFM32PG/device/efm32pg1b_prs_ch.h | 4 +- .../device/efm32pg1b_prs_signals.h | 5 +- .../TARGET_EFM32PG/device/efm32pg1b_rmu.h | 4 +- .../device/efm32pg1b_romtable.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_rtcc.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h | 4 +- .../device/efm32pg1b_rtcc_ret.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_timer.h | 6 +- .../device/efm32pg1b_timer_cc.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_usart.h | 4 +- .../TARGET_EFM32PG/device/efm32pg1b_wdog.h | 10 +- .../device/efm32pg1b_wdog_pch.h | 4 +- .../TARGET_EFM32PG/device/em_device.h | 4 +- .../TARGET_EFM32PG/device/system_efm32pg1b.c | 4 +- .../TARGET_EFM32PG/device/system_efm32pg1b.h | 4 +- .../TARGET_EFM32WG/device/efm32wg230f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg230f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg230f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg232f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg232f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg232f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg280f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg280f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg280f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg290f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg290f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg290f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg295f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg295f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg295f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg330f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg330f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg330f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg332f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg332f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg332f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg360f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg360f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg360f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg380f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg380f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg380f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg390f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg390f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg390f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg395f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg395f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg395f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg840f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg840f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg840f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg842f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg842f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg842f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg880f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg880f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg880f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg890f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg890f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg890f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg895f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg895f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg895f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg900f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg940f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg940f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg940f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg942f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg942f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg942f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg980f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg980f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg980f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg990f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg990f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg990f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg995f128.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg995f256.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg995f64.h | 18 ++- .../TARGET_EFM32WG/device/efm32wg_acmp.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_adc.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_aes.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_af_pins.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_af_ports.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_burtc.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_burtc_ret.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_calibrate.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_cmu.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_dac.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_devinfo.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_dma.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_dma_ch.h | 4 +- .../device/efm32wg_dma_descriptor.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_dmactrl.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_dmareq.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_ebi.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_emu.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_etm.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_fpueh.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_gpio.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_gpio_p.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_i2c.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_lcd.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_lesense.h | 4 +- .../device/efm32wg_lesense_buf.h | 4 +- .../device/efm32wg_lesense_ch.h | 4 +- .../device/efm32wg_lesense_st.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_letimer.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_leuart.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_msc.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_pcnt.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_prs.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_prs_ch.h | 4 +- .../device/efm32wg_prs_signals.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_rmu.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_romtable.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_rtc.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_timer.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_timer_cc.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_uart.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_usart.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_usb.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_usb_diep.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_usb_doep.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_usb_hc.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_vcmp.h | 4 +- .../TARGET_EFM32WG/device/efm32wg_wdog.h | 4 +- .../TARGET_EFM32WG/device/em_device.h | 4 +- .../TARGET_EFM32WG/device/system_efm32wg.c | 4 +- .../TARGET_EFM32WG/device/system_efm32wg.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg108f16.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg108f32.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg108f4.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg108f8.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg110f16.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg110f32.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg110f4.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg110f8.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg210f16.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg210f32.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg210f4.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg210f8.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg222f16.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg222f32.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg222f4.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg222f8.h | 18 ++- .../TARGET_EFM32ZG/device/efm32zg_acmp.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_adc.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_aes.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_af_pins.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_af_ports.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_calibrate.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_cmu.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_devinfo.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_dma.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_dma_ch.h | 4 +- .../device/efm32zg_dma_descriptor.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_dmactrl.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_dmareq.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_emu.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_gpio.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_gpio_p.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_i2c.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_idac.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_leuart.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_msc.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_pcnt.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_prs.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_prs_ch.h | 4 +- .../device/efm32zg_prs_signals.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_rmu.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_romtable.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_rtc.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_timer.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_timer_cc.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_usart.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_vcmp.h | 4 +- .../TARGET_EFM32ZG/device/efm32zg_wdog.h | 4 +- .../TARGET_EFM32ZG/device/em_device.h | 4 +- .../TARGET_EFM32ZG/device/system_efm32zg.c | 4 +- .../TARGET_EFM32ZG/device/system_efm32zg.h | 4 +- .../device/efr32mg1p131f256gm48.h | 48 +++--- .../device/efr32mg1p132f256gj43.h | 48 +++--- .../device/efr32mg1p132f256gm32.h | 48 +++--- .../device/efr32mg1p132f256gm48.h | 48 +++--- .../device/efr32mg1p132f256im32.h | 48 +++--- .../device/efr32mg1p133f256gm48.h | 48 +++--- .../device/efr32mg1p231f256gm48.h | 48 +++--- .../device/efr32mg1p232f256gj43.h | 48 +++--- .../device/efr32mg1p232f256gm32.h | 48 +++--- .../device/efr32mg1p232f256gm48.h | 48 +++--- .../device/efr32mg1p233f256gm48.h | 48 +++--- .../device/efr32mg1p632f256gm32.h | 48 +++--- .../device/efr32mg1p632f256im32.h | 48 +++--- .../device/efr32mg1p732f256gm32.h | 48 +++--- .../device/efr32mg1p732f256im32.h | 48 +++--- .../TARGET_EFR32MG1/device/efr32mg1p_acmp.h | 12 +- .../TARGET_EFR32MG1/device/efr32mg1p_adc.h | 4 +- .../device/efr32mg1p_af_pins.h | 4 +- .../device/efr32mg1p_af_ports.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_cmu.h | 38 ++++- .../device/efr32mg1p_cryotimer.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_crypto.h | 40 +---- .../device/efr32mg1p_devinfo.h | 6 +- .../device/efr32mg1p_dma_descriptor.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_dmareq.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_emu.h | 145 +++++++++++++----- .../TARGET_EFR32MG1/device/efr32mg1p_fpueh.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_gpio.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_i2c.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_idac.h | 27 +--- .../TARGET_EFR32MG1/device/efr32mg1p_ldma.h | 4 +- .../device/efr32mg1p_ldma_ch.h | 4 +- .../device/efr32mg1p_letimer.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_leuart.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_msc.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_pcnt.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_prs.h | 8 +- .../TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h | 4 +- .../device/efr32mg1p_prs_signals.h | 5 +- .../TARGET_EFR32MG1/device/efr32mg1p_rmu.h | 4 +- .../device/efr32mg1p_romtable.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_rtcc.h | 4 +- .../device/efr32mg1p_rtcc_cc.h | 4 +- .../device/efr32mg1p_rtcc_ret.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_timer.h | 6 +- .../device/efr32mg1p_timer_cc.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_usart.h | 4 +- .../TARGET_EFR32MG1/device/efr32mg1p_wdog.h | 10 +- .../device/efr32mg1p_wdog_pch.h | 4 +- .../TARGET_EFR32MG1/device/em_device.h | 4 +- .../TARGET_EFR32MG1/device/system_efr32mg1p.c | 4 +- .../TARGET_EFR32MG1/device/system_efr32mg1p.h | 4 +- .../device/efr32mg12p132f1024gl125.h | 2 +- .../device/efr32mg12p132f1024gm48.h | 2 +- .../device/efr32mg12p232f1024gl125.h | 2 +- .../device/efr32mg12p232f1024gm48.h | 2 +- .../device/efr32mg12p332f1024gl125.h | 2 +- .../device/efr32mg12p332f1024gm48.h | 2 +- .../device/efr32mg12p432f1024gl125.h | 2 +- .../device/efr32mg12p432f1024gm48.h | 2 +- .../device/efr32mg12p433f1024gl125.h | 2 +- .../device/efr32mg12p433f1024gm48.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_acmp.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_adc.h | 2 +- .../device/efr32mg12p_af_pins.h | 2 +- .../device/efr32mg12p_af_ports.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_cmu.h | 2 +- .../device/efr32mg12p_cryotimer.h | 2 +- .../device/efr32mg12p_crypto.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_csen.h | 2 +- .../device/efr32mg12p_devinfo.h | 2 +- .../device/efr32mg12p_dma_descriptor.h | 2 +- .../device/efr32mg12p_dmareq.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_emu.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_etm.h | 2 +- .../device/efr32mg12p_fpueh.h | 2 +- .../device/efr32mg12p_gpcrc.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_gpio.h | 2 +- .../device/efr32mg12p_gpio_p.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_i2c.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_idac.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_ldma.h | 2 +- .../device/efr32mg12p_ldma_ch.h | 2 +- .../device/efr32mg12p_lesense.h | 2 +- .../device/efr32mg12p_lesense_buf.h | 2 +- .../device/efr32mg12p_lesense_ch.h | 2 +- .../device/efr32mg12p_lesense_st.h | 2 +- .../device/efr32mg12p_letimer.h | 2 +- .../device/efr32mg12p_leuart.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_msc.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_pcnt.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_prs.h | 2 +- .../device/efr32mg12p_prs_ch.h | 2 +- .../device/efr32mg12p_prs_signals.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_rmu.h | 2 +- .../device/efr32mg12p_romtable.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_rtcc.h | 2 +- .../device/efr32mg12p_rtcc_cc.h | 2 +- .../device/efr32mg12p_rtcc_ret.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_smu.h | 2 +- .../device/efr32mg12p_timer.h | 2 +- .../device/efr32mg12p_timer_cc.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_trng.h | 2 +- .../device/efr32mg12p_usart.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_vdac.h | 2 +- .../device/efr32mg12p_vdac_opa.h | 2 +- .../TARGET_EFR32MG12/device/efr32mg12p_wdog.h | 2 +- .../device/efr32mg12p_wdog_pch.h | 2 +- .../TARGET_EFR32MG12/device/em_device.h | 2 +- .../device/system_efr32mg12p.c | 2 +- .../device/system_efr32mg12p.h | 2 +- 594 files changed, 3687 insertions(+), 3067 deletions(-) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f1024.h index 304419d8c0..274893c944 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f1024.h @@ -2,10 +2,10 @@ * @file efm32gg230f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG230F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -115,12 +115,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG230F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f512.h index 12971ee07c..36a44ca1a4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg230f512.h @@ -2,10 +2,10 @@ * @file efm32gg230f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG230F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -115,12 +115,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG230F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f1024.h index 03fd2b9f93..49c86eb24c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f1024.h @@ -2,10 +2,10 @@ * @file efm32gg232f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG232F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -115,12 +115,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG232F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f512.h index 90332d74c9..27143a3a8c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg232f512.h @@ -2,10 +2,10 @@ * @file efm32gg232f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG232F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -115,12 +115,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG232F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f1024.h index 1d8480ec79..d6b0d4b041 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f1024.h @@ -2,10 +2,10 @@ * @file efm32gg280f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG280F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG280F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f512.h index 8068a401e3..53a510aadc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg280f512.h @@ -2,10 +2,10 @@ * @file efm32gg280f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG280F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG280F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f1024.h index b03f61c61a..41c170adfc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f1024.h @@ -2,10 +2,10 @@ * @file efm32gg290f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG290F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG290F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f512.h index 6a7c7af70a..f5c4398494 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg290f512.h @@ -2,10 +2,10 @@ * @file efm32gg290f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG290F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG290F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f1024.h index 09ef2a73bc..d576188a8f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f1024.h @@ -2,10 +2,10 @@ * @file efm32gg295f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG295F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG295F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f512.h index 12cb10ea5b..40fa214b4c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg295f512.h @@ -2,10 +2,10 @@ * @file efm32gg295f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG295F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -120,12 +120,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG295F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f1024.h index 88906ccf12..2d1957d9ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f1024.h @@ -2,10 +2,10 @@ * @file efm32gg330f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG330F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG330F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f512.h index 2414e1c5a2..07cbaceccf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg330f512.h @@ -2,10 +2,10 @@ * @file efm32gg330f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG330F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG330F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f1024.h index 8fae90e586..1ac79e902b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f1024.h @@ -2,10 +2,10 @@ * @file efm32gg332f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG332F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG332F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f512.h index f22a18f372..7215bfe811 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg332f512.h @@ -2,10 +2,10 @@ * @file efm32gg332f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG332F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG332F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h index bc1b469930..11d5b71247 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h @@ -2,10 +2,10 @@ * @file efm32gg380f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG380F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG380F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f512.h index d65dbd561a..3b460728f9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f512.h @@ -2,10 +2,10 @@ * @file efm32gg380f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG380F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG380F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f1024.h index cfb18256e7..ec77d2da7d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f1024.h @@ -2,10 +2,10 @@ * @file efm32gg390f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG390F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG390F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f512.h index d6ab45ac94..4906cd57da 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg390f512.h @@ -2,10 +2,10 @@ * @file efm32gg390f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG390F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG390F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f1024.h index 4b4eef688c..b28e68d25d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f1024.h @@ -2,10 +2,10 @@ * @file efm32gg395f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG395F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG395F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f512.h index 52a73d3e19..4b37a15155 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg395f512.h @@ -2,10 +2,10 @@ * @file efm32gg395f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG395F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG395F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f1024.h index a7d84f435d..0f9bfaf003 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f1024.h @@ -2,10 +2,10 @@ * @file efm32gg840f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG840F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG840F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f512.h index 21a6d3f0f3..d4d1a36845 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg840f512.h @@ -2,10 +2,10 @@ * @file efm32gg840f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG840F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG840F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f1024.h index 5fa0fc5e55..757af1fad8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f1024.h @@ -2,10 +2,10 @@ * @file efm32gg842f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG842F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG842F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f512.h index 3520c585a8..38da9c1bdd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg842f512.h @@ -2,10 +2,10 @@ * @file efm32gg842f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG842F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG842F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f1024.h index e8435964bb..923d58e533 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f1024.h @@ -2,10 +2,10 @@ * @file efm32gg880f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG880F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG880F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f512.h index 3243d17dd3..f8d0010607 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg880f512.h @@ -2,10 +2,10 @@ * @file efm32gg880f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG880F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG880F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f1024.h index ae66072804..484076d93e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f1024.h @@ -2,10 +2,10 @@ * @file efm32gg890f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG890F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG890F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f512.h index 1bf14d08d5..c7d1341a3e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg890f512.h @@ -2,10 +2,10 @@ * @file efm32gg890f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG890F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG890F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f1024.h index 215d05171a..ebb9f5ea3a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f1024.h @@ -2,10 +2,10 @@ * @file efm32gg895f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG895F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG895F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f512.h index 7c8205a416..b7ca3b09a7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg895f512.h @@ -2,10 +2,10 @@ * @file efm32gg895f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG895F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG895F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f1024.h index 6b442e444b..6b58551d6b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f1024.h @@ -2,10 +2,10 @@ * @file efm32gg900f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG900F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG900F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f512.h index 5da1cbf63d..51edd3ca9d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg900f512.h @@ -2,10 +2,10 @@ * @file efm32gg900f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG900F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG900F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f1024.h index c574483f53..038fbbe44b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f1024.h @@ -2,10 +2,10 @@ * @file efm32gg940f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG940F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG940F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f512.h index a215c9f774..2dd8032a0b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg940f512.h @@ -2,10 +2,10 @@ * @file efm32gg940f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG940F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG940F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f1024.h index 243e8c6303..b90938ac0f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f1024.h @@ -2,10 +2,10 @@ * @file efm32gg942f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG942F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG942F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f512.h index ecc9546983..e7da805488 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg942f512.h @@ -2,10 +2,10 @@ * @file efm32gg942f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG942F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG942F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f1024.h index d8f89b75a8..5ac79249b9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f1024.h @@ -2,10 +2,10 @@ * @file efm32gg980f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG980F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG980F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f512.h index c50ccca4e9..99ef7bb750 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg980f512.h @@ -2,10 +2,10 @@ * @file efm32gg980f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG980F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG980F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f1024.h index 287ef99066..20adfe3b65 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f1024.h @@ -2,10 +2,10 @@ * @file efm32gg990f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG990F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG990F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f512.h index ffd9057114..2437d51983 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg990f512.h @@ -2,10 +2,10 @@ * @file efm32gg990f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG990F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG990F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f1024.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f1024.h index ae4e067919..6ea589419d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f1024.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f1024.h @@ -2,10 +2,10 @@ * @file efm32gg995f1024.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG995F1024 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG995F1024) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f512.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f512.h index 9e1d9317a4..28217055fd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f512.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg995f512.h @@ -2,10 +2,10 @@ * @file efm32gg995f512.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG995F512 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32GG995F512) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_acmp.h index 994e91b328..1bf9e27584 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_acmp.h * @brief EFM32GG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_adc.h index 375773ff03..81843f867c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_adc.h * @brief EFM32GG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_aes.h index f70658806e..4aff962709 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_aes.h * @brief EFM32GG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_pins.h index 7b4c33068f..dd4ec98f2d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_af_pins.h * @brief EFM32GG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_ports.h index ae9cda5020..d347591430 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_af_ports.h * @brief EFM32GG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc.h index 0f2d0bc282..becaa09942 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_burtc.h * @brief EFM32GG_BURTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc_ret.h index 1f1508d4ad..1d67461194 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_burtc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_burtc_ret.h * @brief EFM32GG_BURTC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_calibrate.h index bacc47992e..f40d77de48 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_calibrate.h * @brief EFM32GG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_cmu.h index eca6a54238..01fdbde90b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_cmu.h * @brief EFM32GG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dac.h index f7993d17eb..dae32c6678 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dac.h * @brief EFM32GG_DAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_devinfo.h index 7df832820d..f52a5997ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_devinfo.h * @brief EFM32GG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma.h index be68a96c47..3cd606b0dc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dma.h * @brief EFM32GG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_ch.h index f38dd4e06b..4abe5b4004 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dma_ch.h * @brief EFM32GG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_descriptor.h index 781bed3a12..7b08013c1e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dma_descriptor.h * @brief EFM32GG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmactrl.h index badbfe0357..34d69c07e7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dmactrl.h * @brief EFM32GG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmareq.h index f074dd3f5e..dc230e19bf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_dmareq.h * @brief EFM32GG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_ebi.h index bd5ca7b128..7806b18cef 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_ebi.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_ebi.h * @brief EFM32GG_EBI register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_emu.h index f6a050b8f2..5016536191 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_emu.h * @brief EFM32GG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h index 8bbc6e0c64..dc24a20609 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_etm.h * @brief EFM32GG_ETM register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio.h index 5d280c0f30..b78033b92f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_gpio.h * @brief EFM32GG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio_p.h index 0007874e91..14689972a8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_gpio_p.h * @brief EFM32GG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_i2c.h index 0530b52a2a..da4faaad00 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_i2c.h * @brief EFM32GG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lcd.h index 6fd4d48fc7..76b576f597 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lcd.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lcd.h * @brief EFM32GG_LCD register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense.h index 761a0e1edb..d785aacf14 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lesense.h * @brief EFM32GG_LESENSE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_buf.h index 5c063b4318..120064fd05 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_buf.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_buf.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lesense_buf.h * @brief EFM32GG_LESENSE_BUF register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_ch.h index 008f1ab977..bc5d5661a3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lesense_ch.h * @brief EFM32GG_LESENSE_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_st.h index f81323ad1b..e8be4b3c20 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_st.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_lesense_st.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_lesense_st.h * @brief EFM32GG_LESENSE_ST register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_letimer.h index a15ef1f7e6..420cad96e1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_letimer.h * @brief EFM32GG_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_leuart.h index f2455657f2..9a46fad1d0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_leuart.h * @brief EFM32GG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_msc.h index ccaa36a6a1..284c5ac966 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_msc.h * @brief EFM32GG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_pcnt.h index 625a6c507a..b228387cef 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_pcnt.h * @brief EFM32GG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs.h index 4a8169f7f4..844590e350 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_prs.h * @brief EFM32GG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_ch.h index 9d50eb1029..e0debe019c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_prs_ch.h * @brief EFM32GG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_signals.h index 83ca5c305c..5d6b0a8926 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_prs_signals.h * @brief EFM32GG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rmu.h index 2913a13f85..a00e094cb2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_rmu.h * @brief EFM32GG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_romtable.h index 4db9e2e36e..ce454cc9c5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_romtable.h * @brief EFM32GG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rtc.h index 0fc1784187..5d54586360 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_rtc.h * @brief EFM32GG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer.h index a1913c8f94..611ee7a110 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_timer.h * @brief EFM32GG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer_cc.h index 700e913e04..2508142c8f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_timer_cc.h * @brief EFM32GG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_uart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_uart.h index 2c40fb9ff8..2bf2046da3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_uart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_uart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_uart.h * @brief EFM32GG_UART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usart.h index 2341301946..b25c4b612a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usart.h * @brief EFM32GG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb.h index 76e8dae1f8..5cd0a36cbe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usb.h * @brief EFM32GG_USB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_diep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_diep.h index c416641edc..b2b29834d1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_diep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_diep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usb_diep.h * @brief EFM32GG_USB_DIEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_doep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_doep.h index f3dfccccf5..811e5f652a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_doep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_doep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usb_doep.h * @brief EFM32GG_USB_DOEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_hc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_hc.h index 16e77b5107..70366971ee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_hc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_usb_hc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_usb_hc.h * @brief EFM32GG_USB_HC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_vcmp.h index 291f2c0f43..563cd3e7b2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_vcmp.h * @brief EFM32GG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_wdog.h index 0d9543e847..def53f3b0e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32gg_wdog.h * @brief EFM32GG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/em_device.h index 996ab74ecc..0a2771769b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.c index 07501db6b4..99f60f7a75 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32gg.c * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.h index 40e650ae28..f72dd8a9fa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/system_efm32gg.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32gg.h * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f32.h index 01c9a9ad62..8100c9a89c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f32.h @@ -2,10 +2,10 @@ * @file efm32hg108f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG108F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -97,12 +97,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG108F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f64.h index fb7987894e..b0a39e0a13 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg108f64.h @@ -2,10 +2,10 @@ * @file efm32hg108f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG108F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -97,12 +97,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG108F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f32.h index c286e86499..4482a13c12 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f32.h @@ -2,10 +2,10 @@ * @file efm32hg110f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG110F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG110F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f64.h index 74d9ed02a6..dd4c381569 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg110f64.h @@ -2,10 +2,10 @@ * @file efm32hg110f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG110F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG110F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f32.h index 3656223bbb..d0b453fc3f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f32.h @@ -2,10 +2,10 @@ * @file efm32hg210f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG210F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG210F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f64.h index 2b7cfce71f..51ebc9db8b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg210f64.h @@ -2,10 +2,10 @@ * @file efm32hg210f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG210F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG210F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f32.h index 41a5ddcf3a..1b76246e45 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f32.h @@ -2,10 +2,10 @@ * @file efm32hg222f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG222F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG222F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f64.h index 488c63ac41..2c8137209f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg222f64.h @@ -2,10 +2,10 @@ * @file efm32hg222f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG222F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG222F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f32.h index 7329bb777c..4ecd799427 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f32.h @@ -2,10 +2,10 @@ * @file efm32hg308f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG308F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -98,12 +98,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG308F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h index d5f91bf956..3c46c52e92 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h @@ -2,10 +2,10 @@ * @file efm32hg308f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG308F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -98,12 +98,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG308F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f32.h index 9efe29a3d8..d76bf9df69 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f32.h @@ -2,10 +2,10 @@ * @file efm32hg309f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG309F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG309F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f64.h index e494249e66..65bdc0ec5a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg309f64.h @@ -2,10 +2,10 @@ * @file efm32hg309f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG309F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG309F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f32.h index c1bd7aea9d..16a47c4aaa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f32.h @@ -2,10 +2,10 @@ * @file efm32hg310f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG310F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG310F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f64.h index e17cb95292..830d509195 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg310f64.h @@ -2,10 +2,10 @@ * @file efm32hg310f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG310F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG310F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f32.h index fdfb27482c..c36722c91a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f32.h @@ -2,10 +2,10 @@ * @file efm32hg321f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG321F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG321F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f64.h index 13c6bdf2af..a0543bce6e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg321f64.h @@ -2,10 +2,10 @@ * @file efm32hg321f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG321F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -99,12 +99,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG321F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f32.h index 68236667a8..6b7b2709ee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f32.h @@ -2,10 +2,10 @@ * @file efm32hg322f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG322F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG322F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f64.h index de6b23112f..be4a568067 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg322f64.h @@ -2,10 +2,10 @@ * @file efm32hg322f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG322F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG322F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f32.h index 4b230ef165..67c2d715f8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f32.h @@ -2,10 +2,10 @@ * @file efm32hg350f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG350F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG350F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f64.h index 86e92e1e43..4998b6caf1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg350f64.h @@ -2,10 +2,10 @@ * @file efm32hg350f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32HG350F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -100,12 +100,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32HG350F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_acmp.h index 242362b32f..a4a9d74da5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_acmp.h * @brief EFM32HG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_adc.h index fdfbd2162a..d0411fa02b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_adc.h * @brief EFM32HG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_aes.h index 9d1f6db964..acddc22c13 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_aes.h * @brief EFM32HG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_pins.h index 3588e78a9f..7f64dd5623 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_af_pins.h * @brief EFM32HG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_ports.h index e974f86401..58aa7579cb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_af_ports.h * @brief EFM32HG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_calibrate.h index 381800add6..f9a14fe090 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_calibrate.h * @brief EFM32HG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_cmu.h index b9a69134cc..665a8db28f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_cmu.h * @brief EFM32HG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_devinfo.h index b44828c429..2cdd51b4ef 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_devinfo.h * @brief EFM32HG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma.h index 72ac84d805..bc49f81b07 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dma.h * @brief EFM32HG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_ch.h index 1d03460b61..f0bdd8c271 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dma_ch.h * @brief EFM32HG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_descriptor.h index 7d3aa0cf7b..b66b18467d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dma_descriptor.h * @brief EFM32HG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmactrl.h index a733daea6f..9a89dcada8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dmactrl.h * @brief EFM32HG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmareq.h index 15fa8e993e..e3ce9d75fe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_dmareq.h * @brief EFM32HG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_emu.h index 2ec3c342ee..454218df9b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_emu.h * @brief EFM32HG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio.h index 6a0e3e51e6..da58990bc4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_gpio.h * @brief EFM32HG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio_p.h index 5ed512138e..222ff88a6f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_gpio_p.h * @brief EFM32HG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_i2c.h index 31105e067f..1b64b9a84d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_i2c.h * @brief EFM32HG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_idac.h index 0a39150d21..8f5b5aa8d6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_idac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_idac.h * @brief EFM32HG_IDAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_leuart.h index 9d9a5bcdec..e9e8b9fe4f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_leuart.h * @brief EFM32HG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_msc.h index b83dbfd4f1..723d463491 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_msc.h * @brief EFM32HG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_mtb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_mtb.h index 24f2289462..487da05670 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_mtb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_mtb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_mtb.h * @brief EFM32HG_MTB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_pcnt.h index 0d60292236..1b9445793d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_pcnt.h * @brief EFM32HG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs.h index 715cc356e1..b096020109 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_prs.h * @brief EFM32HG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_ch.h index 46c129f1be..509257a655 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_prs_ch.h * @brief EFM32HG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_signals.h index 8ff72af64e..97c0a92df8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_prs_signals.h * @brief EFM32HG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rmu.h index 0c3d6d12fc..766063d087 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_rmu.h * @brief EFM32HG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_romtable.h index 4bd40db98d..e69b2fef0c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_romtable.h * @brief EFM32HG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rtc.h index 767d000a0a..923af7b2ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_rtc.h * @brief EFM32HG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer.h index ab51f66d01..18f320cd7b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_timer.h * @brief EFM32HG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer_cc.h index 6263776a3e..bb7a5c958a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_timer_cc.h * @brief EFM32HG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usart.h index 3fb359ff74..12471b8c8a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_usart.h * @brief EFM32HG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb.h index 223dd49446..e4828139e7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_usb.h * @brief EFM32HG_USB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_diep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_diep.h index 05c706f76c..7e5702ed1a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_diep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_diep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_usb_diep.h * @brief EFM32HG_USB_DIEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_doep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_doep.h index 09039271bb..971f8b76ef 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_doep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_usb_doep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_usb_doep.h * @brief EFM32HG_USB_DOEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_vcmp.h index b1f5f45e7f..6018dce3ae 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_vcmp.h * @brief EFM32HG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_wdog.h index d0f2ac350e..c5cdbbcecc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32hg_wdog.h * @brief EFM32HG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/em_device.h index 9c916dcbf4..aa59dd2cb1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.c index f3848b4b05..5cdead97bb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32hg.c * @brief CMSIS Cortex-M0+ System Layer for EFM32HG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.h index e1dcaffb89..ae0e789830 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/system_efm32hg.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file system_efm32hg.h * @brief CMSIS Cortex-M System Layer for EFM32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f128.h index 35b0073e94..9e4e78ad36 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f128.h @@ -2,10 +2,10 @@ * @file efm32lg230f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG230F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG230F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f256.h index b57fea9255..4a9e168d11 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f256.h @@ -2,10 +2,10 @@ * @file efm32lg230f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG230F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG230F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f64.h index b29641f0f9..27ddffca72 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg230f64.h @@ -2,10 +2,10 @@ * @file efm32lg230f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG230F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG230F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f128.h index 71add6c549..e0d638891c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f128.h @@ -2,10 +2,10 @@ * @file efm32lg232f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG232F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG232F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f256.h index fd9611ba02..d6877d205e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f256.h @@ -2,10 +2,10 @@ * @file efm32lg232f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG232F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG232F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f64.h index 5d4800941c..e3fdec6028 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg232f64.h @@ -2,10 +2,10 @@ * @file efm32lg232f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG232F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -116,12 +116,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG232F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f128.h index 47b1c2426f..a71f42f5cb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f128.h @@ -2,10 +2,10 @@ * @file efm32lg280f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG280F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG280F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f256.h index ebc3708e50..f5e96332b8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f256.h @@ -2,10 +2,10 @@ * @file efm32lg280f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG280F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG280F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f64.h index eda3b05b65..39f55d62ed 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg280f64.h @@ -2,10 +2,10 @@ * @file efm32lg280f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG280F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG280F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f128.h index 962d9140fe..03bcd469c8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f128.h @@ -2,10 +2,10 @@ * @file efm32lg290f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG290F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG290F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f256.h index fedbcc7ff5..011abf1b8b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f256.h @@ -2,10 +2,10 @@ * @file efm32lg290f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG290F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG290F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f64.h index ffb488e2b4..197484638d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg290f64.h @@ -2,10 +2,10 @@ * @file efm32lg290f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG290F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG290F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f128.h index 776f1cb70d..bd38bdc054 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f128.h @@ -2,10 +2,10 @@ * @file efm32lg295f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG295F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG295F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f256.h index 6f2a5b2041..ac37db8846 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f256.h @@ -2,10 +2,10 @@ * @file efm32lg295f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG295F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG295F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f64.h index e34aaf3872..33f571ea32 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg295f64.h @@ -2,10 +2,10 @@ * @file efm32lg295f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG295F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG295F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f128.h index 5cdbc7cf62..cacc58ba28 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f128.h @@ -2,10 +2,10 @@ * @file efm32lg330f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG330F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG330F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f256.h index 2899451dca..3051934b07 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f256.h @@ -2,10 +2,10 @@ * @file efm32lg330f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG330F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG330F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f64.h index 41bfa38a05..6b5858b74f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg330f64.h @@ -2,10 +2,10 @@ * @file efm32lg330f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG330F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG330F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f128.h index b0c55a4de4..469c35b803 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f128.h @@ -2,10 +2,10 @@ * @file efm32lg332f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG332F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG332F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f256.h index a8d063de0c..65ed5a7839 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f256.h @@ -2,10 +2,10 @@ * @file efm32lg332f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG332F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG332F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f64.h index cf5a08fc78..15623f2519 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg332f64.h @@ -2,10 +2,10 @@ * @file efm32lg332f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG332F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG332F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f128.h index f1b43d2df7..5d5563303a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f128.h @@ -2,10 +2,10 @@ * @file efm32lg360f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG360F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG360F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f256.h index 614fe9dbd6..1fa10d42a4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f256.h @@ -2,10 +2,10 @@ * @file efm32lg360f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG360F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG360F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f64.h index c373d89d7d..62269b8e2d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg360f64.h @@ -2,10 +2,10 @@ * @file efm32lg360f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG360F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -121,12 +121,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG360F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f128.h index 1413f40b2a..78b36f0f9d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f128.h @@ -2,10 +2,10 @@ * @file efm32lg380f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG380F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG380F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f256.h index d24e7cfc33..087eefaf69 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f256.h @@ -2,10 +2,10 @@ * @file efm32lg380f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG380F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG380F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f64.h index 8bab9e275a..09d4094e3f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg380f64.h @@ -2,10 +2,10 @@ * @file efm32lg380f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG380F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG380F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f128.h index 291d5f519b..4ce8fd17b0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f128.h @@ -2,10 +2,10 @@ * @file efm32lg390f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG390F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG390F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f256.h index a19c291685..8a96380058 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f256.h @@ -2,10 +2,10 @@ * @file efm32lg390f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG390F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG390F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f64.h index d3a3c49ab9..66be636be9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg390f64.h @@ -2,10 +2,10 @@ * @file efm32lg390f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG390F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG390F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f128.h index f40cd8717f..c3f4abd4ca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f128.h @@ -2,10 +2,10 @@ * @file efm32lg395f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG395F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG395F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f256.h index 06c2953c32..57ced454a7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f256.h @@ -2,10 +2,10 @@ * @file efm32lg395f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG395F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG395F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f64.h index a33b682b87..aa0f1bad0b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg395f64.h @@ -2,10 +2,10 @@ * @file efm32lg395f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG395F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG395F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f128.h index 11f2c7f8e0..56dc58b56b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f128.h @@ -2,10 +2,10 @@ * @file efm32lg840f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG840F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG840F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f256.h index 2a2fcefa4f..3240db478f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f256.h @@ -2,10 +2,10 @@ * @file efm32lg840f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG840F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG840F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h index b2c6030704..7800c62a74 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h @@ -2,10 +2,10 @@ * @file efm32lg840f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG840F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG840F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f128.h index 0a822f3e34..b248f987ed 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f128.h @@ -2,10 +2,10 @@ * @file efm32lg842f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG842F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG842F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f256.h index e5a5cb474d..6bc214eda6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f256.h @@ -2,10 +2,10 @@ * @file efm32lg842f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG842F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG842F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f64.h index 28f709d71a..59546f3e5a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg842f64.h @@ -2,10 +2,10 @@ * @file efm32lg842f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG842F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG842F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f128.h index c984885402..57a541c515 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f128.h @@ -2,10 +2,10 @@ * @file efm32lg880f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG880F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG880F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f256.h index 8e9def0b9e..827567ccba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f256.h @@ -2,10 +2,10 @@ * @file efm32lg880f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG880F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG880F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f64.h index 784099620d..ed37542285 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg880f64.h @@ -2,10 +2,10 @@ * @file efm32lg880f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG880F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG880F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f128.h index 6913d62228..1f7c474f9a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f128.h @@ -2,10 +2,10 @@ * @file efm32lg890f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG890F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG890F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f256.h index 9634c9e2f9..4b4dcf18a8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f256.h @@ -2,10 +2,10 @@ * @file efm32lg890f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG890F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG890F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f64.h index fdb82f5554..38cb854106 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg890f64.h @@ -2,10 +2,10 @@ * @file efm32lg890f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG890F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG890F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f128.h index 1f72cbed08..3eddf1dacc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f128.h @@ -2,10 +2,10 @@ * @file efm32lg895f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG895F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG895F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f256.h index b4b2b43886..8215068440 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f256.h @@ -2,10 +2,10 @@ * @file efm32lg895f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG895F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG895F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f64.h index 77a5b3fcb8..3f287a3631 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg895f64.h @@ -2,10 +2,10 @@ * @file efm32lg895f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG895F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG895F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg900f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg900f256.h index 7b31945df6..dea1404748 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg900f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg900f256.h @@ -2,10 +2,10 @@ * @file efm32lg900f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG900F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG900F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f128.h index 3df5c67be7..e8c8274f48 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f128.h @@ -2,10 +2,10 @@ * @file efm32lg940f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG940F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG940F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f256.h index 4910ef8500..aa2c9b0a59 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f256.h @@ -2,10 +2,10 @@ * @file efm32lg940f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG940F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG940F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f64.h index 2ceac32b36..8777184a46 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg940f64.h @@ -2,10 +2,10 @@ * @file efm32lg940f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG940F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG940F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f128.h index c8ba094f70..f902a76e56 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f128.h @@ -2,10 +2,10 @@ * @file efm32lg942f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG942F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG942F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f256.h index dccc95d33b..c5428fca95 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f256.h @@ -2,10 +2,10 @@ * @file efm32lg942f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG942F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG942F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f64.h index af421a3c65..66ed5de5fb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg942f64.h @@ -2,10 +2,10 @@ * @file efm32lg942f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG942F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG942F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f128.h index f5f205c90a..5162699e69 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f128.h @@ -2,10 +2,10 @@ * @file efm32lg980f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG980F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG980F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f256.h index 4afb513a8f..6940beb844 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f256.h @@ -2,10 +2,10 @@ * @file efm32lg980f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG980F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG980F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h index b59be1ce82..0bed24d851 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h @@ -2,10 +2,10 @@ * @file efm32lg980f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG980F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG980F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f128.h index 74609a4fe4..b8efa8c2ea 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f128.h @@ -2,10 +2,10 @@ * @file efm32lg990f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG990F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG990F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f256.h index a27e711abf..a1baed571f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f256.h @@ -2,10 +2,10 @@ * @file efm32lg990f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG990F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG990F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f64.h index af427afb3a..bd31cbd004 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg990f64.h @@ -2,10 +2,10 @@ * @file efm32lg990f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG990F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG990F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f128.h index cc9cd86055..461fd50dd6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f128.h @@ -2,10 +2,10 @@ * @file efm32lg995f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG995F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG995F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f256.h index d1398b8b77..0c28f892e1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f256.h @@ -2,10 +2,10 @@ * @file efm32lg995f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG995F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG995F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f64.h index 17359044e4..10ad3f8feb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg995f64.h @@ -2,10 +2,10 @@ * @file efm32lg995f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG995F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32LG995F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_acmp.h index 1ad27b8233..9f451866fb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_acmp.h * @brief EFM32LG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_adc.h index ee30a4531b..154c2af3ee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_adc.h * @brief EFM32LG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h index c2ebe218ea..e53ec353ff 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_aes.h * @brief EFM32LG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_pins.h index 0dc982bf76..5f779444fa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_af_pins.h * @brief EFM32LG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_ports.h index 541240a17d..d99c8c8e77 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_af_ports.h * @brief EFM32LG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc.h index 96eb19659c..0ba56c6838 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_burtc.h * @brief EFM32LG_BURTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc_ret.h index e9ca084c6d..7c0d5aa044 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_burtc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_burtc_ret.h * @brief EFM32LG_BURTC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_calibrate.h index 43b8fa5446..7864fcfa5f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_calibrate.h * @brief EFM32LG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_cmu.h index c6ca47c528..a5fce19951 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_cmu.h * @brief EFM32LG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dac.h index 6d46975dfa..259e446990 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dac.h * @brief EFM32LG_DAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h index e08d2b6045..9fe1e05ca9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_devinfo.h * @brief EFM32LG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma.h index a68a1caad0..8ade291b47 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dma.h * @brief EFM32LG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_ch.h index 6abd7a58a8..5650501296 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dma_ch.h * @brief EFM32LG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_descriptor.h index 3e7618088a..030fc85688 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dma_descriptor.h * @brief EFM32LG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmactrl.h index 52171bf6e3..ac7e3a8717 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dmactrl.h * @brief EFM32LG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h index 0918a24609..b5db52d44a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_dmareq.h * @brief EFM32LG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h index 705c6bc621..1b49d89bfb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_ebi.h * @brief EFM32LG_EBI register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_emu.h index ac6466c1a1..28f537af9f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_emu.h * @brief EFM32LG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_etm.h index 21112d31f8..c692a0b8de 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_etm.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_etm.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_etm.h * @brief EFM32LG_ETM register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h index ea4bc19af0..86a66d533c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_gpio.h * @brief EFM32LG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio_p.h index 43e45dd6cc..8a8694fc65 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_gpio_p.h * @brief EFM32LG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_i2c.h index 35b1c91413..7b940193cb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_i2c.h * @brief EFM32LG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lcd.h index 618f006abb..29586a380a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lcd.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lcd.h * @brief EFM32LG_LCD register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense.h index 3ff319ed54..65d16f59b5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lesense.h * @brief EFM32LG_LESENSE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_buf.h index 70a2de6a7e..3b94d44850 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_buf.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_buf.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lesense_buf.h * @brief EFM32LG_LESENSE_BUF register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_ch.h index aa754a8107..9f37985eca 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lesense_ch.h * @brief EFM32LG_LESENSE_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_st.h index e30555d28c..f9474858b3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_st.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_lesense_st.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_lesense_st.h * @brief EFM32LG_LESENSE_ST register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_letimer.h index 2f874de534..473089b362 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_letimer.h * @brief EFM32LG_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h index 93ff07fb96..53b86b5966 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_leuart.h * @brief EFM32LG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h index 919eaf02d5..2d15ae58f5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_msc.h * @brief EFM32LG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_pcnt.h index f369b79a10..037be6bac4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_pcnt.h * @brief EFM32LG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs.h index 8d38d71b01..f3a9dd383d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_prs.h * @brief EFM32LG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_ch.h index 9852c30251..9912e5a70d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_prs_ch.h * @brief EFM32LG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_signals.h index f34970d94b..432b3a6889 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_prs_signals.h * @brief EFM32LG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rmu.h index 65a0680e01..71b8007032 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_rmu.h * @brief EFM32LG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_romtable.h index e7a1bc8cf5..372cb8674f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_romtable.h * @brief EFM32LG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h index 35187b6688..6781a4d574 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_rtc.h * @brief EFM32LG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer.h index a0ad7b4465..15223d4ebc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_timer.h * @brief EFM32LG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer_cc.h index df9e7dc007..88a63c112e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_timer_cc.h * @brief EFM32LG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h index 99958cf658..4b71f5a91a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_uart.h * @brief EFM32LG_UART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usart.h index 2d9a73d309..54945b35a5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usart.h * @brief EFM32LG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb.h index 6106899331..e013e220d8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usb.h * @brief EFM32LG_USB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_diep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_diep.h index 06ec1d0680..cf40ba8749 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_diep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_diep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usb_diep.h * @brief EFM32LG_USB_DIEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_doep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_doep.h index f04de8e626..0f4a62c55c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_doep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_doep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usb_doep.h * @brief EFM32LG_USB_DOEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_hc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_hc.h index 8bd79f6468..cb3bf30e53 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_hc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_usb_hc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_usb_hc.h * @brief EFM32LG_USB_HC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_vcmp.h index 2e1b5426b5..fc1c9265c2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_vcmp.h * @brief EFM32LG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_wdog.h index a20b80c9f7..8f3e3f98e9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32lg_wdog.h * @brief EFM32LG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/em_device.h index 663cb80026..5acb39d931 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.c index 79c9f65706..e6d9d4a7b5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32lg.c * @brief CMSIS Cortex-M3 System Layer for EFM32LG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.h index c3070afddc..7f0b499096 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/system_efm32lg.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32lg.h * @brief CMSIS Cortex-M3 System Layer for EFM32LG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128gm32.h index 29372e57c7..de3a6cb0c0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128gm32.h @@ -2,10 +2,10 @@ * @file efm32pg1b100f128gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B100F128GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B100F128GM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128im32.h index b1acbc5d1f..92f170ef7d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f128im32.h @@ -2,10 +2,10 @@ * @file efm32pg1b100f128im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B100F128IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B100F128IM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256gm32.h index d12defc8b5..78d0ae8413 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256gm32.h @@ -2,10 +2,10 @@ * @file efm32pg1b100f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B100F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B100F256GM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256im32.h index e9760e58f5..ae4861c222 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b100f256im32.h @@ -2,10 +2,10 @@ * @file efm32pg1b100f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B100F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B100F256IM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm32.h index 55ec34ce9e..90f2071948 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm32.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f128gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F128GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F128GM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm48.h index fd7e743b0e..c2c75f98d2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128gm48.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f128gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F128GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F128GM48) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128im32.h index bd050c247e..ea72bca16c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f128im32.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f128im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F128IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F128IM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm32.h index c2cfb8bd3f..8c8d894bb4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm32.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F256GM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm48.h index f65e64ce29..f7c5530925 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256gm48.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F256GM48) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im32.h index 9e74f65544..c4a351eb06 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im32.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F256IM32) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h index 3078604580..72b8a6ad65 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b200f256im48.h @@ -2,10 +2,10 @@ * @file efm32pg1b200f256im48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256IM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,18 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32PG1B200F256IM48) @@ -132,39 +134,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_acmp.h index a092855bfe..d2ed5871e7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_acmp.h * @brief EFM32PG1B_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -329,8 +329,6 @@ typedef struct #define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ @@ -497,8 +495,6 @@ typedef struct #define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ @@ -667,8 +663,6 @@ typedef struct #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ @@ -835,8 +829,6 @@ typedef struct #define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_adc.h index 4f241bb379..ba9916f6bd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_adc.h * @brief EFM32PG1B_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_pins.h index b017fe1c67..e7544078c1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_af_pins.h * @brief EFM32PG1B_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_ports.h index 72dc23fa7a..1f1f8c02bc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_af_ports.h * @brief EFM32PG1B_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cmu.h index 38627ef518..bd83c0a46c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_cmu.h * @brief EFM32PG1B_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -56,8 +56,9 @@ typedef struct __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + __IOM uint32_t ULFRCOCTRL; /**< ULFRCO Control Register */ - uint32_t RESERVED3[5]; /**< Reserved for future use **/ + uint32_t RESERVED3[4]; /**< Reserved for future use **/ __IOM uint32_t CALCTRL; /**< Calibration Control Register */ __IOM uint32_t CALCNT; /**< Calibration Counter Register */ uint32_t RESERVED4[2]; /**< Reserved for future use **/ @@ -637,6 +638,30 @@ typedef struct #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ +/* Bit fields for CMU ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_RESETVALUE 0x00020020UL /**< Default value for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MASK 0x00030C3FUL /**< Mask for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_ULFRCOCTRL_TUNING_MASK 0x3FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_ULFRCOCTRL_TUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_TUNING_DEFAULT (_CMU_ULFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_SHIFT 10 /**< Shift value for CMU_MODE */ +#define _CMU_ULFRCOCTRL_MODE_MASK 0xC00UL /**< Bit mask for CMU_MODE */ +#define _CMU_ULFRCOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_1KHZ 0x00000000UL /**< Mode 1KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_2KHZ 0x00000001UL /**< Mode 2KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_4KHZ 0x00000002UL /**< Mode 4KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_32KHZ 0x00000003UL /**< Mode 32KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_DEFAULT (_CMU_ULFRCOCTRL_MODE_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_1KHZ (_CMU_ULFRCOCTRL_MODE_1KHZ << 10) /**< Shifted mode 1KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_2KHZ (_CMU_ULFRCOCTRL_MODE_2KHZ << 10) /**< Shifted mode 2KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_4KHZ (_CMU_ULFRCOCTRL_MODE_4KHZ << 10) /**< Shifted mode 4KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_32KHZ (_CMU_ULFRCOCTRL_MODE_32KHZ << 10) /**< Shifted mode 32KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_RESTRIM_SHIFT 16 /**< Shift value for CMU_RESTRIM */ +#define _CMU_ULFRCOCTRL_RESTRIM_MASK 0x30000UL /**< Bit mask for CMU_RESTRIM */ +#define _CMU_ULFRCOCTRL_RESTRIM_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_RESTRIM_DEFAULT (_CMU_ULFRCOCTRL_RESTRIM_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ + /* Bit fields for CMU CALCTRL */ #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ #define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ @@ -902,7 +927,7 @@ typedef struct /* Bit fields for CMU STATUS */ #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ -#define _CMU_STATUS_MASK 0x07C103FFUL /**< Mask for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x07E103FFUL /**< Mask for CMU_STATUS */ #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ @@ -958,6 +983,11 @@ typedef struct #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */ +#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cryotimer.h index ecf546c833..d093913a42 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cryotimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_cryotimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_cryotimer.h * @brief EFM32PG1B_CRYOTIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_crypto.h index d0253d4832..4c173087da 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_crypto.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_crypto.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_crypto.h * @brief EFM32PG1B_CRYPTO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -843,7 +843,7 @@ typedef struct /* Bit fields for CRYPTO IFS */ #define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ -#define _CRYPTO_IFS_MASK 0x0000000FUL /**< Mask for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ #define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ #define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -854,20 +854,10 @@ typedef struct #define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ #define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFOF (0x1UL << 2) /**< Set BUFOF Interrupt Flag */ -#define _CRYPTO_IFS_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IFS_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFOF_DEFAULT (_CRYPTO_IFS_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFUF (0x1UL << 3) /**< Set BUFUF Interrupt Flag */ -#define _CRYPTO_IFS_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IFS_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IFS_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFUF_DEFAULT (_CRYPTO_IFS_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFS */ /* Bit fields for CRYPTO IFC */ #define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ -#define _CRYPTO_IFC_MASK 0x0000000FUL /**< Mask for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ #define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ #define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -878,20 +868,10 @@ typedef struct #define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ #define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFOF (0x1UL << 2) /**< Clear BUFOF Interrupt Flag */ -#define _CRYPTO_IFC_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IFC_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFOF_DEFAULT (_CRYPTO_IFC_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFUF (0x1UL << 3) /**< Clear BUFUF Interrupt Flag */ -#define _CRYPTO_IFC_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IFC_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IFC_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFUF_DEFAULT (_CRYPTO_IFC_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFC */ /* Bit fields for CRYPTO IEN */ #define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ -#define _CRYPTO_IEN_MASK 0x0000000FUL /**< Mask for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ #define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ #define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -902,16 +882,6 @@ typedef struct #define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ #define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFOF (0x1UL << 2) /**< BUFOF Interrupt Enable */ -#define _CRYPTO_IEN_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IEN_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFOF_DEFAULT (_CRYPTO_IEN_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFUF (0x1UL << 3) /**< BUFUF Interrupt Enable */ -#define _CRYPTO_IEN_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IEN_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IEN_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFUF_DEFAULT (_CRYPTO_IEN_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IEN */ /* Bit fields for CRYPTO SEQ0 */ #define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_devinfo.h index 8f332ed358..300c732f1e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_devinfo.h * @brief EFM32PG1B_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dma_descriptor.h index a0944a1d72..141b29e024 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_dma_descriptor.h * @brief EFM32PG1B_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dmareq.h index cd66547683..1392a44abf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_dmareq.h * @brief EFM32PG1B_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_emu.h index dcb8164e24..40f2d3d8f6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_emu.h * @brief EFM32PG1B_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -63,24 +63,32 @@ typedef struct __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ - - uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ __IOM uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */ __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ - uint32_t RESERVED3[1]; /**< Reserved for future use **/ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ - uint32_t RESERVED4[1]; /**< Reserved for future use **/ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ - uint32_t RESERVED5[5]; /**< Reserved for future use **/ + uint32_t RESERVED4[5]; /**< Reserved for future use **/ __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + + uint32_t RESERVED5[49]; /**< Reserved for future use **/ + __IOM uint32_t BIASCONF; /**< Configurations Related to the Bias */ + + uint32_t RESERVED6[10]; /**< Reserved for future use **/ + __IOM uint32_t TESTLOCK; /**< Test Lock Register */ + + uint32_t RESERVED7[2]; /**< Reserved for future use **/ + __IOM uint32_t BIASTESTCTRL; /**< Test Control Register for regulator and BIAS */ } EMU_TypeDef; /** @} */ /**************************************************************************//** @@ -351,7 +359,7 @@ typedef struct /* Bit fields for EMU IFS */ #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ -#define _EMU_IFS_MASK 0xE11FF0FFUL /**< Mask for EMU_IFS */ +#define _EMU_IFS_MASK 0xE11FC0FFUL /**< Mask for EMU_IFS */ #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -392,16 +400,6 @@ typedef struct #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDFALL (0x1UL << 12) /**< Set VMONPAVDDFALL Interrupt Flag */ -#define _EMU_IFS_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IFS_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IFS_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDFALL_DEFAULT (_EMU_IFS_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDRISE (0x1UL << 13) /**< Set VMONPAVDDRISE Interrupt Flag */ -#define _EMU_IFS_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IFS_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IFS_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDRISE_DEFAULT (_EMU_IFS_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -460,7 +458,7 @@ typedef struct /* Bit fields for EMU IFC */ #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ -#define _EMU_IFC_MASK 0xE11FF0FFUL /**< Mask for EMU_IFC */ +#define _EMU_IFC_MASK 0xE11FC0FFUL /**< Mask for EMU_IFC */ #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -501,16 +499,6 @@ typedef struct #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDFALL (0x1UL << 12) /**< Clear VMONPAVDDFALL Interrupt Flag */ -#define _EMU_IFC_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IFC_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IFC_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDFALL_DEFAULT (_EMU_IFC_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDRISE (0x1UL << 13) /**< Clear VMONPAVDDRISE Interrupt Flag */ -#define _EMU_IFC_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IFC_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IFC_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDRISE_DEFAULT (_EMU_IFC_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -569,7 +557,7 @@ typedef struct /* Bit fields for EMU IEN */ #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ -#define _EMU_IEN_MASK 0xE11FF0FFUL /**< Mask for EMU_IEN */ +#define _EMU_IEN_MASK 0xE11FC0FFUL /**< Mask for EMU_IEN */ #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -610,16 +598,6 @@ typedef struct #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDFALL (0x1UL << 12) /**< VMONPAVDDFALL Interrupt Enable */ -#define _EMU_IEN_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IEN_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IEN_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDFALL_DEFAULT (_EMU_IEN_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDRISE (0x1UL << 13) /**< VMONPAVDDRISE Interrupt Enable */ -#define _EMU_IEN_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IEN_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IEN_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDRISE_DEFAULT (_EMU_IEN_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -817,6 +795,34 @@ typedef struct #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + /* Bit fields for EMU DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ @@ -1035,6 +1041,65 @@ typedef struct #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +/* Bit fields for EMU BIASCONF */ +#define _EMU_BIASCONF_RESETVALUE 0x000000F8UL /**< Default value for EMU_BIASCONF */ +#define _EMU_BIASCONF_MASK 0x000000FCUL /**< Mask for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM01 (0x1UL << 2) /**< NA DUTY in EM01 */ +#define _EMU_BIASCONF_NADUTYEM01_SHIFT 2 /**< Shift value for EMU_NADUTYEM01 */ +#define _EMU_BIASCONF_NADUTYEM01_MASK 0x4UL /**< Bit mask for EMU_NADUTYEM01 */ +#define _EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM01_DEFAULT (_EMU_BIASCONF_NADUTYEM01_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM01 (0x1UL << 3) /**< LP in EM01 */ +#define _EMU_BIASCONF_LPEM01_SHIFT 3 /**< Shift value for EMU_LPEM01 */ +#define _EMU_BIASCONF_LPEM01_MASK 0x8UL /**< Bit mask for EMU_LPEM01 */ +#define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM01_DEFAULT (_EMU_BIASCONF_LPEM01_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_GMCEM23 (0x1UL << 4) /**< GMC in EM234 */ +#define _EMU_BIASCONF_GMCEM23_SHIFT 4 /**< Shift value for EMU_GMCEM23 */ +#define _EMU_BIASCONF_GMCEM23_MASK 0x10UL /**< Bit mask for EMU_GMCEM23 */ +#define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_GMCEM23_DEFAULT (_EMU_BIASCONF_GMCEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_UADUTYEM23 (0x1UL << 5) /**< UADUTY in EM234 */ +#define _EMU_BIASCONF_UADUTYEM23_SHIFT 5 /**< Shift value for EMU_UADUTYEM23 */ +#define _EMU_BIASCONF_UADUTYEM23_MASK 0x20UL /**< Bit mask for EMU_UADUTYEM23 */ +#define _EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_UADUTYEM23_DEFAULT (_EMU_BIASCONF_UADUTYEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM23 (0x1UL << 6) /**< NA DUTY in EM234 */ +#define _EMU_BIASCONF_NADUTYEM23_SHIFT 6 /**< Shift value for EMU_NADUTYEM23 */ +#define _EMU_BIASCONF_NADUTYEM23_MASK 0x40UL /**< Bit mask for EMU_NADUTYEM23 */ +#define _EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM23_DEFAULT (_EMU_BIASCONF_NADUTYEM23_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM23 (0x1UL << 7) /**< LP in EM234 */ +#define _EMU_BIASCONF_LPEM23_SHIFT 7 /**< Shift value for EMU_LPEM23 */ +#define _EMU_BIASCONF_LPEM23_MASK 0x80UL /**< Bit mask for EMU_LPEM23 */ +#define _EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM23_DEFAULT (_EMU_BIASCONF_LPEM23_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_BIASCONF */ + +/* Bit fields for EMU TESTLOCK */ +#define _EMU_TESTLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */ + +/* Bit fields for EMU BIASTESTCTRL */ +#define _EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BIASTESTCTRL */ +#define _EMU_BIASTESTCTRL_MASK 0x00000008UL /**< Mask for EMU_BIASTESTCTRL */ +#define EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3) /**< Reset Bias Ripple Counter */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3 /**< Shift value for EMU_BIAS_RIP_RESET */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL /**< Bit mask for EMU_BIAS_RIP_RESET */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASTESTCTRL */ +#define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASTESTCTRL */ + /** @} End of group EFM32PG1B_EMU */ /** @} End of group Parts */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_fpueh.h index 386e8b6f65..818dec5e60 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_fpueh.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_fpueh.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_fpueh.h * @brief EFM32PG1B_FPUEH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpcrc.h index 8a8445cb28..14a2dba31d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpcrc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpcrc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_gpcrc.h * @brief EFM32PG1B_GPCRC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio.h index 71655bfe1c..65a6962fe6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_gpio.h * @brief EFM32PG1B_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio_p.h index 8c1b0cfbbc..2bb3d5d116 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_gpio_p.h * @brief EFM32PG1B_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_i2c.h index fcb01990da..7dd1b19105 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_i2c.h * @brief EFM32PG1B_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h index 47b2f772f9..76579247fb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_idac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_idac.h * @brief EFM32PG1B_IDAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -43,7 +43,7 @@ typedef struct __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CURPROG; /**< Current Programming Register */ uint32_t RESERVED0[1]; /**< Reserved for future use **/ - __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ uint32_t RESERVED1[2]; /**< Reserved for future use **/ __IM uint32_t STATUS; /**< Status Register */ @@ -259,12 +259,7 @@ typedef struct /* Bit fields for IDAC IFS */ #define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ -#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ -#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ -#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ -#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000002UL /**< Mask for IDAC_IFS */ #define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ #define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ @@ -273,12 +268,7 @@ typedef struct /* Bit fields for IDAC IFC */ #define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ -#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ -#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ -#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ -#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000002UL /**< Mask for IDAC_IFC */ #define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ #define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ @@ -287,12 +277,7 @@ typedef struct /* Bit fields for IDAC IEN */ #define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ -#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ -#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ -#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ -#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000002UL /**< Mask for IDAC_IEN */ #define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ #define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma.h index 0037bac3da..aed20157bd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_ldma.h * @brief EFM32PG1B_LDMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h index c7c53a1ad0..3633f4147d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_ldma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_ldma_ch.h * @brief EFM32PG1B_LDMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_letimer.h index fba7016b13..a2680ba9d1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_letimer.h * @brief EFM32PG1B_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_leuart.h index 4c821a6159..fdf21dc179 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_leuart.h * @brief EFM32PG1B_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_msc.h index 6543ca80b9..355ffdaa21 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_msc.h * @brief EFM32PG1B_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_pcnt.h index d3a0b2be4d..21dbf5dcbf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_pcnt.h * @brief EFM32PG1B_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs.h index 82a561d643..875f839518 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_prs.h * @brief EFM32PG1B_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -756,6 +756,7 @@ typedef struct #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ @@ -821,6 +822,7 @@ typedef struct #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ @@ -891,6 +893,7 @@ typedef struct #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000003CUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CMU 0x0000003DUL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ @@ -908,6 +911,7 @@ typedef struct #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_ch.h index 4fd64da92e..4579e7d4df 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_prs_ch.h * @brief EFM32PG1B_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_signals.h index 0bc2eca0f3..4ac390db0d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_prs_signals.h * @brief EFM32PG1B_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -103,6 +103,7 @@ #define PRS_CRYOTIMER_PERIOD ((60 << 8) + 0) /**< PRS CRYOTIMER Output */ #define PRS_CMU_CLKOUT0 ((61 << 8) + 0) /**< PRS Clock Output 0 */ #define PRS_CMU_CLKOUT1 ((61 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ /** @} End of group EFM32PG1B_PRS */ /** @} End of group Parts */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rmu.h index 708b12e8f0..76f1b37b10 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_rmu.h * @brief EFM32PG1B_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_romtable.h index e948d3503f..008c130c5f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_romtable.h * @brief EFM32PG1B_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc.h index 788321cb3e..52f75a100e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_rtcc.h * @brief EFM32PG1B_RTCC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h index 402208c0c0..7713190d4b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_rtcc_cc.h * @brief EFM32PG1B_RTCC_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_ret.h index 95989994a8..08d37ce0e8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_rtcc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_rtcc_ret.h * @brief EFM32PG1B_RTCC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer.h index f36454350b..d3375e816a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_timer.h * @brief EFM32PG1B_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -188,7 +188,7 @@ typedef struct #define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ #define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Ouptut initial State */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ #define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer_cc.h index 4c2de40945..6f59d048bf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_timer_cc.h * @brief EFM32PG1B_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_usart.h index 703809c891..bdd63b4acc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_usart.h * @brief EFM32PG1B_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog.h index 0ae78a240a..de9d49cf9f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_wdog.h * @brief EFM32PG1B_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -215,17 +215,17 @@ typedef struct /* Bit fields for WDOG IF */ #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ -#define WDOG_IF_TOUT (0x1UL << 0) /**< Wdog Timeout Interrupt Flag */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN (0x1UL << 1) /**< Wdog Warning Timeout Interrupt Flag */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN (0x1UL << 2) /**< Wdog Window Interrupt Flag */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog_pch.h index daf5c3d81e..5c5498d109 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog_pch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/efm32pg1b_wdog_pch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32pg1b_wdog_pch.h * @brief EFM32PG1B_WDOG_PCH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/em_device.h index 53766bba5a..7d3ac63c37 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.c index d925c0557c..73c6352b6b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32pg1b.c * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.h index bf3a225c37..8aa24f12e7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/device/system_efm32pg1b.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32pg1b.h * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f128.h index 3f041f7785..0976138409 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f128.h @@ -2,10 +2,10 @@ * @file efm32wg230f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG230F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG230F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f256.h index 264621120c..5a5fa8c140 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f256.h @@ -2,10 +2,10 @@ * @file efm32wg230f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG230F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG230F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f64.h index 455ab9e5fa..4c29b86f6d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg230f64.h @@ -2,10 +2,10 @@ * @file efm32wg230f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG230F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG230F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f128.h index e3ed1a79a1..b06d9b5b41 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f128.h @@ -2,10 +2,10 @@ * @file efm32wg232f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG232F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG232F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f256.h index d15eba63f3..1f9b76d10b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f256.h @@ -2,10 +2,10 @@ * @file efm32wg232f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG232F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG232F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f64.h index 457486acab..ef1ac42b7f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg232f64.h @@ -2,10 +2,10 @@ * @file efm32wg232f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG232F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -117,12 +117,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG232F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f128.h index fbc49446c1..8f3db4efb4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f128.h @@ -2,10 +2,10 @@ * @file efm32wg280f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG280F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG280F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f256.h index 8441967725..65740741a5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f256.h @@ -2,10 +2,10 @@ * @file efm32wg280f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG280F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG280F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f64.h index 632db480df..7810f25484 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg280f64.h @@ -2,10 +2,10 @@ * @file efm32wg280f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG280F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG280F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f128.h index ab5ab78134..6722cb3c30 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f128.h @@ -2,10 +2,10 @@ * @file efm32wg290f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG290F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG290F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f256.h index cc8f1425a6..1a33b194c8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f256.h @@ -2,10 +2,10 @@ * @file efm32wg290f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG290F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG290F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f64.h index 6e54e4df6e..0e79a6b946 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg290f64.h @@ -2,10 +2,10 @@ * @file efm32wg290f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG290F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG290F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f128.h index 54572f0eba..89712b13c9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f128.h @@ -2,10 +2,10 @@ * @file efm32wg295f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG295F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG295F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f256.h index 2ab20c3cd4..62cbbd9acb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f256.h @@ -2,10 +2,10 @@ * @file efm32wg295f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG295F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG295F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f64.h index e832031bcc..54aca949bc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg295f64.h @@ -2,10 +2,10 @@ * @file efm32wg295f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG295F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG295F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f128.h index 60748b64fa..8e17d65623 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f128.h @@ -2,10 +2,10 @@ * @file efm32wg330f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG330F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG330F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f256.h index b9326e8815..3091585eaf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f256.h @@ -2,10 +2,10 @@ * @file efm32wg330f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG330F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG330F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f64.h index d8bbbdb9d7..53ace98297 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg330f64.h @@ -2,10 +2,10 @@ * @file efm32wg330f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG330F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG330F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f128.h index 36eeddebb6..32973a88e4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f128.h @@ -2,10 +2,10 @@ * @file efm32wg332f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG332F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG332F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h index f85bfc897c..14dd40b6b8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f256.h @@ -2,10 +2,10 @@ * @file efm32wg332f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG332F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG332F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f64.h index 555d720809..4e30b9a715 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg332f64.h @@ -2,10 +2,10 @@ * @file efm32wg332f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG332F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG332F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f128.h index 6e825affcc..293f6ebcea 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f128.h @@ -2,10 +2,10 @@ * @file efm32wg360f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG360F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG360F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f256.h index b49660b147..a1b1608908 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f256.h @@ -2,10 +2,10 @@ * @file efm32wg360f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG360F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG360F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f64.h index aeb5aa846e..654dad97e3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg360f64.h @@ -2,10 +2,10 @@ * @file efm32wg360f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG360F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -122,12 +122,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG360F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f128.h index fd80c5e4bc..acea57d5b5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f128.h @@ -2,10 +2,10 @@ * @file efm32wg380f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG380F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG380F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f256.h index cd2ad874dd..d1ce01086a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f256.h @@ -2,10 +2,10 @@ * @file efm32wg380f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG380F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG380F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f64.h index 68da0d1003..6efff59de9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg380f64.h @@ -2,10 +2,10 @@ * @file efm32wg380f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG380F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG380F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f128.h index d89f2f6ec0..7ee4456310 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f128.h @@ -2,10 +2,10 @@ * @file efm32wg390f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG390F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG390F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f256.h index 67aad0ff1c..aa6c7c1e03 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f256.h @@ -2,10 +2,10 @@ * @file efm32wg390f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG390F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG390F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f64.h index f8e7b0fca9..3989b6f64c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg390f64.h @@ -2,10 +2,10 @@ * @file efm32wg390f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG390F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG390F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f128.h index 867e8ae8d3..20d485d893 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f128.h @@ -2,10 +2,10 @@ * @file efm32wg395f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG395F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG395F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f256.h index 5648a0db21..b5d1114f42 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f256.h @@ -2,10 +2,10 @@ * @file efm32wg395f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG395F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG395F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f64.h index b8b0abdeb4..630b51d93c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg395f64.h @@ -2,10 +2,10 @@ * @file efm32wg395f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG395F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG395F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f128.h index 019ad14057..cd8e5e496b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f128.h @@ -2,10 +2,10 @@ * @file efm32wg840f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG840F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG840F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f256.h index 24aed469c9..e4dbf2ce31 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f256.h @@ -2,10 +2,10 @@ * @file efm32wg840f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG840F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG840F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f64.h index 17c2291849..6a81de12ea 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg840f64.h @@ -2,10 +2,10 @@ * @file efm32wg840f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG840F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG840F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f128.h index b163f7f9d6..87475c53a4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f128.h @@ -2,10 +2,10 @@ * @file efm32wg842f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG842F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG842F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f256.h index 9d0417627e..c56e34dd5a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f256.h @@ -2,10 +2,10 @@ * @file efm32wg842f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG842F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG842F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f64.h index f34de7a25e..49bdecf572 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg842f64.h @@ -2,10 +2,10 @@ * @file efm32wg842f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG842F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,12 +118,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG842F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f128.h index 159f19015b..fdfc859234 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f128.h @@ -2,10 +2,10 @@ * @file efm32wg880f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG880F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG880F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f256.h index 10ac7b01db..fc620b6ef9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f256.h @@ -2,10 +2,10 @@ * @file efm32wg880f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG880F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG880F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f64.h index 8a2878ef6e..e0ecc5ee21 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg880f64.h @@ -2,10 +2,10 @@ * @file efm32wg880f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG880F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG880F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f128.h index 0634138239..2d781eec47 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f128.h @@ -2,10 +2,10 @@ * @file efm32wg890f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG890F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG890F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f256.h index e5bc463845..c65150bff0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f256.h @@ -2,10 +2,10 @@ * @file efm32wg890f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG890F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG890F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f64.h index f6af8b8755..1c1770ce43 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg890f64.h @@ -2,10 +2,10 @@ * @file efm32wg890f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG890F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG890F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h index 324ba3e082..68c961e735 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f128.h @@ -2,10 +2,10 @@ * @file efm32wg895f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG895F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG895F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f256.h index e91cea86b6..e17248c46d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f256.h @@ -2,10 +2,10 @@ * @file efm32wg895f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG895F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG895F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f64.h index 020ec7da09..3efb6fd41b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg895f64.h @@ -2,10 +2,10 @@ * @file efm32wg895f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG895F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -123,12 +123,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG895F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h index 82b495307c..340d1fd377 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h @@ -2,10 +2,10 @@ * @file efm32wg900f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG900F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG900F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f128.h index 3a7b901c44..3624116323 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f128.h @@ -2,10 +2,10 @@ * @file efm32wg940f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG940F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG940F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f256.h index f9ff3ddf92..951ef33cbe 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f256.h @@ -2,10 +2,10 @@ * @file efm32wg940f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG940F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG940F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f64.h index 4dfff0e49f..3717854856 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg940f64.h @@ -2,10 +2,10 @@ * @file efm32wg940f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG940F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG940F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f128.h index 837a50f2c2..1afa6e13aa 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f128.h @@ -2,10 +2,10 @@ * @file efm32wg942f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG942F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG942F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f256.h index 2b5d115998..28ed3e2517 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f256.h @@ -2,10 +2,10 @@ * @file efm32wg942f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG942F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG942F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f64.h index 0132cc50b4..f2e13852a1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg942f64.h @@ -2,10 +2,10 @@ * @file efm32wg942f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG942F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -119,12 +119,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG942F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f128.h index 6af43c4466..cea633d452 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f128.h @@ -2,10 +2,10 @@ * @file efm32wg980f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG980F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG980F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f256.h index 4395cd683a..529f951d8a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f256.h @@ -2,10 +2,10 @@ * @file efm32wg980f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG980F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG980F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f64.h index b2c2faa03b..2608a1acd9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg980f64.h @@ -2,10 +2,10 @@ * @file efm32wg980f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG980F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG980F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f128.h index fdbe31b88c..d60f6b3a89 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f128.h @@ -2,10 +2,10 @@ * @file efm32wg990f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG990F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG990F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f256.h index 354fe249f6..8a971fb732 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f256.h @@ -2,10 +2,10 @@ * @file efm32wg990f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG990F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG990F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f64.h index 341601ee6a..416d4e710e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg990f64.h @@ -2,10 +2,10 @@ * @file efm32wg990f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG990F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG990F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f128.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f128.h index e7ce6e5dea..3863fe588e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f128.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f128.h @@ -2,10 +2,10 @@ * @file efm32wg995f128.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG995F128 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG995F128) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h index b192d642f1..e2575f7572 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f256.h @@ -2,10 +2,10 @@ * @file efm32wg995f256.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG995F256 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG995F256) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f64.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f64.h index 5d26fd8890..571bf4327d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f64.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg995f64.h @@ -2,10 +2,10 @@ * @file efm32wg995f64.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32WG995F64 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -124,12 +124,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32WG995F64) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h index a3b459a50e..ae1cc299d7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_acmp.h * @brief EFM32WG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_adc.h index 8875dc9cef..81229269a9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_adc.h * @brief EFM32WG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h index 02cdd806cd..186552f044 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_aes.h * @brief EFM32WG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_pins.h index 18a7dd9948..21c06b9d9d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_af_pins.h * @brief EFM32WG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_ports.h index dcf8cb68db..6b02f8bd41 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_af_ports.h * @brief EFM32WG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h index 9f6ca5a754..2028591cee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_burtc.h * @brief EFM32WG_BURTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc_ret.h index 82d73dfaff..d1dc9e7fe1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_burtc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_burtc_ret.h * @brief EFM32WG_BURTC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_calibrate.h index 2c27f37a79..5670ec155c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_calibrate.h * @brief EFM32WG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h index 7af287d0f5..a03cc49ccb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_cmu.h * @brief EFM32WG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h index af7a596bb6..51dce4e00f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dac.h * @brief EFM32WG_DAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h index 4aecac5ff9..3820271f32 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_devinfo.h * @brief EFM32WG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h index d93e5715a4..e245d78816 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dma.h * @brief EFM32WG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_ch.h index bcbd316108..a313dd2462 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dma_ch.h * @brief EFM32WG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_descriptor.h index 90ed75eede..ade4f8ae41 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dma_descriptor.h * @brief EFM32WG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h index 195a1791d7..099729f164 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dmactrl.h * @brief EFM32WG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h index 0edd04116e..584b133f62 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_dmareq.h * @brief EFM32WG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h index 2bf86080c1..02593572a0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_ebi.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_ebi.h * @brief EFM32WG_EBI register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_emu.h index a23a23610a..2050be183e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_emu.h * @brief EFM32WG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h index 8cd95dba3c..8b89d7edfd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_etm.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_etm.h * @brief EFM32WG_ETM register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_fpueh.h index 5def789081..38c583aca8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_fpueh.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_fpueh.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_fpueh.h * @brief EFM32WG_FPUEH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h index e0c72b5054..355eb50669 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_gpio.h * @brief EFM32WG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio_p.h index 8558d7780c..fd0584c9ff 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_gpio_p.h * @brief EFM32WG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h index b9753c1a77..f71303db9d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_i2c.h * @brief EFM32WG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lcd.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lcd.h index 244bdd75db..2dbbc6671a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lcd.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lcd.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lcd.h * @brief EFM32WG_LCD register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense.h index 7ae1ee14d4..52a4d951ed 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lesense.h * @brief EFM32WG_LESENSE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_buf.h index 7d1a1396b8..7a417b85e2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_buf.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_buf.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lesense_buf.h * @brief EFM32WG_LESENSE_BUF register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_ch.h index d40bdcbdac..d4d5fedb29 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lesense_ch.h * @brief EFM32WG_LESENSE_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_st.h index 49bad15ff9..1f93581997 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_st.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_lesense_st.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_lesense_st.h * @brief EFM32WG_LESENSE_ST register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_letimer.h index 3ee19798b8..f2278f73af 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_letimer.h * @brief EFM32WG_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h index 84a3a427c4..495e526bd7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_leuart.h * @brief EFM32WG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h index 8acd0d1271..88035ccfa2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_msc.h * @brief EFM32WG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_pcnt.h index 2223f33220..39ce9aecc5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_pcnt.h * @brief EFM32WG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs.h index 8184e1fc04..6f018b1c02 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_prs.h * @brief EFM32WG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_ch.h index b485925479..99b29a903a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_prs_ch.h * @brief EFM32WG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_signals.h index 3f8ed15eb2..dfb5366f84 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_prs_signals.h * @brief EFM32WG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h index e0cebb4c78..66bb4466b3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_rmu.h * @brief EFM32WG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_romtable.h index 91abd7da6c..47fc2933b1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_romtable.h * @brief EFM32WG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h index 2c0191ac6a..f989024a98 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_rtc.h * @brief EFM32WG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer.h index b357695ff3..0f0cc4c661 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_timer.h * @brief EFM32WG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer_cc.h index 99b285e76c..8f2168cd21 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_timer_cc.h * @brief EFM32WG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_uart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_uart.h index 4e894672c3..815b0cb9a6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_uart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_uart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_uart.h * @brief EFM32WG_UART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usart.h index 1313c3711c..5b93bc2673 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usart.h * @brief EFM32WG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h index 8a14d12068..4148095739 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usb.h * @brief EFM32WG_USB register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_diep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_diep.h index 12fe618100..e7f802a776 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_diep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_diep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usb_diep.h * @brief EFM32WG_USB_DIEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_doep.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_doep.h index 68102871d6..0edea23f83 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_doep.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_doep.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usb_doep.h * @brief EFM32WG_USB_DOEP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_hc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_hc.h index 20e4f4ec3f..963e508e95 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_hc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_usb_hc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_usb_hc.h * @brief EFM32WG_USB_HC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h index 8bd3b0194b..d586a3d375 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_vcmp.h * @brief EFM32WG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h index 085565cec7..8a01da8b1e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32wg_wdog.h * @brief EFM32WG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/em_device.h index a184b2646f..965748a13e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.c index 4b45b092df..4627ecbade 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32wg.c * @brief CMSIS Cortex-M4 System Layer for EFM32WG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.h index 34015257af..41c8fbbc4f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/system_efm32wg.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32wg.h * @brief CMSIS Cortex-M4 System Layer for EFM32WG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f16.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f16.h index 3829f8d074..580a81c44e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f16.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f16.h @@ -2,10 +2,10 @@ * @file efm32zg108f16.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG108F16 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -94,12 +94,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG108F16) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f32.h index 6283ebf277..dab5568a15 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f32.h @@ -2,10 +2,10 @@ * @file efm32zg108f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG108F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -94,12 +94,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG108F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f4.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f4.h index 2951705ff2..31ab90ca39 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f4.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f4.h @@ -2,10 +2,10 @@ * @file efm32zg108f4.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG108F4 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -94,12 +94,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG108F4) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f8.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f8.h index 84030149a3..d37603e5c3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f8.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg108f8.h @@ -2,10 +2,10 @@ * @file efm32zg108f8.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG108F8 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -94,12 +94,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG108F8) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f16.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f16.h index 38dad00217..9c87f961e5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f16.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f16.h @@ -2,10 +2,10 @@ * @file efm32zg110f16.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG110F16 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG110F16) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f32.h index 3736eed7bf..cd9d660df0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f32.h @@ -2,10 +2,10 @@ * @file efm32zg110f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG110F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG110F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f4.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f4.h index 476c389596..d90d7ac3c6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f4.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f4.h @@ -2,10 +2,10 @@ * @file efm32zg110f4.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG110F4 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG110F4) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h index 4b3a4cde9f..492d06c833 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h @@ -2,10 +2,10 @@ * @file efm32zg110f8.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG110F8 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG110F8) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f16.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f16.h index 3e0237714b..822e1ece9f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f16.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f16.h @@ -2,10 +2,10 @@ * @file efm32zg210f16.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG210F16 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG210F16) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f32.h index 2a420b4e20..68dbb27eda 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f32.h @@ -2,10 +2,10 @@ * @file efm32zg210f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG210F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG210F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f4.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f4.h index 9a50658154..8115f49fdf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f4.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f4.h @@ -2,10 +2,10 @@ * @file efm32zg210f4.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG210F4 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG210F4) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f8.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f8.h index fef237144d..9182c1c146 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f8.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg210f8.h @@ -2,10 +2,10 @@ * @file efm32zg210f8.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG210F8 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG210F8) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h index 75f522208e..3c0cc3c1d8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f16.h @@ -2,10 +2,10 @@ * @file efm32zg222f16.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG222F16 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG222F16) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f32.h index 4d75f60666..e607945988 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f32.h @@ -2,10 +2,10 @@ * @file efm32zg222f32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG222F32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG222F32) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f4.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f4.h index be3d9bab0a..b22d8a9f85 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f4.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f4.h @@ -2,10 +2,10 @@ * @file efm32zg222f4.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG222F4 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG222F4) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f8.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f8.h index d72c224e0a..4e59bd9430 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f8.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg222f8.h @@ -2,10 +2,10 @@ * @file efm32zg222f8.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32ZG222F8 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -96,12 +96,14 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ -#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ -#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */ +#define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_76 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ /* If part number is not defined as compiler option, define it */ #if !defined(EFM32ZG222F8) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_acmp.h index 7337825864..130c10e18e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_acmp.h * @brief EFM32ZG_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_adc.h index c2a9c53edf..2d45bba276 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_adc.h * @brief EFM32ZG_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_aes.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_aes.h index cd662796db..0fc304b7dc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_aes.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_aes.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_aes.h * @brief EFM32ZG_AES register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_pins.h index c4571cf5d0..cd7c37faf9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_af_pins.h * @brief EFM32ZG_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_ports.h index 774f68aa08..2b3e703d00 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_af_ports.h * @brief EFM32ZG_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_calibrate.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_calibrate.h index db294aafaf..c0c5cb6db0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_calibrate.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_calibrate.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_calibrate.h * @brief EFM32ZG_CALIBRATE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_cmu.h index ab9d92d8bf..4395a1ee59 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_cmu.h * @brief EFM32ZG_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_devinfo.h index 774a089e02..9b5a9365a6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_devinfo.h * @brief EFM32ZG_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h index ff51291810..5e2b025baf 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dma.h * @brief EFM32ZG_DMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_ch.h index 1aa6884cad..abdbe970ab 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dma_ch.h * @brief EFM32ZG_DMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_descriptor.h index 6aa61a9e28..83df2b3748 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dma_descriptor.h * @brief EFM32ZG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmactrl.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmactrl.h index 9b7bd09654..b1c665deb6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmactrl.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmactrl.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dmactrl.h * @brief EFM32ZG_DMACTRL register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmareq.h index 5944eaedac..4164c99a80 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_dmareq.h * @brief EFM32ZG_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_emu.h index a27f2d4709..44a06ad859 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_emu.h * @brief EFM32ZG_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio.h index 2ba1d940a6..40e7cb4262 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_gpio.h * @brief EFM32ZG_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio_p.h index 8614268bbe..939d676c12 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_gpio_p.h * @brief EFM32ZG_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_i2c.h index 6b296faf73..e4e9720815 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_i2c.h * @brief EFM32ZG_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_idac.h index 8b5d1c966a..3ac8310a3d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_idac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_idac.h * @brief EFM32ZG_IDAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_leuart.h index e50846090c..252771833f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_leuart.h * @brief EFM32ZG_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_msc.h index 98f731b416..21ec685a7a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_msc.h * @brief EFM32ZG_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_pcnt.h index d90e4cbfb9..ac9f7cae2a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_pcnt.h * @brief EFM32ZG_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs.h index bf6ad5681b..719d1d9919 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_prs.h * @brief EFM32ZG_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_ch.h index 394d6c0e52..d647366514 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_prs_ch.h * @brief EFM32ZG_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_signals.h index 11cf956add..4da5fb01e4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_prs_signals.h * @brief EFM32ZG_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rmu.h index 5c5067d909..ee0b42606f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_rmu.h * @brief EFM32ZG_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_romtable.h index 3889b89e4d..a2bd59691c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_romtable.h * @brief EFM32ZG_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rtc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rtc.h index 39891b2828..b416e788f1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rtc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_rtc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_rtc.h * @brief EFM32ZG_RTC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer.h index abeb4b0d5c..f8deabf05e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_timer.h * @brief EFM32ZG_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer_cc.h index 349a3e8f37..fcba4a9e44 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_timer_cc.h * @brief EFM32ZG_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_usart.h index a381d739ac..4822e8ac6d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_usart.h * @brief EFM32ZG_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_vcmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_vcmp.h index e6b1024183..49422aa893 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_vcmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_vcmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_vcmp.h * @brief EFM32ZG_VCMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_wdog.h index 2dccc0f091..64dc1ce2dd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efm32zg_wdog.h * @brief EFM32ZG_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/em_device.h index a169e283f1..324adc04d0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.c index 448c19d31b..c8f986bbc1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efm32zg.c * @brief CMSIS Cortex-M0+ System Layer for EFM32ZG devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.h index 113a9d8ff5..8a04a2638b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/system_efm32zg.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file system_efm32zg.h * @brief CMSIS Cortex-M System Layer for EFM32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p131f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p131f256gm48.h index fbeb567812..b45160a7a5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p131f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p131f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p131f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P131F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P131F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h index bb1ebb1e28..91f10a5241 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gj43.h @@ -2,10 +2,10 @@ * @file efr32mg1p132f256gj43.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256GJ43 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P132F256GJ43) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm32.h index a54e869854..6a70ce0639 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm32.h @@ -2,10 +2,10 @@ * @file efr32mg1p132f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P132F256GM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h index f555d25c1f..59ce0ef086 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p132f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P132F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256im32.h index 79ef333565..1198f133fb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256im32.h @@ -2,10 +2,10 @@ * @file efr32mg1p132f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P132F256IM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p133f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p133f256gm48.h index 9dc9e77e70..db738dc4e5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p133f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p133f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p133f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P133F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P133F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p231f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p231f256gm48.h index ec17e34369..99508169f8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p231f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p231f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p231f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P231F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P231F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gj43.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gj43.h index a980bde03c..2042c75201 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gj43.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gj43.h @@ -2,10 +2,10 @@ * @file efr32mg1p232f256gj43.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P232F256GJ43 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P232F256GJ43) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm32.h index 97ae7baee2..4f1c91ae6c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm32.h @@ -2,10 +2,10 @@ * @file efr32mg1p232f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P232F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P232F256GM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h index d3d0349f72..84dc741754 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p232f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p232f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P232F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P232F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p233f256gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p233f256gm48.h index efda4690cd..ced9ab1ab4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p233f256gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p233f256gm48.h @@ -2,10 +2,10 @@ * @file efr32mg1p233f256gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P233F256GM48 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P233F256GM48) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256gm32.h index d7cff49a0f..d6acd3c29e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256gm32.h @@ -2,10 +2,10 @@ * @file efr32mg1p632f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P632F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P632F256GM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256im32.h index c15b3a3cb8..0153e592f4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p632f256im32.h @@ -2,10 +2,10 @@ * @file efr32mg1p632f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P632F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P632F256IM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256gm32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256gm32.h index bdb163d884..3e6d47a142 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256gm32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256gm32.h @@ -2,10 +2,10 @@ * @file efr32mg1p732f256gm32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P732F256GM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P732F256GM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256im32.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256im32.h index ae2df0c68e..088e6e01dc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256im32.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p732f256im32.h @@ -2,10 +2,10 @@ * @file efr32mg1p732f256im32.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P732F256IM32 - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -109,16 +109,22 @@ typedef enum IRQn ******************************************************************************/ /** Part family */ -#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ -#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ -#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ -#define _SILICON_LABS_32B_PLATFORM_2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM 2 /**< Silicon Labs platform name */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< Platform 2, generation 1 */ -#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< Platform 2, generation 1 */ +#define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ +#define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ /* If part number is not defined as compiler option, define it */ #if !defined(EFR32MG1P732F256IM32) @@ -132,39 +138,39 @@ typedef enum IRQn #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x15UL) /**< RAM_CODE used bits */ +#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITCLR used bits */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO used bits */ +#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x10UL) /**< CRYPTO_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x20UL) /**< PER_BITSET used bits */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */ +#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_acmp.h index c0f3cfa414..140119c6ac 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_acmp.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_acmp.h * @brief EFR32MG1P_ACMP register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -329,8 +329,6 @@ typedef struct #define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ @@ -497,8 +495,6 @@ typedef struct #define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ @@ -667,8 +663,6 @@ typedef struct #define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ -#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ #define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ @@ -835,8 +829,6 @@ typedef struct #define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ #define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_adc.h index 5bc32c55c3..05a8d4f88f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_adc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_adc.h * @brief EFR32MG1P_ADC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_pins.h index a82b2d4a27..ea097badc0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_pins.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_af_pins.h * @brief EFR32MG1P_AF_PINS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_ports.h index c7b3bc3768..eb85d8e5d5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_af_ports.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_af_ports.h * @brief EFR32MG1P_AF_PORTS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h index 22185e0240..7f00e1de50 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_cmu.h * @brief EFR32MG1P_CMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -56,8 +56,9 @@ typedef struct __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + __IOM uint32_t ULFRCOCTRL; /**< ULFRCO Control Register */ - uint32_t RESERVED3[5]; /**< Reserved for future use **/ + uint32_t RESERVED3[4]; /**< Reserved for future use **/ __IOM uint32_t CALCTRL; /**< Calibration Control Register */ __IOM uint32_t CALCNT; /**< Calibration Counter Register */ uint32_t RESERVED4[2]; /**< Reserved for future use **/ @@ -637,6 +638,30 @@ typedef struct #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ +/* Bit fields for CMU ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_RESETVALUE 0x00020020UL /**< Default value for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MASK 0x00030C3FUL /**< Mask for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_ULFRCOCTRL_TUNING_MASK 0x3FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_ULFRCOCTRL_TUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_TUNING_DEFAULT (_CMU_ULFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_SHIFT 10 /**< Shift value for CMU_MODE */ +#define _CMU_ULFRCOCTRL_MODE_MASK 0xC00UL /**< Bit mask for CMU_MODE */ +#define _CMU_ULFRCOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_1KHZ 0x00000000UL /**< Mode 1KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_2KHZ 0x00000001UL /**< Mode 2KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_4KHZ 0x00000002UL /**< Mode 4KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_MODE_32KHZ 0x00000003UL /**< Mode 32KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_DEFAULT (_CMU_ULFRCOCTRL_MODE_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_1KHZ (_CMU_ULFRCOCTRL_MODE_1KHZ << 10) /**< Shifted mode 1KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_2KHZ (_CMU_ULFRCOCTRL_MODE_2KHZ << 10) /**< Shifted mode 2KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_4KHZ (_CMU_ULFRCOCTRL_MODE_4KHZ << 10) /**< Shifted mode 4KHZ for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_MODE_32KHZ (_CMU_ULFRCOCTRL_MODE_32KHZ << 10) /**< Shifted mode 32KHZ for CMU_ULFRCOCTRL */ +#define _CMU_ULFRCOCTRL_RESTRIM_SHIFT 16 /**< Shift value for CMU_RESTRIM */ +#define _CMU_ULFRCOCTRL_RESTRIM_MASK 0x30000UL /**< Bit mask for CMU_RESTRIM */ +#define _CMU_ULFRCOCTRL_RESTRIM_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_ULFRCOCTRL */ +#define CMU_ULFRCOCTRL_RESTRIM_DEFAULT (_CMU_ULFRCOCTRL_RESTRIM_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ULFRCOCTRL */ + /* Bit fields for CMU CALCTRL */ #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ #define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ @@ -902,7 +927,7 @@ typedef struct /* Bit fields for CMU STATUS */ #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ -#define _CMU_STATUS_MASK 0x07C103FFUL /**< Mask for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x07E103FFUL /**< Mask for CMU_STATUS */ #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ @@ -958,6 +983,11 @@ typedef struct #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */ +#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cryotimer.h index 9ca92fe478..2ac2c09254 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cryotimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_cryotimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_cryotimer.h * @brief EFR32MG1P_CRYOTIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_crypto.h index 3751bc35a1..f45bca536b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_crypto.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_crypto.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_crypto.h * @brief EFR32MG1P_CRYPTO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -843,7 +843,7 @@ typedef struct /* Bit fields for CRYPTO IFS */ #define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ -#define _CRYPTO_IFS_MASK 0x0000000FUL /**< Mask for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ #define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ #define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -854,20 +854,10 @@ typedef struct #define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ #define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFOF (0x1UL << 2) /**< Set BUFOF Interrupt Flag */ -#define _CRYPTO_IFS_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IFS_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFOF_DEFAULT (_CRYPTO_IFS_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFUF (0x1UL << 3) /**< Set BUFUF Interrupt Flag */ -#define _CRYPTO_IFS_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IFS_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IFS_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ -#define CRYPTO_IFS_BUFUF_DEFAULT (_CRYPTO_IFS_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFS */ /* Bit fields for CRYPTO IFC */ #define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ -#define _CRYPTO_IFC_MASK 0x0000000FUL /**< Mask for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ #define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ #define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -878,20 +868,10 @@ typedef struct #define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ #define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFOF (0x1UL << 2) /**< Clear BUFOF Interrupt Flag */ -#define _CRYPTO_IFC_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IFC_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFOF_DEFAULT (_CRYPTO_IFC_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFUF (0x1UL << 3) /**< Clear BUFUF Interrupt Flag */ -#define _CRYPTO_IFC_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IFC_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IFC_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ -#define CRYPTO_IFC_BUFUF_DEFAULT (_CRYPTO_IFC_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IFC */ /* Bit fields for CRYPTO IEN */ #define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ -#define _CRYPTO_IEN_MASK 0x0000000FUL /**< Mask for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ #define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ #define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ #define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ @@ -902,16 +882,6 @@ typedef struct #define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ #define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ #define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFOF (0x1UL << 2) /**< BUFOF Interrupt Enable */ -#define _CRYPTO_IEN_BUFOF_SHIFT 2 /**< Shift value for CRYPTO_BUFOF */ -#define _CRYPTO_IEN_BUFOF_MASK 0x4UL /**< Bit mask for CRYPTO_BUFOF */ -#define _CRYPTO_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFOF_DEFAULT (_CRYPTO_IEN_BUFOF_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFUF (0x1UL << 3) /**< BUFUF Interrupt Enable */ -#define _CRYPTO_IEN_BUFUF_SHIFT 3 /**< Shift value for CRYPTO_BUFUF */ -#define _CRYPTO_IEN_BUFUF_MASK 0x8UL /**< Bit mask for CRYPTO_BUFUF */ -#define _CRYPTO_IEN_BUFUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ -#define CRYPTO_IEN_BUFUF_DEFAULT (_CRYPTO_IEN_BUFUF_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTO_IEN */ /* Bit fields for CRYPTO SEQ0 */ #define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h index 228a38ee4f..2100aa4461 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_devinfo.h * @brief EFR32MG1P_DEVINFO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -118,8 +118,10 @@ typedef struct #define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */ #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dma_descriptor.h index cd1750ba53..c890c388dc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dma_descriptor.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_dma_descriptor.h * @brief EFR32MG1P_DMA_DESCRIPTOR register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h index ade9e67281..8cbbfbba45 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_dmareq.h * @brief EFR32MG1P_DMAREQ register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h index c02c75f48d..c6b30b1f5b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_emu.h * @brief EFR32MG1P_EMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -63,24 +63,32 @@ typedef struct __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ - - uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ __IOM uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */ __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ - uint32_t RESERVED3[1]; /**< Reserved for future use **/ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ - uint32_t RESERVED4[1]; /**< Reserved for future use **/ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ - uint32_t RESERVED5[5]; /**< Reserved for future use **/ + uint32_t RESERVED4[5]; /**< Reserved for future use **/ __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + + uint32_t RESERVED5[49]; /**< Reserved for future use **/ + __IOM uint32_t BIASCONF; /**< Configurations Related to the Bias */ + + uint32_t RESERVED6[10]; /**< Reserved for future use **/ + __IOM uint32_t TESTLOCK; /**< Test Lock Register */ + + uint32_t RESERVED7[2]; /**< Reserved for future use **/ + __IOM uint32_t BIASTESTCTRL; /**< Test Control Register for regulator and BIAS */ } EMU_TypeDef; /** @} */ /**************************************************************************//** @@ -351,7 +359,7 @@ typedef struct /* Bit fields for EMU IFS */ #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ -#define _EMU_IFS_MASK 0xE11FF0FFUL /**< Mask for EMU_IFS */ +#define _EMU_IFS_MASK 0xE11FC0FFUL /**< Mask for EMU_IFS */ #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -392,16 +400,6 @@ typedef struct #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDFALL (0x1UL << 12) /**< Set VMONPAVDDFALL Interrupt Flag */ -#define _EMU_IFS_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IFS_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IFS_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDFALL_DEFAULT (_EMU_IFS_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDRISE (0x1UL << 13) /**< Set VMONPAVDDRISE Interrupt Flag */ -#define _EMU_IFS_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IFS_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IFS_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ -#define EMU_IFS_VMONPAVDDRISE_DEFAULT (_EMU_IFS_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -460,7 +458,7 @@ typedef struct /* Bit fields for EMU IFC */ #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ -#define _EMU_IFC_MASK 0xE11FF0FFUL /**< Mask for EMU_IFC */ +#define _EMU_IFC_MASK 0xE11FC0FFUL /**< Mask for EMU_IFC */ #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -501,16 +499,6 @@ typedef struct #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDFALL (0x1UL << 12) /**< Clear VMONPAVDDFALL Interrupt Flag */ -#define _EMU_IFC_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IFC_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IFC_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDFALL_DEFAULT (_EMU_IFC_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDRISE (0x1UL << 13) /**< Clear VMONPAVDDRISE Interrupt Flag */ -#define _EMU_IFC_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IFC_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IFC_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ -#define EMU_IFC_VMONPAVDDRISE_DEFAULT (_EMU_IFC_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -569,7 +557,7 @@ typedef struct /* Bit fields for EMU IEN */ #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ -#define _EMU_IEN_MASK 0xE11FF0FFUL /**< Mask for EMU_IEN */ +#define _EMU_IEN_MASK 0xE11FC0FFUL /**< Mask for EMU_IEN */ #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ @@ -610,16 +598,6 @@ typedef struct #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDFALL (0x1UL << 12) /**< VMONPAVDDFALL Interrupt Enable */ -#define _EMU_IEN_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ -#define _EMU_IEN_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ -#define _EMU_IEN_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDFALL_DEFAULT (_EMU_IEN_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDRISE (0x1UL << 13) /**< VMONPAVDDRISE Interrupt Enable */ -#define _EMU_IEN_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ -#define _EMU_IEN_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ -#define _EMU_IEN_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VMONPAVDDRISE_DEFAULT (_EMU_IEN_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ @@ -817,6 +795,34 @@ typedef struct #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + /* Bit fields for EMU DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ @@ -1035,6 +1041,65 @@ typedef struct #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +/* Bit fields for EMU BIASCONF */ +#define _EMU_BIASCONF_RESETVALUE 0x000000F8UL /**< Default value for EMU_BIASCONF */ +#define _EMU_BIASCONF_MASK 0x000000FCUL /**< Mask for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM01 (0x1UL << 2) /**< NA DUTY in EM01 */ +#define _EMU_BIASCONF_NADUTYEM01_SHIFT 2 /**< Shift value for EMU_NADUTYEM01 */ +#define _EMU_BIASCONF_NADUTYEM01_MASK 0x4UL /**< Bit mask for EMU_NADUTYEM01 */ +#define _EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM01_DEFAULT (_EMU_BIASCONF_NADUTYEM01_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM01 (0x1UL << 3) /**< LP in EM01 */ +#define _EMU_BIASCONF_LPEM01_SHIFT 3 /**< Shift value for EMU_LPEM01 */ +#define _EMU_BIASCONF_LPEM01_MASK 0x8UL /**< Bit mask for EMU_LPEM01 */ +#define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM01_DEFAULT (_EMU_BIASCONF_LPEM01_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_GMCEM23 (0x1UL << 4) /**< GMC in EM234 */ +#define _EMU_BIASCONF_GMCEM23_SHIFT 4 /**< Shift value for EMU_GMCEM23 */ +#define _EMU_BIASCONF_GMCEM23_MASK 0x10UL /**< Bit mask for EMU_GMCEM23 */ +#define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_GMCEM23_DEFAULT (_EMU_BIASCONF_GMCEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_UADUTYEM23 (0x1UL << 5) /**< UADUTY in EM234 */ +#define _EMU_BIASCONF_UADUTYEM23_SHIFT 5 /**< Shift value for EMU_UADUTYEM23 */ +#define _EMU_BIASCONF_UADUTYEM23_MASK 0x20UL /**< Bit mask for EMU_UADUTYEM23 */ +#define _EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_UADUTYEM23_DEFAULT (_EMU_BIASCONF_UADUTYEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM23 (0x1UL << 6) /**< NA DUTY in EM234 */ +#define _EMU_BIASCONF_NADUTYEM23_SHIFT 6 /**< Shift value for EMU_NADUTYEM23 */ +#define _EMU_BIASCONF_NADUTYEM23_MASK 0x40UL /**< Bit mask for EMU_NADUTYEM23 */ +#define _EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_NADUTYEM23_DEFAULT (_EMU_BIASCONF_NADUTYEM23_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM23 (0x1UL << 7) /**< LP in EM234 */ +#define _EMU_BIASCONF_LPEM23_SHIFT 7 /**< Shift value for EMU_LPEM23 */ +#define _EMU_BIASCONF_LPEM23_MASK 0x80UL /**< Bit mask for EMU_LPEM23 */ +#define _EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */ +#define EMU_BIASCONF_LPEM23_DEFAULT (_EMU_BIASCONF_LPEM23_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_BIASCONF */ + +/* Bit fields for EMU TESTLOCK */ +#define _EMU_TESTLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */ +#define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */ +#define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */ + +/* Bit fields for EMU BIASTESTCTRL */ +#define _EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BIASTESTCTRL */ +#define _EMU_BIASTESTCTRL_MASK 0x00000008UL /**< Mask for EMU_BIASTESTCTRL */ +#define EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3) /**< Reset Bias Ripple Counter */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3 /**< Shift value for EMU_BIAS_RIP_RESET */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL /**< Bit mask for EMU_BIAS_RIP_RESET */ +#define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASTESTCTRL */ +#define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASTESTCTRL */ + /** @} End of group EFR32MG1P_EMU */ /** @} End of group Parts */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h index d684c508bc..ff839cdc74 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_fpueh.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_fpueh.h * @brief EFR32MG1P_FPUEH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h index 0c32728539..16b567fe47 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpcrc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_gpcrc.h * @brief EFR32MG1P_GPCRC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio.h index 883f647310..8311aa84a9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_gpio.h * @brief EFR32MG1P_GPIO register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h index 37a502a013..93d08be621 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_gpio_p.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_gpio_p.h * @brief EFR32MG1P_GPIO_P register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h index 64544eede8..b3709a685e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_i2c.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_i2c.h * @brief EFR32MG1P_I2C register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h index 9fe0848cef..8e6e49e99f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_idac.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_idac.h * @brief EFR32MG1P_IDAC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -43,7 +43,7 @@ typedef struct __IOM uint32_t CTRL; /**< Control Register */ __IOM uint32_t CURPROG; /**< Current Programming Register */ uint32_t RESERVED0[1]; /**< Reserved for future use **/ - __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configauration Register */ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ uint32_t RESERVED1[2]; /**< Reserved for future use **/ __IM uint32_t STATUS; /**< Status Register */ @@ -259,12 +259,7 @@ typedef struct /* Bit fields for IDAC IFS */ #define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ -#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ -#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ -#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ -#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000002UL /**< Mask for IDAC_IFS */ #define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ #define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ @@ -273,12 +268,7 @@ typedef struct /* Bit fields for IDAC IFC */ #define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ -#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ -#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ -#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ -#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000002UL /**< Mask for IDAC_IFC */ #define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ #define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ @@ -287,12 +277,7 @@ typedef struct /* Bit fields for IDAC IEN */ #define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ -#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ -#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ -#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ -#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ -#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ -#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000002UL /**< Mask for IDAC_IEN */ #define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ #define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ #define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h index 053b062738..8c9a3a21b0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_ldma.h * @brief EFR32MG1P_LDMA register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma_ch.h index 607a8e9f7d..1153f0bb66 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_ldma_ch.h * @brief EFR32MG1P_LDMA_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_letimer.h index 29388ceca7..a411122501 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_letimer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_letimer.h * @brief EFR32MG1P_LETIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_leuart.h index 8cc320cf8c..b47c546f1a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_leuart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_leuart.h * @brief EFR32MG1P_LEUART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h index 10b477aa7a..39503771f6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_msc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_msc.h * @brief EFR32MG1P_MSC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_pcnt.h index 738e0943a3..cb803866c9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_pcnt.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_pcnt.h * @brief EFR32MG1P_PCNT register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs.h index 89891796ee..8d338b1b2a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_prs.h * @brief EFR32MG1P_PRS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -756,6 +756,7 @@ typedef struct #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ @@ -821,6 +822,7 @@ typedef struct #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ @@ -891,6 +893,7 @@ typedef struct #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000003CUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ #define _PRS_CH_CTRL_SOURCESEL_CMU 0x0000003DUL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ @@ -908,6 +911,7 @@ typedef struct #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h index 3239628cdb..2916bec5f2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_ch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_prs_ch.h * @brief EFR32MG1P_PRS_CH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_signals.h index ce02dfe5aa..d9ab908d29 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_prs_signals.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_prs_signals.h * @brief EFR32MG1P_PRS_SIGNALS register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -103,6 +103,7 @@ #define PRS_CRYOTIMER_PERIOD ((60 << 8) + 0) /**< PRS CRYOTIMER Output */ #define PRS_CMU_CLKOUT0 ((61 << 8) + 0) /**< PRS Clock Output 0 */ #define PRS_CMU_CLKOUT1 ((61 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ /** @} End of group EFR32MG1P_PRS */ /** @} End of group Parts */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rmu.h index 4392cb0c2e..2b5189d5cc 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rmu.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_rmu.h * @brief EFR32MG1P_RMU register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_romtable.h index cc6596032c..41b6623ed5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_romtable.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_romtable.h * @brief EFR32MG1P_ROMTABLE register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h index 3d6098ac84..f33f3becd6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_rtcc.h * @brief EFR32MG1P_RTCC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_cc.h index 4f5770110d..b29f210b14 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_rtcc_cc.h * @brief EFR32MG1P_RTCC_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_ret.h index 00e48da5ed..f91263f96c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc_ret.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_rtcc_ret.h * @brief EFR32MG1P_RTCC_RET register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer.h index b58d22588c..3711bedaa7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_timer.h * @brief EFR32MG1P_TIMER register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -188,7 +188,7 @@ typedef struct #define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ #define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ #define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Ouptut initial State */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ #define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ #define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer_cc.h index 2122f93c21..5b5b5a1835 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_timer_cc.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_timer_cc.h * @brief EFR32MG1P_TIMER_CC register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h index 60a3511217..6992e70406 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_usart.h * @brief EFR32MG1P_USART register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h index 27200c1f9d..a1402e7cc9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_wdog.h * @brief EFR32MG1P_WDOG register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, @@ -215,17 +215,17 @@ typedef struct /* Bit fields for WDOG IF */ #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ -#define WDOG_IF_TOUT (0x1UL << 0) /**< Wdog Timeout Interrupt Flag */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN (0x1UL << 1) /**< Wdog Warning Timeout Interrupt Flag */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN (0x1UL << 2) /**< Wdog Window Interrupt Flag */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog_pch.h index 31a087d2fc..5864e5e971 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog_pch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_wdog_pch.h @@ -1,10 +1,10 @@ /**************************************************************************//** * @file efr32mg1p_wdog_pch.h * @brief EFR32MG1P_WDOG_PCH register and bit field definitions - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/em_device.h index 99afa55bc4..2cc49181f7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/em_device.h @@ -12,10 +12,10 @@ * * * @endverbatim - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.c index ab75a31119..c909a8e861 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efr32mg1p.c * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.h index 0df2036b78..a9053e92f9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/system_efr32mg1p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file system_efr32mg1p.h * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.0.0 + * @version 5.1.2 ****************************************************************************** * @section License - * Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com ****************************************************************************** * * Permission is granted to anyone to use this software for any purpose, diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h index 3721367123..5ba18370a8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gl125.h @@ -2,7 +2,7 @@ * @file efr32mg12p132f1024gl125.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P132F1024GL125 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h index cddbb780b0..b012dd912a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p132f1024gm48.h @@ -2,7 +2,7 @@ * @file efr32mg12p132f1024gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P132F1024GM48 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h index b51f5e4a2e..bd47f6a40e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gl125.h @@ -2,7 +2,7 @@ * @file efr32mg12p232f1024gl125.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P232F1024GL125 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h index a8912b713b..56c7b6ff16 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p232f1024gm48.h @@ -2,7 +2,7 @@ * @file efr32mg12p232f1024gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P232F1024GM48 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h index 401fdacadc..09733a7e74 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gl125.h @@ -2,7 +2,7 @@ * @file efr32mg12p332f1024gl125.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P332F1024GL125 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h index ece9e5e9f1..1ada364f4b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p332f1024gm48.h @@ -2,7 +2,7 @@ * @file efr32mg12p332f1024gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P332F1024GM48 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h index 0a7ac374bd..677bf598f4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gl125.h @@ -2,7 +2,7 @@ * @file efr32mg12p432f1024gl125.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P432F1024GL125 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h index 1c60c74a7d..ea7cd8f772 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p432f1024gm48.h @@ -2,7 +2,7 @@ * @file efr32mg12p432f1024gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P432F1024GM48 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h index 3f76f64ad0..5c27123be5 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gl125.h @@ -2,7 +2,7 @@ * @file efr32mg12p433f1024gl125.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P433F1024GL125 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h index bb037bab7e..54efdd7621 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p433f1024gm48.h @@ -2,7 +2,7 @@ * @file efr32mg12p433f1024gm48.h * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P433F1024GM48 - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h index 1cccc2ca02..6bdf56b9f4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_acmp.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_acmp.h * @brief EFR32MG12P_ACMP register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h index 15584b14b7..6d485bae4a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_adc.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_adc.h * @brief EFR32MG12P_ADC register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h index a7b7e3d269..0524a8562a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_pins.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_af_pins.h * @brief EFR32MG12P_AF_PINS register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h index d10ddbdbbd..2e02e70c11 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_af_ports.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_af_ports.h * @brief EFR32MG12P_AF_PORTS register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h index 9f16ccd842..a36cbb697a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cmu.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_cmu.h * @brief EFR32MG12P_CMU register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h index 1fbec9324d..0688cd00ee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_cryotimer.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_cryotimer.h * @brief EFR32MG12P_CRYOTIMER register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h index 1f77ca3526..3fd64d66e2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_crypto.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_crypto.h * @brief EFR32MG12P_CRYPTO register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h index b8a1b5bc2f..c7d480da7f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_csen.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_csen.h * @brief EFR32MG12P_CSEN register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h index 93450e0bd4..dd7222602f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_devinfo.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_devinfo.h * @brief EFR32MG12P_DEVINFO register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h index d145021dd3..753467817f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dma_descriptor.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_dma_descriptor.h * @brief EFR32MG12P_DMA_DESCRIPTOR register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h index 611e4b5892..aaab226a7f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_dmareq.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_dmareq.h * @brief EFR32MG12P_DMAREQ register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h index ea3347b029..5762f8777c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_emu.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_emu.h * @brief EFR32MG12P_EMU register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h index 8b4ca79dc2..0f4b66e07b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_etm.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_etm.h * @brief EFR32MG12P_ETM register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h index 649db3065b..0ac910613a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_fpueh.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_fpueh.h * @brief EFR32MG12P_FPUEH register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h index 50dc85eaad..19a26bc306 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpcrc.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_gpcrc.h * @brief EFR32MG12P_GPCRC register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h index 9bb4b2ef1e..fcc15c2c68 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_gpio.h * @brief EFR32MG12P_GPIO register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h index 3329331344..cd06090dee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_gpio_p.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_gpio_p.h * @brief EFR32MG12P_GPIO_P register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h index 3642c7f8dd..e333039b86 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_i2c.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_i2c.h * @brief EFR32MG12P_I2C register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h index 8f15a6fad9..981d726d98 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_idac.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_idac.h * @brief EFR32MG12P_IDAC register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h index 59b3632e39..d8b0944cb2 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_ldma.h * @brief EFR32MG12P_LDMA register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h index 3809e6f62c..11b358ecc0 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_ldma_ch.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_ldma_ch.h * @brief EFR32MG12P_LDMA_CH register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h index 45defeab7c..e2c1b2c8f1 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_lesense.h * @brief EFR32MG12P_LESENSE register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h index 668922bbe8..79c905dcba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_buf.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_lesense_buf.h * @brief EFR32MG12P_LESENSE_BUF register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h index 3567289be9..d4f4be4018 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_ch.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_lesense_ch.h * @brief EFR32MG12P_LESENSE_CH register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h index 0796466298..5a2346bc0d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_lesense_st.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_lesense_st.h * @brief EFR32MG12P_LESENSE_ST register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h index 6069c66530..1ceccc3c88 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_letimer.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_letimer.h * @brief EFR32MG12P_LETIMER register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h index e93be21f97..f6bf221ac9 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_leuart.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_leuart.h * @brief EFR32MG12P_LEUART register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h index e85bf5727e..a9e27c6615 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_msc.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_msc.h * @brief EFR32MG12P_MSC register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h index af539fc315..817768f617 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_pcnt.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_pcnt.h * @brief EFR32MG12P_PCNT register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h index 2af6abec9d..c11b41cc08 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_prs.h * @brief EFR32MG12P_PRS register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h index 230aa69208..c94f080dd6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_ch.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_prs_ch.h * @brief EFR32MG12P_PRS_CH register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h index 7ecf6a8714..5c1686a746 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_prs_signals.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_prs_signals.h * @brief EFR32MG12P_PRS_SIGNALS register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h index fb4355e5b7..1e9600a9d6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_rmu.h * @brief EFR32MG12P_RMU register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h index 4f3684b93a..a412a4c8ab 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_romtable.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_romtable.h * @brief EFR32MG12P_ROMTABLE register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h index 2895e69f92..5de4e9177b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_rtcc.h * @brief EFR32MG12P_RTCC register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h index 0ca6692db6..b266ccc431 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_cc.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_rtcc_cc.h * @brief EFR32MG12P_RTCC_CC register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h index 530a6c2668..612723e91d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rtcc_ret.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_rtcc_ret.h * @brief EFR32MG12P_RTCC_RET register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h index 41559ea3da..faabd81a67 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_smu.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_smu.h * @brief EFR32MG12P_SMU register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h index eb458aba92..464acb33ef 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_timer.h * @brief EFR32MG12P_TIMER register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h index 1eb750e4eb..66cb6b400b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_timer_cc.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_timer_cc.h * @brief EFR32MG12P_TIMER_CC register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h index aaea21f258..bb3e36a051 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_trng.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_trng.h * @brief EFR32MG12P_TRNG register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h index cdfb85dfbb..5640971c08 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_usart.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_usart.h * @brief EFR32MG12P_USART register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h index 002edb3e09..dd1912f6b3 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_vdac.h * @brief EFR32MG12P_VDAC register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h index dcb2ed4e12..ad0e6b8729 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_vdac_opa.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_vdac_opa.h * @brief EFR32MG12P_VDAC_OPA register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h index 818ec145f5..8f29cf766a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_wdog.h * @brief EFR32MG12P_WDOG register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h index 1021582031..2447840919 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_wdog_pch.h @@ -1,7 +1,7 @@ /**************************************************************************//** * @file efr32mg12p_wdog_pch.h * @brief EFR32MG12P_WDOG_PCH register and bit field definitions - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h index da56047efc..5dba505475 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/em_device.h @@ -12,7 +12,7 @@ * * * @endverbatim - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c index 03ead32d08..8737716b13 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.c @@ -1,7 +1,7 @@ /***************************************************************************//** * @file system_efr32mg12p.c * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h index c41e3a00c9..8e00b80fdb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/system_efr32mg12p.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file system_efr32mg12p.h * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.1.1 + * @version 5.1.2 ****************************************************************************** * @section License * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com From 59dc6da5c455af675121e9ee0d982afaf9478118 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Tue, 14 Mar 2017 02:34:23 +0100 Subject: [PATCH 04/10] Update to Gecko SDK 5.1.2 Update RAIL library to 1.5.1 --- .../TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp | 55 ++ .../buffer_pool_allocator.c | 25 +- .../ieee802154_efr32xg1_configurator_out.c | 103 --- .../TARGET_EFR32MG1/librail_efr32xg1.a | Bin 190086 -> 0 bytes .../librail_efr32xg1_gcc_release.a | Bin 0 -> 216622 bytes .../ieee802154_efr32xg12_configurator_out.c | 133 ---- .../TARGET_EFR32MG12/librail_efr32xg12.a | Bin 193280 -> 0 bytes .../librail_efr32xg12_gcc_release.a | Bin 0 -> 221840 bytes .../librail_efr32_iar_release.a | Bin 378444 -> 0 bytes .../librail_efr32xg1_gcc_release.a | Bin 0 -> 216622 bytes .../librail_efr32xg12_iar_release.a | Bin 0 -> 545938 bytes .../TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h | 190 +++++- .../efr32-rf-driver/rail/rail.h | 633 ++++++++++++++++-- .../efr32-rf-driver/rail/rail_chip_specific.h | 17 +- .../efr32-rf-driver/rail/rail_types.h | 344 ++++++++-- 15 files changed, 1116 insertions(+), 384 deletions(-) delete mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_efr32xg1_configurator_out.c delete mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1.a create mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a delete mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.c delete mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12.a create mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12_gcc_release.a delete mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32_iar_release.a create mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a create mode 100644 targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG12/librail_efr32xg12_iar_release.a diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index 925895bac5..bc677ff89f 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -826,4 +826,59 @@ static bool rail_checkAndSwitchChannel(uint8_t newChannel) { } else { return false; } +} + +/** + * Callback that fires when the receive fifo exceeds the configured threshold + * value + * + * @param[in] bytesAvailable Number of bytes available in the receive fifo at + * the time of the callback dispatch + * + * @return void + * @warning You must implement a stub for this in your RAIL application. + * + * Callback that fires when the receive fifo exceeds the configured threshold + * value. Provides the number of bytes available in the receive fifo at the + * time of the callback dispatch. + */ +void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) { + tr_debug("RX near full (%d)\n", bytesAvailable); +} + +/** + * Callback that fires when the transmit fifo falls under the configured + * threshold value + * + * @param[in] spaceAvailable Number of bytes open in the transmit fifo at the + * time of the callback dispatch + * + * @return void + * @warning You must implement a stub for this in your RAIL application. + * + * Callback that fires when the transmit fifo falls under the configured + * threshold value. It only fires if a rising edge occurs across this + * threshold. This callback will not fire on initailization nor after resetting + * the transmit fifo with RAIL_ResetFifo(). + * + * Provides the number of bytes open in the transmit fifo at the time of the + * callback dispatch. + */ +void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) { + tr_debug("TX near empty (%d)\n", spaceAvailable); +} + +/** + * Callback for when AGC averaged RSSI is done + * + * @param avgRssi Contains the the RSSI in quarter dBm (dbm*4) on success and + * returns \ref RAIL_RSSI_INVALID if there was a problem computing the result. + * + * Called in response to RAIL_StartAverageRSSI() to indicate that the hardware + * has completed averaging. If you would like you can instead use the + * RAIL_AverageRSSIReady() to wait for completion and RAIL_GetAverageRSSI() to + * get the result. + */ +void RAILCb_RssiAverageDone(int16_t avgRssi) { + tr_debug("RSSI done (%d)\n", avgRssi); } \ No newline at end of file diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c index 5a216c000d..d112b4277a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/buffer-pool-memory-manager/buffer_pool_allocator.c @@ -9,7 +9,7 @@ #include "buffer_pool_allocator.h" -#include "em_int.h" +#include "em_core.h" #ifdef CONFIGURATION_HEADER #include CONFIGURATION_HEADER @@ -19,12 +19,11 @@ // Configuration Macros // ----------------------------------------------------------------------------- -// Default to a ping-pong buffer pool with a size of 128 (127 MTU + 1 length) bytes per buffer #ifndef BUFFER_POOL_SIZE #define BUFFER_POOL_SIZE 8 #endif #ifndef MAX_BUFFER_SIZE -#define MAX_BUFFER_SIZE 150 +#define MAX_BUFFER_SIZE 160 #endif #define INVALID_BUFFER_OBJ ((void*)0xFFFFFFFF) @@ -46,7 +45,8 @@ void* memoryAllocate(uint32_t size) return INVALID_BUFFER_OBJ; } - INT_Disable(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); for(i = 0; i < BUFFER_POOL_SIZE; i++) { if(memoryObjs[i].refCount == 0) @@ -56,7 +56,7 @@ void* memoryAllocate(uint32_t size) break; } } - INT_Enable(); + CORE_EXIT_CRITICAL(); return handle; } @@ -71,32 +71,35 @@ void *memoryPtrFromHandle(void *handle) return NULL; } - INT_Disable(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); if(memoryObjs[(uint32_t)handle].refCount > 0) { ptr = memoryObjs[(uint32_t)handle].data; } - INT_Enable(); + CORE_EXIT_CRITICAL(); return ptr; } void memoryFree(void *handle) { - INT_Disable(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); if(memoryPtrFromHandle(handle) != NULL) { memoryObjs[(uint32_t)handle].refCount--; } - INT_Enable(); + CORE_EXIT_CRITICAL(); } void memoryTakeReference(void *handle) { - INT_Disable(); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); if(memoryPtrFromHandle(handle) != NULL) { memoryObjs[(uint32_t)handle].refCount++; } - INT_Enable(); + CORE_EXIT_CRITICAL(); } diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_efr32xg1_configurator_out.c b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_efr32xg1_configurator_out.c deleted file mode 100644 index 213dac66fc..0000000000 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/ieee802154_efr32xg1_configurator_out.c +++ /dev/null @@ -1,103 +0,0 @@ -/***************************************************************************//** - * @brief RAIL Configuration - * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com - ******************************************************************************/ -//============================================================================= -// -// WARNING: Auto-Generated Radio Config - DO NOT EDIT -// -//============================================================================= -#include - -const uint32_t ieee802154_config_base[] = { - 0x01010FF4UL, 0x00000000UL, - 0x01010FF8UL, 0x0003C000UL, - 0x01010FFCUL, 0x0003C00EUL, - 0x00010004UL, 0x00157001UL, - 0x00010008UL, 0x0000007FUL, - 0x00010018UL, 0x00000000UL, - 0x0001001CUL, 0x00000000UL, - 0x00010028UL, 0x00000000UL, - 0x0001002CUL, 0x00000000UL, - 0x00010030UL, 0x00000000UL, - 0x00010034UL, 0x00000000UL, - 0x0001003CUL, 0x00000000UL, - 0x00010040UL, 0x000007A0UL, - 0x00010048UL, 0x00000000UL, - 0x00010054UL, 0x00000000UL, - 0x00010058UL, 0x00000000UL, - 0x000100A0UL, 0x00004000UL, - 0x000100A4UL, 0x00004CFFUL, - 0x000100A8UL, 0x00004100UL, - 0x000100ACUL, 0x00004DFFUL, - 0x00012000UL, 0x00000704UL, - 0x00012010UL, 0x00000000UL, - 0x00012018UL, 0x00008408UL, - 0x00013008UL, 0x0000AC3FUL, - 0x0001302CUL, 0x01F50AAAUL, - 0x00013030UL, 0x00104924UL, - 0x00013034UL, 0x00000001UL, - 0x0001303CUL, 0x00010AABUL, - 0x00013040UL, 0x00000000UL, - 0x000140A0UL, 0x0F00277AUL, - 0x000140F4UL, 0x00001020UL, - 0x00014134UL, 0x00000880UL, - 0x00014138UL, 0x000087E6UL, - 0x00014140UL, 0x0088006DUL, - 0x00014144UL, 0x1153E6C0UL, - 0x00016014UL, 0x00000010UL, - 0x00016018UL, 0x0413F920UL, - 0x0001601CUL, 0x0052C007UL, - 0x00016020UL, 0x000000C8UL, - 0x00016024UL, 0x00000000UL, - 0x00016028UL, 0x03000000UL, - 0x0001602CUL, 0x00000000UL, - 0x00016030UL, 0x00FF0264UL, - 0x00016034UL, 0x000008A2UL, - 0x00016038UL, 0x00000001UL, - 0x0001603CUL, 0x000807B0UL, - 0x00016040UL, 0x000000A7UL, - 0x00016044UL, 0x00000000UL, - 0x00016048UL, 0x0AC00141UL, - 0x0001604CUL, 0x744AC39BUL, - 0x00016050UL, 0x000003F0UL, - 0x00016054UL, 0x00000000UL, - 0x00016058UL, 0x00000000UL, - 0x0001605CUL, 0x30100101UL, - 0x00016060UL, 0x7F7F7050UL, - 0x00016064UL, 0x00000000UL, - 0x00017014UL, 0x000270FAUL, - 0x00017018UL, 0x00001800UL, - 0x0001701CUL, 0x82840000UL, - 0x00017028UL, 0x01800000UL, - 0x00017048UL, 0x00003D3CUL, - 0x0001704CUL, 0x000019BCUL, - 0x00017070UL, 0x00010103UL, - 0x00017074UL, 0x00000442UL, - 0x00017078UL, 0x00552300UL, - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_base_min[] = { - 0x01010FFCUL, 0x0003C00EUL, - 0x0001303CUL, 0x00010AABUL, - 0x00016034UL, 0x000008A2UL, - 0x00016038UL, 0x00000001UL, - 0x00017078UL, 0x00552300UL, - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_2415MHz_min[] = { - 0x01010FFCUL, 0x0003C00AUL, - 0x0001303CUL, 0x00003555UL, - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_2420MHz_min[] = { - 0x0001303CUL, 0x00003555UL, - 0x00016034UL, 0x000004A1UL, - 0x00016038UL, 0x00000009UL, - 0x00017078UL, 0x0049E006UL, - 0xFFFFFFFFUL, -}; - diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1.a deleted file mode 100644 index d505e1ccad6065ec8ebff87183998ca36b45484a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 190086 zcmeFa3w&JFc`v&5%;;fRwq?nHEE{{IkwJc7BtO6jP8iL|V@o4jLXv|qq|#_KvIgrh z%*Y@+B*+d)os=XHoYpa<*9o+xd9=1cZAfwCU^gX{o@)o_F_3ek6i!1;ZjTHi2uS1m z|JGygwU71|N7Q@?e*Gg%Gbxz@t%(sTVM~|L^zLtXf;MhVwfL7_)E!CS^CrQO=i)PXqoz? zeveuIr#?UUD6{B!KKDQV`CtFYtlvFT^1!okCHuh7_CIAF{ptKM^JIH&+s8cFo=dQ)Nb9@+}PM& zyKAU5F*um)-;rtV?QI+wNOi{IJ6RTK%oMf`4x|(?JkWo8B0UIgjRSSb+uH_O5<5N? z>(#{F$sN1W3B_m~jHL%zeWbm%F5DiD^(H&hvB3nZZwc2nwnLdjr{nc$Nb6#QF)2f2 zH}(#6#(KeS+nrKgHfCo7E&bK^CzZ1`c6$QRLlg!R8Aol)P$ZqWZC9c{zFRRVk}X3v zHIQF$AaAL7`(t3N)N98i9w zfVI@t)i<>_ZmDgL$9lIk#|C>?b8UOmuEErU4@J<#_)U|efcYB1TC+>;>BQ~XG!TF%HwY>o|0W!5%_H}uCkd$}$Ub;*pP zniH{|b&0`5d~hJWDY>JkWmi9st;TK~xI=P7u|W;f66;H~CHoRoCWs@Eu6$E+l>>^F zF%7rv>Q6{_D2B{U^dc6r3P2xkHq9+fZS|Wsv>23V!?uuj2R2ooL3I1ktuUL_lE_db zm9h=Ju~a6}MUi)yZB1L-h?90})7aE+*g9-JPrlL|4rfteGhGTKw>~3^rpr++CE-|V zkoqk<$kupIqH9-gqHRc(rX6fA+Tc{S^3XEHgCnu)f=ky_A4sMh~E@tsqFHdDv8 zY!g6{hiyIS`hKNaiDap`Wax;8WP=l7woHkc;!yK-V_e}6Va$@`W3k3W{|<}_+}LJ} z8&MC8d{DYCnn}|L?QF;@Zy6HN5Vql>}xKyO_l6Hg0NJ>GsQ z1GH+JmiaZEXHg#zg_NRdVRU;D0M{M9qism};0z496R|#nsgnaKhYHDYqYM({ zhQ8F`ZZz*W8o<^R-e?JE9n7%KM7nKYFxJbPQe&cfkT|V7lcH@Y28ZybqWQppLB&uc z6v1F#=p+-v0*VI(V>43&=_y>EKH*spoMM6(c@jCFplJ|~nbg+0VN2_V_SQr{2F_3} zNbNPISak`}fhhz{ew7SOsHM9p6Q|j(&9ph2_OO<=aJcoREqEVtZ;HYwthG0hNICN6 zfz05Iv7L#nDF%GoruLR@Qc9Ip(BYoeR4k53fWxXcAcB^4ReIw~2%4A7s??f|h?r1{ zCf^e4-;t=#pkgMwRM3e*w82J9)&^C-E91lk;ohCHH0R-zxQGh^ZHv*!jKz1Q({_#r}Z#f=jhUtM)kDOJ|I1uY<8xrF$F_dxni}dcw^jt(PJhly?#$l<%LH-X+@2iRl@UV`mj_fQ z*>mY0)DRZyq%L$_5_9Q6XZ6e_RMk3*KAG|$|cET6-|!kilk?HxBggm`0q9E#g?eVZ(-X z)vIdOu5qc9c|48O&fRI`H2S6C64v$fypwEfF-+m2mXZ{2=&7;|Ln$-?cb0Hf&Vr<_ zFC6PfV@Y=J#$1zOJq8shj^>M3$&U66t^2xpc%{`hVv*GzSG{s;-dbb;PaJ8knC!aB^JD?W#J<&QhOGmyBSRl(A^UV z1(cywm};1j+Bt|0dZ0hC;r2lWqQy-_(tVf>2!UFzWGR}Upnnq!_^5i_)K`J3CLq>> zX{t^7(y=(te5x(j#K{bF58e?=Q(0i1BC9Phc*nO;10K#A z596S|bYtfr>28T^QX?wiL{>EqCTU1C5FeoV8<*ovwSm?MIK?A_9FXKDtRP@Het^Hu z1Oj=1*D?(+M0SPav2dm@W)lcpxYdw=PsJ#tmLWt`)e0UO&jwY!MEDrbh!?J6Q{%$E z(xBXv;AP0OhsTnnoI<0GCy*wafy8Q*%1cM?w0+KVCd9U0ITN<&mTo@D5?Uo8Gog;! zaJW;&nI{Eh#&<9=-=$p|y9n?;Ph+1iNfTk34N}%1vRE+4#>QOGrImMzVuGkj42wT< zwn?fGU653cyEN^tX}g4lF}Qd3%4AI7o%pg4oaki*Q-zYXsWp{|C%cpJa8H=l)Wad= zm4S}4wJq6k}lnsgoli^^R*Hb!WXl>K* zw`OR?hc7X^J&49ZuQQjP8)L~qEYLgrwxKNfNGQA*TtMfw?aF0`?apY2Z|1cl(O#f( zYA@pIAW+*vX%s*lTU4^k$6kFFlo$YI5x53GS>*ZvD2o_%y)T)G@4}#5tIn1M2owYgScn z-n6G3FYv6=nzhqQJ7bx|G#*JLlMw1ntlHd};#*=OXTYhM!jUUXR97LdOC-f26Q>(D zU`E5=inO$SBQlA1(L9l%#tk?2U~P*whlz_BZ#lrKRQ?WNFPh%GXu+w{{KvBi=RDbc*33F|czpTks-3`Dn3Q0! zQce>{{$^_FrnfJDMGF!2?R;C6i)Bx}VF+7gs8fL8ElWzLzDG%bmkfI6DX&-(QP(dg zyL{x$)qgCJ&frC5zXbW4j%q(IJc^Lb5z)0t+Y6A!JCD49>we|YMp8RQzcSTWdY}_O zijo}@_o;RNpu?RQS@7P2GG2UgoD3*NuS;838D={JuNg^WG4nD z9Xvw_P4(CXQ7i|q0?7~WJK%H1_xT3(YVwJ$hN0(`R?;nw&;X;hV$m6`H-E7 zT^JB$VQGm0z^R+^g=6>TltYrI_2e2?FEk0%-NV(MI&VRZZNEodye$6p zx21-4y(~4p_O8^p#!HYSe9-083y>o5cA-lEO=5Y?v4>@LVK{wzyLjhmFG1l)L#W=A z!q(VEIcO3@M0-sd-XN5($*BVOYjUdG^_rY2Hs66+5ax^2fVf|ihR~^rUCdo6*<S4FA_jhhsPVB`$RQ`6PDo!{;=c&Gr_p~wZ8Cpk@q$3FEF0(l848AoNk)f zlcKmZO$-kX`c`~uhLkC0x=<7K%l58o8cMxM`MWxPf#U>n2X5BsY& zZrSQ@8yM)#_;I$?U)!?TzoD-)(S-#KKSuI6FPa%hXO{Zcu3Wvc#=ok%=9=o&)z|u~ z(m3vjf$viP&G2${LVCGs?NvCA+#m1p)3Q7biTtZpW4QUDkF(lq5Ns?F>r66h1)Moy zEVCwtuG+kY<<836Ji}9vTkM->U1DA4Ew$!bW!3^~k*`9p(LCC&I__iVF9@#q?{!HT z^D>Vv2JJOyADijo_;?;Iw0S<;MGh~^G4MGCKF7f48u(m}7j2TDxduMZz~^y%k&P0K zT9IBh!@$oFcstu>C@8nRK)ciHro3zxn=5@>2HOIy8!y-HaJ;fMQE+}d#mvXn!FK2z zwpG&WxjdJ}Bt4JQd2CqHrSMdY^xOwp8A|s~h8`$;NkP)NTsUe5olFEMScCw16t>%FOP*!B{8k!L+b@lnZTa zkgcQ>iEL$OCc{<|V`Y}F6tr&`ro}kt@?8)b4J)Jc{RJ4hzUQEi>O1KpzS8#( zaO?Vh0)pDSGO9d&1ct8f73ix1kMvP*ru2=$P5P9-WpGfRri_Z}c`(RbEd{l}4JeS5 zk^CJzDBF}09RcoIMZi}2C?2W~khl;9U7&;-j#w&ggnJc)A5Ssd^oFK%P(D#wb$$6r z?@92KQL2;O?O61)hmwAKEQwEw_3w<;ShA+(nst0A`98*yXGKKqvE)qDfYeB3<8zY} zG-?Wm$D1)Kn!xC)t|mOrT2H|)3Y?nURMX|B@d$&vttNL#)42cA=ipi$CR)gz1L}d? z-y0?VqnvMjr0Lwpa?hP9#Avjw-1Fw}D&MM;aGjjobi=cgbr@%|mXolbot*GjOt4VJ zcr(VJ6aLh3K7RV`9M;(NhsyOoVqAmao@RXfO@6@UsMaYMG(Oag7cHIY9@VXbc<8-e zt^r8KWQ9|&-6>zBO??mYc3OZ&S_kiBf1vl4{d$=a(r^4W_}}#|s74l09;@7612^Tj zGOCp5ouT)6J!p@rZy*dk)F*GmL;6TBnP>21>&u$K*ZZ>T;OYJJWkU$J1AdjEu*i@t zx(H6PK`>6hNp+AOil2(F-j}U`r`3=tqx2=y^a0)b@5`>ecJ2F~7f)cE1!MPRS7TJ= zt@5A!>8otqQ*zmYl7^B!)^g98=H0J8p4#Yv>)zcb;PNh?edhG;gK*7^Zrj}qdq(u& z?jY>E=-J)XuxVav1w3P(02}iLJPnq=Bn7TCR^%i_!PMAN!s_IXBhvqJiys#u18Y)Ze8`_?Fa_CUXv-?FH zye+$J-)^?5bkwTYe%q7Mb?7$F9>II@w$Prkv}fqDWkoOSyL0a+B{Kcworlt%PrjHA zeKK^;syMXQ`qY!3oHMp>&)!eih&@1j0*FsY#GOxa*Nb~Yca{w@KjO~&cZ*ywG;gii zytMK8$)cJ-$Mchu)mLtbcVvvQ24ZjY#$%5TR5U#lyRPr$*xw|7I=O#1 z(0O*!R~_$sezLUYA^cxh^D_SXYXb4-Co5~>_}^UfQ2cNDUygrkXQ1oRWW4JWeGhd} z?v3&PEZ|RkB5`&ySUszO=Jrp)^;%DOJm`I`qxjB8lf@p-M5;3|k&2guAC2*uHqEoi zq+oYQH_HzejrjPydS-ON&LAt97+ySYw6d(S)X%y8$JN}r=(s<^%K4kkUqt1HIs43p z`;&MVmK2TLAN$6etfjRlzp-RIHSi9fq31@ein5M)&&fBuanJI1&cGLii+B{W{BUlx ztfyl9f~Tw_r@<<}p>umrF?_yzhSwKh(7J=O8fHiDyLDzTJU$!_Pn3r5?`%bQ!`{}| z47?|c%0m;Z;w0>6Cnx>FJt@{%kj4vE(J+OzZX^*+Y(9h&Wfc>5wN#8>?+HzGw1mb# z>N(W)VsG)R;+)XLrJ&b)UhFzF;2FOw6qd;}hR0`kABrnErEogm-|C;)aPo~yyj71Mj{$&W;^_b@EG;a~>xz_O*J`(!wXimg;z5u!L z-O-04zhC7&eSOu>UhqX;{`t4g=lK5q{DxfU%Di&ym&e!=&;2vc=ghoiL(c!W{;G$%5{icqd!anGn9YjoK|^E_}c^u*|ri058wjrCE|dG_a3k(?vw znZD$ydTV4BR{pU1cZS{1{3Vfsh{b!F)mZn#AncDQ|JWZ9WtEHG3MJyV#wc&RN5+q@ z8zBTe{;0pPtOxbAd^`S6`WH2PwdaP|3qALB&QIRgbyM<8*H@GG?U-MGHkqF&y>)-A zbn~`bdpZu@iaKwd#s7s?=}xpoYa9MoS_kpJ**d#(e|Kr`;rO=Rdt--s8xr&T&i1PC zmiN*M?((je(FX**FL$it?*v{}c0ZdR^q{v|Zw;f?iS^EW9^d^(3!(=@1=0K$3L3tg zeDaNb#lB^QquY|DNj7#c8D8i;J$x+xIHi%^mlu9?=(;0&$L3HUin8BWvDp`SB)LCw zU*r%kPisYPWKP6;y7XD^irg128KW4AyqY^E`ts1i+|$P={nagzdRa?_oaf`3N0Q`Y zctPy7Jc|Xe)|)1pUHPR@(=UI0d;aKWLn}seQOn~CeW!)Kx^ua8e6{uWS#y3cPn1Db z{^`8>Klt3|_x$K{>^=`KMO988pY**e-uu6$%dmXRhbG9)f7X13#v1V#l@|!jO#mMqr{$xBE4*(fp>C3=v!pSv3RQ)FY_C6KM(I78{@ZKd>A&#DNl;g{%?>p z)wE)??;c50NfjgZX-QL?qJ4!=O8Nw+XHD6M_&WH?P`~h)B487J5)XyH9#1ja<5}3s zko;9ez$W_F20as=9shILd?KVF{8dt333oBtE=GG9fUOMq-z(*} zz+H^?^94hGNXkY2&1WN$KEd&2?3983v6Mf}|jlsNa`MI>_k&TWR30m+}K#zJzTvORpA65Yrc zjRy$dOLPpoM z>~+#^koGod-!AQM!=~^Lz+MDA4+ontRix+RVqLKSFWEIjx5)j+kID7io5X%i!FI*~ z;d<7|@WJBY^K^BHzLUbCzOta5v2RM7mgWj#484J{tEEj%oxAaozNasDU zDStQ)`9^(8K~nCUb~FAqA>1nBqXVoXyOXg7vg3>)2^5PJNmz`zAMiSJ_#?=Q)90`6<`EWr+^D4?VQ3{f6nS1z+Uwi{MOwxCX*?C0usM zl$5urYvT0CP+wyD2T%1XrYK8yG7W_9)vt8Fvwq`k4z>VQ7fqYDBUrp0ldTNZcQWO8 z2VGVHq_6MS%GH;o**7F_h4{GZTTuZgrSGRqjsz7 zI|#ZEk1|SM1Poo@gV0C*NgwqkO5aYnb$t(mo`**nr4L<$OW(s<{7A3Tw;yg@-*-VT z#G{PTNBzEzdk*v?3Ito>D1CZ59@E05nWGB#DBQZfJ3*WPPZ_1}J7DPgPC=g^Jj$0@ zc$B{X8*W|SdQ=eVvz1Z${vHfn-z%Cvnt3XH{|dLRkM@(Y={slW^I>|a%5AQu&jV$; zzQ>@i5^`l!{4OzYw4Yt4K(G}~jj5?_kXeX|P2*{06z&@E^z;@YenEgJ|7fO4IEwG@ z8R0$y!7bn`qx5Yz^fhYwXeO)lr3`&lI18ZHdnAjSuNb&Bz@3mXvQ)VD8R6c8aQ%=| zI%o``!u<SL8r@rxSz z8lg|+^OXQAeR1F@o~pk;0)o=7jB?*D!=-+o4B-ZZlm90iJ$C^IT`476j7+*#5fVcr zwRsgL(Orn&m*7_!6)xEtn{9)>BdA+6F5ZNP(m~}&WufcK2Xmk1QR(aLk2#yre%#Q{ zZ}7+Y>^0fX)O@HK0&d>>d^XLGVRF`Rs|qU;c?@gfzm=y~RDMxX{v+0cQSCLOYN=q+ z8C>0{wO&>Bv^K=3;P}K}%phGi@_wMfJ3lO$MaggPSd7{~<&}EJQT@}ZzU|&1ajFep z13Ft9#`MtDhW`Zg`)R{pMI?R?SY=clQst=lKY`;g9%{4nOxK2KtaCZ!$|!v)cN2En z@Y?Kcc-^|y@B1uCqgY0^+wgTb{ahMdFjO>B+8BOxsOpOUaT)ebeb}LH4+q9SiIe`m znjd4w+o2bN_RYP2T~6TMci(tp#_9)H?Zl0>^Rd6`n+xPzqGp0xSYzQ-2@3=|_;~{) z@}A=SFzu~b(MR9*P|pElMGp@1eKojCH_eZFdY+wRb1TM&aYpVk?A;HCLgVv1<>PtQ zN$@=#km3sv`oe?Z+(2P@#dsdvh1?w)&yntY@K3;<4}L!Id%2s!d36per#NH_%R40; zFZ^W-C)WuFrwS^@e;~v1l~+szLnkMF^mU3I)|`eC>@N-@KQF`S0Gx%u34xN1nb=jV z1pZ%vuS7g6aUSCH((Ol_=_?h#OHU5U$+O&|UGY&%+T^BuEN`eD`SIlba{uNZhnM$w zCVpK^JNw7p+4nk~4LI>eckFqN4S^GU>=Z?;e zEcRO!pAT9e{xWv_S==*mS8-XmFuJTGc&@gH@^Z~lI!8e{8=PRl>f;rXsy=R&=SRkV z&VsXpDv!$%Uu${M$ec5IRo=5A6gHOUU)XSYbZ!sMg&>5Ij^SfP*tECKmL6qe*t%VJ z;@INA5!9>~kDYuiTymo9#4&4?RUJGRDw=VW!lZpoKh99L&M2B-O@x^@O5e1w%Ei|O z!jz(-cRoFS_pzt=847;{wGW2kbUiyUcJysleK7RMXldl|`KP>975BgU`s*#Byk(D! z=2cj)J&8|}j=r5+{kb0YuD9f=QSY1YWb&5LmotyPJ3gLs+RICzbd=&D>u;cDaa4kYLvbCPU`5}o@%t2aq?MOKfhsS&%UYv zN~Gv9`etYDPZk#VChlqrgcnuK?3nYDA5Z4vbcTf%n2#2Rvqf;v9-|VZ@|%foa`JI@ z#E}cPzXtoXQC=(T`nPUm@#c}YebuFP%TXTl&Mb^x-mswO^2V}YZeY#ZB}Mx~){EA4 zZ=WfxuX(#9Xsr&N^Tu(etmD$L-l3U~2O@0jp@qc_b(Ow%y_MyBx0=eJyvlRtv9~=z z?^yZeMEfFQU-?`6Un%oNdxy(`A=n`jMzu_@ZLb3Da#)bD4 zPHA}=&LgqTvQC~>-VdJLPyGZXCpQ}Ed9nLYKjPL|F+Rt0sQat^o}Pm6p>7~LaL%i~ zdgPh@zwdv#e}DfM`ajoy@{PQ}lW*jOUOD#TvLC$RE%&@*oiAJPw{Lh$JnwklxOpxc zpToSb#Y%kduyGtJE2^e)fSwHM!gBN?zKHL%wY+e2)fJCj!N&gZio(aOKq)_UfD;R= z>HNTvcV8c`3qSVmFDJUJ$Iwd3j#{f*@^3!&&d=v8_xyw{w_g08Kc5p=;OU86<74+* ze@Hnj>H+-^ykBhlh`Oj-+^7^jcn=e`1&_l!j+oz6PQ!^zie;_jcUS zk=jUkEArJ^H!GS`Rm@L1dgm4v&YoS+P&{NUYZ|Zf6>WV`hp0T&^ z{~HzCJ1Bp7`5<5EJW~GSbcTpxbvf0Tj_nQB9BVV}n1K|fa#e(}tlhCokAN4%%CV{E@lFsE~!%yc}e{|u( z$A@qAG(L>q+#0^o`m<-SCN@0AzK==pvf+E!(@!w$XtuDC$7MXMr)GY#`rQlPVheM; zH($7rVgKg&3D&Dy+4I)-{}S=Q?%pd;(b?B;vwQ!J=48F>D0E!O!Yl&$AL{Y2`sRFn z-#ZsR#eU%3y_n&9s#mNDEcDc}YpuWg5$QO=o`#O)te?Gw@UOraH$q_{atv3q0y#eXs+S*pUd%> z-b&+^(zy~hC*Qz3K1l(cD{nByC52o@eS zL+4Q3cq|-fhR&V1<(F`MPWjVno@40Ti5q_z#}C^OTCH;oojY;k=X1Q1DlvgjKD=0= zcjFfrcv``Cj2AN=H~w-1ug{1mzZV<$#ReW7jApzT-n;deb9|kRDYsqZ@Unn`4{*Gb z>j4A5#K14%_;ogFiR~f>ojY;I=Sq%uTG5pTeyM?9%JH-oDa=yk;5MB*aqC~k@lJY| z8TjP}emTbv+oqiOe~p1(!`Cdy z|7<*#vD4&bYYqHb_7NGFkK@-$N?2b0Wvs*UVkM%Ln$rUtJG^Xc68e_PL&eTz(nrlX7ZP#VDP-T=W9IcTfJQP86em__~w}dNKP; zNjGwNIr|}jrJ;W5c`5h9U5xgu&h@P4^b+>AloxXPN|ukzBo%&6FJ<#3E%Ij>TPkU) zW5pPytfS1AhQgz@XYyZ(rx>;2MwkDUEMedWrCj7kwQJp$^f4^>@TI?4D(;-`!FS=H z#SK7RfXGWoQgq)CT~(!M?RTS^dgTvh(XT@_{q8rsjGqw;|EKTEpt|N z1${!Kqu@@FPsAUVI3BOPVy~9MrO|J}r^Oy>!6zB(AbKa`XFChhjO`(MSf&s7546;8 zpH6Xg9M1WSsl9+p#;-1Oe#uXq5`iDwgs1ilk?$yQgjx%heyqkboFT7c|=TypLA1zr3W?Ux4atR!ZZ5>!}`?|NdD#8u#S z|Kti#`#nO3@9w1djUX$vccQvu!+tl~4C5V1w}`AvWqncp=DT9-|5s;}&~@5|`b07- z@X(q;5D%G6=ZA=-Gi4)He3!sdbq;~m)_G9 zF1_zmxRr)JzgLXu&2asOzJt(5QdEL;Lk4#hbfL2wMK04b2 zsGWbmm`2|W;PiUs*Ywefee0l4)vI!VmA;6fuNnIMN}0qF z88Y+*HGKhzBmLcmz7+J)+)x=6zfMEnCQaWGfK~iHW$61h^c5;)5=Z17LtnF|?@EcI z_}y>l`|dR9{icCC3*06ONE(%nQwGkDj__^;f~{~TjQDLs{Hh?Q`b?`pD!nfl`W}Y9 zO30N_`u>-JdkVO0@q5h(cNpQScC->oRk(TRC-iz+gz=V~ z7D#=txOoKnNWU`5y+Yy;O>Vvo9IXv0qtg2k1NQ_9bG8D(R{pmF2NBkign0&p(m@>M zrv8(Hp*WKv9If>zLo#}H1Bbtq;$MfvU#kd-A<{g9b^`hGITZ;FM>xeFkluHaoO4XzQ@v zmi{Z+rM+R{!cl8gSx0G)+EevLOM6O>TI)(X*yEjlCH8ICjm+6Rr_m~};``XMqk#_L zqTPC&Iv5XnXs4cB{_zXmhu$2{oWQ*%1LG`wxHAyPZnh7V8sAH^xfb(9o5qK6uhVdO zS%-(;0e~=m#>R$OK{&^jLGI@}*x1>`9xUYhA@@Yj_ONk_aUS$}XlF9EJ$5Jt4rruk z=iboQUt`|&NYw+Sr4hlm0{M@78rYZz`}5@Y0CYWwhk5d%OCN8pI2hmFZB^t%ePf3! zwsmdqwnK)_dx1NM#~aOmeA`YoR@!^wjX8dyHzykMl+@AgD9%!3yx2ANM7Lq@d3ZK- z!!O-ekQ4dLk^3TrJm*BNJ$~Mr<2$n=`asfJy|B(R_V{_voW|2t(VtE}e0agmpH3b; z@?dEH=qqJS=W;G>I(NUN|g7P5wJMlkCdeH*>ByR5!Qchm*s> zrze^JrODE2@0aJ}Oo8WqzLWZZ_t3$R=YhPlFHLq7%{`Ytr*PCN$725&E4Qwtcz9pS z^ZCx?UhO%}mcDc*Z>;91h$H#NHD!En+w$k|I}1<_NYfx5wT@+61uIG)|q=k*0ZrPibu}*8Qz?R1s*zyQL>{dvI=*Z zrh*86RD@?y8SfDJof;|Rx200-c=}c<&C_TsdA8f75%F4wz3oeQY0TJkvOh3BiF-gM zOMK^N;GEC!YPzxGWcM=UpnYctr7!Afc#+N&z>VI-!uhKt)gz+wM=Y+b=qQhopZ?=^ z7oOr9y!XfQC7+*PApaISKOAIl=J-!f4x=Wo8!6emqNj2q<*S=0@~!A7c>G*9nO@5&slQ|8gbigtrh-R*UPs)6c2HYGUaGbWAT@}k@v4#p|TxlYZTuFR;f4Y zL!1Ry#g+K^Bjr4f7H@m`$4{Vc=Z^$jyi=T4!FiM((H@S!iW_ElxjY5A72Vcn>y2(p zD7QEIQcuZv?wom}mY?4MOldA{8fR90Eij@cAl*d`xQ!(IN6AZfiW?b@9QAQooA37g zOCpbjz8JsQDXLBs1JwLFLSZg}hL-678lm1P?v|N3*>5AtbV9>3e~#{0$R8cWgJ zhjw7;-9lqo+V7^Zu`@nbZ%;5`Xun$@i_s{T*6zqZ`SE}z|MWf+2K~8aX#d;oKcC}+ zHiq8hj-mZ;H@?7#Ux5RLi}t_W_?aBBePlOx4kmIXul)myo_(cYOkr5wi zeU731e7F9^2HxDy_ZxUW$FHze`fV3E=-vsp{t81LFysNQuh~WgY!^A`o(Z?UB^>Y6 z+9d}53Il(Ifxp7QR~h&!17Bs}ml^nF9PgCMG6TQDz^~wVr@lBjNgipx-<{s84E)sn zem8!l5r3M|ImXMbHuPWZ2;rjrez!iS<`K}#Y7BV|56@{YHHN;`2E7L7-W)^axE2q+ z9~$w{etHFZ5>YgIX#p8fuspbz0)7N=vnMLlBPbY7&FEv zUGyCGf}~e)c@aA=X?lMZqkqH=Pg;1zY@wvja(M|`C20}!vCeLOVXP-{xbF{ z(8`dXFH1R<1MS!UxuhwNi_xE)H1KM@YYmq#T^D^I+w203N_75)l zD)vt<|0~&BlBPF#G3sv#Cc%^*L07Y@B`xw3_0OIF^IiS=Ep6>;_XeB#M9LpmBPadL za2VHu+m|%RpFydsZ?b=STm2RrU4vmW)$eiJ9>vAu8j1TOY|8mnM4Kh<(Xh!4y|EO2 zX`X&`(ec*Sw6%@@3?siU-NtHc`W2k1eEQ1V=7z&rRM|a_7j`$ z{2Ha6OZe@l8)NA{3fCPK`~*ZAKhxPyKTq^e!O&#Jt%(1QldZ*$ zB;w%CSL}$n89<1%JCSM(wS~L+ucq00z{1ZPHR5;jP<874%{^ z(xq1XP@&teURe+fl!@OWbECkd%{-l1pQ()xCU4hrGs`t2wuh~mwgI=?QKo);fZDaE zSM(obQ#+%x0>q~?0@QBlYypkz3WgZFlk7pp{z}r{BOAl$C#6mAI@)`ukr&}V3VYFR zu_i|}*EcNIgo#fx0^+ZbIGSP5UOkV;Z6aO;8F}YNO5QC3{~Y(ZsWuNE@ulz=AznN@ z=%Y6y#rxm4=dX7w&X%dxyEsfc_r>iR{0l*wC#sFyBSW3jDP{5FbWet_DV=(Xw8Dg9BQ>< z4cxlH5QUp^{3jfSB;1%dl99O*5A{p$g`+W=8Ez?f%21z2hWbj{9|+`NKIvehX1}-0-vX#fr z44i)&+^-GXI^d`*l~M6ia|~7gXbzFB+{i!v?0Px`!mpIUR{Cxx zlpEDaDmPlGA$?SS8AD$R4I*3q-EZKAfy$VRLWp0edb<2{l-dN7M!`)->Zd7D>^D))Lcu2OM9DopP<6M6yfOke7Dv< zsQxQ`*8ztl+vVEhlGAUnAEQv>(SX>iXNxW|Coq?Ex1$<0&1 z>G|>s@`c(5)fcP`*!l9Z)TiqDub_b5J<3oS(DMu6@Rw5jojCLHe)jq&5bm$wQ5n)j zhHRB~q92AnKO#&zd+|^@D87^i%{x0ao3WtAQ2J6myW4jSCVMk-v)|t9zb5-#6|2^+ zTl0SR`u&(Q!Q_bkO8g!ueb-!2wPv(BaBZNp4*S#Rih_9jc#0yw{KFEGhp~H&-8t;c zMQ2#!i>>C#0DCGZIPA5(xF3CQ$aA`O()W>fevW;-iqD4%Pd86iRNw#3LvK9#&Zpn- zFZZ1Gz7{INZ=Hy=r4T12;&q8wH z8u8TK8=8AMe+dgI8@G*>Ue~p>k`6_6FT@)%z>|d4^n6K&68A2HpOthjR@5wxwH6 zt;jL7SLl}OJrcFILPM_ilq8?!de_paQngz}Iq`me`!c|BqK(tNL)S~1c4>-{e_JJu z?gMl#+v%e7>~Sx>gJ`Y%>r!69=@~dkAo>`32hiI18Q98DHGV}Au!(-%pe@z0NO`eA z`wjYP(8Q|7!*>Fm4oO|3+&eIk%Cx5v>GoTb-QByHbMG$}(dg$MHzn{>@U@wEGO5dY z67ik*#wt0e`v@fmGl{|a3||D>bW{7*w))1_cEROqf3>~6ni3(v!TUsJ5MDq|5z?{! zY*ICIv?rX-@{7ajCxvP{D<;%7IYohc30JQE+G)TKR5!PTT0c}rKf5X31N1wdR09i8 zxKvgJs63aFT`A^71=#w6lP#jk@PU8N^J2vyXXAF{!dhXNGQCK$%j|;5E_M}9c8I%> zw0XWALzUa6e^<7OFBr`F_*=U+umZ(SZBO;0^q!`AqKq16Yym^Z)q$q|Mj3^>6$~BM z37YyLWfbnSVCc9((AjW*V&KRhRaIq_zNf&@^?e(3g#y7=xN!sb-#}A8r;Nh=0t|f& z_#j?G)IZI|Lp{C^54|~P?yiSB2_E5;QTmohoEm=7_Y9;%8Re$m#3Ox5#|jYH#*}s7 zLsv@qe*pCR8B@~lsgXsR zD!%8K@w7x(Siq}ugBbg* zLF-zg#u@oRWD{FAGJEsvXjRWo1~wg?#bdg>hrQOy=+vsUj(KMA^Kdg7Dkts=7vttJ zueT&zN+(X~OdU7S1HF@U9~+FX;n@K~J-dV7sMNvFzp?xv$;H{a)JEZ^^P$4+!|i1U zs@d`rG)8sf#qR_;b7WPQgeMxay74o3ALXE?j$z$+@w-9}o_aXP(0MmE zUi_|*6CZ4dX@IlflXuXRT_ZMdf!X*MnirhXzClA@z9vO$B=(Y%4waB z#^m=(nsSPMpZ+^8x`6$?qy>H^d)Xx~Wbe9YBSvr$4^1vAMpfy*b%Wo@xB->{RPJ_fyU{I54&8<#1|KsYHKQqN~2Ydq7vxPBGDi zS-iS-$2FCLKUJIHD@ByI1sF_FJubLX{w_lmzBM8m_QS9}e)&5X`1tA%K`#Oy%P6d1 znb>P4c_U~KG*VkN zeZ1?`I{q!MUiE(C;WIx!M(s=Wq-)^TjT+mOgGo5A6q-1akwJCf+dxR87 zquvB7KNAv4`i8*Jam^s8eJG=F4}hWLZkYzB)(}*A^Z=JF-2Y+dyL%dasy|cu?wtllzd1ws zsLJg@&?@ef7Uf?0K5^=9ekx}&q%YfeJPbaZ_LEp>!1Cp*o=JYs2_{o>Bsta;9Tl$pLLdZjZ;Woo0=e!o>|Ib6-({r(k`svu) z_{KtfiBlce7WSUMJM4Y)M2Yv8lNoQ_&6XIgS{SiH|GBZjd_D?S-;mXXeQ)mRYMOYb`7zvlN%z~b(T*GPSU#-}kFxW=l=a#P z>vPNs%tV+D%>>QzMyy9@wlF_h)^KvNu6)z$|C~NKxvsovBER$G!O^OUvP8o#uMZvSnA6ZSe&V+KI=}H|u!WUBIr*!ine|UjK3KFJ zH;~@t+1|PR*3ftWw)Y7CRnK64@Wem2-mvFN40ft9hEL@Ohx_8*@sUd#o5p=x<30a# zhZXqDkyDey)pL;B6u0lOnuzm#)vRcsdsgFtSM!+lozLL^feKb$!1LrQpzg-Ao_~Rp z8x4j^J9F@xuQXRUfqOpbp3Yu858}c1N99G_msLJT+OwrC<~de*p`>R@TZCej&)DRA z)5GUX^qpQEo?iY~hWQf$FNr!HxNAUZC%I!n}le zl}7uCh9~{lMIh3OF6b$xITCl@th%&H;2=O^-^^OUMK-;Ns;)Z|1*B?p=QNSkCFZ<=)fY#oI#L@J*KGhc7-4_2FB)Z5?I9MMv!~ zAbI?Tukz6MUiLSl`6D?%TK=+ON}C7ikza-(ErEs%jO@)B6M1zBeeu^3%dws(esMGqoXNj< zn>RjVj_>pwo|7c`MxH>-8!sC0ofh+V;y+}0pI1E>?E@jNR2~-;ps&sk&x*d(TQcs) z*O1Kb^S_W=H|nWAajYy)*f&Z05Nr$lm!wTKfW9$(c5;|ejqp|-fPbEQ2*VRC?UVIn zl)?n9>W!qIojk(*i87+!M;3Ynjr{GU-{>a4!%WmYhHnH9R|h77nG>+djjsXA;YRyN zja=JEsr6iOP4tR*JpPw~cw$ZTiVn6U-m$tN^t#_0?_AQ|*}cBv)a2d%>V{L3_ckw$ zoSHn~ufqSws>$!th{bD}RbI_&u~jZ=-I8coZ^ihyr>v{2H#B}2c15(J;YFPJn3shsqs9ca&sF|mYnx9Ha4?h=1kTB9{R<@DA!>-->OHDTfxeS zxA||GBgcaDMJ0I6wdd|G|Jr0>u=d=k^4fD=eDS$&Rp?xfMY&pi{4IR7x;WyC%!5Mih?jp~{SMJ{NYL9=JXY}M7rz%<(N(8@Gy*PR(=^3xK{7Z{Q zW}hjZII;N2H%{S(c2C`-?@mmVj&`xGeD4axwz6OhdM3s)L7Xyp^v&VBtTUcUHfB{) zZg+$!{uCzeDQKLtnRw+r-|PwW{OH(A$Jp}HQMNSn#^;LhMKZp9Cu#AU_(`HOZ0Wz8 z@s8o0w={pWEK(G~Ixp%ijpGZ+N@Is;tchNp`W<>$Ii8D~-<>(Y{7Brl?PQer zKAGl5G-syok;$gHl`v|SC@5OLrFoWP#P`SKpZw7G$mE~qW5QsJsu^0(b^FifdsyVZ z8jpw1SRD^^#=wm);NLqCp7vrqkn4ulXWjUj{BB0VQ%XFL>xR~6-S|R&rz7EM?(A{R z{AqqU%fQdF&lCv!)b&}n{@DzlWbnDDz|#tvV`zQWji1AQA7UrH=KAbh13#BNDDkw; z;=y_?l}8mGVQALv82WzL9bO3=ftbRhlJnRnGK3%ce%Ot_g#AF`smwi)>xRA`cH=L# z@8=bG+JScreLw8RU&iB~vLR}Ue4g6w`r?M7iv2t*m?)P@br`*7o8~A{M4;c7>fnQ?aml$|jL2(S- z@9mDym5vZD`W<<zuJ(m=Ha#3T2|XGa?t(R?)+M7$gefz*K&P+8>O$Dk-iTZc(LH5;9ho}A-|66 zqqZi@b;`kQFK!NV$8WuXUvJ<)V&Few#P=fx{-Xx|qa5$NUp{K!g9bjx@lN{*8u*Zb z4{<#8dBTL0gWF!5K6j_L&fYJ27zhvKkWLprkVBi}Je1n0H8u+Mzj~e(!1K-H; zPWd$&_{|1>vmxJN$hUBPV>W7w?IMR4I|T0hYc}LJ81fqod8;9BHRNrE+-dm)^y0*! zJN&JN{~HZC?S?wW%Wg8{H#tJMy!b-Mt^a18A5Q(d*}#9?z<=D3w;S?yqrBP;e20PW zFz_7)K4#!!20musI}LoNf$uc%aRVPW@Nom*W#GFEe3yYw82ALoJN;?Gz;_$?ZUf(K z;CC4K9USlUx;qSf(!eK;_$LkgP6NM_{)xFK$G4@qQacrzsrcWy1!3nB$%D8g{^N zdD%V#zmMaCHfo>kB8L|zs@?Iwo8z7L*WCvGGhFU4Kf@*^;el%Y6Qnv}@!6FF@ZyGlH-106T(V1;-U|XQw z{y#5;!t&xam5;jO`v(U84-EW0hWs9Tk5uH(JqG>@tiz@M3x@wM82B$5@-MQq^e^(~ ziw6En2L4NIpTtw2Xt6IDcxNO<0x!Fd-^Zdri!nd^e+>DX zQl8@S`OHfhBMs>*FlhCg;XRPi?ONrA{2I^{gpgm(!iHSk-$He|823M^`&$HE&eVOn zf)21RNPU7{!VXK?$NgW)9(Bo=vL{{ia`uld`YQI%F8XTwK9>rvuZHDg6P)5tW6WZl z&MKGmEu3C$f5Rr?vzBd?@=7khmfa$0D*s~4H!?1L*Re0U==JQIF8?24e>xabD< zCoVe5o|3ePPb2%Oq$|0;&CHV{^AC|I#_G{5(8^GlR~dAj#8af{_l#O49Rju(<=VO=ZTB)>qv(rE%K|49g{SzY!zcX`Lv{Iy{nkr$o@&vRh+(wy)Ee=r*CGL zV&R7J56J@l<7~O4MS9!W4KBKa4Y}wT`@Dl&Qo0SKLG?bqUK~sE1{F1C%(xUu#vN{*t$38CUX80+_36$F;y@J!XvCl}ln$sEf zRY?o|yV!Rm?dS44*h!asH+#V)-^1Q;(RZ?kD6-N}{AZ$}5KGjbPx0f;M2q+hv-MKm z2wpMXrwx)Ozs2+gk~om^9+xYLvu>fSk?@W9h=+c9WUzI2e_S3rBtHKxMA96i$(zy| zv28%7YWur1*^RN}U?Xq^RtLPPMk& zph|&Q8rf1CZg1UigUM=X-K?`}H@ZC8A8BcdsIYY}o15y84H`hil2_b;{_f-snI*&s z?H){IYHyDvd--)#0@)@@99b-(iX*=LQYgEab)e1Eu`Sy~eGoa?)|0Ns#bq+{q)49H zbjk4L8tM|iBT9m&#H>YfoRU@?8GfW~Lu*@mD3RXKmm1uSXv9%%wx)2wRf4W}$*5=y zwWW~@^bwn=-!@;wycvax8fWB`3hScTIE~QGsI2l9S2LRiBBIukh;LR_o4GHmj66g(lKgmmWy*EV2ttlp*1_B!=v& zCLlNWq(y6$is}-516{l#HTAa)WpD*tyk|rIV0yPJGp0qU zlgJ{mb@6zt*X@xwZcy9Mrh(or{I-@0Xmj1*kHrU&mIOK-7usRF;m*}|R518WDfKf; zPA)hQhu4CST-%1|);XswV z#e|QMz0wljUR+`E`&kQM(@IVOK9)QHo8m(&3yVPW^0`#z)3p}A$D;r?jX%lWChcLe z5$E7HV%Kk0^5U+GG8V89o*$X_P;S)P669% z@pT)@-(L}pWiy_S>t%Vvruu8I?{vuBC`njLGz=6 zEm9xq*(#!8Q$6wgt1N%mJY3-XQqJocaMSU9gacmbUnXf@KJZ8NlER_+m;J3c=qk`2 zjQn}Mf<0TxmCf~T7wxFvCQInKS*8>98!C9chQ&PCHYdCXjfCsNHgqA;s5Df+JP3^H zjc2*6M@SUK*HeyvALLtg`&*k2aNnZyR&-B2^eoDT*o1GFdSpV%nmIg+5cwRdlvCg)w!&hcVKhiV%Z)lkW`dr%1#= z*korL$vc=VV|uqx8*@8?EaQB)&=~PMLSyXj2(rxr94S>0efaN4rpyfV65#bpW(&Xn z(W#8a@Y7K!AZm6%@7w8QVl+NgYL9}md$z^WzZS8qa|%5{3LpnTa%Q0;wE2Y@Gd1MQ z7A+;Ck;ioYvZt5wSeuvYalrt|n1HyY*{31dFlK3Kd8SJ0q7XaJFM_)0^dwuP)X?44 zXvIFxO*O?mk<`@>^W67 zzuD$dX58$VlRcxF7NO0prp2gPmI*-g_I*5nNW0(xkc>I1mgrSG%2p*c5(42)#BOV%`E2H$$+(Fm(gr<-DDt&ZnN7vT@ zx*Cr%9_gUdLb|?F&`0wFiXX*G>7!E!y1sis)BHslrSD5%=(ul!R&gh+!u^SX`wP$% zo-zveT`+Wge+4=l?imC3{b_Ko7`PvT&X$fb@b!FoPRkcet?hilG}RS9@<(N^j7s|j zFm!#dXyrB+GL_Gmmb>&7f>w2cbgF!*0AJVl3r$~%rq8@@nC^?C@>NFZYcj$m{n>E0 z8n`u}_bX+vReHO@*W)*##qTnSqjJ2*(DwxBR2F^v4Sm0YzAE6Tp3cXk^6z0o-wGtK zCyTzrhQ3P7gM+}4K1`Kuecw0q(LKl6^nK6J*9CpmQXie@R`E0MIi`DO3n5oV<=+`Y z-vQ{O{G#~LiEpLvZ6kiPSD#HEooUd^<3UYdxu%cqIR@0ObMvOrR}7r4?_o_}K+|`% zq0c{!zU79#Z)^INX!;rreRN;5$}_<1_OZ#(_n4;dN=;wV&{sW8{1S$~Cp3LaHGTUG zee0*uM`t?p{5z%TgVQeG!-l?1)98E9(D#g{k50I&`tm(PU)wbL{>sqzoTl$;P2U+q zUkCJ6K&}kL+|WJUdcE2Qoc?}OxS8PVxPzc?QOaPevZmiY*7NTth@a{YR!bbUmn#i@ z6QK3>p~4Lq`h4ibRePfo_A38282U(13Ar*Vezk_aLg=IZl-lpLc$B^_LtiBX6s|HV zew43zdKYT(`w+lN-(ExCboXa}!@vchKrau{N9L4)qdVy;g^2%GICTa`y{m>Gp!Gy$ z6z(M>9hF)-Xx*A{l>T>(a1TIGsFX<@k#8CLR%rTy5=Z(jgMYnV9R{5(ekI`R`Md`D zXk16-7Si;sHS|3J`eDeG0m)4b9J;8ry-IEr609D4jZa0X{R_{tEDOuvDn zyA!jGJHKq;9s^E)pDTSM2JX}}xU&ZCxoL2}HgK;@gS!%ZJ-rj4vz4zp3#IB6y_hOR zR`CC-ecWc~s{{^PJ+?u#xak8DyrFdk6ZeAXi4Eqt?*Z zsO8^H04sgnhQ3N9BB+!}9Fd)dzFVMAwR4&~DScls^mRcW$&^v?`<$U~P)jd;A))j= zV(9CEzHIgWIRiI14bDP->E$~-4Q{@HyJs5QDg$?L8r&8G_wY2hod)g*aM|87`wiTw zX>i{(aA$$5Q-vY(naDo{POpD=qCEWIQ+?inN0rA@hQ5XHl&w5Y8Tua7$~UR$`)5O6 z74&86$N$OD_pny~c53>3NS|K5UDN2J#tM;L*Pqbz^=bO9H1r*Yr)J2NQFS|D=z9+O zssN(=8^ELTZ-b$49Qx3u+D7TCHT3-o`oQA)ZiB7##SMK6(OFg7+60csc0->Jov!Ln zGn&4=hQ3DV%T~UhH1y4bKCpQF=nD@OzyHh7w+;IIkSn9o`+%Wup{DN+fR(<#G4u^h z6Tg=X+}+cJ``?XlE46UQv~YWm7i?s`2v1$~t&QzVYa%Ynn6 zT~F6&`sh4@%9jm>zE`0yTRp8c^sU$Q4Qu+k4SnloiZwPsxKZWSY3Qr_|JZx?__&Ju zY<$k{YInVon6Od zjcH$DNMaJ&8bVr&;QVARk+`KKA*~I#@dXkkrG*%p$XF&@%v=4QXU>`3bB@-AG=KDc zKc9?rcIG?Z?>uv#Gc#u{z*FVw%aByzyTgWe5AZ0bl)}3oa!5jfZmLxGLr%RjXrau1 zn?^1qUFbgw?!x74x3z|D=%%Nsj)b;G4{Am0n@fuJG_9H#=sAwx zhk6Q{aT1H*xiT4bYvQ@%U7cqS^DGyh(^3${nKL1r%_Y25S&@Qx(fFjpf1n`htJ4Zs zH?5C9k8|qW^Jj-M4nG*L8V@!Lf`2BU}C zjz<04@?(d#u8ZB*z9*Jf*APD%^S9?WHEdni^lDQkhX0`=dZ)rQ+{H-&imB-pvM`vycwA`{~b@KyTp2vAr$ME}zf9BTb z6Z`zP;P-L=16y}B9ou@iX=Zz%*;~7=eMj_x_QRXqwYxSQYd^dRCqY^KroWSu9^tRs zjT6sjICn>9@a(nLJ#9r3V?C8f`#rJaTRTrWDmzc+R32~s_Lr%av#35KG1fSApwi|9F6Pd^6=UZ1Tvh5vDgPd-AMwf%CiEGB4f8U+1{TnX$le zIJe_g&+m>fy?AaL-DK2x53Fe~MlP;tVg9Gip2OMe2WS(#DOm3bUmm{dd!&lvxkK8u z#nFq$=Erjm&WgP_2u|l(vOYSk?!kB`kX~YI18)hKsABIgv~mgRiw0PjoeZt>q_eRpXa9e-evqE1noz6KVZPTkb??m1E?` zZIu(D${)u>(eo{pIFBvIQQ6`uarit9%-BE8{E=z(<;n*WiBPW&rfHUF>&-lqbIB-&)u>_7fp)4p* zz|wQTAA*h?onQl_X%5YSm3nv_PN(aS=hw4McG*q@a>;dkOs;x7JP(QA18VT-O1+tM zigz^e)tXWnQa&}ugMqq9IdQtXRo)}zmnCH|&@d^UXK$6CCgt0cGJLb76wg1h%4gc- ztz4dGWVM+t<*SpB(~~9|c;38KK3mF{B&D*GCSBfdllM#c)T>W_DJe%hU*3uzkn*Xy z626&J%8A()t9*`>Po=+kHiqHPv&rX4`5j3}^Jtgy7uw`6l=3Vay5g$RlyYKL!Wy1@ zDWA&URLJPciP;#de1VitrHXmBhVrv*@~M>3@#aYPsSsg7sYyBUHHzgqr7X<~@Pjsf z5H`AMfTpjiH7ua<{30t}VTvjFMRFZAEg2_$buTGhIYqHDO5KT3NEjy8zaSoUhZl@e z5u*(c`5dR`pgwVYMw;Ur-Vg9s7CKYjqfS1v^6!gw>IGdvdgb3 zTUsU>^(|5I*009?fHN z>0j07*QW6LaG|=sHPB{hCOf-Q6n1gRyU2{?b?fvX8|%K*&aqFt;Y)XITjXe6xu@3l z8HuD;BQ>@5tnKWJwM)14t(*D;Y}RaT(>Eb03n?P^6!ns?yFf0e6w{LtaY`kzOnulG zJJa;2G`4ni_Vn3pWpWyhE2?ophFb2buaPrSqsbI51_Jk8v|+nStGtJUOt}S)_0bp7 z@3^Ag4%%^LN@p?TJ`pKbq0dv!sny40zKGu5`0Dj~@4HDKA3JWw8V2I5($9EupkcnB z^tJkT1qT|5he%_Re=l`xGTya>c2wu9=ppSu0Z-hO9zU?bBDLDRSqoR>qPzlmD`E zO+kIvtVqjcgSEIHQ}-6uJCSy*^KuF=(`Lz z)D&J1%x1hX6CUjq-Zx-2iW|13!-0U=R?4y~( zmw=~imst)tLQvtWu;Fo?&Le5?uD9WNF-&6m5iie#x6OtZ!X)6jG)ihW$W9ITQ`nOz8gT`pa@zXWo0 zWA<11MNnmCUzu_$UO`*QB2{0DNQnRPP? z*EHqEa-*v;511FM&P;jGf-M}P5-824Ot)m1(`)A9Jl%*gDxcZ_pyF8QnJ z=5WdP@@iVWp_!}3Jz7zC)wpn0oDv%4GR|C;>pXL`ndhoMQ@L#9##!Rh8O3|w-Rbz> zm9AH3VTLs1J%Kw2mUacJF@qUQJR1x{mn!&h;y^ZLW-rFQp402@YZLQvlKQ3M(%Iq6 zL&TmInG@$712pq-5A9!>ad2*QIT1!&GheP!aR+xqpBr|_J3crMO#Zcz-yP73JjSgO zmkwQb$6k+i==S(bc?Y}*Hjhm|<#y;ZjyU7L^z@;;@vIrM58ocYJn}$g{;?gE_l|@M zvJ1X3gc}tcSwV&(K6Gb%5cV$=%qsXs<(Edjp750YuY|j-dOXXO5iX2;J>d?nkKS>| zt3#NPkGaOPoZbcALs<(l54jdhKU{!w>mTsUJmMX@2&VO(3y(O*E`Vv4C-;b$mm8TA z&5c}x^vJDc%DBcCyVf_AhU=oUqtnM6^BiNYd1A~vkKtf>SX#9^M)R-U*6(0oocFTv zWPYPO=;@4KwCI^-zYysc@IRw#;!T4!R$dwz>{6KWpYzflCpElxh}S;bi=dm=|1&7aw|cp z^Q?QTd#_xRLHE^oc-B4LFO$;z;hQO?c=o;3y-&Ww={|^uXW!F3s)>l1w*uOL@j!SL|7(6z6WqPpN#d-XK^q^b;^rT%J8|m7ken!o;~< zE5AUr8WK95&QHz2>iHE+qL_Qe#G94m(7?IiZ6+J0+wC^`t2UbB2&E`LqzLGwe~5?W zqXth7^81KEGrT#Fc*mfb(wqzZok4To3+Fyv(CL1kPniU(>?#V`jZfunsZWURDqsSUsd)hj2R*xZ3)g)TCEep5DHVgAHUK=;YT4POZ z8@IQ&wB3f|bHtk4aX8ktdhAhMRn^|vyp>xHmEAhK)u*g-%C9x-3#Gg^ZM0Vs)z=XNj;M?YmMR ztNGA@TtXTH08CE_-xbDO*aE$8PCO|O_wx<+)zBTlr<#K~E{U59x1fE{S+0GUGoy&_ zB4dsX`ccxrdy6_NKl0y!@UdJFkMW`V2I>gcm#G8i_nP}k?xg*F&aki*DDymxUet`D zHI-p1WK)?&5tzy_6^5xyqgYI3=-bJY5mdzpK}Z%1A?JvaoF<`93@MAG914(>RJGv` zo)lv1!|JTwawv`#rG^WIu%(On6KKg?B5=X1plqYCK9QywAYGj8_dJ2s?(4 z;Zk_pVK(DE0y>CCDTUV!3o{B`+ea0? zU&3t0+Y2IH{=R9$d&Y!ko)h}ehW8}!_`Xw0h4lkin8WuXh!E@;U;3}YhohA&;TuK8 z*$2K-3U4~(%y=$jD$70b%yU8uA;)x3^(YR5!XTzH;|M0{@5jk~+J@JD4m^I>#D8+l z9p%!^X|zKKtS*LyihGLC^d}WDr~-JvN-C};zDqG-tBllDTSMVIL~tAq*^gpd!}zj1 zFzw8ET${Z}fq9#r+4oxPQ%AylPx?c}E@!ag4YB?8G?cCW5Zez_c9U zh*W-{1 zCPGWUcShW}A(Bh;EeFpGY&^EbJF;hsc1qKxk8o`nwhb0PeAZDsdn7a4=Wveg*&>Q* zzxt*}ZXU4Tt2qrc6iGNq@7$@pPqkBqCey#WL z#ELVAvoND{-`kF*ceZFH@4f8;MXbms?ZLm;lzGaL`IC2@ju{b0_4*b^QGvXj*n!)L z_rz~)AAL7dyjE~`<>W-~KV(I;V18FtBtMG#@`BF&&%QJMm!iQN>chjl=i0|mB|39Z zTsNfDJ;GPTJAWH)UfM4fi19rGtLk4*40L@vUN!NS^V`w-2=7JKeRM2Y-}2e^+DHIv zIK@t;<$z2@ti7Aqaib%A&7mK?i|N4Py=T30HtKJ-Jkq)9q;^^DNq<|$nSt%APKwg` zVNo1H`qOoeukxg`DX&@-&qsdLh8Ov0`*@}HnpV~_Yf)r&>{#dVEn2mV@sCN|3Y?_T*hSzMy3P{9jH&%U$;-y{M+?m=%b&cy@#mvvIwmDCEwTut7Q@+X> zhYK{6_DaW@jG{lQd=-8=j&cS~8~fjt?$>tGv@~PE7;d^w++DaS!P|}R*6-Y8n#=Sy z5?H4HALma{=JdM(Rk>r!%F@VovkVXCPcDOAibq%KO`}tsKe3Kr-BLbf$6i!Qv5cp9 zwD(B)H&jDyssrS5ZJbqpnv}0e%JU77Qd}Fy@TOE|@>>=|uGwZQIDcZ5&%$Z=y3*yX zzH=>ImBD8aG|*P}n4~u;&Zn3a@BV8rS@0be!$T~ZbC90q_bcrN@Q}~%8e9u?AIwUT z&psIWQT%Xilt{kpJ8cim7spOMmK}(iOn^eB)q&ai{;1Q#KHV2XiC0AGMpP7~F#}&eoa;m>(mm`nr zQat9q?z!a3AZPcNc1o$1Y9TC8D@4d(v?Je%&%P*S_>gYEW5#O%?Z=~(!i&SgEXT6L zx~Y_sqkFTzeeic3?C39yNq_Hw*^Ji@tSBuErSJwooAF)&NCdO6Q|6 zC=9TY=KY^gZX}JIDR?sM#666M_9_qPuemKFkI!*DV0A&0Y9#{qNyZ9Uh}=o#2)YUb zbyM<-0pOLvg4GpGf{ZWok!hsT1V*tR1@>tg45jcePUwrPfdWPVA2(LGvV6%hjubx0 zSm7-O#57h|gxNUUsh#}hc`md5-EMl_?ydK2ec|-;YqV>f3;ue$dg_kcx)nP+#0hUMTmZ$HKhjX;99ma}QAZi>497m9 z<=ViwUyPm>e%PUJs_xoGzd!5_XFq)S*ZLPtG54Oz?eA*N=_i(;=jcn?@2%{9H^ce( zh!zyVE{tyQjQqoCF(9tG=+7Aj@h8V0r>6EXv=lvgcKozBn_Jyf^~BlnadA+))?4G) zS~T&SCP%Yl>n*cy_11c|YqhJf3rG@knTPEyiJ&%&zmtU5|N3LY4W|1remp>D=m)iO;Xi zO=MnoG_?QhsZ)XK3+e)i%)2g(myF-&dI>J!Iw;=#vc6G%`hqLPBpA~~! z=Gs6040^__9;k@uUs53*sfA{3#0)6(AB5&oXJ39gZd_+i+7s5lr7npqy%{N9s4dPK zDH``XD)GDknlk8RNAId~ga?qiW3E^x?Z%tMCP{W%fWS=XsGRiXFSG}cwszn>M;&gPZ4&ip9Pb>>qo{EqF4%x*>h zTHa)@=ZA_rM`i9`7M=gbV_+;-#;avGEpYoz2U@9eXI1PprriNd%!8r?=89_ zl~U>M0jGrCgi~&6U*8)3Y#IKVB&2;TfO(=Mj|RV#4<+qVKGBNbQmyhiQhrBLo^QOA z;yxIwe4dmaON!(rO*Evt$D8pjNlI}>GNt$})ry}l@l(0Pnaq?*caJymQ}XzBXj1&P zYQ-s8UCsFeiJ{Hzq4%eQ}6w@hKId}lyYKL)*7BUw(xM)Hl?@^$0~n`luxDl zB`IN;xX;F{oS1%Ncv7k;WrT_QYOMTX8^6THPvs;9o!A>}buV94Nem~x7+U%Bl04o0 zrE;!-X4ZU7_S{M7%4wQ4pbhU8XAZNUMcf>?y39hmW!+8jy>eYJ>1rwO6H(|&v3B(0 zAwP(Rwc*PK%{1mdpk2_FqWr^nD9?U4zkUCI2Cd`!#UX=!T=H|oze87w?th1e?)hW> z7QPTx+?RtZG9+J*U%n`_&@)B7g)R_kew{hPdkXFQhW^qbf3f&G3q41ueL+F#{u1#H z_*B#a$iLGD&HM=s`#3&STnBMl3&`TNUcpor;S5=jj!=FVe{8`>8!r9y6rX-O7D`cWh?Qy zQ_VIcKk-Xx9L3xi>)6~{+l%W^+VJ6D51qU{sJ?9*w!Y}g|1FHF_N|7k0!=L(knSyR zs^YPZj@EXbhpeMlw{33h#MLgAJBre=)cOX4XTR3SZjE5klNC38Y9p^es_$rQ?$j^- zO8T6HutI;_jY?_w3gEWp&XuvYjt1OM)6(41tj7r>8Tt)|ju$hFm+xlu&!9WPdb{CUrGGo~tv1#&Kxg@+9N%r+x3iNv za0aP|jD0)6+ef-m@P<7xXN~R;@mN=VjRv0KpYK!pcVX@mijoidtA_p#bVtaz?*zEx zq~YHL^=f_0I%lmuKSiDI6#C0I;+zfoH#^Gx_vVN6B9N*~saYPKlT3P62s<-X!P0Y7 zRnw=MbiicoGF#TFI%dbQ*DgC>FD;gOmR=-P(^kE63#dYFkx14d zb+UVMLB=^MWO~=>u+!ADb9jM z)p(Sm9MzxTF~>IuJhqdJFGorW??IT&;d=;l5RXy{Z$B)|a?gOyQ$o;{+>dN>hd?uo zN--`}FX1tVuMFYKhaJPmk&_DFuVFU(%l$#suv1F;`){x?f;VQ0uX!!WdK+Ff@Y0p%J8g0e=aBolO^$aaSb3awO@D(GU0GVvB9)VmCv{EX3+&5$nU&55m9MP%p zsr^9Aekz{ZOLt1qFRDfeunvGN)gc&^U$ju>&7V;2j!!7}mylx^KF;4qZFsN4feJgr zr_2WpJZMr;PKBKoO716y9P19%xxN#;4mm({=~CG40I*N;oq&zSTPhH6to)^JvXm@Z^=w8=JRnH@+1lzY|=YeofJmvL&B*pA^s7 zg-Y&|3LsLWr=3OGeE*Zqa8}rJ$TeR(Jgv?(_Su9h!g)_m-3zB(OC6_NJO&nzLZeDtC^lGoW5L?JagojvJi3a)hT?TdIGBP%;b$ z;*slKpmF!oh=bVL=xJ||-y0Oq7tTEFAtz8cF~mla*jgUGWwlItRj&b`$#IWZ#lAk>7D8xX8w__E*I z%wb&`Yfb||ah7uqIs|-&`|z{O&_jk^Z|IB%`52ChInW2FU!=cV=3wHjh%{fIzt0&I z$x)Ftd{f3VRDKby|6Ij^_lR@@awpYT0cev*E|UGVpZ3e3PF zNler0Uc3j3Q9Nu5*fud9G&2t7e!}A*IL1iG;W?N4D#1oSXoQEn;dn#AY)(-D1o>`Pp>j>U=cKrR^>Yr>cF5a;{vb}5N z{x6NqXvf)+F5~;GV}WaApm?`DQ&N7@{^L6qd7OTaX{v0ilC9@=y7K}#enk^*D7|y1 zD87@;ifbeTuweONThDhOzbujFyO8IlB@2~$BduL=Q$tln{YJThOcB^Nx2dyd+wa%n z%TtFGg1#WlVx>U;;FkG+YJQ0M#6mxHgA!ov}7J+Y3K zPuxx|x$4SKJf7iQ0#M0z>H?JFMZX?jbuD`NFE{wYU)i4(7KL}q^)V~PUvYlDQp2u- z=CNgw6Y-;-|9pLE4M!iMbmDN&_sdr;x#`;YEj%w`>9x_a$euQF-;u;ULG3=AoI4(E z+!Nc=Ryi)3_QXoCPUoJoQn{W4tM{wEvkAXzwl=N8E{Mm%kA|yPTzqVPN2BYbBgYdW z_*zEd$jk4#+>ojKQ6e66J?gsrSYk)8BH>!JZ^Sh(^Ifl465e0UkX-WNj>IqC&WVTz zxRwN`5bSvYA(&pbD@NCQHeDMp9`e*_*XBl@IJ+Vk&d^u>W8G3V#$w)3bhVx!c$0>B zhO8H7CwmS!3UShcAikq?#^GmiM#8EOT+Tg}u8~zAWH`Tz^AlVV+U{x9f?`ZyKLN&g zXSudriwtfXcmiW6nDw<{HA5K@cijWq0t0)tWkd=FGMEZoJo7=Wg_qf(|9B5%aV?BI z?ZFqx-{El8j0}u7VQ*Z)fTu2Z$4poC$lXY{yT>z~w}`;Nx)4xI>bF1mrw{))7GvE` z|DKpgrj=?jbPKlonMocEZaL4%zM8I73#C)(&Klr*g?%txrA(yLohwWEAemCJ2a{6i z&XuKns%^A}mSZ)(r>NM5a4kILQ;MxnN^vc`m7krQ|6@C**|=OQZ8!K+E-iQIBJpXb$cwXV@3`o!EJ_+d276ZLmwJ?I{UExzDM`ducfJyR?$?3wX(?z22DyAMJMs*H=w!NdNMe$_iUTrH3%5%@hgbQiDaHskis?G(|!Gey10Rl)3y59~J*k^}SSm zR4p6Z7S>IrR13+nU>+m7;2;P)HU6R;TRSWjko8gFag4}vqLjkB2^MBN-bF_D#G_k< z*9|j+qwoemux=}*@a~6&S?*pCjGIzQZYM0v{w@S?5O(yJ_R3$5Va<5YfC#}(DTVh0 zEX;WICOo#z3hyNpLCQh1wNJ8BtLZgo7CyHaU(sgX}lvP3)cFIQ&c3;v;j1xU(`Cp0%xXOy{|z z1f}>~h(2HL&;{rfu5Y>^a;sdOjdQOK1tJ9IL-g@Y z-Xm3T{a}2MGy0Qzhy2Cfv8daBWI@L=IJ!0%Ze=aH)*e**G< z>+u}A0(Ni0ZVBvW!EP+$(j(=Fg>$^C`Fp2EJA;Q8LE@O(d1O8%+6Gt7L%d#f`(LMT zrFEsXyhEd?E(d$GMUQvH7oA&|Kav?me|>Cy2k+ikziE@ldn7+HtNl%n>viaHZ}3+5 z6!f@`TmZ@;shG=oBmn9``0y>5kxuawFz3|e_TN1;Ei$VkciivHJe=DFbN_>G_YpTF zwBW66OgEWoBdDpNEZ*Ot6w)mV_ieZ^CdilfZeU+qr0c+jwt_8rp?~+h5py0{43t~9 z4z6rP8Z3l)7R-CKX^8Eu{kI_2m%{Er*fF+EurGoAiD}M5g|I(i*cZcoPUOM+*RMU(A?)C~rc{xbSB0p$j4Lb>ziT>}(!f>6-YjjCY*Vj`$Iq2jI_ArUT+T zcVgg*Ee_8SA7cr;rE$MZpQZ5!+lz-T9x4r+;%h1wfja*I?Bfl+nz*-Yc4)8b`NWQp z^T>3DX3OBphclc+jNb}#6U;1q55ioWEPMXYi7ojnu_Gj^mo<(lLy=!3yuX|i|H^(* z=-A~ASI&04`{j&zA7-3(j$e{_O=RAOj)~%s*p0m;AL3Afo$-r*CbXS-Vb{V{hhR78 z{LuAL{YjDajYN&O?xb)Q9R5Zky!RK0CwFq(cxXlD@mmtE8Nm;=(}~c!kbit~#PHq{#e6qE@<}1NSR;{vy#o0QXt1tjIdPPIv!dBJ|ahXqSMH zbvWykmNovi3%`LH0i3LlvcPjzA)JF5W!f_DRoc$)zAYZi{4nFp?$E_mjt5=yt4?M( z9lJH`kM@VZcGwkh>?w#EBTba0!h8H859MkZo~sTtBJJ`+t0UUZ{OITt{&8(a=>6uL z(bFMU=>1r3{zz^(Yp4q6@Kt(hMygO|SGb{L%>4Yc6?KO?@?jQh?mj6rZ)oSHBORHc zxd`2%O}jT8?#QfqZPV8i8NnQ2W{rsARgm0ClnK$hTIvJMIi4%9$K+liZJTu*7tC>7;P@ zL+ds@)Zvrv1~;wW^gxHNYR@L;{xXiAlgb;C<&Nb!zX2Nvy`f7Z-lE69^wYh*KWQSab7$Mu~!`j#LoUaSEb3NR%Mdv(FFa($NJtF2 z`FbKhI5$!-R1mKm4>=rTyn8C-D2QGiUJ^Fk$XN{sPSkWPEHiMHADoHs-|BM8cYzDM z3vnLh>|jBcwlM3k<8q%Nr|;I1VXMxl7A4cUZ>a0Ca8X!)lZFoJeo%ss6G+r~ekbE^ zeg9>Ivt@j&ap|(9hr(JCzRVT_T{0N%dRFaa;yYsbfefq$psTq|ezzPimFFiq6MdQQ7}84$eYf)vuy)k2`5gyP_{W>hT=W z4EH&(d3D;ix=%t%yVmts4(@u&O=Mly++7xSq1>`g@&2d_!!wLMawP?iJb`mU!^>ri z%5i!L!>pf*$~}pHx<4rImvV>WlJjf=-^V_f>>aFh9u~#T(c*!;G3~K($<{MRkj6^*wXwl^xDR&t?YBB|UREPv)b4jNvJX9FM>1`P@he zZdwaOi|Yh_*T-|@?QHM9t(UaYAzioj{^&X%v8j^vHpjTN4ebeU9g7C!4!PE$K%G{+ zrpa+C)Z;kwRopa2S2|9$tj{jY&Ytj8j_5n;mNOp_7k*C~K-pxRWIaF{sl9l#Q{|U; zifK#>q}K(J3u|WLoE-Ylj*^)x=X-M_qT~hi2wq6si)UwuTvfJdZlUY6zp5RRd1K@c z!v^`0F4P%O8b72JE|b1!h5GFBlE}jTf-OZ8p{9bS_MwHh7i=jRs+5$g#4%PmAz)vP z6MVF>f-MD2Tl>E@ggzzYMNdJ~$^N1t+E$OdTu$&I4cqE*hwEY~GXUzbeza8J(7fP| zEw|5dRh@JcpS+`>Dlf8rb3tbjcI6g8|D~t$qzk5uBcfO~O{?>T_H07!=;mDY`q-Y>G0cEZ zmd|WH-oo`kd~f}3^0X7X?LNXh^43w#BbRwYj>yc;<}a`Mmrqbv!I<)Z_+Kd|QI`3t!@foh?W3FRjQQnBF$XSHbaEd~x zuXjhQaPrF+tBP^sTvc?MvnpP3(p4C!npss5mE{ST`nw2kisit>xiWGNJ82(?hbn`*M6ww6eeMptIjwr!Czb!@X-L@r;4@*~6aGuRqYQ zl{b1H=t{gDHNwyG%5$ef7y%VTjeXFDUC?IdfSe&QLU-N+^(eVcS*9Ga26>-l|BJ;> zk3*^PKDYJ_)H|HE=pi<#J^}12m6rkJZ(Yxnp3!KMZxMW@Bx{9uqnl2YYnf&8g1k7FO=QFAL$QeJb zJ=gH$1c3{9sas zvyLgn^?+7+pOjC{;rUX+FmXMgRX$6~zmk+P&&EMr6hJ%kK^{ z{qW-epYi8fe_f?gf;9JFTixeK`TC?hb0ej=2iq#2C*}7hMN&CMEAGLz%3~p)Npa7$ zmCsyHDejrJ@(ZMYB}ox}KuIZ{FKv~dE#;RbMa(P07`{0+`8iVl#iTq_FQuF!Xp;}7 zm@sjVv(^71iI*xxMK<|jn|!g2Ki9^eEAjRvrRFA0G&r%V$m;*4HvVNc{$&zxT~g|@ zq=^P6b}3l#7D)NBq|}0>Nta(_lV4=xFShX)OFVub(bZyQkh)Wp+vLlod@6s+ZSqTP z@=K+BD*cz*MFwM|}~)~3Tc#kDs6 zwG!`*q_5W|O*A;g^)~tIrF>~p>iVQfm%qU#e}gUlH`wHFw8`Hn2=ofStaFDt&pX=hxA!tlV2g_>yxM}k|r9Q_`+_* zUn%8Nt>{Xde2q=M#wK55ldrYO*GlumCMQa%;mI-7jGO}<{rr`nHH%<0gH z6$IA!-Yn&-lc?qu29$5G$)|Ek$7{6l8EEYq@}HLB zOVv`kPAMmL=2_#j&L*F#nRMk8>uvJuZSw0=;8K2rO@4!o|2Z4~a}qCAem-ZD-)NKH zDCJZ6yU`{ewaG`Ne5(9JZSpaje9Xpgw(*;7{8k&^yuyU(x7o(uYzxn38(!QdAGh(h z*!Wu{UaI}rVw2x0_|2P&Wk|#B2kRSrtK_L4CvNDp^4rDT2Gb?ow<}SpJ8^r3Reqaz z&?3LhCf||Vd#Q(~!{(l)Jf)oYx@^Vo`HA%2s{uU3z`XnCiFEOuYAb&2Ih9Z59jb06!Rw4Xw{|WDtQ;PCmv(bA&)9NT5 zo_X?&jsKdB{VsSYOlA##Bh>dQx(RUi|_4J-A zzGdS-YVhX)D+m467j67E3_e@Z9Gs{#VdJ~8#z85D=VBYZ7&OBl!jpskYn4HBd-V7)n{v>foda4a zhJS&}!#h`WnYQ=X9T5nJ4#7_82shaQL!6{HAjSYY+ zSKPd!v9@YsL(MH4v0bmCr3L#Ld&6z*eONx#vH7N0UvqqI441%*^pe%FzL@B0?ZCR% z#{SQ=VHND>S9G+9m>I_e(%M0+ma15LdlSyA?iIbw@z$2@uxjkDiS@Kdx3|UG+9{Tj z;_)f19epVa^U_#zz>)`5<7OWvojSd`zH)7CZ$)!o+ik5W%c?4#X02aPopfH+-WtQ@ z>S+=QcTsILgUfx98yoxeE8!auDWsx`fpPge+{nw^Yp_b#mXeJXR=9?WjSa1_t<|l4 zt<8O%JvD8c@&zjDx%M^aHqM|DhyQ(yl?Zz{>!|nyIGS0<*KRKOHAk3GC8S5%iFy zuKZb zGEEK9ok1qt*5BH4UIC`i+S|LV?|Hr9w08*hAx8`)Fa)2-fPsd^?Is*Ktw>wAi6^aZM7U42M2wNoa|juLY=B@_9)VYejZ zc~a2ALIJC7ZEbCcb=2D4UOHnnV%aFbbl4n8YA`dG0Z(+e@#^P;UeMGaxJhEr@&fyl+Vol|)$`nynttqCQeYJ1UJ z>Ogna;-)IbO5C>T_6jtk?8`fTppQSOa|**Zs(+L9J*V$wqJ9nSq2ECLdHw!D-b2D! zE#9U15Ol{u<9y5S>2olS$8c8x?eW7glkY|2+{%}*hYB5e%5(28`PWg0JjWWof7IuA zd>B~8N&g5dc8LS|*QrCEV;<7{-s$)*XzJLE(qQ1#(cMpkc*Ky~M;&~QT^Vja^?%ai znY^16_8g1&;8`|w+Dkc1w8?Ym}uj zs3ZO6QU4eHZbIMBjJr?4-(bjZG34)|e$+^}V?z7|>En95d?)mDX1*XvB<_=jyJrmj z73dD+2cjg?SH=(F$|4`(;@lU*CBrwW?`>l|N@G$u3{V$NlwEtJb{v8A7*M`6UW~9qW{oFm~w@g>a$?(E{ z8Qjy}0e#MY7cAs5#i2B=ajn)60`v6Hmb2=g|a$EOi7K^D&y9ADNn7UQN0TC&HHxIo21Z zmoHBfA?hC(>5N05Wjb7_>G6l&M?Uns41Iuljwa8o^bP3 zju(VrIduG3h*9c4#94CGG12`9^f?8ZULS#X9cbSyy*@B}vRr@;8ul_DFV^((`e#OZ zn{+7;x{SD3q~WGMPfv$A$T!A!4)ROt$p8P|UQF|RLTYcMX<8v=X>P%juU+#1I=!fU zn4MnAK6*|sHFYqYUJh?t`zzcub&=jp^5w638oj3Tea&$P_{WK)8D6LNG~KW|y`&m3 z8iVQc3!N+E_K|XWlqrK$eb=oe4fFwNdiQEHXBwKGUog$M^85~rq2>97*h5b*p~i;k zxu!v3dV%D?O%4y!%cRDIX%bHjFO7lUREgB^FFm?#Aede#H6%>WHxH%KOH3I@O%17P z2=v+`rV5ybOH-Ls22E2%rVgFbhc#J!ZG)(fkv0#fK29__u$mf5%a|ZJ=b9!t&NaxI z3YqMO+gq}86zcSYuJmz|L#OntWIBFAZ!IxDN6@U1K8H}M&6YFK=|g83Mx9s0GN3xI zqoriB4eoYOG^g<27&I6Jf zj!ng|49esg=Tko}NbA@+zA#8;tNk;BwC$bxtwD!U)AgnoG|zLG^3~xFJ~8Y6uCol; z2Uf~u7&y+s=P%hGrq#q^y>HL{FJ<_!4;{v%;bH%hsvb|CH0eJIuM(sg?;{f)-736W zVK(DML9_3yl*0QAEX;T=badCjj^Sgt6yBf0Y{o+uU#`!9wNwi4%b?778-T|?Ht{%i zQh1NUY{pxQ4m7&aNu}`i!N!btj|q=s7lrpK%x1iWSd-9@MAPL+{u3TE-s8YyJQ==h zJPHp(D+}ITz~lLiN~!Q+h-1Nf(uC&+PvKn-x90HO4+htlD5db`!_FMOXMjf>hA#(? z!uyO3?<1@cV45nW@YdMyUI8A~~D7-stc>7S8W-Bo0$R4R~v*EpE!n+U>3h&!C zycdDT@GGV8zG=hz$b`pmD!iZC@QwlxqDiIV`y(4(UU@2iIks1L@7wUa7}GCLqUmxZ ze`CX&4LthG^ke!cyZ|Bu(PaG%0q=FtN~!QohnzWo>wz~2A>whYsqmKD@bXYd*(NBZ z(vNGC%y@4BuK_~D3*u3Dx7zTcz+?SUN`;Sit(xP}4!NKbg0B4Sv-!JhNvd2GLr(eo zunq5C;H4|4U$^1aoABnE@LsjyEl1?%r3v3Z+3;FSc$b>+erLmr0&jx}Po>Lg8{S>O zD}@}>`7#rpTAPL9Db+K;3mIl=3hx56CtxLckC?)@z>q^yiK`%I&X14aNMVDW%#Wou zyk~$%_YB`6JSsod+3;Lwl$U|8lnUQk8{Ug1JiKy}cx)HV;ad*8Hx!s5N3!3B_X_Z$ zuxI#CWRrNji@=PRhdH)%<@70=T<{!n$8B;8A(t-w{snU8{8)%({wn>rLSLodqz!Kw z@Z#VrrPA-L4R0Cnq7Y(yxq@HeT>^tSz7GLUVL&XIzq4Rz4&VKz@Lg@ftFYni1>QRZ zGL*u;-iG%O@Jb=W@Lh|Ca*ThA4Q~fBBVBp( z+)>Dt=q&lG!qAC3QaM}e0|07I$p-EZ^v^>fJmz$T~e z7O~^~#wN!*KFs|C%rAq-KU{2>ebiQ6zo*Hr_FNB;K?>*q{ zfIac*@hH42YaG5 z4{>d$IX@mT;eFbK_kj(s1ce|S-upJZ$4z*wCo27d=uesRW5YS{W<$;#z9&t1{5GTT zYHfJ;+wfF=tgzud13ZYz{AE8u;cc?vy#k>;@Rgz*)t}qs#vqrkv*fRm`>stc0Xh1s zl#=_IP0kz8$5~2F#p5-|nbYMJQ@X?;tm2Wd;pG4iS(H=?Z^DN6x(Tn@gqM%XV9vMv zbKtRmYYyKVCcIV?-ZeJ7An?+q%V%wJW#{ns7Ms6snf#5L{QZIrZ#nRS;47u_U`+o>DnFL`{fgdEbOOR@eDa_k2wrNRg6q@U!yhx`b$U>HitQCDSAvT}qN#j_p6 z5AZOoEEjaD@&ZONT7v!y`b0`8yv6zy1U{)$Wq3Sq_CfN zNRP$Or>k6+ZWBWiExTKc;=G&C7yBJqUjS;OM@uk`%V-bxF2A-;Jiim?^_1jQY}i{= zlKW0kNuc7g@~gGW65I2KxA$u@9~^^&C_y{Ctp46mu-^#7uvW0kKcft3`Md*-2~)~- z%-t>B82L7E!rkK-{G7|v>}l3c__}ugiJt~m;P;h^fOFV&?7ALL z`K}!Aac{Td&9a`HF2}GZin5%ou*@Vx*st@ z42BB>q1w@7f7-pbyyAk;6LDk|{@N&}_H%WUy{KJs!h=*gTE?YyH4L;+SIoFaQo)*s$ zJMV(kIi4m@(`aE};pCF+?$D0adG5iEjEX98e?k1 zY)8Y6N#uy*y~&b97vz455I()SVe+V}yS&;H6*YHCnnP?;Fal$8kjBK@b)n>%5fe4s7Juuc!$_K zuS<;jfh1mxBJHd5Q2(m^s4-b+#l*1xI(LsYjMfqtI0{!g>OvUAXeoHEfPaU0 z4xQ#uzP~z1YM=bAe`@<3`TpyN{5vMlUR4Ks`i};C``^K{>Iw1Uh{)pk7f6i`?;*>i=tw=)<_dT)f{A z)YgSc-P`9puDvIA!fvPd;V9F2hqm7n7ccMxxn+6I_KJoXWfcwH+!mz-Wzo za2#)&gpSIh15g7AWhI#xS#SDm*%?q6UC0fcCYqk7TWA;aOd{V>z{_!!z=A8 za-F|mO?737H{Ct%!LF<|`v;yDTg#UFx~IL#c4;t+DbEnN{Lbi%GO^dcV<_Nh8#v}e zJskid#vHqlORx(aBUaoip6h~qUJkb6zERR$^Nbi}d2#tesF~WZdvK?B{CHLmN=>&z zQsM>TOb%;7FYDn-^R^-inE&($hRbMc-Yp3^0sTVBR8h5U#T(HYgsGUAj$ zC=Fko@xq4jGOe*Rz>o*avXLS#zrSHZFGC^FIfbh|v8-}WTcEKNdEg#=+$Tm8jAP*P zM^Pf+M`3?azZe~a-Ni%se!M@YX@SWyPupbq>hFmcPft!xR$LpnMO^0I?u|IQR)5Dm zxWT88J~EIJD4D>sM z1shkOth@l+ewgR>m-PQNTq^sMD08|iw{#^?pWTBGdByVsh!^GrUJ!^=`SL&rt+<{G zh`AWOH<><-{$#4q&1d_?aP__$_KBoV9PnH}q+Naequ$|8^zyXCTE9RaQH z=;&WE2i9J&I&bm{PfJDa)c)C{=h97O8(@G;jaAQ&jVAua2N2F<%$=_{CG3uAU>K)XxE^JTT+_mjffZ5 z!M^yeYr0$~CVHm7`5UwyA=u>k6RhLw0;NIN^uxv*@I<`<^zvA;WgX{x-5V&|A<$O1 zy?CFE(l1xQAzL7}cqO;9WU)5s99JzV_u$W`2UfHGp+`rTMqR78K)c@4;%U*YW9l~S za1VY#h`&OQGafve)$JW_?av>+4RP`gx1%4wzWoGBtgc{<-LhZ?OmCVRm{GE)fA@q*(x@QmH-hXHR9SFUyNAH>_smNu2=LSy?YE3W;#encHclCh3S8G^;Qj5pqJFDB3`c)P@leqdDOW)(Ny z6}nSvSd7-=qvB;b;@?)4deHD=uGpd3kV2S^1S^OUtebmg3US)>v=rWx-qFWO1wEWYHCins7l_ zb3Di$VZCjg9l<3_mtC>^>d%UbE8%6VHP+N7G*0toRAFODYyYB~mI?QC&rQ=DK6j2Q zPrE?7$eFLr)C#m&+8kGrnv8%0rOZ|?aSAa?DW{xSG1KUUn3U5p^TBx#>)o-bSti{P z@98toMIzWHG`e@&Xpg*qoR%o}xLwGF(+_m@2pY)%-K)LRt($t5F6rM~zOlEp`*Lie zZc&``?K%7XR#SJjU|-|q>9(?6-jj~^hu<3WKezsfg^FcE2G}cQL_?_iNrHw-&f}G*zo+EN<)3^WuMhK!P|15rmf_2_evYj}-V7pw z`aN*!OxWW1E%Cv)I%U>7H&W0)e@GPJbm_8!E=m-~^ZR+;`{+M!5o4S6 zGvT~L4!Cg8#fXY0?kwkt+Bj3)%ahVa`1lWG;QZ5oJi%5J1;XqciTXsO}cU<Uvn=2l9P@&p0OKlJ$=DO;@aaDaH2RD({x^*Cj>l z?+33<9(VCVHY+L5FAOQgvr(=1dZsA}o`q`Vr;sSavrnyjb3;eI-^TaL@UV^4RVwDB zdA6w)kEc>08x?9TU+T?Q;OX^N>fsKEGjen7if02zp)5f1^MTKA2*{#IsDT{308_#KteN@#oq2^KAT58^6@XpKs&O zxA7OsdtqtGlA>9@$TR$lgbERx5)HJqL@uJ!q;g_6pz8nVc$X)6G&qx7-P(z-W-DPN zb{-zy$GA>s$zPVnRy^dhjPia(^E;IM-FTEDy;l*?N&kb5{-KS219ZxNuXx|ap8+QM ztZ6L$3k;eq1J7FH{#d2x-&PAhTX0>eQsnP2_zf`UAcTKqV{%d^;iY|wgm za>dVV^6%Ja7dl9^(%oMmxK2|k+7%gmmYf`Mk+{;vud~sgv(Y^^`fH%+U$w-WDIT%$ ze{Ase@XQkL7_^?AvxSDvl~R-`0ZlxeKS$hP<2PCOLGc9}{}BtnNIYZX|J=ea5nQ*X zlnf(0PWeAiEMY(lMSi`7Un;iQ_&Y58`Qqy~zU;86yFXj7-CRF0Lf_6|Y-hqyt+}S5YGvu$p$s`=Z&dG+ zu4OB0?hrazT~%Gx*xHAE^HuFzu^9#j8`R*caRjgp1HwKG1RHRI6OQzNw^Md+nK$rF zVd_p=o3?Kb_q29zZ|!Klorl}>w6);$1j6aN`t*}0^dQO&WK&L>(0M$mBDr5mPosWp zIcZ$8rq(!cBt-!nQCYjaqg5o&=vaesZ*w1GNUK%7&28=NF&v|$XOA8tZegJ#32*FY zNu2;O#lm`G&)QC$l*JV9v2*x>^MFFxj0~-fl~LiyI>i&EUF~MJheAQTQ##FIcyCrFOr` z^s`_lH#u3{Cv7dV>HU|x+$^rs?|Yl-H*&?mw>URhPjzES7K<}0XR1qUnpm9LSkf&k zL#(B(Q{5_@y5ZJh%_iM9|J7bvAR*5s)}=Pc^5`(Cc-+?`8vcm2qYQbc)V_y$nyIzD~=x#-KlC(4R5F zg^mUHXZUV0!iB|f%Sm$)8`K<508oz^db6Rk0|GT?v!S;c`c^~V2L1Bh+qd<_nxOaf z=z3h4FzJQ;znqv6+#6=v3nx?D++?SAxJj0^QMNIsG@N#R`XbCfb;6H*E}* zT-p5TTkljc(ycIUXtQPumj)ocwYkN!IkMDIqnR>!Wnr6}q4U8Q4bu5URJ(INnPfX+ zkEkV3dJA$s98;5UJ~3+(a6U;}jkk%~>%M-wbgI9h`=gSY+Zj#W61%YBm6C48(R(;< zQCyDMB@qCdq~M1=rez3`QviKy2TZ;Gqm3`WL}t#^bn#k5USc<03QOa^Nv6#A6yL zyg1Beyq%!ag|7wnX1qA?@?l3jhD+h?fZ2@q2xzv~N~v_d2Nq_$0pJmbcpM`tyuXLp zjJMz5L6b`1JqF5*hxIKNjj=^lkd(z-RlS<(o0cFP9X~KgsiT6ItX1rn04S1BI zzf`}$W5yc86;OzFbe8-*9Q;cWn2t-zow zycQeYxG8*`?NNAtX2aVH+8kfXQT>BWZa-+nBVYOZ9oU=GIbrgbvqH+>S8aGto&)cn zY8X6W)9i-Vp;&y=M*q4@E1fKuYyK7E; zdll1}^^|#GaxVH{@g$jsQg}SBbz{$_jqzCf<(-Rz!Q}U>CF#FsEm^X(Okc|W@$1q* z!WafB`914?d@Aqxz6*DsuAV)6L|al2&5z4F=^(^=@ACiu_Pz$b%IeJXy!YNfxJ0-F z#E2Mg64ZdG0TE+sYe?V<1Pg^&vDK0gf=LAu6R@FbjrcLxYKz)!UDTF-Y?nH?15~;) zm4S|J*X`K(1s%KA?aXG{PW|fa#zNbuonim~bI$X==RNmcpxXWIbbfu{=Dg2&p7TE+ z?>Xl^-)B!yU(u@eul^QnL8HTYp~RmzjigR7cl{-IUpJC^8@CQ#v2{1+g$8nooiq=O zlrH0qw2wA!9DL^Wl9I>wmb_7>C{fc!<#sh@pG&=w9`oJTOVYt(i*j|jAC9DUP#Qcu zIyZ4YxwCQyMp7Ab1FpI-HGk5M5#8&lI+1I9GR&d{#f18~^l8vIhsW%^}7Jt`hbRK+QE^<;6aI z)2^N~4DYDKyU_O~LO-Z29Zb}Y!;REubiP!QegQL#Jtadaa1Z0Yc-(JEmj})JtK0XT z#9g~nxx@<%^z+zP62S{J+mmy(scL5r;vVirD{q)`!(rS)-ca*k!*`C{KH;>*!F!X_ z%RBGG+fZ+)We@KyJN&?2-1qsOmWrtjCD#SJ%H{{NN~iy)p5GiEHidhBKKzOJ#KU$29-X^%IZoz-{z1LiedqD|4U>{-kh6 zG4FeoIotNmhZ@g3oLNG@YWjIMYE92qVP=wF)oK1T?r;BU|CojIaqoJ<+GRVb%^znv z1N_1(S5#{8icW>4Lp8XqxT0xUtHP}6I`|vZCI?47pQud?;$2iFhk`0KgcM}{Iaq<) zxRb*@?caRkPs z8g_NvC3tS=PT+60J2;%+j4pn9236-JhS|M;TUDJgM7u!WM_z_oZON4nH!K~0IAKGS z9!%&EF$|gRr1k-21!33s&;qw--zZ%U#_G2-7Wdq5ZJ2a)V9uGjQHN`ATlk)>bsAR< zC8w#H^IGW#@9|c=9~th?fAzObqYwf$ylbGhxo^=UH+Jp?;iPKGWm8ev1`%Jx79t(P2WATVE%+`>h0tl9mCv?w@ZWM z+hZoA-X8rcRYNRCUcj6`_kO8+GqC$Zv;W`+l)$>AVbF@Iq1`_e6z5M76fAPx86Pin_BLB>dtIxdr zueIO)@v-Wc^1|`Gmy@gm??9PoMfnB|+=&)o51vu($PbR;Xc_u<`;xi4cDH^rv32=3 zM?Vwny7QIM>h%7$JqJe8>YHz3=gr$e;_;Dm_R*1&?D8r1;crll=VcRe!CQ&posGeB z!R$9*{*PN5N=x1jlFv6hxA*ap(mK>qS?XqUTt~n-v$jEb-;9m>bC7eV>2%12>mabE zu zRc%KWOq|$*n_*isCa>GIA&h6DSq%pYUs9CCJ4;oQ)IF>d+B$bw{fw-&fJ=7;2EHWv zyIaz{y}$d&g7WP>6`kRi0AB#KP4<;dWxNv8OLED>jGfBXbG68^GPr3R&L-%F{21Jn zT$?j1P^xs=B=p}c2;ZT-=Duknil3SNXb1G;uIemfVD6n(3P|BPjI;Ks8KaxAazm9K z#9g`%20MeA#Qpb;oKi>sN_5+RcyyC${xDNnwIUWDHX*X%KPC6-Xxt#IYw_2T=@+t{ zO;b%wvbY8Nz$^6)bdT_<%)U`eg6f*B6|+#9-^kQ$X*j)ULQ@se*3|EreWP(_d+Dr} ztx3p}Z>izZriRy24H>PW4)PnIm=^Haq$}2{R=;$8N%eej^eue8?mrEt?R{V{$en=|_!xdG3|vhxq^ z#TTQFcZHKLL5VEMP1X0w2UR<+sLjcH2#}jlgX=Uhev7}y<51LazdMnG+KRz(`pZ_a zr@eFHa8LKh;dJvgofC$8)|_&9Omk)D1=`oz`Bk|?dw0WUxx=%bxG9Z(o^~ zoV_`5e(9k3`klR5T|6p>Tz59UW9QV|oH(y^(B$Nro7F`LN@^gf{_@Rg7M`nu``d2b z^VaQe;O?3G>vGdI9`9EkgYWyq;bY@jCIX#zO)ZqlRp?rZH()3Dg~fNm+{K*LcQH5E zyO?R0MGogp%wlKmVb+|zm;BIHogPR}u3n?^X zi@5jfJ0&+MSE+sM*?+#yKbbwX{Y>Bad+KsKu4vek()Y2OTts_*>*+Sp{QSth3iT>u zjrYmC_5XsBsZ=TZmZ_0H&Q-wD7i8M}A=Ut+>*~<||NF9?z^G#PV`sudNW1FLFML0C zG?o}W(P5$cv0Xr}5sRmfJE}(a`S)GN-RIwLJrfEHKF6&SvC(Pb{r>k`bNnod6-Tin zDt6y>G$uYJQpQuE`>tJuV)t7|W1$R9L|hXVPrs}_*KAv;k`15uQ0%_zHKA5@_+<2_ zdHB;b{<2VOTKHu2&++un(fUz(a5OEVcY6PI6yE6(7@m@9hUfnb?SD(CH6wiDLlSGy z;^{Y2>vOKw5OY&RTyqxJzd-B17?zg{B4s>r%~@Q(&Xdpf_D2dab;_l6T*DFJn zIpGr@k~rZ%u0L0YFUr5%DG^Z;qi=D2cQlT8zyE#L5jx!$zTY}p`S?Cp9r}gut6man zT^>I1A*tqh;WzhBN2PS0r=NfSw5w3)zUjD}%?+2Xa2bTB@cqzHDOu#{H+y)Tv5P3F zuJq(r>h~Fyrz<06JSEjqPk*T=|DY%TpvH^d#|J(A{QIC;17$<4<>3<_l4^yAzrvGW z<;kzo{zvs27E(BrR9AcYSYY8$QeET8vEag?r22>_|A-@Hc(3#1*Lm{7_d7>lsa2kS zn}^rtrEi<3pMQTd)0gchL+$dQ%_LT+#`B+DFk-a|-RJBABvqH^zRMLOJ#O&i=04_y zp_W~U68g8^)8_(}h~4dp-SLPruL8 z@6-BG{n+Q}Z}jvxdiWbX{hK`fo3wuPJ-Nx#@Avfkz3}vV`kOud&7S^dPyZ91{wF;B zPk8z_d-^wf`Zs&}w|M%uc>1?^`nP)ew|e@wditOA^gpTfqxAfwr$6B74|w_mp8gh3 ze~TBMEuQ`zp8g#k{vDqFU7r439{ydP{@q$0S>CN0Ewd74pze-DcuL}QKKVA5X!%x8 zevgNDkG>m*N-3>>kEj1BPybW;?6pY$Q=a~(J^fEBiIKtow5NZs`kb|4lPOU5dhYM_ z^zZZJ_o**i4TFE5r~esG|1Rb~dMEOx+V3LpePKM{&2)eJpAFk=2MaB~K7kPZE$MXzmA?km|;~)3)Kc&hN3dknIkyxz*$pDM>}axTVa)YUN_Hw4G{$*LQ?5dFB*%8h>&>OoJw%gQUD zTaFu|zT?UNhsVEe^-cJusy99P_@s&7OpRBm5cO~H_)mbRe+sn%8JSo_0RSA zdaFMIN9E{mE%4+Y^7vkl_wR%Mk|+O5kAK$Ve+r)AU58&e`fqX;D|_^!4Xi2C;PtxIA zrM~0Ie{AJhEpJnAc=9ANHp6G~Z@W6j@?2L`j{eQ1%=ng=K3Bx#*Q@J1`G%OhOW#-T zx_{Klm%*|e{hR;dx&NM(U#sQo)sH;+5i2*}k8Tx=6?Bu{r+WN!@Qj~HpBvTtVmxlF zwmjojuKHA0OukXwYWW5&ze)WE@IrL+Sj>IDIvC?Os~2MYC)8^(9_@D|Ji}-FzeQEV z_*+$-<>y1ETzyh4itz)gHKxBs^;`Zjt$&BQ8@v$xcsQnims0K`E4>%Zy^jwkRX7*% znOzIH6$?JFVgWaNty_)#W2)Ug^r`i@#&~_x+W8&rb-6a)INx_c{oG3~QtMXBJ*(jB z=c*3>Mx9<<(9R2p7uZxVpD1w0Ac|6}ZEWF96OKY*=$5 zM+NS)vyPYdTi}lNj;@<zT)o;wMhj&H7a{eoWJ=&rq7-miD7a975rz6IFUqIJT% z=X-iP+ScRR==mKRv1bmTYq|3dT%CC-K*Gj3ycG-A;=&;dw(IR4-1Tz3*-VF6h8}hp z`!%Ysd+o-LxAk%(T$DfDB+~+W^SKUoOcUN9(=O-M!ajtg;I_qHeXluh1jbP<+=7Uk zpEuz8=iW^{Vc?hd&%$7|} zZbZ13lh;zu+tkmkL`yeq?C~xvE_8)s2o~N2uj8w)U0bmkH(IY>m|MBDiPyek_eX4Z zn7IzyPad-e#Mi|}6{!f~x6+#ejXju=ShCXE~8N~XDxY~ zJu{j6ZgqCh*W6o&+!D#)7}()9_@~Dt(~Qs!i+Gblrq{PG{s*P3>(>ee2tzJ)_*X$}olAT-Ddo z9j|2~8G_KX_Ijd+>ae=1uVYDD-$uKA#!UfJZd*`Su3z81A?66hr|4zaOm>D8xy*!G zF4t`7k0r2Ji#Ik|miMCon3r#DbYZsP3twV<$C~zYKKG&VYI~+gY-6z&FKcVsh`qBq z{_|Efan~51wM^%KKd*_U6un3j1+TpWnTIhoMF&7`(iuygNRg6!Ve%A35UEDD%;hOZ zBCWn+^ZM1@>y}I2)ENmc3`Mr1r9Tpyur_vK&!x@9aZM{RYRlK+Gt|d?YCgTDfHJaH zg6wETTG8fCo&HU$V{ZzjQMPI08gtdM;L2r9*uA~1qZd26)~iL!^Ev%eq^!2|w_#*x{tmvYU9QBQ(wqhgO3!W`*Jaw-m9*w@N;eaR;VC zM)2d-SGRR-%ysuh_NWqdrR*lS_x-V{L#Nn}Z(W=IT;d;1zlkP?8F}YD#{tqmXI}~C zKUw}|yAS*ovyUzPs=0GA{hGP&Ed9C}KTQ8pDbB#8|JmHLLplCyyb+p^|0~V^jqw+B z+S32W%neq)Vf;U#`5UVbFb*4}-?H)ek%>p;+ZN|vOgIzIF-U)i<{9vp>5Yw(YiQ!mdhRJqR|cw==2?Ndg(m#F zlP1#PQ#9f3b2PJo+D#Mge_+j@z)bv&*&CJk3FZyR{}6Y6(ZACJliqO8a97sY^h5kt zf@i!rKEd~+)9qZFZnZZ4Gpsq&zL%dvm$-P}d~bBGae=4P=X~Q2)9oDU!G1PP_^;C+ z8#mui-lh-TFC)&6EG{N7Dl88}RdPcp&5NyhNq~`ixWCk-f8tCnR+aBH`Gj~G>cd|Q zuc-9<4PN?kqhHxz;!`=_#tR!iHQp70$)5|Y{bC#6W)rW9} zI;=4HI)OJDuM*}TzXhVTt!_f?a&?--X2cr$l>9|rgnI))dl|i zj<)RZCwa83H`Al-HoC+4+J@h`aL&h^FVvei^K-$wK3V7tG<(>>Vq1+g#~9&Xw&h4w z_)$-mg7|u-mG@>_bh$Pe||@ zVd3Jv;@~k21n(nwcJW%lv;8Y1>B7~&F5WQk7!QVz;S#)FJiBC-7xCDi7Q8Rv*~R-B7|9b5={7yhhw*d6 z*W=)^zae=470)i-V@2@3>EZP|c#MzWJ?G)EFIy;lf9v55IC$j_-Y-17ZxzA&sfV}K z!DIfC@L@P17T>3e;9-~|mVVnDJobkLuhPT&F8D(47sCWGyoVe-=0m|l_cs>4zXM;W zys_KtzTX|dll;v7uHd1&8pHb~_(Jak-P{=7lTP?po&;}$hj$b_%f1lxNa$w9@D2fw z>GA-6mG}wX77s6r0{aN$LW1{64{s27Stt>Yrr>?a!+Q#NJ&+3t-oqZ=Fz_0nM7(PJ z1dsU*|HCxnn!lCcg#>S}hgWw|gf|V!g7@D%ygPwc=>7h}(|ZJZh3d7Rdj9snU#U0F zb^LwH!{ge*PKkuoBRdi41=TRVSp>XLe8)r2&42yyw-)Z0ejJ~W_||!N{SY)jE<`=j zOb>4d@FYJoe+gc*hxa4|T<<3&cvpCMPXccMN(>*zIRtODhqoJrV;$r|5NqOj(r$d~ z@nMy8u7if)^?P_+1IO|xBzPM=yawP&`9M|-@gDH->VelPU{;UpXFR-Rz?1aDV~F>d zhxZWh=&z8Z-}gPeozQdhDa4xo+Vi*5iN__-kaT(3!#e~#ekX+l?`IxfKky`-FNLz; z@%(K!pZ)-N{7wo9-oJQw15Wtf3uVERwY^d|z6iXmfLT4Vr@~)1A8Z4jr1Sf%9>Y7w z3*QLvS_oiC(z(vV+X=h|=rEsh$C`w1iHElYp1Ada;4SpmQScq71*_t6AR3E$lw-nt@qTRc2h0=&knj zYN01(kBSn$k3!E4-!dotRzQz<4Bu@YUL721Gdar4!$)AQ!yt9$qW($~A)d zBjNkJhu7oavCkoRJTuOHAHBfK7Qox>;ca!|dyRv4*u#4Oc=St1!uLZDZ<~Y1z7yRr z{kZnt4d3UB;JxnQJ>=kB=ip5!iQ_#2yh)G?(O=Rj(1S=dkOA#*@VG-#!dK_v?S`W) z9as{)nI7Iw;7NXNgRbB$_wWXR=YBr~?*ks*At!w84&H4Z-cNwXewL8DkDEQbXMiX5 zO9zxCe2;i|uNA?2$isWl!MonUd&Gur$?SvBjy&FIA_cRZ$^pyB*nDmQu3H0zk92d<%PyC`>p4qNG z8NJmfsdrNWJqZ*2mFKMm^dwAf__jljZqN+W#CS+r(n6m1TD>}>rplqm`b>xz{CyjG z!0HkE+o8vPn~;QW0xZN&%Icu>H*hN?dNd^rlsyT&p3}_zSN{l}abkYtyLItu&sOSN z$O}S(cj4?gS(i?9uI`*m#leZs)qMnE1BK`6PQ&Q=DYZC-ZE)<8vCZRZOAk)PNn+_G zX`HnCxyCbdrGq6OFlWX-(U=%C=bg=L#pz-m;q0t~xc^a~#V9Ag8M~5&JXb4a{x+u; zPif`3W}b63abIb3@QpLJK0cDFGbq6~aC@W1%QhU^o4^TmbTfJ%&P+r%8mA_z;2Zj6 z*<L>^!{nU7xrJj?AI{0zCZ2g}+h&pkf04kc0R zx#Lu(7K{{l-d9|XhK)l!-zzRJ)8S!T%8*mIVZrmg;`-yX{xngKwVtV;@$}uV8s*&a z?NYhRKt9QnyR9g?pX|ved*Pq#;hpB`pXTYK(sL+@R%JYV6mQ<&E`loAs zsm~SUE+uipa~%H+R}4JnmWX&>81qX+m3rM7dFGtJI}IVJ&Wcp=lvG)LC!$#LZMffY z@_izNN&bG1{|oTUzx0oHCVtf0+`(YvX%d%K4crNB&#ud>9#?yR4k!c;(1{ zJ7fH5O70+J&L~Izkug-Z)5`JwM>`)-;$^|pKhCd|BR|x8ajcjdxQ6qU}pSfqBT*n$NMOsMS24R`&uv5NMs*(KbOg{-nQ3 zVlKyafDg8d9mwvyspKj_}+OtleJ^ia}gd6f# znDK-3A~5f09j$qRg(?bvJx`R9vgj(hXicx+iWH=r7KaFnR^DQ-2qnL06~`-FnvSb) zipOzPVg=>6nr@kJ7d%C=VYc^5MsdY>`6#RxD<#JbT&%nl*OUTcS6=Cx122euE8g|O zC$?hvO_SCt%a}{d)1)f=s3)I1Uym}F5WiqwfG6qU($cY&&AsfkUH2ge5@ZO zd@tkK#d{KbA-tc#-o@iME$dO@vAz^MY~zXH4MFC%pC!K7mJ!3l6$jz_U^)ukdpx|i zir~%l@D#=m<^8h9B6!%o5ewfW@YEBM@U?n)97h(sNl+HNdptaBFDf{H%ylgIAC|ZJ zB6=@*dM)6Y&O-E;6d<53-a0V+E((d>zrfyoZy6^Z?CD56&hzkg!X4YYLXs|Qi@SIn zHh{r9^6%sv~jlZYcP*3QEDgoc}ndf zelV3yvAJW&^@%Xi^B0Q0f*uY)?6(-vja9GKL+4CbGw1JwYNw4)(V zpEy^IKMFI87cysFpazh!>S6xk&kzKd>v1;Ye3*xRv0}ocRTD}hE8f>1L1M@4yhpEE@bNA>{)d2H9!`*zCq=hi&1&7j0U_Six z;*HB-4kKT*Soun8UJEk_GIgymm-XCs+Zt;>sV7ixA=6dBWJNHQrn+-Wtu_aOg)lEe zn{)}xr%<4KU?zh=ZG_o~eA*9F)m){Hf#lsw+WB#Cb*Xa|<`k*(W#BNL%;VG11k5Kw$SsRBfDYXXiQWcSxO)7CGoK2H-sfQ9>TQD_^RJNT{Ut1@ zCvAnVL9b9-;c4igDh}HU6TzHJTY=|gJ};hHzsR~_BhR&ks77^rdpvlCuTWdz76|?$ z9atg`>B38kv=uJOW{t%BomE#ickbM5_M%Jd)tA{5w-xSXr^0C~oQ`qQ5!_pMy1v1t z1~&t7Mr}>)_`g4L)=PUQ&zSIHQ1f6z<>Dy~z56E~RcB3YK644@@k)oLE}7aq^#VR8 zhE7|ehNdi;f;q6SU|w&`;HgW^ZIw?s^LoTRUQ z4DKKs(KlN?)R-JJca>#ZM-DKcV`HP>v~dVCYyp0y`*M0NuT;+in!lr)OBa_eoT6hx zpGP5Pa&MP|5I)NMqQX6ir8+EVvoD^o=J^}0s^uMqWw`e+Nb>H(=iBuhT`TTRd}7R! zq19FG6LK^51U0Ivy?siqG>1D4YgV^c5?}qe{set@J*5VpJ*bE{PZ-xP4@)dlE`Z!6&KtUvRHx!5 zgos#A-X5{K-h9C0zvA)V^Z3_2zEmn!*b~3j<7I4s@#DOi%xf8bwAu=NI+?HKrRwvZ z``sS@yvK9zi4gri2A)<-8JOLM}x2X5I-$E*6+@YFx5_ z9UXg9ac@z{*Y zH?HfLedX$&KE^4unU!Z_4`nk42ex!$w{%BaZ+j=t5{O*lsrY1>PQdt)1%*QI%wr*F z^Eq#`P zHTin1GfBukv9ZNsddy37H?67wF%KpOBPHQ>Y61M@WesKXzua6?oa@0V5v zLzBd#1DxycFnIBcilTSBr*{j6}-Q|vx|o#np75cLK40o!NS$!m^IT>Nc5hAh3jtx7>1wzo`RqF z`zt)tUh)Cgod^c3!{<@3r@s;}>XlK!lDOesVi)gg;6+ANd1jvu|3f_L(VdX!&4j%h zkE|09rZ@HIj`xiakNJ?a3rwN@>T=j4uFP_p&On4N5e6nPNdDM1_W-RHA>{H%Q__U) zTEJ|B2dFmn8DtC}-#6nRX^cnpbM$|&aU2TXg|q4|%{mm0Z5QdU@>6TnPuyRfk2)U| zj%|;}8`NXlNI;HjmL9^W7hcRIyU?xz6&m**3mrY~-G(t{qyp319rtED{*dF|!NT~s zcd#fv?p=yFaon53rX2THtuMvLy+3wTk9$8h!yEVhnEJiOy%!c4_eON@0IAAx?;riuJ)d#Mz3)|jr^mhFkK(xZ;pB{hr>~RfD%5Z``{ClVTkA=G>w?mMwXK`Gk2u<`!hGKiF;ra}-1j(Nx3 zyEQVyH^!5*R*Q)1a9v7b#A%wfm;`eI++SgNemmSTbGA_@!2kQK-0&&&-z`rZj=BHB z@@7mO@kb-d?;iPs=>=4NpB_~4?$62eu+Tp`sZLVSKo;}<9go}>^66wl=`?cvRM$xw zj{g_(BQW$^Rcbw?pM274jFv)991 z(0yT6(}~)3bLP&%Yy|1V?YiNy+PAP>cP`#wW?w2d(5Z%l3`gv=W6{fk6K_%AVO*rnRQ(nG99?_TkI{Gx|QZ`Si}=eOGp>>aug5-}`7|`p11u zWt}fq{OrSbG$vlWdFvgG$>)OEZ@e62hYu+JK;_M6bY}J?a{qHrMd#3-YdZh?9yRU3 zy@{>c;i3_LM?DwJ`EsLr1Fg}+Sa@)Na~ThDwnNW2WIHnlDsq_vrT8g~{~HQ02chQ< zzy`pt=m$rtN#59W;~h6n-}Cg1spe#BrY70jbH#UV3|a%2>fo>c`U^i#VQvL$7G@+4 zCKs!!39Whuk#VaWuDxv*%-cYo_w6H2c%9iwSoyN|8kxn9^Q=BUlOY5Hy?5w_mAuI zMoPCo%${yU9QTjwPxAELnv~(0?CDR|`q>bYvqTXkF-j1}KTYdLs2oLzi2H%!`loy0 z;VQX^xF0C4&rz$0xF0AkKQj{IiTiz+J`tUTwxJ>B9Q4K_5uUgoD6XFkHH?1N)35UM zt2}wN$Jgk28`kyg_m?C8Ug~J@Z7=os4}+(E7C+9DY=9|5{ab~BN&W%+sL!0w{YGDe zDMa}${3z!;;ylQ=EzkIIKhfVVuZ&x4s=zsKs=;kg|7foGEm zQT`7eKWur1cY>-4?_=X~nvGmh(;hp+xE<%r;z}}^o6)<5)|#mY|HNL$);v;~6A*dV zE%7!M=PD&%$9jU}qGgYWJvrJ;0j-tWnk*Zk(V?BsSkT|q#~WW@#mh?IMSP;eOswQv zTYX$QgL_C~DIrjtnKA;o&jY@GsH3+JH`G98c27Q`=zPYO58g9UAQTUeeT%!!^Po+snNg1Iwar9g(vSMsx_oxovCoeUaxw{e3542$No_Rek7iI#k%`! z{N&rfGK8WLe%tV<%UhNYmISX6yo=Z1;PJaiOyaG4cAUjNmng$f0iIpFL*QHR6B4}d!@|Yu2g7{8^y7OLynn{Ci^u&U z48M@zy$TB#ZyOkSA8Y{&UOC*mc-bO&Y{R&C4>@>ze}Y%%;c?Dsngq`3kzMTRaonKL z*hUWauD?6LNWN#wS^Qn=;jIH-C|x-3-Q^LZV00u~v72;Td{-C$sTm ze3>tpc9JG|RC6#a|E7R|mq#;()PK@rNVDoMJ?Sx|LniUVF{BA-y~tQmP@BSuGBSe1 zks^^S+hb0eY1pIsvr`W3b#(&hneh{joUGh$G#6^k={f3}F_Z+xP&kfqXm2S;n+{_1 zBIb%T2BcZR0lk@y^z4={|>~q1Q5& z7<<-E+~bl$k$%^$;(tr)pIA-+;Ky<# zBzW^-;o`jrJbrtLN4J8v3ePSc+p2DP6}*qY-o@iSJHcbP1aGs4_Z9FgheCq42^KD1 zDFBGW@VRZ`FMwzG>hL4&!mrRbdI#(gq#hWWaE07SeWNq*cegl#Nxw)mC9LGRS9k}0 z?mOW#;{bm{ItoY6hg^iGztI~De4}wxTpg!#>|fb$GW*hcNJuB1=jlPa02F?s&%m4E z7xVmAhv#vgVsh>*J!{ixzsjxpTl?PJ?40@D4$q@@0=qJXZx8g}iMe!6RnbGcK0;driXGTD)E zEp#uuHo-FPc+l3u$zIXV4y*mfzw^G*0+lY0r0=uCjX7<{OlrX5B;1wgctN z?_9IbnuT&w<#cPF2lJh`#3JG2g z7B1d*fyXu=@#t3Y*5TR3h;A2;LhW9=}DD2}$@k9_xm0nuF(#v*OzFSomIoyFz%Qq37bw zbnsXYO8BZQUY!llKfo;1#-9N_w~c=#_>&ojn*)D&){&4r(v-MUb|)+j!Gd+Hlo6&Q zBCTCy{B>F3`YF=~NFwa)8Dw&@XPmu( zzJ2Vkq;i@4ONWnLq=u56!Govnr(Q{}R`+72=YpN&C+{iS6Fgkgn%Lc=#}gYgT1hS& zu5PQ%)gSod>|L1hCF%T!=wGnBMU>L}eVA`q|8W0z4a`W#EzQjPqZ}DgM(O&E?&&50 zp6*#z457d|#P#D5HU*_xAI%|4CUXnN_2O~;wAQZ`g;;IK@RfP`Wmh3b7=6}u5hY`%$}v7?=zVvh!Ps7dAKyRInEfNx*W~LopH_Fl z6r%p;@uPeueq47XbCY~C?EgGt<;;&fm-y$FXZX0z=(m=itNBT)gkYA4&;4bzV%^Pi ziO==qrvKC4wytY6j?}^071I$~^nsRDa*ih!1Ch1oe(DB(Q`?tB{CXIMH;5=3teE^ zTwLG7+9!Q6^8w8B@aG-%h1{$Wbt9Y{5?PvVsFSWb0gofsx#2i+lMRle5M_wtC^`AS z(aO&x`ND!-F3BT$6^mCqVs<8W|GxTH%+o^5=OpH9w|)CL+rC9NU6%#wF)!!vV|657 z#U*%l>vzFxguRRRh=WJBg2%CV7q1okH2j1F?`l}McwYlZ7Iq9D!zFk(7hvJy{n80v8DxU@6rNqYA@Gz73Eq>i zaPi7ecQBp|pWDCsNAND*FTodjzkd&V7jF{qs7E}0b0mE1=eT$&FcK!H>3WQ2680|M zOecJ9|7x0t$Fo)V-4kNHNXmM6Tpu9eWB!ux$sGgCL!|e^9qV2p!Q+^s8@?sLV>}sO z*0qAS6naco=@YF4@5Wc2xz_h&^fo~c|HC{-yh8oIPr@F4_CQq=*Zy823`}B>F#Q>Z zjr_HU$7e(cULI*m+^I*V6&~<=g3q0f6XVY`k+|YfwU%I=hJb*VM?J^WwrOKG7SnPu z#)huifHK97&6y07ACR9$B-{ocn%5_JYi zFl%$k-E{|&n;XsxUWDDj04IdeJkjruvo|L1moMNC(HCQ$ibzU}v0+~;E|*d(@={OE z5*88rPI31pGrunsm&ZBwed0FxeV@48{Swmu$)0=GJQ49u znz(zn=BE28p4_eJD4*)dqh2U|;TVFPD<}v03&Q(1IQ;72K;79of@MB-=?_dg1{)#X#$^XvdGjL4ze3RS*;`fa% zw{qiunOZ?*OT_Dp$;YW%V|+$^&eP`^8?-Wb9@{h;lQ`P;R-1H5l;*KWB?DZMaKh#a${GAAFPv?QqVT$nbnN0k%+-M)(nGHcDJq|SZK*_?7$&eyhJ4CTJ&^((z>YI+hL-PHXc<#1 z;8{z51nMS&YwuuO)z{I|UnnJF0>=TaX=(3R7v0ffKX; zr>j|xVb+*-9OwUZAK3P>IWI`!*n%@EP~~OTd_T;0)aTYk%qEnS1h02$rBUWDESHnBqSL;d)OIp& zVb_vli%D&EDkcsyR$&FnqQ#`gMR&4iVfSu+EUXb_!NT%*j(gWj@BU5AliDn~+#6dhHCAHQMzvE1?d%kPl1$X4T-G9kfR3=6j(wG58wo_KUCcpLES;;jWw zKZFGDW3X`XRsyURcElsD;C&j;F5VO1$KfX=cz*^97jFO{#33H*3&GokXBY3Utqg`H z!P^PW#gltsiO1HZ;Qav4F5dU842CAbqrHo_%?TglBY3ak*~KG1WkQ1YPq1+D9&+&5 zeh@rdc@V?9$V{z_n3$G(;|3Z z_wb%^@YuQ+ydPLR`+3u61{E4-;Mub1@Atr|rmMi8%s9g!{QVhph2)W@D#;hFy+B!MkwQ+`{wB7t1PAGprzMNoQR;r#`Fc#A`{PWni3f zhH|XPHS@L6ncXt)Yj$oVnyWjfw8|MAc5YXn5+1q0*(ZOrD?LpamY4E}=>M}n8IehF z;o1L>%SY+4x2TsZrPa9L+-h9ERO_?eFoaC$5XT4N`mFII;`l(k$6cn^LQsPt4Pqm& z%&(_Jj`76tgXvmN`kN`eo=B9K&ld^X4xOd-m* z<3~Be$Nnw9TSAnZ{@t3cw(B=^_igNI5BL7B?&vk`#4FZyuWnmsrotLKdbwjEwz^Q; z8L{0Zty`+FHtu691w-2y9u^c@trQhkNI3`fcbdl>lC6MX#sxxmNei; z`Y!O8M~Fwag4cm(7q1mO^@Iek4HhomPk@(&9q|}0!Q;4=i`Q>uFf_@hjPp${-tT}% z9O5xg3m)f(Xb-WbTku!HL<@PAc50p0!d+u93w_u3!5&yWR!zN*hm-lPr{K}|#1Tx! zkwjDCM4s(9?ltB71Ir%6$2c*r5(hjg?h!f22TOu?;jH>u<~wcvhVutSzUvpyy4bb@ zPW)Y8X)<0oe{eQhAEo<}dEe=Y`|zbcmdb67%^{3loay{v=MA~!)17*bfjZfo8cJjn zyUltqe&4yPvuBUmN@+>1RhzX<-`m^TNt@cHLwoBF)a&!YsLfy4lEBUsSzqSvBh8+q zJzgsO-nyIqwD$9FR{!0h|NgB1zL8QrpOLQn8D=%g>JmF^?s| zjd>P!2iM@l0sc$CVl2j`8=9A>hW2Yd%h#^o`JeW)qFfZdn}p@Ykd$)66>A^O5%sWk z6#e}6QK*WClW7md+e_@xM#T0`T<+HJ#Lsy0C}u?Ad`aAW{(MPX&YC46&X>gH@zxvX zOXBhh-M+gwgm7zohG&YWZyOF)pYtbiAKWhx-Jj{n&kWm-Ou0bMCWoFwztYpM4A0;21vUWVT=3xns(gSot|xo>pB{wnRD4ZxABS^B083f5*Bv_+{#)7(Y(E z72`8X=2Q6Qxwh`T&PR-R*MX-OMm|Xmc=E5tVBjg3H@~3z^i#CWE}->u{ZaR`*;jsXLqkSwH>1f z7IOElaUIb}s!v&K+pq|;MERkKlerwX`3=lVs4+Fn?=}YkkRB1a2a<@%*MjYHxzY_CZI$XjxczmPjcctgseSBCj zpu=^!sbkag%=)f0I&Pdg!`^E%FNg52BYy>kFla6`eVg)JcIwpuH$5LF_@b?~~QOmti|Q?VRZB~}$2SJSN&j;rVu{^RTRcCYX1 zYv0tpsqf0}HF*c?IY}2Q(8V$RRmEP(_lt@>S`ND-&DE>sYp3C@O}qJ$^{ID1%5ny> z9KXS%@FPX-alF$5@_$o{RSwc!?u11@F6fcJWp^;VZLl7|z%6 zbMgL*mBG*?crSx<@md``_Mjxbrvl8y+iPVS41WY~0+d|5P6v;5wBT{=tBdz7$e1od zg2(-WE?y7th{N~6x?Au*=HdM4Cx8r6&hQ-1bRtl zY_SIX$&4*#;O`aC6#~2_nvS*N{R@W>sA;gDfgi)i{Kz=K-;kz`R_a;DLh$t3WL&-> zhs2#|Y;pG7lRqP_0)B$Ru|3^@eLm-Qz@8u2x zdyYTO+UKeLTDNrHsOB^JFVead`@<_9J3^xSxvxy;9&GpoBGXEdvYGqTNBt!fm<}2ND#+)}E;87jNoEQUKw0<;7BrOEvhVz$k{Zg$TmD%WtE;wEn*T>ziu#fQF+JpLKo_?99A4lVOUfhOX zqlh@3$NHbdvc3>8ll@al-Uza%EcNQ$@mSN_26}H5MMAz>PIa9`$f~S5KKhBS? zf+C+t$ml z2&7HRn;5GPajMw_y6`olp)hu#to|PG3>lWa1U~Z2hm~iV?^_y~iusB5Y)^cpPgpOs;e_wqg<^dt8xo5({Z3}HJF?medrPO0yS%@Etw$$Lu@SMd@Nbu&v!o}O+ z;L)w%t;Vy9*8|?Idj;>K9^R9{V|W-onu2#5o?X0Kz-RFj5u%&pZ;|X9%9%)LPDB1yw9k4hR&m1pc Vx@7QUTqO>8R1FYtt)q}U{$J@hb2tD1 diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a new file mode 100644 index 0000000000000000000000000000000000000000..bc0ab389b7e484c90b771e200f829421bcfdf5f0 GIT binary patch literal 216622 zcmeFa3wT`Bc`m&6%t#uKWb0;wEE{{Ik&W;zvMdr4+%TGv#*#+1gd~FlB%0A^Bn_4{ z!_1h-T*ak{lWs;{a)S0&Q#upA&j;jTNw)?a9W@D zTWhbq*WMZ#=Oj6&KhM7&ZSB3j?_KY@?scEFt2RZ`v7wK7KIFBU^$i=ZSYOvr-|!Ky zw~njS|6cFg3mMdyS}1s#^OhQH`l$dGPe7X|2Nl@*D?10 z`uf`tW9PemQpVW%uGjvCvHxP1w(uhMJGs_`n3n6h@*vaXwfP^J_Pe+~`AMd!*T4^$ zM%Rw<-|h98Z!^t)eeorxeGspI*~2ut-uvVKYnP)kpZ)*Wf6+A9`#t9Pb+2!Jk~!4t zfA%v+uIqb4%#rK*Tlo2#UjOtB=E!xu3Hke7GaqG+IWDKGjQ!fz!aJB#y_R0Xoc|}+ zn!jVtU*~G9XU@5=#%+uM5^caC+(v)RPxV5W0;xILLn^+jVlSPpH}uI$bxQxX_V zj@}$kXTjE)6T{KI;kbZ79N3kOXKdo0vBuaA;T&NQ zP({`i&*YHiBI+75S^9Pk#Ja}1v*~zr1c|DLQwJa*R)OM2>uAEJv_lbBiiK6&luo8{ zh&z#*@vJSvGMwj&15Z+TBYkO)j}B&sMEr8Q69{s*H9lsGLMSmB9ZuX5ZyfEXxKrYE z#z*_R#zN`nNW3|nPNuoAM@g~PP;X;Xuoros=u1ZtlGd(ZV|%YrC|EkynufM1nvLo@ zWZ&lDWM6a`;+|b8=>%Tp5>sXiPM+rCu{(Nm9Ay^el9E`L#j_OB_)RrUk`sXW!6(x3d)sBWb!5T4?xDS`KMr*zgCPY)#1BM9Tb&e2#lk(6$9 z1?y^TYVGK4-`dz4iw2&TMLDwln#uc$&xuJEJ0-NXMle0|R)AD8(VE zuj}s{5dd8>OCS{H$hDm)(^RB7 zyE=MWw={R@4x~*q28NQiD~7E#gD8$tRceStt!Y@Bhoh-Xyq_X$VtP8Z^^hcOWmCk| z02v&HoF|zKSTLA_!Vp>ru1!Z%TXqg-6DhPh2Ca^5&4^6ypQQ;#Q(0;jO&7y>XM4tE zp^zczjt#|;jPb59ql8FRkX&@la)F3gQv?DL9MiM*K+m>Jygi!9>Um}a0~%YdK++lA znNfnuG3Wx=9A!nZlfe^ASy6lxVQZ!l^~}u*UuQZV8_jm0A2BeT{8UeJTgIf`mgz}a z^`=gy&G}MoR(je~2f+*u4DvEA1KAWGj_#sBw0yjGTTg3yH?=|3%V~*^^&}fJu|z`E z4aH+SI-}^K>{6tGL^c!8wu*|#;1N=uagD>nv*38G;~AuYhnN~ezOo1$5rlc{ILZcn;Zyg;-&VsAT98PzRp-PB~iceM;2n0Hc zB%jSD*LH#z24rW(lu(zvwi(S;+e6=cS+#FP`#;c$Z@lLK{C%+WymX4-o zn=jPTqS{0El)oS%dR=4a9VB?KNA$S#=LK9cO`HE_ph*I0&kH=5!5E=%IiiL&NwQw+Tct3#4lK|NzF z$>DzVBrHHfY6V{tOQO>mN6uQ%rq~Kc6ORr|yk{&B-PzB3n|fgqa`c#U%F$olHPV+H z?xOyw#RZrWSw)Omx2wCmRR>W?9*hNJQB)Msk&G@yAqoZ?dxp~S%n)K~<_lsGqfQ?> zVTokF$r0=dQt74vR#&K}xx1$~5KlLcq_Vq^`7yjJq9LZvY=-rr4cw6sgM{|@0D9r^ zbWbuH9p>G6i-hMkcOd|%yrc)bH9${S_m5gt#YUayXn!IpiqB3YBsKRs7KH^}nDYQQ zckoj^3Om|XF@~}URckV3+7N%<(Cc1`a6o8=kr!DGqeL-+mP)3xb}0{!a7-f>OZ$)Look<&7$?oBJJZ0)TlbP(b(H-$^DF%E`OK;Zzk)mYk z_TUhWn$g8FMXfdnAJr@BOns_hGXfz9@pg4ZM+f7r85GGxzw{=aMF*@MUFEE-S9Jfm zA~?K5uWf|XY8i@-j*4!*&^9FoyOMZQySQ8Z-OiE83l_h-h zD5V%x7RXaxxGf>bp_c?V$C8_)iP28f6aBINmn4;g)yrq){*}N!8iyZo)%ig+mGm7&~ z=uo1R2#^qNMZc_@vN_$8i0z>Iis^7d35}HWj9nW|k5H$yD;@)qMg{TNN**4;Zn~hb z>%?dXlRaZ|(3nbvMxSmtuQT38N`>KF#f$skFI3Fy@LThW1>kxac}x!kEgOE-VQn z2LI%>1#5~GG=&`#RlNPSyD+ndx~E3|XM;m1%DkhQky0><_++veWumvNqahcWB;{S9 zuEwoRy@aQhg1QXJ)GpL)T-+Ux_jjg~St?1WO8S!{QUeFM72HWCzO$d|9-9MIyt#R6 zb5|?+cj$gorw;Y7tkIdOGdf~9wR%S{r%vtlHqnGu46Yh+}r!f^NcuON=H;PJ-HUdsvA-XUQYMrb##oG|cT|YpdY%_! zOsbq0#iM&(1aHn%&yDz<*O?_2=Lx(;g*Ux59*=iMM_c=IDY}Qy9o43|FH2%z7Zz|Bra4f6Vt9SgP7L;DXkykXL$9Z`9kZau07VG&w?}^q zIA+$1D5UYeorBb|;=M4Mph_pu;paN>CW)6oFo~W7twL}BRqnBMabKA@0UUJx}MEsDS{Tas9`MlTjYwkTu|nn%W>G0J9+Q1JIXha9P)bL3E3 z-{sjJTB{>LKpCiZWKuiO;b}^a#+z@>GFYh7If4PTc$Tx8Y=GByozYB2C>s0l#-rq? z(pWG=eJf`CAsC>#6Sg|zX+1#6>_{48i1aS~nHLh2FP4tRc=k}C#$r$=IgtHSG)=jM znF0On0tPK#7nS3T9!449H1CtryO|NioCde3nA1B`S(e5WgkHu7&oB#|=1Wx=+3^5S z_$m5){(#4y2eiE}OO~!siyT^rN909kHbK3*WGqQj7+jCGx*6+-I)sWEl32HP>_9I( zjm0tesEb-q(lP0uYJz_L4Kx`W*^(MNd! z7%i)r3!i2H=aS3!tUDEtB?c0);82j3DuMy&l)C*q$@Y-BbeOAtfN2o*x zUFU4vnN6Z?wv;SgW>o7u4|JhYqpM;|66#QTy~Px_)vvBGu{aSSD*G3arw6mt1c0!mnf$kfj z&_%WY`9es~SST@&)G7HEf!u-|uRbrkzSO4drbbVjw5 zOKF6`ww*_$9kjwf+lCaOppxV7cNCIh;@fcQR^&Sg0q~t(}K|~IPWe|}=uMQ$|s8L^xBr>s`7}zRRf*Az_ z5MBq9$#g$<_h4p!R^S?Av3M%WJAFAr&NZ|Th=zUk5YYQguR{XkBr$5~jqyQgZ+%03 z-IkVHdNBu?Q@j51xwU=KOneT9q|!qX7>?I(=}Ym|S`jWt*3XhCtp)T=@r0PSr|Kcl z-i%oR-jnOzH5$7XiG=i$^zF^p4q>@~b~BI^-8~sM9zJY)35@ViDw_I+%Qwn+NF%n4eL!=Bf*j)o6&h$+AulC+_Jx#Unh8kGe zl@lsz)I?v7?0Q4dJcdPBln#h!)PY76O_FFs7|veIuR) zBHDbhz9t;;{)dscXiw!1FrJ@VdyL(C$Q4<4!ey&fLsbCx)+Xm0BXTJOm62!Ys_C_e zDpGyB!MF z((6#V&xxO-qe4`3^;0a~*t;pZGIuY9l)RHdJs*;a)ee{ZhO*gY8rB_u|tnngCwGa8QR5L|7*}_r~48jCu};qkar;FaKLpI2Rl=G zL&h__Q|t<1AF}^g(fZTHS+@E*@!LhOH{#K!K6~Q>=?(Q`gX?=Sp|dXeArEh*lulK8 zpm!)bOd3UKIEv}(0Mx(h#k7#YK-~k=DcRoNP0So<8$A7q=-?x0d&vUD$ zZ>wxO$^6gHG%(;xs;1AaubLjesqy6Zs~S%hR0HolF|!>UcQS8qdHeHtZu9vfmxM2g zjN{%h&78i-l5k0NWu!9f=Ko20ON!Vl!s7^i$Mksmy2#?8g>Ccl&c0MWbiM1Xm)vk$ z8ZN0?9P#_QBaXMnyC|)E#5Uz}263k}JN(AfXV}DZh&!bj(jbKA&<%C&5T%EUjWbr~ z_QT$U_%|*KT^z~_?dI{?fA*cJg0pNowsg_4jiL3SRiPl4JJvdmQ^-7%PW>rwlI$H* z=g7CaydnCpIh-t?72sF83y`+Otdf$LEn(PI^-*u_=B?YjJ;~&7#ygNqdmFp9c$-K1 z;{BLA^kSrgJ>r>UI&+z~Vciw$HhAmn)?Z$CdHogM+BCK}V_a6wSmTG`Z8RQ5MWL<1V_uM^cE{FkX<+&D3%1O2c=F3! z3$;bs#m)+Cu~w-q(U!TYHMTCZYa|=(!#$f8_aXTN=UKL{AEQ;at`Aej>qxLJ$B%QA zpYF_wF@Jerf$(O39pY<|qWwpgcJ>c?asl<9_RLa=p4hr{k|MA!*nMqJuw~u)I<_u` z{rA`z&ekDq*G03~wBLuVJsHZj3o=W9qW3vpM~nB^bn4I_t8gcrc-1#3lJA@l1Tu-M_(dG3?Tij?7!Q=(&z8FnMrrlX&F+Nk`XNTqpx6F2ui^f%}NG z;4b+n9I~vC`pJdeE<<`=fji|9y@O>)uWNLB4Y%jBKHV<#1?(=}PL9eDpD)5L4W;X2xQLJ5 znKFd_0PfQ8beEl>7^}&$nto>1rRQ%8a%jy~Kv(kmUw@vf);HC9U2py-LjLZ+V52c& z_b%+PA883~@8CNXX^=?qa9kwnV9zCtr-5fVV?~gAszkl#S;iREu^u$x)R=mZ@SEtq zl<}Vl8l6G(@{IoA6}kI^A3>u`y}=9V5B7*6Wb_9&phhW1Z>Z$Z(V6ioT;BQN`E3;u zh8|#PsP<_$bfl?_lpL-Mb-;b;sB#KXXhKP*rhy++R?yUC9oy zw>9sN-1)2XPyF-^=Tzmz3riOix|z1VaO|Gwukrt*|9t!tGp@6#&3Aw6*YPEoC`@VV zFZjRVOPz0fkm5k0XEz=>Q^bzE%~InBQ=4aNQk!QEdD=DKb2HzrTM#PXJ;*E2$E*)I zz0_;0VZd*erEc6%Rvd%U}(dhfvDH{5<=7kz%>O&zLkuMYd#oGVwxVln?a z=Q6Q4Td^|I7m4*P3$GZ64J->kH*;^~xtaSrpPPBG4*m7+=VqR&s|{Vo!+u#v<1uk~ zwJP$tE+p=y;j-2#^yZzXS!Q2#U8pib+66`_)qIckQL2zsq(Vx>p9+#<{0x0}GAO$r z36~stac0u{;>?@=h5n;6Z}?*cr9a*fUNUx~VE&Km!<9o6y7~ikZRL@=@RFe=Lwh!B zlOKXDnpg1S%YeJC!1?1<&^!c9%vk~1;-M1X`UADV)FNG3S7l`WnuRHeBTk1l&8t3K8 zS^MAwN*j#;;V(vmBYJ6@AUn#`@DY@0p_6Wey#)L`-=4;(XT!dfFBMCb9CmoCLau6( z`*t5a<97PS$-m5@{E+rINe|Ds{2eG?4+j<;o3~}v?!=JhEp2+Fl63juHRGaG?-<$; z@rE4xQ5yKTlqS*xXt^m8g#lc_0;+=l4RM2atnbs;K3*c`a4Czt*JXb8@zSql$;j?eYp-?;P^QI z)p@^-n0|1Afw?06O^516-#MQuQJ4mCGycnQ6uN-C4=hJ7b{zGO$z14Iy$)D%qx#!U z1iEqQcj|AdBZybg=cK;sdR&B|i^k04R^=OqeHfQClCK2Cmi~6z_}alo@svjLb=df76uxqRCEuuxZ#(#MrSpw8 zzBS;J>AXnc`@D^BH~5~Efzxqh{fv#T349UADV=FtEW`KTZF~)QL6<@%jg0R@HonKe zR|^pFEygAJp0@FILZPM~g3HYz8{Z2``k{y!d@tMhZUA4da{qTWzLyj}3`Y&VU)uP_ zz-P{t2pk2l5&;F&s9){}E?4>6WW(*V#TQm?DBo4SC+Fb1*M@rrxK%m_-Js@X91m)F zeiiYh@KJvFaFM_CUOi^xdjpCl$fY41nSD0CH^C>%-wNm@-}itcURjT?!E})yc4;V% zWPX|hC;cM5eEww)oDoUjB%cQ!UWmWm95~5A{>tZ%=D^7?5l%jLULbA&IO3M?Hl@o= zM5G(i(Uk-ae<>;dDsUGvSNRffcfz4GG9GkC5*ntxl(G9U#a0i=4Y(*CR4%BjD9+id z$lU)>97;aGEJl_8Hs&fR4^1QHF8zi;rn(T&+@lpQ<{~={ylnj?-fhFX`CQ>j18-%c zxksx+%th81c=ZjV^z+#87%wV@<|eIt_PNO-o4$yLZ;ipB)|BMm0vn!MNYglxvsV8~ zIG@QvId2*#W=5^}QjRzK2Piy>abo4viZADQQ${VFX`F144Zn!vYYhmsWTtVVB{I24 zelf@2XFx9IeF7?j)FwH2OJgXJK8tPc7jyTM283EB(>T#vwfaXbjcJ_h5}Te{4%0Z< za+`iR_s>i}On55B$-Fkam*dU+@hWJ_?zuJcP+3-G_euYiH zg7a-MP%DfldT^q*jwxMk{P?fIZY}ZDn>URUJqD}3me*5+pf{h^@m1qwm$7CkKwYK5 zZgqc|)bhI%EoHYZ@#C(+ZpEuDDTRNvO}|=qEpATCR$JY#Vf{Kngm;Y%zt)Cd%XV7u zLci8|D4Kj8Q$it&=Z8P zW%xg$+tJ;Cy_DSnJEbk*OW9lJ{y^6kaeXA zr$&?b3wXH_ebh4456g7Bi2o(*a@|gSp)$PxUAkR_-^)fV?yH#WzX^Rc`x9MHC9e!U zvuAXB6SuEmCtxQ-!7N42|10bie{xUZ6AL49VTey9C=)KZrWSI{DsY%Fp`hEa3tOMm znl)K4Yo35R!90>VbHF7zX4AM_ok!yWWd@DgXV0BUv27ZLi>yiqOnBQkk}oH=`6c6mv3^)h`gc+mjCnPKE=sFe7_n}>O3bni6w*hlP4Xo|qUDdOpdRm+bxG9a`2W<~|%l zqCTNJy>5iB#hvWcxGw{q+Bgp?N%D{G?fSh(zu!pr5yr;p4hz+@o=>2!jk{x%u?Oki z!gzh_2r%|A*~4P(*MVm0bA*Sx*GP_VPthImD#DBJ*vi<;urG^?a4zfBUI(!cFl=4D{khCFTn1`>mg@2Y^;jFJ%4n2vttle$l{h)P}p+#zRZO zOWIrB>U2~_I;ODJ6EDHaTg&=>zJkT@+_S!8%DX7Praav5y@an=6=S`mrRt0MH%t__ zEsAKHI!)@R3i8P%!JiFf7fK9-;_5pw7in<0~ZC$`VV144zsJH6aTIQ_v zVuu8qa+F`Zq`a;C7HzfTc;~J+o=$Cc;OYKdNAToaz2Nw6U7~a0C6Zd)HJ-ht4 z7lcpjs>7Z3`f5JMq{GK1ojymK<}FV_sv9j_LAD99mK<`nd&g*9);oqZTrLYPbsuxJ z9-rA%RbDiHa0#~9es^ZmdbmLS=03z~TaP)%N>_(|vLYN9t4!TJc3tY(vArqBu9tDj zU*%1A?_%{86I%6kH$AIA?Y+ryi;%s1Q{a}$v}5ezRV6>U`?kAo*OBRGZ`+%8-2QSp zaC_h+*3s|M?s)e0;>o*jx$9N~aSIT)0&%O3xb0c~^zvPS+bXln>pskQ&92cC%*t@; z(8~4~XG*H7BQMU(cx$%wMQ%(y68XlBKaYH4xH@_gtE=Bgdbd6jtsnV$^kAa8Z&_Q{ zP+#ARGZj^j;Q!L9pX0x`syg=KOifiE{&!YA5<58h^VmZ>eEm-(V*QzsNBb$=Ci#En z^Tspr1=xjweGqTo*b`Skemg%dTEH5FdI3h#ZIe5C!yC5OEs#&=;bFVD9+x8Fni7RpKv zRYvB8uNx|xN+p+u-sL-(^Z9P;*wE24&X{BMd&f%-S42d6g|LL&hl<1J5L)7%AHJTW zoU65o!nOy7d{a}-;MAnkJ@G)qjo4k+M<^Fi<=}tsI8u889DL7pe=)s+ZvVVCPxuQr z7W#uzX0@}xdmN>r+A;d1Gz)Zy^lqbahoK`ZvFy#)Fpxx|kdtlf%eP_3C z>MHE&j&uj7KITjvdZ7Qs;p?_s*M9xhCG(f$1*b29e3SFV{s)rIsXM{{3b6Ob9vFP! zM&Hx~!uqGq2l}qo{bRn>@h1{n+kDfL8SHM#JQ3|ij0%9tb9P5sDZLQymu4!~Z*KEV z`GXYV=V0rY_6Nmo`-R?e=)G0`aJfG?y*oxOpPTWne`%&>y>IFxVDiFVBka?geefw3 zoObzw)B9p1-vB>m(qeDS#w%&hJ5pl92Aek0{ap3*)cSsqb7 zDL*J*C_nMsv=mqUnXArq;=YmkIxrjcvg%mlI9?w9$yolRbB*H|mClWai^Gd|EeLx< zm1EcQ+9kL&FLe4Cl^wAINUJ-^ZRD1uPPqLUe_~$hPZ9rBwGU4mIqhe(H)ZWFW`ZSC z#a zRQ5FAs}o}@FAp_@KKx$6nM;oQx&A9N^Xh^JzA{r-_s4<47b!H_<*ugu$zpn&`zv>R zG5=RT{`c1jRsOVx_VL8D5C7xqZ0*8{+K}db@a)vo_(5$F`(0A(;NdrB?or=w{MMl3 z_xFz@oE!H$zVL<6-cVi*yL9tA=XO4K+OK{8pyQz*&anOE2i&2?5S#Re+CtqtOsfw% z4!TZzw7r4vAADxwQtTu9%w^7FS6x;V`uR^@d;PZMe|5S!|Fwhf9AqoNb=$3%JRHdT zhpX1EJn@&O{dxa-uzJ#$|I3$NIza42N3L3P-$WID*O1$%e*nU9u=u_E&g>05GqECc zZ%AvF|TG>xMrU-8&qJpBP>|LVnRT&sHa+bdf- zH{UfU^gJ~ih>P5eFNvNi(3lUupGlLQUHXTCj(7g^X7|LW18XMo{cL4ysq2_vY&x0W z#DA^w8P@6c7l^#5bssBe{oE~||Lpfa%f8^?oHD;?kEM7AKj32++qXT;T{FhlF|42P zumdnrWCQTMJ%(##_mYs=b|~q=qPj3$QoS48XzaSo{Edm_0ZvtrqU6GZtpM%2Jq zw~dK3hD?5Q#7?cBG^>7nWDbbf)--7O*voG`?ENpbN2#Azj^ZDNh1}T3y)&5Xq45>X z?h}SC8uzy0qVbp*1JUB< zD>hs^aJkCMAKCnMW3kf<28xHeM@gSB7HiD1RgTl95;d|4@S5zS8r6r|IXW9d(mX}WO)#`jz3ZI4u0czAk`@u)? zkVf(?vf+*Z=a(SdC9V`W)!#ArE6aV2jw3tm?Nj|F(4HK8YixYu;A;Vn(q$zs@|XC! zZG3wmq`Fud8NLo1-}6d3*8(j027x19IrsM*EEHa8JhDzKhJIafDEUaI8dd(g zn!lv<6~@Ipcre>PF~50(R2!vB2xxwj@TSSSirb}{0dxNZa z569E{D2!E0dxfl$LXLk-!l73U{jSl9pU?5smI^~Hm}%&DjaGay$8R(s)Iynt_6Aw; zr5ta*57YvghV}+o@#P%vHz3r)n1=QSS@DZFzSe-)_Xb^L!(YVl<3=H)mc%qp)O=R{ z3XV6+gP9ZL%88k1E1p*TO+$NytokLK?@0qPd+(4HPc^z}Xz!3!Pc^h@Xz!0zU&Z~q z&wx}JPxRo#UIHuL$MNR-;IrXtZ1@_E7i)S1t+C-(+VCqm{y_spHK}Q6Z;v%RwH$Be zulYo-Xs?cZmnchVua30@uQJIwezncMhVMNhxBa+ieS+$Ds;207+O&7#qqviv(xeRU z|JAyk`nY9yzlU`DQf~LKv~GW#+Y8z4y8YYSKA(L7cWEf>Uy~Nx$^Mkh{w(a||0Y~z zcpv}XrhnaL{|}qp1IOf^-dWlkQ$ZHpkbkRneJ7sF@IKOB8)--%w%I?S;|1R$Hm2LD z4_Ahs*%xj2$8>!JTxEE_)V?0^AJ+9EeJj}s-7eB=347hf_qMM89_PD+EkI@wB*5*< z*%IAObzm9ZhgGmkL;ihO*V8lYrSa=_KeyMgt8Mr`UB8FxSF&4e`Y-GHHC&JKsV_#! z^(^Z+R19;CEidf?92P&s zMjG8CF$EI5kPSIT&}Pq&*j47d$m|6~1B>|)%Wu+!BIh)TP#KdWVp|U8EBImTlJM91 z;Hu#>4%QO{G$mp@$%&BOUVdIo@6O@=#LXl4#Fs$im=BR(f#}8YlJ>78S{$LM@_pTo zR>mTDb_7MAlkU`m@wAA#i0sri@U-iDP=FsGdx!X4lcy7V{$Y2ZQlxr|_*|s#*7wr% zFy+rj2(tiSSyv%f`J%Dtt*Y7lLB>N5e{Yl)(zguu$ z208b4s~Bt0o)+4>?%6KtJx`YyGkC5MeN@l&j6uXaXxQ<`d8j@kemLRx8|mJMv8k?a zAbXUtKi2QmbD%vy)%v|ozf<)<{_=E0Vo`fQ@xGbvi1&TCQ+jb6(y@%>JH(j6gT`cy zj^qA)lCcok(KsOqnFo7&kW?Jc!|^eE+ZbnJT0$`t zI@8d3IjWK4NEt`!cQSfWd8Z*qDf6VPFR}R+ug|^1<%+tE7revewIUui<1PL@_ECnN z4P&<+7^|KC51zIy?`WCw$OBP2*REswTCBN05Or7Qg|*2%zGH!}#DT(vRp$q>>Wr&N z3xDff2h{~IT6oX6#FVy`V{Lyt=$pD2tMb@+FtyNG9+}@(;1etPuBuX;pLa)~2i@=(_RK&A8av;2 znV%I}I4PW7@X`*6e+!6x0v*$z!;@Am7$`h72u~i;&9PdeHS!5fztc0NLp^r8EFE*M z`NT18P2H9S#|vtmCs?g}Li4i80`ID!HMD!-B#W(%V0H8Gs-erm)l=_wVZFR8FnwoN zV9M=SgSHsGXu(=UaE!i zu&z59*EYg-^^t?iSL{Fg_S=7Xs=54V<&u2o>G90J9;^&%mutQ!{MwbT91NViX9HqQ zJ0F~v9jJMFep_gI{O0nAHc8Uw`F@AG5cb7*aq;+2oUdX>CYgVMpH^y7qZGK2AGn&_ zhrH7)czvmM<&iT-)>9bS)N)qQ#A==YaIW_8iF1gv<~?$d) z-g2DQ*t4esWsjb6I2TS}w?!kX3ZC?rxP!E3=)k+IZcpHG#C6~4=bg3H;M9M`VYP94<{c0XKYwg9+CEC0h=?>#D10S`F^{W7_KSBqQUb^KNp;1#d|> za^S@ohP@znmeSoZeMed2$u7rHJQq&V?k=IJP&9a^9lhz7qdYt)Z!cIA;f9AXKO7i(c>r%gY-j_{*wOd?IEHxb5^?*d4lQV( z9R2y|&qlvK`lq9RGJ53Tvu6rwe3gH7###1&|GQ@j0%c3Scg9)uIe%BF<5a9XZ>rdF zzu$Q(QZjXzb``7&f8w~nZnF7j`B`(PS0f6Q~|397HY0GvT0KV+T!5-k*iVr@-oYJCukds!|vLP z_+H4oMGF>`l$4j_*L`heW7?{YsU}C>F;?}J$h=8(k|#Id1RfWE`X!zo!6~AYKg31; z(vG_A-=a_zRWEN5dnbHj%i0{P^NwGF9Ur^bmrt|h3nw+$7wdL^anWS#>5IdQTCczH z_{{E7Cr-(_2bVTIt`!FJk2!tiDU^(0_c-mo^9_|pVnf}L$=xz_@J=v#E(kl(F3^+4 zcj?J6QN2dHM7Hz#jP&lX8~Ir_Mmf4SkasLUTrnivAuhD1aY9W;?HpszvtRw^^1Ci6 zyz%habNk2d%xkMZcP=}Ak@F;a>Q|2+(k?xS9aQ73+P!~?_F?=un>vbq^mvvvJVpKK zFgtmOMhw3~VGy~q{I2b#?Sc2seQo>)dD@rHo%_W2jgI!m7;7BAR{PTz&?_9DWZ(G# ze(gPeAN#>G48L{jVuzmA!=XK2czfO1b5F3PdCu$4oy*|2yRTwo(#?LXedn792V1PY z_B`z}ev;k)S2PkCW(UA=DGRa?^j}iLp^X%O?e6!^-NC-=+_jvsZR|B|`T)YgKBE2A z_le^O`vEvsvr+a-_`eeKPoI07v3t%>IZ^zCoz9?=Sh;PwxDL!PL!43~PScmTnfg600p>IU+S>$tw#RQ4nkr6f!a*yZ( z2ny*eeS7?7@r7ke7;)HtA{EczBjVk|2^^2h1EjjO1H{KkgY@ZNBSPH&5Dxb~A6O;j z4tRj*;{_x14Zrh-N_eL-DCs^c$XlXg=TkR!2E_sJRzD$@9}BRAr86GgAwJWVOt&Nk zhv+j=X3Q03d-79Urv@_+%^Gf0c^AH(OW(<&X(EG+gh~#|;v%uL6G3V$r6@>W{+pF1 z0UXKHjYE!O>H$w;c!C0C+a(2w_@ulDjX08c9bN*FZvDDokiJ2M^Mg?G=;O{f92qGp zPXA5GPu?2>`eX!si9|p2{5KwK|Cidu;}=yr|1Zaj=tJ`nu2j8%*3k{imAD8)7unJE zv5elcuovNyM)CzApb@h)FDZO9;~@EBc&5>)oP`+2b1uGK$W^{q6+Q}=8$SJ zc@uV(Z#OI?lScBr0fEZrsur^o#8-@qaFjmS3u@uZVpao_l7@km8z*oo-$L+_d*Um_ zCHZP?d^Aha$r;2y8NM1D-%^E-)>tK9yNz$DQ_T2CN*TV}ZMYuba^>4Do4+;imu77! z9yEh0{r#$q?{V-^nUO}ugLd7h>Cyl`DhI?@flKmD*!UWtSSZPK99jRDjc-^9AFbs| zzE^B~Epzbwy^ZfSg^$Xia50n~VZvvcsx z2To1D#}q!V!graC?>_LgLobaC-wGSwGvJfu6pu#uLN>k=Ab`j)@_E39dlk4f21@Xe zl~(1{csy5a`nv*p3Lk~z4jZ2v6LCe5OC#e!yJ=Lu7Zkor0hWBUBSuZ~9&oFi;Wm&d@jFNeQQ;M923fKR@^bqe2d8(&j_b;et!%Mu&k z4dC;Fhtj29;k#Vt!;PCU@KHWWBcDSy+^#ury*dub!_95Ll}HjuWcX4x+WL=W910vv+q{ z@rw*3Jviaos=tWyndwEjZyMUoWyM!;{FnhTQ-Vaao6Cx?*+bkoquPgZ`f4evFPI6S>4xh_xBkP^UWra z6D^t*U(fNi2A*0x(>Sq4yjZtV9jV#YjGgRq6O1P()^@FL(1(q_1GQ}$U;8zkIMMQ0 z@gG473PWw2rt6m&PDFZ{`D;%P>Is;}iEn899;_7hB3!ilt^;>!cBo9z?!1rVZtC4^ zhi<2_2%S82yTx9}{y?{rPi0{J6WvZ>DnotwjBbCE+l$!`b^A5kUdm5iA^$qLy_`9C zx`;7S8Fr`A=@6tB{$Iqd((RO|wEOK^-A-eXGSoK-i+w3Sxr*FV%~Xc^LY~wr>|Q2+ zb(-~zKWIWc1o8r zyie6ctQ)EqFSpsluv4FbF3O)9boW%Vl%aGC>2{HR>-bl8pyG!3eqYz`!*dzl4|NAR z=^uq&8nVlNb_1Tv@P7P-uBSMZQu)ThIbT$_Ovd8tD9XH)G3}JHO*dgiOPLa+S+_xa z#9n+)RZgIqGqsS|rduJg&dx%Rb6!@GS!ZLV)R==M=Q(CxbBLAsR>|@{Gp!P4onOsG zO_R8gD=9z3B7oALe47~)Ekl<~&lVK&$l&m_|Ee(4$cWK5glS(z*qv1m^= zC2po5S!YazE!ZB`=aWa`BN-8H%k*iEc~X?=I$VzJqW*IXn0Kllq|BoUQ~gJJs)xwGx#XPhQ#vp1RPU2JKklA8Futezt&H7G_uE7` zNWPEkcZyT39pn1$L~Nb=Hss`<^WG!oG{~M$_}>@d@O)a2CmIh#mG8Er_gYZW_vs{-D&lFm1<%-hSD$;|&c=-!#ep>!u>0;|F`O{=?OchG zG)`dXSl9lctzP}BFKfda@bwN_qr_VBr}m%y<=Y+8??t|TmT85K;K`Dh!?6;pt>YCR zZ(PyFe1vm__Psrx={VWx#;PfHJ$yd&t-j{dOoRKhKomM0+$~nw=T%^Wp!Jkfs}5by zeOVY@99bBy&aa4!haNdw;2Uz+c*;(p=$&+P{mx1?=KWd$^9QVB4kRnSn9?yd-gT6JTggGEozRY;pRq}DmuKjp z_d3JkTbtn3^^Wj~AvUEkz7GI+oUT?~8NDvLHwp>tu5jg!y8>T3#hjZawEBlCDndf; z47;E9VilXdekt8DM}D~K>CWmsvFip(s-2Vjs<-!FH{cftaFLtsJJ@8!@R2jcUcr+W zc4*~I*fT-F=`3)w_7}hG_#)1cDB>wJ9untpTpIq1(^~P~gyXnY zzp%+M`4^`h#aA6$w&SV5?uo~ifN9t63D@a!4gbSE@4dWt*`=$rCE=gW4DElov*gP1 zrc#9Hm6-~!_Qg_t=g0nlwzuHKD>FCLEk5ZiE}GDMw1a^8w2zQK1*aS?*YW%hIgYW_ zKRNE6yz+nug`bCsd7U@`L#%o``MDDm?r~gohuDg*2HX?(2ecQ*D`#HE-U5d7)hf1& z6h|EW+H^!?nj_pe<i2ToVn zKcEWy>>G688Pl0&chkS;dS>)A*oXQ8^2f+Q^K4OMp zdt5#{!>{06p8Vp46PlOKfFkZf>sB|oJ&Lb_(IXXvse#U z;XIpP$`&UY<^C&r7u@(>k~>^?Xvq-X#wNDnpU$%8Rd~mKc9!`{LW@Jj{tjSg4qarF zEXuzEy>w~owBvso&`$hp3CciK-sySHytXBdAa+ue57y$#Sa>u2!1J_B9a@C4na}fw zICwc&s~yL_q!U$@9uj*}Dh_a$HQ2GkxkL$bhWA8^goe(SLAq=_ zbn%uoLp9SWSJQNfYfZ%S^vQve&{tRcb_9Sz1048+o}SZnU; zK!2&Z3tdzCs-M0tZ3^+@2AixkgB9=5#OR=1p?;;v@Tz$@n##ocY2Dk7@9EgqL-Mrv zJgqf2iZVyI46U-3F2fuQDx~K6`z&=1+H2F%)RvvY*+go1R%mrv^Aqg0WYP7(Xex_O zOWETZ#HWVSJ!7-?Ajn{K$A;oqQIB_x$u72?pBTCf25V{|8FHmC#3ESs;Is#Nwq@e& z(M(pZ_RmfzVC2_*<%fffT!pSPx-(ez3SeH=S=_utp57S~HEY zY~tpee&zV3jIxhI@^8!ZB&|qw7l=g39JsJtI!{i@yvUiP!GS>@&Dl!%l}-NbrWF4P zP#0~mz}dmrc0=EUQiQGaX=Re_%-BG>fCD~IUv_$p8cf~LxP%P#*J*7-n(b9$>~jSK zgrSSZ98I`rPJzY=Waw9vG-o7@Hf;p+j8#z4|Y+@~Rc%J8>; z4%|aFTo$+rNrt=R`yV#keZbLJOd5%M5dziUeXw{X2zQA)ZNnXzgKs|M_%q`15-eWW zrICDVY`AIIY3@lHiKBfFYQ8;QCB|HoZ!}^c9OYY!jc-2&e&+nF7zYBzC|&Vqgpbx` zbLGdqHrz|V9@JcDg6ppjqe+XFXbo2 zm*$gYd~dSx-9HE4h>dSb;k!iP`)@Wr+J}-We4n-P%_w}!6~4!8d`G~SE1f57xEJQY zy==ps04`Vg!`5a?{=NxZu5$G@aB4bZ35k~%N@vPHna=k0_!=mv?v#dbWbEtlB?{k4 z=p|n>!lRZy`odQeXAu7+Un6j8_%H@%UO*^(wYVf-!p8R?6n^NXk$iC*pI_ly1+e7% zZ#KS{prAP&X(ZogZF~{%QMf34ls=M=%8?phSDu(-vhzJ=#l$N9iZ? zfWnt+f5eA?Ll9Fk+$+!!U&#K58-TkCZlxi=$k5%vpTxhHuw*@n0{Kx`cj6)^ls{BP zW!mA9J%vgo*M1AqsYd!kvfsx32(@k@MrsR>5IHwW1YxKB5LSFX$D8#D5=Aj|nzt2S z!0~4NSfHSZ-)+OYIo{-;5@H(ql9s6>`8*q5tqF+VW5auF;TIF6(g!*%$I4&G@sxkU z%-(Nd#TRkB+3&MzX}^V4GT+8OUwXvv^kpt9egVgu>AAp$FSg-}IsPdFWt}Uf{TWt% z`~D1C0aXp1FQT?jYEOyMyWEB^x5dxCpJSm7zmVh2TsKP^g@R7^v4&?6$2S;3q@Ipx z=*wSL{KYo@i%l?|Xg`P*Utzl~xH%L#G2-`Im6K znJU!NF%5lL%!*KmBDfvPc{=)uWW+VCqm-bAgm;cIR9T8{S{s9NKR9_X|o zYxq}j{3ZiMJqXj#m%ps|H5|XjfS6AtqWvUR{5p=07mNt8eWZ@$SSqx~mV{>%A(4-=2| zd&SWH6xGoFlNLol<>=$Ms7-wh7yYV!5O--vf19-6PWCV2B0SaUw7=wQy4}m|1?-!; zov?J;)3X-4`K2>@$7#RGzvy~;hv`da|DoHx++M^M!87tt=;s@!FA4nu=GXPlaC|Yl zhQPX^FwlMxX~=%7j;ETMPIvl(ZWrM#V^8RI;a@qE<4r0zWeA1*GVVrhU&P+FxJUhp z&JRSqoYDT3ODy)q#%YQ*+`ojh>wr`oo*N5uVHWL_BHUM4E4bRbjrxTCT_3A&(HCo8w$_w>3Tn&%kX|* zYtz$d66C&)>({W`b^9>4uVXacH2Hxt7JTLTPs*GdpNLcJG{vS)zbP|svkv_+W={Fk zJKsYP+_J4VIGl{_(5DiuLOP3@CbtcTVlGy(Vv5zUnRD`nNX*6?R&^fU5E|3yd~({d1~u~x~dUbr*9+aY3*&?Io2P|M#UB!GkL)wCe^KO)qGYb(XA+b z`dk$n6X%AobN0bfhAzh>xuKJ3W=xIiTWos9u8pQgXyw6DA|%{MO1UFv4!AyHZg_`S z>eJ+gNKTI9y`{RugS{lQchNJ(*vIIO!CXYYQyW3{$MyS5xI0peouE4=ZeOMQjTi^g z9SsbPGCcQC{ek;k_-zW^Zx^S^lKqd#ey`4lJN2hXPIbz%yG7gR`NP?F(i49J-QgeA zu@nyKl~6c1&mKKKUlMH!@os{ic%?r)zI#P`=K+rDO2c35o#ElXMR$+LQ!kZpzwhi=l%Nrk5hMPcLkis zn6Gih^?UEWj&=Cz&jpH(b}=czymzSC4c^*Vh$LZCbxB@st; z#9KN-u5r6U75qy;w2my+x7Tp{;Wsw&_4JL0Q->T)_XkRkxmRHC#gyjy?iqGb)5)N- z)t&WgzxT?)#*?n9w~n(J?aEWHyXowe58~>wSg&jOc<;8J*7ojRtS8`NsGcZoyQX2C^Zr@B-ciTgAJDqkA* zT)3~>aQDKlj{GFw^ETW!V6Vm{jl@ksp!)j)?5iXQcZquw&*}_S1eQ9;cs+?b)ti*Q zZjh;b??6U4X(ZnY9Vc~kB4VyN&vlR^&r;I;mtnt?zL`E?*2Wr*Jw@H9# z&eN(dP+U{Gixa&~A?2`XXin4WUM(TyUYzi4y6~8fcygk*Vs%fgxoK$5Q8hHDNO?nP zOm`Xs%lDPuy)vXnK-bf|Lu20U7JC6NW8|LR85;Bcfv&IS_IWrRM)1=+Kx5wT;4TgM zd0bj>C;Lxr_J6b4&)Mv>RxAyk>TvNHOS7ZF2U+I%uCv{6qp zuq!NWgk5QE9Zaok6O0~djv*Hx+Zh1cfNd6mby38&_2;TBzSt6Yj&ATs7epV>8t+4?c41&u%Gm(YGb5Zt(>74&MIsvNrFn4(#PD zsJ?D6daJ8?HQ${#d27{e^gM4;TkAQ#sBQArMUgxpNGkR)FPL_oD; z+Fnc&?!`f;?i#&LVCY;$Is=XPAekV%&EDj~*;o(OvDME^IK$Wh%?L+l^O1YPGMih) z{sI3IvN?LTom*onoRGXyH%5cnz}BR+B~`675$`TVe`eO<{nX2a2G)>Icu zBXJKwpz_fJHy^!M)rhax_zjUP{X#%}Su0+Ay@t|4 z7}@p-8})6i_<0P;qO3`&Zw`fr&IebG_}Wd8AtKkNq4jzzUVQDw4A1QKdMm!j79P_l z@`d`&R=oH+j)|Jxx3-3GfzkV>l-DdLdl3KZujkPCiHyKoSHGN=H=Nv;V#QRHEvoCN zFJDiNbwlNHv$Wt&_G@kSLD;DbQr$*=oTE z@P+J*MPI}U;n;MK^rMcXTnaH;CbdyA+q$`zHtb6sn>$-OdOH)N)XdRtXp`f-Yau2~ zwwR_wZK_q0-cFiuSDN}9PAx6CLTPEcXUQcIl{e2yeg5@Q@r6cDt^ONC+@FNr;njb` zc!~HT!!pPhkh@ik`E`9K-JwrM`x8l}_x^r;_x1I4dguN9PyAm)o+|UOJ@_7uhTf>= zW2cWqKJRzx&*SLN(@dA~Z7SEsFB7|uKX)ftypTlMfn zZFOb5?VYOvdm|<2@g7ObZ>I`b=U5!^iNrE`BDedpE8oz>zjZy(+F^Y7{U z-Tov0(tY(Um*VBEbNlJ*!{Z|{=h|PKYh2jgG3DA88~W!#&G+2QcwKR5oR2mdLw~{Y z_1{v}aY^BGrqdo(4NiihQEIuanX$y4$gQn7f)6Vzly7%u?>H|J~7Ahji&q+ z1@nsGHXq|9wth)|$sz5>6e?%<@Eaxm>xG_vGs^iNGVlfA>xU4tm~-`sgL%gaRy&V5 zmv0YjZ^Rqmm1C{>;a7&sr@Z)GCG)zxKgn;JaMT?+SXm(MAJ^}Dan~S!MZZ(L-2VKq z^VB%QTN0x;2Pf30=Q(i7JiR#+`=GBoRMhSgh<{0ehb%l^4_Yi&J^MPTvg*q z=LT|%Q^@Nb5&Hcfx%(x5+b#|*3*iGz53CCL=*!@Iq>b-^f60MolJOM4cffH+%JSbo zBG<`peXKb>ZrX9iKb4WxX3{Coe2mJvEbgWhJKT8{cg8c$j4$<42wdSMJC3+fasr*f zhYr$68o#KF&~E`t!X>SHcigbUF;(Dv?o897zrNwwGe6X{v(63Ao@owT&m4Gq?#$iQ zuBqj&yt9s`Qtu5xVjRNB*V9vcybT`8Q*my1e)yq;bE?kaUFDcKdgi(6?xnhK6Xai6 z7{9oks?)rel^j}dylnc&@@LOH=X>^yqv=~`r>83>`dPo*xu$l)RpXfi&-7%*kM*K& zy*+-XcHDtqHflBGcO+P%p9?L%u3izoVaPR=>VN7qyVG^db^7+ka3I_Ww6Cn~kA@z3 z+uzlE=Cg}>49uS$ z!SU63$Ikiw^G^*cB<9r=CI`fO^ptK8JjCo@SXN2P=T2azc7a zU#c70wuZsYf*T@j;k`S)y5nKWH%CFJ)LS~^7^hg!`R0KT|8*<>?fGAx`JqFr7c(@^ zAxGu2E3`Y*F?GHFiq`5-kjLmVf$L8^cDA6o;H-Pwx<_C91@n1BmvN1DDSlzTRIC1+ z|L#EEk4i3c9J`YhhTeX?*te<;F^w*9l;Rih8zQy%y}NMnQT$$(Ler1AA@OTec52+| zJav!ru~YZBUOVXY(Yfo(S1)awe`3eeUr1C<&y+S!kFWni6wgy*H#JVP(l10yCYSrj zep_SX$??ej(fbqLX}p>zoxum94<4?Vr1auxN)IS^ zpWlX)*O89nU)qEI6V2Ob)fLgb{5`}e<9@0qfULrGUgLDR-0lzVlA-8NU5jPFc=xVR zd9bvQiuJo$;^1%^6TY*=9qC!3?aA3PI_{c#WUTneUfcP=%bw^e>GXoL`a za5fmv@;Kx`+>~>s$~-y5{H3Dc%ncXk)!4CJ@xeqU8&9{UZ^Ef4!+p`%4kZMku3&Fx zS8H!;*VQdJ19~`~R+L?h!QQU!Epscoo3GBTY}_2otuW@ib9%@>9hXx>;moPn($Umx z4WTlrhne>=`IAsZ+%<*|za@rgakf1^I+z{O*MCLgV)NDr9hIIwoOe`JPIWU0q z!vWcHp?D6U_=PNo*-8%QB(jXaSQ5DjLmb4fIi1E4;ye>9;c1GGB>VZKf5&LoSO&lC zjSV#;bh~m)70!v3LlAY=u_=aQZ*q~4JePx>v6kd;KMq35;mFYCa)_@7h7zN3l)oG< zO{L+~mU=kk2&d@Bd&X#XGmZUAvyx9obiFU4XRLeINMCXoKZTu>1^y(mIRV(a#J>V) zf5(vJjf1gZ%sAFuDQtKZg2Bd~p>#Ymgw)GbI*=~0u1qF@Fa0I(**`Up01tKr>3zQ@ zik%EJ?b{scYU;YCH-YzgxR2gtai)4YJ{X8*;u(=Px=_bP@w4dUXlN%@p1KBQDn1e% zXo|<`LQp5uaQK`42zUuvDVh_&$b*{({Vs2E{*4+m!pV6yJC1Z@F2&`>^?tZDz}Wqz zc^7GQ0^_3@t}@QE?mmSN8@q|uQbx%dmvE#-41&$+?Q>*2<#qQ z(n!8{bZ9<-%o9P zboPF(^rN%m)%Z>;d|rib#>RJI4nF!#yvp}0g|AxSy9n+9HOljAbMTcxuJXConfY6z z@YUJ)reG(%G?dO{s9dUiMc|Y5%Sz~Feze;77NSDWm43}OzNJd|=sl5q5gVTue7VB+ zDI2Z{xJ?vr-N<iPaQlFx_e~m!`-KfhzuiVu39ae69cu@0W zlae1F)p3-+tv0@gVQ&`{{J-RDw(&J7<%P;M;fQYs9@Kce0ecN+68{KCW)Kf*_we{!BL+zD}J_)(?b}VN!8%8}3Qq zyadpVI6jzzXcx1o26yIr)i2=LhBb{ng z`EO${fSTqMI;va$H+OFWALVtQ3!ispBn=~hMhhSWh7l6B4A>TnvAi@HEew(dj1V}% zOUh`&BO}m?Bim`B#BNJm=PShSt-K_W9p98VZZ0^X7ra#R*1Ac03${rGWKkS{v4ee6 zVZff6^zuE=dEfIcMm-N^B%Yo5(|K~jCIqQ4gvmg4wpztmPx8gcjFFr%APa&S} ze4dxNn`!4-18;bOxb4skzlrBxM{%uz7e7s? z{uui#KFyYE4ZQe}+zZO^u#M^S^q?6291Wi%_lgqFnEE_lF5+is_!;sH+N;n|XR6z@{-hG)KpXG`5tei6~| z5e*-4z~gxybn&y=#YEez5G{d_{n?Sz4%pH zcvflQxk}@|O2fOqj0{huhOgAZL@>2Bwl<};@8@csQttTKXyrY@zoOV)Q{B~zE;E6 zN_?Y@a$;ig$25FQ;+qJv0q#-4)6hr zO*I3uTlwWpAdZP2E$3GpQMS`gX!8Ho-YxR1g^x&isrb1ivnJx*At)3w{QMH+&Gc9)zV4B)6#G5+RpK8#@>Swz9(<)Z>yfV((-AQG7m@y7BNj2BmSPxI zS@vu3oR9kNdP^>o@+U;nk{hKQ#c~mouUpF1;wzS%kaDf~rX{l_mM>!BS;$J!zkjyu z*%!@65AzL6rd>W)#G4BTcdlGB%#8sLJtC|ZsEyCU?rS?^sLExO7cV2$ujT<*%F1aSz(cRR3 zdq*Fp%y?LVf}4}{xWuEi`wn5<(ZRw@yBHb#0G;{xH zX8dWS>!s`|0NN^_hHa{(jP|y_H7Je7zOyNi+4P`A5#tPXTde=Uo8zoV;c1or#wb z!Mw6u17L2wGjUT+wR>`EN|c)Gw#Zsr?YVK6i5Fx~v3q>5O}$`eR^5YkjJ@#5Q|xvr zR_Du@;hH?t?lJewuWL4HR^2pKbLpnUx6wU=ZkncTv1b-~#X6S-I$NHUZ?W{-Eq$-0@3Zu$EuHhJ^q0zqu|s_3gb#rZ zQZKN^yYSKDch83o3ESL0Bzh6`>E^yI-yD1nw{GdjIS=+qdV3u`cDkCE^q7B_RaC56 zwJH)>wQL1$^`ZLsb@XEh7nHpRb}?2pS6j;#KGcGHN_vmu?<2j%t>!x7)B&z&48*Sc9`%bF3X%o;jcW@M7md%Y4<+*t zVNLzOGy6wRXBEu3e$KiNZozpe!nkI|E#=8j;@a9qoP9F0Zb`zQ46g9YRp9yY!EjNZ zaovyK%8eH%bK^HA@2##J!HFoi2W48r!^ym4sNuotRWw<#Cvkrw#Wk-Vp@Ii8u#&o9 zqPy$EBMhN0?!#JAtn-Zqqxi)Nu(mXOz+8cz7tdR(R$Ut-xefPY7wv?Jcn z=g((}f`-?Sdb$4B68R1HbIo$k=%rbQ_n#g8!nDJKcoL-r?Sb)9tYxm581&!YJS`q- z;2Pi0*Hkcn;@Cx<$Z9Z33-I@TtVks<*Q{QLeF3@RJi1iDXjGVc1k5$o8Q4{D{8qa2 zOLu;_Lq5B3TstmTw??`CJ%Z=VhK)%-)_7+u@f|7HadX!DM`b#~p6*z7q6iK196O}X z47SLUGg2#pweN<5wUr0v)XiB}yq5NX2>%u}Y}{UY<_oQidCf$de`9+_>9#~cytIwB z`QYdV$1kx;cY*(x&8@(WZ)|P8A#sard_yF#-isk2Ugo|LWOQFg)`UU#WtFSRd$c04 z-YzY4lK(ZI-IO*2I4lo0M7B3?r}ZRPlMTDN)A1lV z-J06FyL$VlwwLK@QFA?G3j<*@@wmIoTaZ09)?#JkjD^DX`wn!S+Sl1z-ucz0qUnk6zQsK*ir*3}(7;|D=l~TAM zK<;#DbNS15uZqVd8Xw2dauk_`qsXyOx4)IZm8HRL(r~u`7fFL_1kN44PFMKY9#`Sp zuJL^ie7n-{b!dG3;G@4x8}?Te-@O`N02Z5IuM}}qf2Q$00KQ6?laJ*~@qJt4+YAea zUn#}MwT$lg{>T;IVt^IjKWTiOuqabx7LMY}8sF>SQ{^6A8k_GIzy%>A*`(SHKIXqt z^q1(v8)#CI&m9lN zr^cvNJh-MvanPZ9Zn5|(Ogiy>SfpEHvJE(Jbz3m82$kMdN`S8X&BL?ulh$0jbe9UO z3+Ijlamg9@gUb3+Xw~>Je2f>%ikmNqLY0mWFppBFlHe$=3Gw3dC7$n( zsq{4=1sc9UDFqzY?JM{x~_7e7zpBR0fISsHN-3H^5zN9-KM`xCtOo~{_&muU7Sj$=G= z4T;zNLJ_eLETe|!v`OMi?Gx@9M?;?eVL5>2$Ctp%SLRqs`$d|3u^c1h`#Ovt&;E1r z#;j+YchQtF>}V^7VK07stNF_l@0~xS$v@QOyWcnY$FCXvs`_Ppl|1?~njEseE1O`)IoAc2%r_?=<@riWHvO9?)v( z_DVLRCnY>~P3_HXw72HR)Nnp~bEP9{U^sI%>iSpz3>T zJ|fxNU*9q|e^*Zx>bYH!Bo{evX+3yI&&Guku zop}~m=z4430OowBeOEg=Uxg5w1VQR+E&bEhJj`bE{x#Ys=?=@Q_?@A@mDJ%cf+BpM z5F$z);f0l8ctIr?o<`~jH{VUld?!OU;79#Na~LuyqgH)i{S$WiR^~ll8r3|%>{`K7>h4V-m~)0=$!QvSw__GP8_cl{^i!EW z=?_jWJ$<-vA}4p=kvo!?#~-XNI<^aOj}^}-{`&r$$n;ZL5|`Y6S8@pEFBZ=&{$BMb zN4}QIs`yGOv!Zq)Cy)^qyF)kc$%A4a8z7e5TB3n>}zmVYC-)BjHd@Ct_a-JQXXqa%u7rk z_g(B84_qw9gBLTrEEg+qDg~e4c*~FTUIgPD8)m1M>CAGW6w*9(VE9zf?_Uy#T|2fw zrY2p^kLO}c|Gx`AQat0-;Oe>Y;KGcvTNmN9nu}}R_pMmcmib}egIV!NVAk3NiRi>4 z5oxEp!iGqxQJH8jNW7HVTd{R(9!~NROU@nkm2TbMx;26`I7-`L6Uk|qomkRltfCt+ zE-tQ+Q5&YIfg@{h@`HnQ%*F7rt)(w?u-q(U(j-4wncY)xC&_qB5MfH{Jzm}*+A zkyvG5<9Ki>$9mhhuZ(pz&W7=TinF-{PHz#b1V{Lw#remwCQfXwf#Qi>0sHxJ(c z_{w2MK88i{-HK<%NrjK&h!Mz2DZW-1xWhLLK8A;U)D_<#p51(0ugdSLQi_l5cQ@Z& zSA0XTQ+yBN+08cqL2-~%<=bE3+0FNgD||VyQ+$7iXEz_uPc4L*Qi}U27`XWkyZG>E z^Zg5+-F&+taLiUI#m9b=n{NyxQJ69P*xpd#`xTzue2*Z4Pr^(o#rFmb+j=}dOtu@;~c@y z2YZHx<;+wpS&rf!EU){J#IxOPD!$o{;vOt7o^Pt7xaZ1iKSS~{|4hX<(NXEf*BIUj z8{)X6QM&Op;_tKZPRg11Lg~M4jhdsz5|}fFrzRo)ObtKNaf&C7r_n!0&9Ya$n|!9d zGYVzqcf@v}=ihAGh7TNn`;^OsvG362yENH}yZN3BYxdvM>&Se(iRw&`C#8M9m`gG!y3gZH_o|a+u2NR5kd8h%5`h5^)p~F> zf|QZf^ig6>i%>0!3mPt%w8U`Z9XLR1`&z7FT`#ZUlc9Y!W8Cq)feIr(%7sG^?BR%I|X0747!s;tmSZnW=p?-#a z2q4xCzEZOeWnY@_I{C_|!+kk*nAZ^(!5^sk%Pl+#7~k*^bbg0IsJJ8^FEPtU2>KXx z@V!YLd@MXZgfBon!ZHDKxNo3dA;jmYgQvH@wY3kYt*Oqoy*6*EzIMfxSfNMt@qO)1 zt*>2xa*1_Nb;Zg2GlN@#BXg7C13{b@=`UT6JG+7-k3`u=;R%!IUq=Gb!D;z8JG1(I zBma22T(^{%5xwl!AFMZ5>GZ`jV>okk_iL%5VG+T4xyr2AHO7wk*EVNN_%n>l3XkNh zXpB9$nViXZ)~TTH#P*C2eeV@l2aXJ`E*}}hNwdE3a-4^Vi-fMqxMKXsv@_8a-#aTl zc}qh9pEu$J$}LB33yysCHsh3GOds)`9qh$WbLnH}jM8}{*)u{u|M*vL6Qwl&d1~{c z$5X+uv1fgKeKHU0@r=VFvU~jJsj~eiQaOz?Co(hMKZ0zV__M+On!wpJC6Ap8-kKK) zp7Vd!IJ>*2dhLGn^cmK`sm$Q;x!{-iyd>s})yJZ8RZ_OE=480l=X<6)IPz5W;a6$D zDik}JwRQc;+2zCMGH(^^3?jNR-jR<{3S-r912dUZ$xQQHxo{bf2#*76GMc2QY3Xc9bb<1GU znZYjvkDOV3=E(H@*@>^b2>-@5 zA4VXu6MK?Pon^)M7C%;f{!HKhnBHLE0NTC;hJhn~p5XhJqA?il$B%0Zc|Il;=dq+h zStyI(UK6Oxex0gWw{FP*wz*6^Ft~R8+W5bw2BYiGyy+{(>6l#mh%+*izU4Qy{c&eq zJP)fp#crmQdBX6u$$~SxKIw~99sZ|xGR59=cuVAol~3O`(zX7iacTX@a0ha8Ak$ZY zbg#C?V)8@PC;ct6Yb#(S+wx4tBu!;ijm^Q^|{SI==$MpzFK3&Q|C^{%I zG~Rp!CmR>lW^XfA;4IYl{O7RmxH)5dVg0UTymM}`Z;5|wUc+nKj~Qo=;wF;5ja%o% zeI;{R=AjqA@z!}*d-kR=2P@^4bpKVyoQ63@)8Av^sFi7=N@nbL`uET9L8jmpBJHb+^AhwDp6x_++i0L>dPhgE6FME#EPj zzW4*PTBiRX^WYD=-@mD*2D?9S^dcVQ_eQP2w-$OSd%fqa%yD<;#?JQkZg&^ow(IKa z|8(=V_8VZ!u6Ao{O@D7^H3pVcO7 z{<4-Kj{e?*pN9`zZ8Wfy;v0nQ=GzCpD9p%5bH(>{Jd@Xt9~I9kQXG`k^FBOZ2yP?| z&J{cvcJdy{t2@eCg>?d9dx!lI6+%gT= zPxQLalz7KXm0pF<((qXl@9a0VzIT>?T$kZ+(Qul?JNswdC6MWvE$uDm(6Z(GMwuZu zv|bpB`;1}q27_>qgxyjP7V7#82kAEJIoHo_V+Z-&pp1M>+59G-%C^jjEU@RrcuOcq(V7UiMVUlecLpM)`S| z)R&<@^6O%MCG72c?u)-2nDfDqebx|O5|$eF1R+H*4=J@RW|ESIfp zvFM)ao$na_=_i)MCM0c$8?NqoC&T~bh!Mg0?C71~XP!HL)$A{mPyEU8C#k7D1Z@ky ze{SNmI9E{HQuEZgi3xGYxHb#trvIinFLBenn}bb3<67gIxkk-NU#Sl}8_?q!sleVE z{9+Xc<~RK5zHo9wGXGBFJN_5v))#jNlXDy9*5AKvT2h?zhYPk9oEcnDgtlVfiQvf1 z)kU?l;%H@_E~pKByC9W)U17smbl%ynp_N{8aYZFm_Ia8)hcNI~#mYojdiO zaShtEE2cNpoV*8nD>BdquVC+spBGah?bKuR@1u*NbGH;wejH)MPu^KEJ!baAGGpeB z3FGp@k@AL18!lZR1}9UkJU$qkm*}slMp}*snzLz^YN^~ddb&Wo7Z9avfzxb3yeP3C z{&wJ^1o|pSriPle@8vWb=L*XLXaA`%aQ22a&Y)(*=e47kQ3XEi2ZuA_L#=c6`_B$;9K_xllS`H-q?IB29_kJU z_Cw?|?q~?8=U66UDbAjWh_k!91I(`pf92>?77zSqzsH4#+pz66AfIug!$9_ae?x)n z597XwS{ZDaSKNUD1%uIlx$O^p?#|r3-L%zix!aR%rcF(9V|Q~awrF!G$(e~WE$ba; za%YEWy0)vf<8}#m8P@kL?_Rlv^Jba{*yr2SyyMpP`aYZ+-Qk|?vw|i!m9ND%@&3t2 zlDi=_o!iVcD3iRH$~f7)V@G=@ma9HH zv;#n>Ck4RXN}rB<>W%oiCuxv2p}FzI>RIjV?KN|9XZwy;TwpG{TQIcq-Z3%@iiMNA zRN7kGTFsbE`Q_T zOIKb#qv7720`~Ey3G@qE4dWrtMOy{vHURY;gzk{q6I$NB@1h9B+U#E*MXer3r^rCcaJuw*m*vqV0?#GCSLId102MPjvO&y>nXdAx;| zmZE<>mc8kIuK2P?o+s2^)(EiNS@r|VJ+(Z%iAOCtAmvi=YmZzaKJds9xd#+b`CZ7v z1hh2}CkHq&jA?Zz?Ov@Z+ub0!n&QUmH`Q%%I=&{v?(&+V-Pu)xnw@POx8qni%LBd3 zYk51lqiZhRsEfImZb<*_4wu!nRsQVsdSuzEXxQCd(;#g}H=UL0HClFd_tZMCOENLxMKSxW96FJ*VnR@T|R zKQilX-?f&G0ezOU5I$ghA4BNO@x7of&DWXV9$%#pgD|JNUDUyIA9c7NqW(!C@4TMB z*5oB0-v#b7VU5InCab8gx7L_I-)hNxU&;3)>fk#}9saydy-J9`gFgRy{4AX{F#Y3~ zXa1+mJ{58DSj8=^+jm-H&>uJcyu9M-3tp>YwbShJ=RC|^jACVqu_S!Jhx?VYuy?>X zGA$k$S9?IR;xC*IEaUx{h5P-u>DL(NZOFwK$;I0GDA&^m4~R1Z1z1IL#e&1r#-7>F zwI$2tDNV%~l@2bOKMs>CX5*&Q$Q5((cl3%{Iw z%-e}yJRK~}ls3G5w{Y2urvs&OwE^yVRTzc?@hHe#VjSj3qmSIi=;2K@3QJ4^h4f- zpHhksRgQ;`7lWhvl6-Wl_`2}SPpRVjEuP)2JH@vR=I-!C5EvCc>WXhSp51&!5EwV5 z6yJR?aPyVB_}Dv9e1D5)@>SqRRSO|q|C9A2`hndNgg*y>yO93pyTJW}as-`zQBikw zBjp(jqc9A^oRd5ZADw9mBHE<==lZQ+BZm`^Mi#ItPYqvZZMbfswjAbzxGS!MftA9ST?@A|N+Hl??+ zvMNKn_OoO!NL7id`DZWXwVf%1*PUHe+Bn-J4Uko)7f2IxUF>``aM)%D;m=A-k6QX# zOW$hgw?Ll{+#q#yS((f8=a_Ao`RFoYL2`F%bEiGqZMQY9NcJ`$dC)nBQzUX@#?-8*8f8ZZVhXd5o}W zZ);cY_TPO5=fCdT%6FB;M18who}>6FrD{DilRY@T3r^i-*5!0_gN3W00CgXJ>Ap38 z40HFl=06}`$hT%C0=olPrOYC3hRyS>0r><#tR-2GG9Ijh^l!~tSX>Tsr4*l%mF_nG zeSB-Yqk-l*JyU;cCZEg0(LPi|mNFN>D~aDGx8nNdJQy$zQT+HVU>}Gw^N{C^*cFkg znLWi`397*3By&u9_g!$Ub=9&}ID?n!<5%;)g0DZ6-9x$>{XNt&nC7TBkoVIN)}p*T zd-$B+2%j44_Mgkh<8F3zFit)n9xOMG4OUiQ)eL?kBnckKjpx>7EqpO`PlUak^=Izv z*>~>L>FheOaIgp~@{Jp-reRk;?Sfb}asB%ViOY;ftBYF9(`^$Q5TI%3R_5PHN->05 zFf$%L@DsUm9*ljF;>|T=@WqRovA)K_w3detWE`t`@0HS_>hh7Im>6%1_|}epk;w5c zn>Zsr_GMXv!VNiZNy9nBH9H^4nUI_bi?i}T*19J>JWG>+J9BO;q^K`Gpzo&CNW4)=YbbJJXe}Sg$|c zR_2e-ldO>#SgpLrI+!mr+?#8L&)%6ZnTmLpt+ZEZkd{lPg2RPXVRk-+4YlD98Tz-MIdewjyGt1$zA@l(AMP z$@KD{{jl$Q=iWO#TCCgOoYwvivX^asp6l1uU%zIH_x=Q@hizT2aDCsVu8q8sp?6b9 z>o#sbb1jXrF#P75n8|jV20q=~yB#+)U@Z(g=3c+~BAti4{Zg_7nFp$5u&!&t@w1 z^*3+tz9BurEJ`+lOPO}quR#;fIW|`(^_$=K-$%ptzwG3ObS+zV3sF6Dl!q-L)n;NV zjICg$R126*5cg1)kmE zdkJzGeo866KZk)keD{HmtvmA3T=A({E*0OmVV92YyOuj>QauhnwxG$!)~n(>f@gR5 zxHC8hW=g5>{WA>Q;rqTT{ZtE`>Bm;Pn~$Sk>B9G}#`ml%zG}pee6!)+&Bs+f>G%p@ z?hfDUuK2R`tm3;$<4Zs;hrLoNzRNYfH(lXVqhAbPi^jJLa=P&SvBvjXSNO0%$_^h7 z1;T&3JU3qDo;@M!a?lWf-yX#y1K% zU3__4oI8B?x%d{j_#V*s-h`YkdS*vnN4 z)>8dg<9h^rEPqUw#rP?{4>dlnj&pk4CXR&fYkWTfpDL$IU3|rG?=Dw7$t6MpOVMAd zSul6U_a`nsj#Q}dU8nISr{Lqs-)_ElU3`qU;=2hrrXw_|cHu#Vi3aMqD-AAPy71(0 z#+QCjkuTjy(4WE_|GQ0;5dRK=d7%_Js8|QX%2pK!&|kR>6pp&eYl8P7GbT_u@VmYd zKgI(_GEH30#qew)o_9G^e1LkC+x$OcB*^Vqx)Yf>@}tt!YF)5b z)HuqIIT0_uK*RIP>?oc9l;(?i{L2Un(f73F7Zx!U+#eM#9Oqz_zDg0)C_dUTebN#Z@}KI{GOf?{ku}GE@mCcs+1$mpMXx8eJYMLZ-%ZE)1?DH z+S8mTPTvJxDcbMBkM=CH+G4xV?SH;S~AI3^7hyxDJA4bok1g5suSC3K z$!2&_{*iEWZ~DJTuEeHn+Fv3r_t=*Uu70OI+dBCupIa=M`IV3IxYLp&QodY#1+r31 zzi)f&5euvHf4Q0o&_@W=;D9yo;2mbO4ATs*O7x0F!8F_1q#-mr2~k*+i@9LuyWJPG5BYI(4Zu?wAUh)bo0cVNph1*Lm9%Q6L{cM!|o)Q-9O)*b!p zZ^w*lXV+&pbzy+ZapN7vhfpC!EScXYntvqz76-3za+Lsh6;Ba(LVxVYQ{h-QGh7T0b;c)@uuj58IQXtJ zysSeQE(`^TP>We-Q09B>j*ql&bL>@oRJ@hWsv!iN3>V_h*;9sh26e2>3^y z&~2uF^jC&^yOWN(jKlAHvDS6+ydlojPPemv`Bjw{Ja728*_gNI4QC>>E8>^^`t+LD zQm;g(#}>y#iFrCx?Zl7#->f!pZq~+eoLH3{%lh}%m(&hnsxkJ^R@&nPF`i!a=Uhq2)fRG2G7*eoHjB4p#*h;j24{gtg7Y}COoNAm9!1*&^koC3-9?0R2ae3BuC|An3YpS}wb_**w zUM;wKM}Kb@?jLt%r7Xb4_V%{M-Y$G&an3(pl`gCX=?Ug)rvg`379Fx`ig2Pe(s)cH!4EbwQAg!IQq8%KQ~_)gzI3Yl;T?l12^9g z_~@Q|OasN&gJ(Bi0s`B8N-4evVBp4eLSWpKQn=kPaQiz9eB?#Rf=}}agG9hb}RD@@aQTfSQv_V_^Gf_-UZw|5?D$-QdeQ6)w{^l-7qM`vl+lKdd~Hxo8Ur@8na8iLbOF>Mb@6(w#y~Jj;Wr zoF~dtjX_0BF#ftr9P#PLpq#paCDBnFgJM2XF&%lD6vN{veGF=bWK$n!E=x`B^vd^sDb! zve~B$ikB>z;b0&8Czc$QGSX8u+*F@1&Bwz0Oqd@C=VRsh+HG&&-iQ8}x0`3L!mXKn z2M`>z;wx#|40QC@^mg=jV6g>G4VItNjg!BYj@R0E((T0csZ&(?HxcQ8wr#}x7Vvbe zRg@Q+y8}a|LZ(@$%q-VD4U2gl!f+Ifgb%}f<xAA$KL zFu&O{FNb*<%x{Ew2{|nDnPAttmS*xN;cgVVFM%z7@%ExfhmYZ*r=)x7r zx!X(k&)Xk~J@B4n zMx+3qTkxEP=ebCM(u|CwTw%rCST}DgT7%VPXm`uRY$(`vWLtLh{#K@rpFBI@=Ni#% z+M8`?gi@}T_AfC;f(`fMF82xCXg=-_j@+MMd-|ppdzDwzx$VCD08@Es{P^}qb`(Z$ z*@{rad`JBeniifJ&h;JnRba)@Mf=O(Yb5sY_NC*doq2mYQT)wE%4No~~Lh@ zW*VGx6*m?Ycbj(viSn~YGOSa4S05^btIe4KGi5rA2-3!9rOo!CHIErq+Uyuw(`u(p zcl2h){W(v+0P(SsUTT;9dSZPv{-^sy$wf(HPcT+J&-c!kau$7?AtMv|nZcSDGTzw1C$aJFlRl$lB5Z`BixZD+t!l`QhR+OkeRC`Bt{)Ml>w(C~ zkjTE5&=-T-)-MLGuD^QSk<@(=Y2FHkz(TlwKD8^dvZ0jj*WAKSB51YZ8TaYM;2S?VQ z8QmC=NKx>-aS>T2MBkT;du5yk?GQC=osICs5tmsFv)8_cQ``m5% zU@d;J#kdP8eBi~@Aod~-M#AXbn@>^uDPljZpBQXX_9!te>bW>Rx1lH@N(&NsvD6`) z6J8YirY3Zh7 z?T=h-`5QT8rm+vVsF_c^OU*zDd5HUH;7{d&4D11>%SFhKU+~Pn^FG{MW`?x#xi1`8 zjMM0U+L;r}lVdIQ>cRl$f}^nN=ez76hJn_^DTmnnqT{no>DS7dHPobJ|hg zwGTfPc%ry=c`9e#8_DXEM)ezs#aThy{1-{sEDhDXkw|7$jrguLIci5}y6}tN&dNG! zSPc0vd3D-jJtu+lpE|!H@I?NHcb_gu~lsNon(33OhC5Ki@Z0?LQ()TN9;&h2zU&#uLOC zf4enNmI`L){&Vh2OOmDdlA;Z=J$wJq8ZmC3MxV(Lj4}d;AWvB2_>`6JW*LYXTx|`;$^#+nVBS@MJ=%D~=HawON;mtnj%LOK zi!Ms|3`P>SI%F_pL z5u<*K8-AV|9xh1M$hx3BejfPs6M<>#<@x-n$#AZdc`{G> zbr5fD$>HMo@f{Cs#p#qa#kU=A_Ma6SU&A-$MSMlRc{aN7c-KR>ep8yg3$wQ)evF_V z-}X=|&89cpv~{|C7c0?1o3M6#Gi|uDjO9Pas+;g!i|1PAL8F*p(;8)jp}JvRrVQ7n zhNU|;CQEBJCYoeEn7RJWj(O2vWj?ue+R^KgdJm(uNH?$S50`G+I%__&Vm&mt$G0+8P#1{%j zaEfUIZZ1eHiZj>z;}_vX{=wdxwzlHE#22OWXIX*Q=K>v+ZQn&%fupk_VUHd{lL+{a zqP3Ph0e>IGGjHabi}vd*+*{BpbF=QyjCgtX+<}|Wo|^_+L$<8HnVEsI$~G<9Z5^`R zhID2gFfW+awql-G<)3*%b9Hhku|_;%*IfonG2V~hf$Vs8-JB#-qHQ70Z;-nbrXk;1 zMqZRa0U>9{BFEU1~;u<_QJ@htgXiN0TC%}Zn)Ex)VdE(5o5Fg}lEWgOjm$FJ`Q zSaK`s#N?gdzLPRjQ-+=OPCv#(76nBlfwo7&Y?E~3If&8y;>5H#>b0Jmw({=Fo0=bL zKGuTP!m>H7$J@APgzc0M&Y$+Poq{p>ZKE8MuLwqc@#3yyU7_ehx0>bR-8!(XTak<{g;Rz*sXu#^>IylxcoE>o>3a>hB#emfsw_ zxBG*)*v^sV31JPJ?Ht^TT00T;nfHUfgfp7M%qQR+`?9q5*wvM^&UBXe;DNOZ{Z^^Q z9HLBTw&hubO|BJIn-A?iS6foG^Ju!>)oz4&wQ55$U1ZwCaYIVkJnSfvX&Wi2r=Ags zNIfgEK0{zlU?cm1#(VdtHZKU(+@0Edg&8{J8C(z<26Bdl1nLT)Pc1xY z_;f73x>ZK`bljIagqCVich)19jv1F;GWJaMqE~}gl#clqmy89zmnYLXcq)*1Pn<6i z@4Z~HCo0}~S^QJYp!inorFVkMBIUx6h1! z!GQqX!IcpaB@1IdS=+eX)!XjsJ??^V2RD{~W-ayc?)nbQk1>_~XM0+w$L>$XD!}kn zgL9))!QZ!ct^~4X_V)q z%Xi5i3&nhqIrMQvwwu)7_}F&z`gnGXoNF}gFjsj>68nbr^pHj*S9|}afts%E+q-s5k#Gt$h4sePWP97r&UO=q``FWa z<%Qukd2=e)9W&k|PYZjB)@`ZiYn%I<>)JcJ+j~C-Sk>L#z5_G2xB$NEf*f2B2t(sj z_=}6>d$D3?3R^7jv5yc>8$T=^tLpFC-qE_YYsw-lClKn}I&n^RS`OUi=PlrJw%nbH zwl6pA=#>6ULTnmP2c@O=15*^YcXaLSGuIhS5fHp1la5k%2Sct2`$$A>2NpT?uj^`S zSFlMTRqxr904vR9mQ8YPo-gORvoL*ho7yo;W0pPTPuiq6E%8=W@=DVa<52~#Dvgw*#n?cA{gAJH@%HO)Ivn{;fwql(ol7y0yAAFj5hfwf%> zom}}NzZqB>+JWUlpIyBJ{?WME{grlqqG{Q_gD-rW>tn0Y*ERRHIaIedcXZN$hUd|e z?K|9`>_4ni>NuaTRKR-Re6V{(!#*qy;#~3V_z}Y&=ZZgtpMjrRUBR_Qn7y!-;%kD5 zn{Nz!bWc9IReYbvvzxCULIh??DZV>l;N}~5@sU^YJ&tEL-vbahm#viI8-{_K?``mf zVaD)<@KbyotabD8c7WGmrj+7)1_o}v6!^MfMn0}*P<$ux?B?U?>V-70l;ZmpWH(RON@4FgbH~28b zZ!494PiTCH!8Z&PafPQ8GPzJzXS*s-?JKDC-^EY4r(gCr!>BVi|o1@3Da?jGRM<;R1-x#L^8!O4$huJFB}@!bc$DD0I|>G$^4UO+d;8PsrM7B!xGmS6l3g4ALC_c-0|&pg^z1b z72hQq-`?rYdR8}IorW6&4qn@ed{pfk?oHsrrj`7waQA7rGr%oPgWCn1J03%b2l<%J z{63J6@74D;zQ~O9=b-G<`1ZQe`4cX_H#EKh@UcEsivCjlOyk?<;)}wbIEHUJzK`zr zayR(ygSk?QZyIp!_#SlSTQ$InZm{zT&|&hwstsrc^D_=;S7c(nN*)A)9Q zFWvX;>l$Cg#fPnQHs8w{-{=&4&ue_;F1}B@`2J1fOHIM|j>cEv;=`6XJA6fGPr38A z0*z*Od{z1t0_QF-mEc3x$?|uzi|=ZUFA2T~?3GgG?@EoY&c*i`fK~ZRXneb-;JZcR z+w9`o;^MnUHWy7=-?sk+O-;VIH(rG^`y!ruzu+~sA^Iy;3Sa`hmlL>~Antu)qwj!ZGYrU%o)xa2lNQi#+Q2xeLU-mIkN7L_YQWP8yu@ z%k8fpi3g}BzUgptfFpMW9YZl)ddx@pmv;Ou1P*D}t*q_;ZudEw`y7csXhYmJ6~i|}!_Sa?UZyd}e0;E{e?dFZ(b#h-KXTF=-mt_+ZM?e% zrGNPvp7%is@uba3$x*y5&C6dX@lLydBQK8PZE0RSZj*ww^WB=|fbrx<%f^c@l6WWo zot&aWKSn;hc#ecPino_}?dM58CzstVLh@at;W@(LD4r|h6ob=)dhNF0{j2Bol~f0+ZulV4n+;jfT*C%>-H@D&=qLc^=t)^z3<%QXBljc<#~QT6kCsI?9hza=iFYNc>tG!k)0B{35F1qZ04bB2fp7 zCqH)Ld-oxwkhL219>o$r#N=Ny{It{;0;+ulEl8eDb6^$B7^JDtP&Bkl|ZtL)as8lwW*W!+%=Cv&ZEqzqnDu->Bi) zqjHpA+^pf*LvoZ~d`7eXjO2654|_n4@{27Rev5`@564k{(X8Q{CEh7N%?=n(e$k@g zTQvJN&Av^u->TWOXW=NnNNV;;Ej&pFj3+-%z4GQ~hi1P`v)`tr$2JY$DU=DzkRduH z-T`$wk9hKn?e;laCVsny->%_zX!bkAS1d#Ty5YH#gZy0@zDxXf557y|@0Pdo(a;P} zx8}ZE!}ns7%gc%-p4}sz7)$qM?k29T^_+E{_Pm}w_|Aq;}Hh~}aXiuYHsW9}2 zCi9$NrD$IZnMRHHaSygS_ctQtp!mFo-=oRjwA`}}<87udY4*o7`8S%J;e$gze#M z%e|TYSBQV{$Q5$@m*FwvgZ3pJWcXl)lbpmXT3CwVFVo~@n!H+*Io?V>CR0AnDeTnj zIetp}F=>C5_-~s1cQpAKP5z3Ctr+phG4V@FHvOv;)6f|pAHTu*XiqJ%OZA{2!W}KTV;{ahOXqxk{5irO7)q zc^71+&szNQ(H{J+C37wyAML$YEZNMj4dR!UY`$MNh~IkTPm6h&mnENRf1|k8Bi}5V zEIA_iKO?$4@)q$GOE&YbS^TXf=SX~ucnPvn#2mNmSuFEKo0#y(TSZQ`86J}_DHd6> ziSH0mOO8nQXic~eq)_L6Oj-`^Uex9+BTTolJ3Ue^IMi3AnTwd+3(}@qi#BN)nu|)U zKx>}7_-xX;Gk4(hrS&*sva!8+TWxzkR_Av0)^*&P#F9Iq8L#d7tYuo=+^;Zh+R1D2 z-M0D){F=#!p_oSQQ&8LlYGtrzF|=*Cwt7>2UsY>=$L;OHHms?UD+sv+-DTK`n@*Yr z%w?6L`i5A|mZpK~om;oI_g3H0-`-cHQd78nx0kLu3;f*HC>iN3)H-`>F~0N;%OXF* zC*{HwVlx`{qFqnGyi4%0RNaX^Bf3dN)HYTQ>?E*l5H2&t)X9_1VVYcSZR2jhjVj*b zDjhqAU9C9xB$H=b0k#F$oXVXYUXL?#4}se#&CUT&RyMUax5-5I=5Q?zr8AAwk)_#P zV4dib4sC5MuxgBfO}$tG%D3HG`JK)QlhG4Qmx1Yw;l93oK!c%pc{APGmf-fowHd)& z2JbR(YElka5L|m_smQ|I9c7> zi|Pkw`e8Ff%g(K>jaav9oklCIJYLxGuy#GT1Mcj1aGPqo9NbpU-Uc%;AeZad)xCgH zu)Y_t!^umxZt3f|vt4~dEHh64-TNU-RKH*AsDzFM`EF0W~1NdnMeqcD1POkVuPh?~6zeuy;eat<5yB7RlQm zUM&^-xcK@bF?RL&k*M@L9o)f@MZwHZ*JIw|4Yl_g8&ykNPq=wViaR zGHQ#t&fYrhmsZw|Y?g_BvzBH2Q701HSBA0T@ZkAD)C|o{KQ6-yIThLkch0S*p&cvh z<6G0*-H#nK>J+jx2b#GP*Dg;VnMs}!@eu{VV}-yu+dJHTS{9y79ck>{TRAjqE3h8# z%rLq(TDaXz-mKxawM*(0uB}E5cBV~AZL=u3$($C@BvX8RXv^&xlkC*Sj7b*Gb_}sejk(i%@2tjXH-+LNA!>iRQm($uFCI z#Lz!j=UYSP>;+}c8if8)VD#T~cRh7<0B)oHin+EW1fFLhlYf-@ej#8beE(gDA5q_H zo(;+HaQ@Wy9dpdU_kFC}r3~{=0T=owbKNp|U?phJIm-}8RJhq?3H>k29R70FF@*4! zQU9SiAI$KukHUB|-o#6Lm|spA@mWs&u(_TvbVP^*W!QI92Y%3!AEExL5RXxRO^9z% ze_e>DsUJ0OnP)oTzvN|n$unl@Z$f7}Oi)LXB&xE|$J@iX6y_i2TAAl<+AIxRA5g!>|gy%Y#tMWGgSLSWyp|>q}zU+94O7R$ z3z;u74Ku%I8D@UtLcV8dkI8Rjz0`jK-S@7!-qSZKgnaJ+dYk4iS@q%bLf};s^XC|H z43FWv4svL=xqpE1mgN|7#4<0ZKF=`o6@i!e>(V72GV^=>Tw_vx`RM)yr@mr3&tGKX z<|FX5XZevj0(XUZh;Tgz-XRb3mvr&2u`K8$(#2?>KrSJ`X z0>3AGzM;K--_Rf9xf4I?Z{zof;Tw7ZzxVMA0Mm=#1HQ~5?9@rgzc2H?DOa+xVDQAe9`WMda4`C4VR)r)ZC!zQwyt1LVOHDum30O8J=1bmbS&7j z;STY1_Z?ZciP2#ZjAjn)nh}Wj@K=WPIfO45KIH#NphsBY2pr4oF~-W^>*tK~V>!LM z4z3vx2Wtmbb?*rW$1;1w!RCR;LDX6)G0JcR3L+;Nhn`NY!6RUc}Xb`RgVe#^Aq~4~y;YFMB-$ttE-I#Y-=IzG9 zlFN+CezLRZ;7-K9X26j73BF`_tO9Q9P^M7IP+pc5Cd$goYV%g+F!hZ^n)4Vr6R=h zd?Z--;leWHKvu%S_e7ozpUCX>4UGmEuTAi&aOQ^mtd^{n(UQES=aGz0br83&CM`8|>2GkU_u-|aPyhkE|@V5qzF_;@dD zU&%`D$;(}q7cI#f#b0C2?t_uzfu81ps=VN_Ku^m+1n*|+z$ME{e;Vu^g-v3>f3PYq zYgw@O(V4+3AA!&1y^jL>)gB+h^P}VU_GTXRoyh6&ZQqc0{#a9QR(r;}wK6YC@}l*l z$3D?BysTt1y-<6p?!4u(LV`WZH*0#YDg+03u-Z~&g zr|0J2z1u5GLY9oxkCsOo#AwFsU?a`*Dvavs$6IO=mH zRO#EL%L+5L8OJkwGV6WutZiA_#3;)|W%${M?|2w>$oY~-QHN*teC|+IM^V@}R2#5r z_VD0XtmohGRd_c?eAVCb)8j*kt8r{O%5Np!%(DDIX?X!tF>q{FPvGgIieQgO{71xC zOtbR~KfFEglg!?tgM99XRu%Yv&ZmYP0Ta}=IUDy4J|nhOREBzhL4D$z&J-noAnZ@% z;@cG7wLdSbWAIoAU#~&b5WzgeV3=mnW90h#pm-j8m`V!s#k0mwBKW?(5RBsOG!AAC zy%(G~p3{rEvBxK+x@X0UI|S#hPYeM6N| zRa9V9mlvP~aBy+Acqsw5Vl)ZgY6}Blqn2T%Bo47QEkX@Kwd#)%4}sXULk zNW~14l0Z1zc*ZO>QONlv8?u^nmSuJ1HI*X|5aN&+O)>U)mw#J~1`wu_frWT$9)Q_J z`{~2arWtwXE3!JyFWc}v@zUw@=g(JNn|GtQG;?P#?(5$0oyVUMqo0$0p>`iMMC9uE zJ^S(1DC*g9SJz!{q8zP#`g16gg?LIp-yimkg?qa1syNs(kQkW0&lvk{j|$0et&pUE z%^aFBO@*kG-(E=fSfLWb8w$nfL88OP($G$E@Z!ChL&I5ObkIVS?-S2YAgpTsx4Amgqh(}#1_y& z#Q$W}5fJ8Yu+@pk*zbAPW$(3DP73qM?>F-~t36r!UGKY|bzghk_Pd6Vrm6(`6r^W< zZBbpUSmzf~E%t5k^CY#aZfNRu@279~VtgAOi7u|S-3DytDopXO|S0BcC-dI~gyj;A&lPIOTvhY!lcV*kha)yxo2jU-}qi;FSh>GsZ=yCGIpT@q{B zoTz&dqsymOfmeB*c#3_);*!ytHn?@6{hoN;@@(GEUh1Fv^A|R3ty)}sc)^nu-@l5! zN-!p_gRhdr7{&d zvGw)G6qQ$0bQZ^ErMm|=sn&hQw4w{yjxa8Sudc@ndh0K{a4z$`WlO=G!?^I6W5wi) zg&2EghDvvBKx$*VdND7!bm)?y4-SbZ-asfURn`yomk&%mf4kWCx2Q%%wRPJgKP~BR zUn-u+L-`gJCzj`Zr@pN)n_L>%9ephFoyg`x;MnWn-Ma5HqLvx znYVb)P3joN8x7p8Udu}KBo)(`UY6<@+H?#(aRPCupHW!ZdR^VMUdw4{`)^m)6pJSg zzklCI(OK0qSciEYB34qcpn67rq1O^CiS1g4ni?CLJd{^dUeA)kd}H4|C||U{WL%bA z(IqS~jy^eFn$(W>?1pH21b@AD4}V2F-$;2ykrbp5PxZzus^vRL;80Ct<5|h-^Dek3 z+1A(BJCI!4*PpC!JwLf*-I`1n6t^X@b=C>hczyi?vy(OR7R_6jT#%Z7dg}BAi;~q) zMU?3n$jnZD5MEBpXfLPMtX_2L8eFT_*`1`GvVoqy^~nVbY8KSiUM}jnQr3~_SkoiC zxp>TPgleYD(5dIwh=Qq;&Yv8K7Zm4}ct?51L`%J6y_w!|URhp+C*}=oS~u9S2KHdT zvb)U_)h4N%!K9iXC_w7#!nW?bT-$%SdH?^tKa5$(9u-p_X=?BnZOJ$0c`00MITF8O zS8a^!mIY2dD><$|(V&&({I;zdJS_EOr4asHgx>W`L%`N>zaWvxvX4xM|zl_ABf_K-@4g` zccdSu9f(wf)SjkkmQfM#%)a&N%-a5i3x=+kzj`3EffwR-8P1V*xy=neNo~w3U=3CW z)dHdVJ3ocxKdk?qxu{mJ8@}@@;1-n_|CY;hagtDJf{sW%<|3(XRy3M=c!^j73tn zj79OwOHC<{R8Fh7WlV@$pfKka+$VX<*rdcQW0O;p%WoMgOm(N@kk3!vG8V%x4$c(V zQ>8}ve0kSoY^Tx)&X`i~>qI})z@7Q!dFdjh&A6PJVj0WHO_P_FwnyI-1L8MNCB5>} zcEc&cnBC|tPSs6Yj9Xf83v4Ow4|!T^h{Y&KYJ*lWi0#o-bs_Z5n)op1#1@8>9B!9( z`|wt2Zyg?y_Q)``5Z|z~U??&#KRxqB@1Z2_7A>rxA5r;8L+qswcRzR8FWMgHK5*GD zO1*`*We>gbdUxb@Xmdv16w161BO=LL5+b-0W4Z8T{HO_eqTDdtx*Y-fCov(hcl`MTiBR6y0SrNzc;>?{O=kxL3TUV}J=BA>hueY}z!FODd z$;FnN)JNb0^$1*x#lupeD@K`xh;-Y=^+>iuvkKJ`p}6}6+$BB zB;Ju^{4)n`ib6>0px2RbkOA7q5rM)dIF1CUBR>HsD`4olSt@D7n6opptiQ3N_b(ra z$u}wA_U0YS5s_`oNU0o-l*1@S8duJY7)}P4yKL_ymx7ENZiz%zf6N$xBQ_k&_RXQ= z)yRfBhm_%u;WgoB<8cJXpD_mSJUG~RdDuc^T!_a!FnHZ~w()KS-HM+vCSSVXVB^&Q zkMSWMZG*Q3&o z-g*bGU;;d9jkNP`(8A-W+TeZ0!NcJJd8)v~&&2gp4&HUZOG1eCc_w}a?<)=-)6eoU z#^CL89_~s5|81c$@}5{$iZVi+2I3!VF=Ss+$e4g##JpjD40fTMu zPIT~Iw({>p3va1|HwrvE|4iDmjvNCrJO&R^nqEBE>3GA+7pB{!<8}uxZvwo}I(UaH zyg3%$w;jCL1bB})cyC*He7BhR{oKJToB;2q4qhHA6Z?7A(|H!&VFxcU0p6b+yg~~v zW#OHK7ph&aN+!UofSg?(B^KTS3$Mk&E1dwZ*}0%ez>GPWc{dfy1N&q9J3uzZWYolS1fua;1pzQ--k( z3|Cyj@&!_!bzB)UT2vIZ3x(xba)F^Xp)j8#nZQIb5(@L}krB&nn!~r>Amk?;evmST zLTx``e2xSHL+w6czC9A9|Dzo~-_(Jj_MWhRzIg*fZ9QTBOea72W(^Fr_k`tVN% zo}zeThUKdr{v3zTH$z~eI0qZ{&z?RoQS{VdK6~!KL@^@>^HTv6Pf?s-4)fWw1}2I- z!oz&_l!1xj{A-xco-Z&_oG+iMN%jLC=x~dv4TSMT?K!rgb{y6~`ejX~wu9N009yw` zB!4M>)Ml^@wlU;)83HzGyH6!OjGr;2zhDU1r2ig2;igJFYqIub-Ea- z`?IFm6HzqzgXPu@VAHfCE}kPK2Dig;U6u2 z=kPh6qmznXsW{$xIWYb;n!gy&#pn;}9e$fb_h@w!C7r{~6XxjB%=V=yM#p)uDSqGk-XCrS^l5IsBU)dWV)* z=|5R&cL?&gTD<1S7a}16e~vhb3Dbrc%R~IRVy(kB+LP&AjQ-(XhyRZu|0(fHhyPZH zzd+2i-ti2-26Pa=8gY@s&xZJCh>tmZ!A%MC6}Pnlq*f}e6<76nmR^06-0-3+ow(SC z?>RfK472oim1^Zye>FF-AX{_Z(rbhw7dI|$Y|RW}`LMC~O00zmiFQHTYAiHS8*v zu>GZ9m7QFN<3g~ChqL^vaNI><6(m1owN`ZTnV1Z7oHGMOAmc?{M+#a}YKd5(j(4Uo zQY{yU{ckK+Vi&q|kcCI56$70;y}cdyE?%#+%6KDG>B%R!VC;YTMsCO<{IzsjAHK6y z$#(@A8Tur5f)!`|IUftFyQ62lT!s$d?A2%g`@xGl`qvSbX*%-PfH@@f2e@s0!FPf( z?xBTY-JEiKE$vsfkUSU1$D`P5-s8DC|LvL_T1E~&4IS^-EP>me!z;^2@*OOW+x~sm zcabu+aBlm~{h{gjn4`?h+PCf9avtv|lr5oe`@)>@KErtu^6IdpUsUwa@_TE#wf=&| zY^Wh;zB=Q0v9X_z)TuE5?oC!-mtkPV*+zW1{<;MV)hW`=YW z`~2Md>-S9IHw^#4QzI%I}lCO)^ZK;bbR=1qW```D* zBuCw;JuIJ~5 zaYFL__dRiNbJ1Npj%kX{KCT;QEfRTeingf-MDmL}VvD@RMRl3W^6vK*d#PBpHx|F_ z;DKo)k=fG^+`Z$AWjM+IzK+Wt9xF)9sQcw*^}mUh^I4T-{&1jFw8i!LOmMO)J=lCtAQ)yP&lbcZcMPhVV6z-4yet6|e-K~=fUU+`& zUVL2ZiDCSZUpxhYI3`ACP3I|$*nY;Rdix}_t(onKipH@mbMtW8 z+YZB`AK7{icSI6DJ~>I>rHJ2MYf4cz(a{?kA9+*UaO{Djnj*kEYUCG@ydPIfsbq5c z$S?Dz%d(l?^s{v{4sD$tJ1|G`n8Lf(C|sO98J7b{JMy-W=OgQI(|Zf@8HVXLXK*^Z z?`$~jfQn6N^Klg~b+uPq+EqEkJIpJyUxQs2{Tl1c;U_08-TSqn#L~rk8%JYsBQK$O zNm)+urIZs@lbe$1S?zr0FPX-z*f^8II;z5F9E?fqOyS0NZ*P9{*Sf{%^ho9C^k@`! zP{-0=Yp1U+#64PF^y0s~Dn_S73MPw+qO_NsG$Jaz^0!{`Dg>U2(g}G>Gi&uRO&>&V zW;-8wbENOY{fQSJd9&_@^8NX+hi^E3Kl3bGTW|Nr#LY=!aT@Ni|XGW znAUVzH)>i|@k&PPRumn0U%~Vj@??DX^~Lu`WPBNZqAx1LM=x<=bs9I@BMjbLPqb-G zmv(>eV06ua6C$(o)A-tFPV@l#@1I2{zYuFG?`EA4$**pqtf&$r(W+|cFPW~DIII(= zzIO1ui!WH!w4-NcdtUnD^F{Ub`}b|R8WchQ?p-hX(`345o#d3a%IJz7=t&eGDoAKh_Q(-+sR_(Puf5B9(k0F0}hc~j~&`0V7`n*w$dun$c)g&rrW=opx>M3c; zPsh^gp7p%+uH8jV#pt2bn{P%off5lY5fxs`?x{^L4KpU7MLW)d)qNeB8@6?A7ku5vjg&@ARg`@;mpg97`r{@7c0flvj?n zubk3&d&d-=EAizs`YJ~YqK%_@(HU37npTVsUwCYLUgh`3Zc52_5fj^v)88@=Vs&?* ze~&j6;N1~#63HjWZW5E}r*&p~^!IPC%v-4Pdc|lvT$n#u!S|B%x7cf9zt8+b{7`!4 zIkEG&Wlcl-4%S819DFjm@8B@(ycy{8U@w^w2S=229egqZiIT*jx*NI<<`qM#s_WpA z;u7Qyj-(#^cyT-%Z-$?WH3#dXP1(w!c3@Rz3z`sfnfL15!BdM&k};Ffk3V@Z+8I4% z%Kil2z$JSNmKQ8vfu3XLUXh&9J_D(cJu~ujv52Md!#iz8(~Rc35U=5)hS9o6$H9Lp zzAO6@=zT>U7-=O&kDLBdcIFV`RxZjr4%SCzW-Ab%`bb5#V0ofljW%+}2XUBQvNyUs zx;#=jqg|H3UK6f9sfjbAxlVBAqh9wR431{}k*}nsDk`!@S8MB}+@8eFf@ZI>VoT}#=v&^KiB!Dt#=04emB`V=9*$GM zU+z`L=C^H$z9mLKjgGqUH+hZBam5!hJhn679Y%RCMSZ;@zv9yNVziv>nwjlIO*gia zm%vz&{mD!{ik!N9<+{p4H*|7@(Ky-_U70}(IW!C(eyO1TGrddo_>j+hSH6*mrB!%5 zm&}o=!OV9NWS&4CeS2QITb7f!tD@bz>q|IWyQV#I*H_ys2TY%=a*lD$$2%rJJ!?Ck zz4EQ+Rr5_PvCyB%_R6TJIGETTi9&CP@TaDaR_~|knR2u`t*LbTrQOA&*}nfca7lO3 zXtpD9AdcQ@%JyXX&hyH)-`CwETV(Z6a^^lc<3T;&gI314pq()e37PMV@8Z#9MD^`Y z9jr^p@trI`lb))ae4KgiMmNHG^&O;ZRbI+6x^;V@Oz9MkEmL<#KeRXAREOT2y?7+jCVSJF?PA2V zdOK~mB8^PnJK-h&i+E@q1F_u^%(NnyX=Tr2UNW5Q&XRN)YS(O8UlZG_hnRO97i>MR zc6%P%L_gj#vL{QXvvLj;LAq|{c$v9@@~GX3F>$g`rv0Xd==175iPP=L*%(_8k13>- zXGzJ`0L-_&kW^yl$1#hgA5YHC6U)ox>^nU7E|+ufc&cJk-krhh`%CybpmRgT2KpA2 z$@X7vD8Pt`Z7)_AvwDne7zf?4x3sYlGw7B~%es9Br>Js8|A4iQ50my%NE_(ba!RlK za5dIZM3#MySIb^!ct^BxDbgQNN*)))3U5#76Jda=x-y)qB>#+K*dJrrAx z(cqfMo5O3W79gw()!g^#1uQLzu~@|ixSccFCs8^>={8IHPASbki?X#lKRWc}&|MAr z>6!y|LkT(V_2e9;wE2Od%AuLN*Blghf9H)f;$2)RXNIp06)!J7zjElp-5m!%3b*#k zQ`)CD)s-LH&UfV$Najh`8M0qi^*RC>^QNuE{Lu7we2??J%6f)hnsc4v(Mb_+fBu{q z2U5E)?XCdTFq$8^6lsh#O{&=T`{C6XMRLumCEC)fNmvASrcMY}{EuY!`zQJ|<*f;FAzh+Rb@?(j{&JIg_PzIDE!Pv2s z`#;>Zyu$u~VW4mA;ME=d{462UZ&dpQ*{Wh*-@C4FU@*P07suxP99Ll}){=GEK|6v7 z4vA^y_a+15N@;xI^$#(4Y8wpT@zohWR)Lz#^(d_MWaAj=L-C@?{QN8>iy}K$4Hdws_;d)=~MURYF5IhZVNm znAIGpiMBY>6I7zIk1QHGcfFnl*;`X`8$th``{ z>%3|XP<5W0gG>YiUI#ahuRRE^v9*y&`~bgtav}q-jT`&>Tl%if^fza&3KzZ#_T5OB z{%~bB)7i7Or?auUu{(n^G7aMbq>Au1ycDRPItLR?xAEd5^H&b?g*>qg;)|Eu`W#8A z-#FM;-+85Je@<3tu5QSo0@o~mTYp@{wZH_0s=4g4)olV3`EMO+>A*{DVm6KjYz%*Y zD9cC(&~{|+Z9~SpRb91LbW8&>Y_y{B+%}7wJJ&86$h7IJ5+;hh>Rgcjxk9+Oqh}Cb zPD-v5LYwK)$H$Ala9(5rj~Dm%;B!kkA{rMbzHu;K#Hj2DtZ-Lu1&=nRJX;^YT5L2b z6|BW}5+%D325*Uk5snmqc^gd(;J=O>5hogcOjl+*Ix~UZ{T$tdijQ+Ug_e4akH(c3w>2)EH$PRQkTdJ4OTNqU&F~1QO2p+b z&hjK3<_LbjLN7f7Oo|@%$QbBrS?H_>MmlQ!nSo5Es})xt^sSp$yQt>$T!~z^UZ#=I z{Z3NoHW(V*(}gn#cGBywU>{AF-Ze($H$y>!JNwqHLvDz9(6}C-vvL zAvKA931puBF+5E4LwGHq6ZjcJSsHE{*?4yVkN%0rJfIxu%ki`0*ACj`5gz4PBifhX zXXD*t;StB+@%WI9w-z+{#+dZ-9J-BnuZ0%}&)|Iu&o*8bbQONaP>$x~_}O?5S$I5~ zZt%W>XB+Ph(7Dq4B?s?O3y){F4c_Ap-dz*m?Q-xQxA0hg25-NEw-t1*_&o!6JH1a? zcs!?O@P377JH6kS0B;2DHr_K9UI};x&z$c!ae8P1ytf>@7c4w}bz|_#5IH-3J0`%J z2_ZXvFI#w}7G8~mw`&5tl!Nyx3vZ@{cfN!7-3joPIe2eacx>+`y=xu3r@+hAe%Cm7 zhb+7@3-1O8?*;Hm@iT_u(p>A{y$w9du|G)SXX5u|2k#B=?D(1XdzXV(vPsDiufoFH z?clvV0p3mrugb!!vhaTF;PLxsQx_rT_g4oTyc*z{{_i9U@82CfC`%XB_!(pJ?==VS zY~W=f#Pn9o8pa%_@mLoae!FvICOX1G+@+&KY*W}=3@j}d%Uh^G{$(MT|R|_0t zOgb`7xU;Sa(lH;xCfv`6#OA4L}P2{v3$^8yq-gQC#E!T30ia6-tojn2G zZymfs3y<~7q_+eQcKntCZx#5)nEXpX&Q5O$@J#)~5q}@=GzV`hJk2yY{@E!+V5C^0Pl4NZ?1)RrG;0B3T4;R zt_kpBkhAM)jfIC#gZ%WK85trNs=k%QN4#gA(S zraUfk@a_N}>ywzbfEyd}WM@UmoOayqken3n8{&Jo$j)V6U@F-`DN$(;D?^jlOH$&LqUFzWd3V0@s#58yxaPZ!+@NTs5h8(Hncr_E?RXBKOTX>(f z@RmDxi-ETad}B=hr5(Ix;8jD2_4zjZC+V8sFg4GSa@Zqe0Dv>Z3H>-WL{7Z39K07SysZ}AKVv$-#RXc)9Aq7aX}4Cy?9i z$l>-3Ie$Ws(wO?P(}~|9#LtxPHy~;13+F?2c~JjXi^ig5@LqKA3h{C=c=uU&e{}G+ z0FQFU7`)>!n76~-3b|bKk7FPQNZ(Xh;XVjglaA9Iycd9n|GqKdwmEXYg3w96RPf$v zal$>@3iq3kH{o(#XQv}xlpC+t!E3YdwpncKZ#sBe zfLEOZ?}v`uHpu15zfnhS-voGXIPtp)@k19O`>StR@tcl$j-7w6P7v-qM{aBaxfVwb zci!Yo$JLHpDdcjE{{|pu*T0*sbbQB3$KN`5WfS1t?cm*E;q9^To^V@y5x znIqRSf!u#Ma@RrbRs#mx;NfU{D82U}ekt(z{(VBru^gvi@MD)-;f&mRSZ70y@>rgd zrUh~)EIOFydW~nsjg;$EUgTdRcMjz2@^}XEyAu+O-#_3-Ifl2=3HR{{!rh?5HSwcd zu6n=D3Abxlh$O;cxKHC}!u^QVkBkH5cz9P%z}Sh%0;UFq}O0=aL)uQ4Vav`wCq zw{>E( z1yTnMs-`w}kInSN9C_BHz)*i@7!NNg%TRx3m|rNv3&y)a$n-{io?&?m-Yr9Yo?*V- zv(SIB!$+rV8S3*4`!5kkfzL8v$|Ip2E8-pP$R7<2b+$ZD9t4K^KEwF-NR4eU${CQHo&6k?zKPmZ?BcF2OlXB$eJM#0Td>}R7 zkzeS@FO>2_zSKhhi4RfiD2L;Jx|ARErMTl9m?(PAu>6@)KIw~`=|Ay-`bop`wNgIl zH55N+^|g-wvmF0tN&oG>)LH%$AEIa-;qcxk<%3>>P*X&vx+74utU(73Vtg z=Sq3J0<<~TJV-k#>KyqxDc|MS*E&bO!I5up_=_EW5Hba$(3%-ePulUn)Zs6c@mb|d zE%l%H5Jl?_<1Lr+LHV)u2PTT0_ON`jBi|ed<0&dGaO5v=_$>~<#o@O){8kxW&?~k& z@@BY%Y>e}$AU^`$U~vrJU0}g*c;sxb3;NWd^&Rd0@UM6H*Gs&hm18r)GEwa4gzNte zQa)%em<(GcDmFXvn=LNmcca6<(cyp0;d6&2Fj4UdhyMvDKRyu%<0&dW>BxUl$_M@R zCms1uJMy1)__sLxTO9sp9sXw>{%sEbHW{CwKe^43zul3)-AV85j{N5w`Oi7>+%X7D z6xzqb<@*IGAB;b~5D4Qbij|MB{GC!hXfJm<@^?A%cS-r+{c@Khe~%-7kCYGkn|mDj zFFW#IcI3b8$ZvJzw>t7$9r>?1@?Ul2zv{@}>&V|L<%9gZ*OC9aBmZ?r{_BqXHyrtI zNclQn>KpzOAEM$uNB%xX{ys^TyV4`B1!`~J#@e~z19R3a&UeMp|aO59#+&*_Z^1B`R#~k^`9Qnr_`R_RL-*NbR z96nc=0~3|1Y62QJ#5n2SYcr9aeGc9}M}D6p|AZs|gp|L|mwLi~;zLwC>Bv7R<Bs|_lwC4 z2quD`C+~`ur2G>V2ORkWVpd50Kp>2#sCdqie@@KP@+yCxbL5|QT6=qDZeXAb?A zL-QQCF^tcd4!y#m&3Ws&kS)gg=9SG)G_%%!XbH%htc+iIF<9SB%`3+04s1tJ?euG1Q z$e}kl^rs#A8xGC$dd4vPXF)UkZv2WxgLp~PtY*cyX>`<)pUjR-8~Q&MH2tr|uNdo{ zr#bvOhrUS5tNOiE^g8^_4*eM|UnudHi?4;~X7QM&S4sW_;s=iZS2cg8u(WM45m-f*N9^^t-`-n%w@&VhWO^3NEXk zG{Z|t|2K&34u79R|ErcyO8L#=ki(Bpwae#5Q3l!=#&f@c_SxvV|{$1kNppBuQw=`e1 zKde__!p-z3`pe?P5WQ8L6{5c?S~RV~zgKjJ=&y@mO}7BESbRf#F+|@dwrN_$_W{B4 zoeW>~Uk{3(fHsChje#PROqBKNr6SFC(4IdY2zABF$;scsi?f+5H zr)kO-i=Be!FNv@C-x6O5@pp;GLiBF&lMwxwIH+mW9={`siWHur_lVOpJy(XeSJa2- zePX4iZRQrHy8sBAT2!XmY8au{F=+&^a?++e|o~O3{p?VEFlV{86osew;5eqB9% zN+TN8F-jS~*evazl3{dyj??sMba|$Pd73YnKBJLS2M5JkL2z0?DspS=?7&S;AoiY2@q@ITdl*StM2JQGJ@c9*wzRYxQZkDBZ~0wHyUaCOBEUt%_>I9lcL}f~Ypi zuEt@7o)lY_A4DeI@M)?QgdEU zFV#XRe@4E(x3{koS^>|`tm}g+RE^S*xuR#iRP&|X?flXKNNt%*GrieNzwx$Yeb+mA zvQ>X+&-!{i!}@Ws7Zrvyq>k2s0&RCFI%!? zNo{Ju{L^bzGi$V7)kY|2f?6oyDnkvS$r~wgp<|=p@#MIcv30G~G-{$2=%A9yRdcCT zMM<{}`N~vPo6ss${ksku8|^B)c-e~8Ep5wI*KZu6!mAY<2eU}IFWlVFrs}p-XeTu? zuG};*m|3?py=p}x3ja!Ed?=%&45RGSM5T($m8Kd*KMQ2l9PgrZfH|3^I+V3aSC>-A z37@tOSmnqZWLIP7zU&rM)@l`wTCt__64C*yoI;vk8&|Y0S-oUE)ZaEjm0b_s9YKES z%nei$D&e7?!SS-l+hqgwor7p-`W8(~hpfyC*&G@+u3f7e$!hdmQkAT#EJ$$u6`gQv z>43)Lfglza4Yc*4>+W1X=y$Gmi8iji0$u}gLz*uwbC~`vs8O+8)CKYTOaZy zJJZ0$uUJ&{${N7vQpK%bJfH)`dMXX|=QTDq*88rE*Xq?BnT|C*t9!e8u3873a>~1_ z_tsAksuU}95RWCj9oYfs>7}C%di?FAtoNvSotEx88D*oWR(S-rr4Lu5SuUaK7wE;c z^KYegHvOK;8RObE6snoV*<`v7(L_r3-Ks`N1%6@QOeR#6s<^8L7gC+87`_rhOX+Ud zi`~s?G~ZJWo~=Gt0ihTJ#ktA}$|`*wyE?S~{=R-)<7D1j>Tz4@S2yy$R@Mi}lYN%k zdl*OB?6Cbh5w85f^{vu_R;L@lG7!7Sq?D@MfsoOtJ5JCr0?|Oh?l|FqCB?%UcU6l( zLqit~4VeK`Wr3xE*OAm5C1%v|8ujIVha70+H7u#O*IaF!S+ntq#xB}-IwyRN=otM1sEdVS|WKW}TgZOO{E z)v^g_9lN+u*L3Fn)VnL&fs|Sab&s;kH!l)-sWZeC*KahEgion89c`?$etp+PS-cf9 z9I*!YM&GXnkl}Oq=f??G59bb$HzlJE>li~TuyJq-*byruRdO#u*rH$iLjr&a5G(!8hr?nXVZo#oD3O=nJ6Td?wN>j+jZeA8-ewdySh+Kh~3GYAB7yrGcG%CkSv z&;^Vt;_3ue;lW3427Kg(GVj~4YF~xszdds?{W!R@KGVEac$xNLX&e@7Y{(o)W{ zCH{I9PCSeI-hdNX>B;@(vJEP{c)usVhbtS<^q{6UYP_qp|4k}h@oPMMU4r;S(PJ&` z>pc10d;EG&e3CM2yLK*qfXakSB5aS>9L=tx7Tu-i{ zMOr-h6$#UgrF#+on9jG4d*UOcKcUhQ|D;M+{8OIPhZX;{C)WhyH>-F>-sj2hdL!p~ zQlCnJ8&9-qnx~uN zpYfy~zsPAiAMZf==>9oR>M@Le-jm4`P8zv#)mtT+^24uNL8 zucJLz2j2#BXRnfP80pJm`s&Xg>shv>*1wS+o&O18wBXQrhs>O8cA0SJ+H{FKs9^MO6}! z!Z3}0f*^|gXS7%e5Wo)lq=Vy<2!V{1kHLJ|F-7u^04~{ z8u`h!T9#)!?b*7VQQle7$WOKh)&prnj%)jj|4G_zq5XK^el+N^?`nFV&fh1HZn#Hk zb-5wjZu&#{nQ#WlM>)xIL_L=E1#(kFv z`9!$jPr0A#{si$!kVd$~D;v@E@fW&Wf2r&1uQdNv9qw;*KZ5!{5B``hG9OUS+d)U( z@T5LT<`3gt_PX}>e|0%Pp6MmOg8bj=_WGud_d#v{UiClIDx!`~e(;eTc`@u*=m2)(r%GKbaT%;WGU*cM{Y?mk}(>`TBOpb^; z;#%^o?`3}h9U~t4%~}W7b(j5YK}5ZuiX*B%LE)>ELt~cjE!eXEM?WIn`?Wi4=?+D* zvfsQ`x0_)PyZH!zv*MQ>7g6;DILwbS_>=kbq^`%`)BRLM1YecFUu8tBr;YNK{UOSm zCh{SbZxQsnj7MZhg%??)@FHEhey-K^`$k=VGpc`yT%p2=pwnV|iS(#`F|y8+XC@+7 z>GpDyu9u(H?~f1b`iV}ii~jm_KeI*0>om289H~@iuOjHo*v~|c72>o7HA&mduc=)G zHTw%{<|mUW$xwgir&4E}aYizE`hxijlze;qh9%8u&r@LlPO$a|ln_aEo+Y1Y;V#t4 z=uM|qXLsiBpVB;~X)u>@|W^{zdZG~DR24AcEOt_9W!Gm?o+@2xGfKl<)svgcRz0=q~By6 z?(OBxfH0GG;+|y`Gj3WI-u>!M!sxck$MXI(F~>`*d;842>jg+#$@Ydr!wbBT3j9?! zX$szgEANVQbOZus9yzf@FsYna##+l*kgYjy z=`}})5~AMFj|*-(vAA2`)zzOF7{FZ-6Js-}9qX5cE^U$%jUW*aS=o){3JrH;u;#w? zSG+4htSzkT8R*=I&BmN}5QV}=6dU{c`n!78cVMmM2r;Pd?95~b4UZo0UE&Tqa7jztlzJ~oK-%&KGzf{ls%Xbn@IewIjl7MmL zOy7Glczpl7lUxciZn%6e8iT%18jgK&)XF!#Gt?QH6X8M`{uo{xel{M*ng#=pemYw4 zY~$SnJo+ad^T6Qoi#{8V?^?c>jWPMM0S-3ay}+X!@rY~i_yv`XceCcflE&cO4$8)R z)QTU+BL&V~0&xZ8Md0Iw8o z#N+te;2i@n8*cBA*Q3u)>%F$r>9>Qw|9`l*?g;OVk zccz24A9x%;8w0j93mv>R3y<;!?;?$7{9&5p_W=ZA+-WX{0OMo&t5Gma+{ri3eHxE# zhlX-&`^FHDzahv0D{I_4K%Z#{EkhE=k^C@8^B#mP_!&bi8rqh#pdRdfh}21N$Ix2F zkM)Ob$fN;}VhrcK1}z7JN1knL_xD1tj@>31yWRYFd%VC5PMCkR6Cd^o3FOcSir{@PDcK#41Kl@+XI1W;HO%oDDj_iwi7^_=bE;vn8MJ zj$+hTEC>09{J#(JrwP40C1uEGKW7Z-Y3MxY#BwS|icb#F#o|0ovn3Uy{;dUV4E=vh z^HqF~7WX;)?>O`iL-M8Kx0+^~VeKzOpTzjoNqUx;YxPkKZ;9r!W)!2o@LmvO$j4E- zp5E0xnM_8Xh3a3sy1S!yo;<=i@ieNc3rF&-akJbHx2872LhO{srB<)$7|5(%*Rwtc zYeCI|)cH%VnUFjGbi-9K3Z@f!(q`{dDW^b0@2mt4W*+Bnr%b#vYU65e0nRw!VESkK z^IebN)5Y&SG&(v{Wsm&FVLOgl{IMm#j4MXFPWI;+md{AQ6j!f-NO`b!no>m zweFbI#$T7j>SL~T$@z;GEmWfKye>JW`ZIrBaw>A+&~#7s+GDi$MaA2&r@_ucPw5RG zg|~_)b?TSOo|E|`#WBB7_FQeJv|Xd^v$b6Zdn@vFsixbsy-M3#Y1avHFYLq30@@-# z*9-9w>GP2}Nvtiye*!j5DeTxy7&oUp@&1P}pM+ht4ByDYrbHcVnyq!7xaMRr{SfRV z3aO^v6T^7X)WZJtCm;uV9d-#9!`}Dnl|?1(YOT5ycJhxi@@B!Fw69epVLuJLD%dpD z%8t&}bP9G?C&5Ki&1y06?~t?S2qsDH z{JILBo;RLg8#y}-l8q^63XX*!rsK!>@%`e?uT$s`zX*3@44$ElZM(l0^J|X717mVe zxkN>NXw6B0whiakVgK&@dXmFOA}vEbx3-BQS5DCmEc+th<25P`^RGxuqIzFxswAB+ zKB{Tfy&~qW)p9dy`xh=4x?=unH3Hw*&-M1zIBLt$eU~k%hv;?#ws3rI&~V3dk1)I^ z3j>`+|Fu!T!ZU02cIG>e0-ix_gz-lKGsQ7tY-d6G*zMf&s%$E4r`=UO{pY_s;kg}0 z&nbG*tGvCgZ28Q({@pVUi4$fu9pB6y%-G1R=2=a%=J7c)a!j)rnb|y3?`Tfmf7FWF zG;tocb~H&JH?MH-=POnm`h5Sb4bhh;HCJ}u-jMh6M0(GwV|C!~y|W>@zf}56wvX*$ zM5l!2&2+I$GJ9TZ=OnrBSAQSpK8~X zKB7pwE3afk((Jcl)p2=I*Yj6iR9!hbJzBW8any@8jz*%-cV^GS&Srb8F4pwonqxcX zZ1*Ze^3qN(JtLhr;^C<%9Zg4=vb~TKu{z!-K73P|7{2F}&oV`_wc;Crvy#>4U2svd zt*@_lAc?KGB(6VCE?KuG)76#fN@A?viLI@^{(;%ant6-nEle&*%|AVL`hrEt>i$e` z2GwVF@`LblT1I<0wPy9AQ`hu&tnchj@*}r_p1$?T1*pEYwU>)}41tCG2tj!4rt=%I z-<26U_52!9Fm=-TlOyqh;=B^?DDRkPsdub5(>u;9%d5aKk%3L?20PZk9_&|kw|Rnh z+}X}gY~-HNxGkoJ<|UjeS=)^CF;7h>8hSGe&R>%qfW&x@y_xw(;K{?UVDplTyL$#R>#@R}AiPXNU@v(|| zcLPeFv&HtCy5QcL^2=!TtI~Y*jCn_}YVj>* z%zk{4&DSVrUzFjG{W}NzHr^YW2TK~faHZ+NUt4YzG{Z2)gqwkb9c~?_b9@UiT)tmS zxF5r_jmI4nrp*|Gw;2vLUN`XS;6^;U8@w;!*~V)IVXwEEbnq>1 z5j@*??I4nHGseX4B{clFA^>FNe6wt=_;fkb<_b6z?qo{eVfjj>Dc$A|*V~iX}OLjW;S?R#$pv0p;9DtN~ zrc56Pooj^06;XSHcPbL}Zbo=rki+37-H!!y}ybd%bRI1d5lMK zGYY@n@@VkLvyJWkUX1XVXMxF+rx_W>F8sKIaw_aQeF0Mn%7G)iuz%Al82%)OKS|;x zeLS|vz;J{Y#+xkVt9%i=UyT%#Rt4{0x62#WvwN zsf)^c7J?ADBO8ZM*YIURY@l$Jyqa9rlhMStu(jc zQ5uG?b`0>wUp;=SVB9ze(~REm;360*41~830)`$#sL>O?uW&wl8n@RF{$h%w8pck~ zTI9TBL8_}^om{=JI16e{ujRf%PNqMd$>D*U7$N8RXRO8{%Ub+dumFGXMLGV^?TnO# zK7KUlyZB>3ri~wP@iW5A`T=~smhS6coayb@WQQmxRK909NYo$FL)AkczBkQu^mlgi zLr7+Z62#NQ`y4V$^;j>I`wjkBQwNuOl<6}=V@vhbn_NO)oEhjG(8#Dl>_y{vS+KXE z{Q=sjaP8V&tKDy?Iz}s84V}CX z>kJrFoQX^_E2OrYTup{Y@^Y=5Pl12Aa=w`-p;c#Lubi_lc`sMay`|xmb8lIA<(xP4 za^;*0v|KqC?JtE^&L5cb|83=b=>#k1NZw6cIX_{ar&i9BM_xI9IxoC(j=JP=<@|4u zi(EPX$#*~b8GGgYX6O>*$~g^J&JRTAj=>gJ&fCTQ z%|}`}&)iL~_i#2aH zZ=dn+m>fc~JI~>6Jo9~%ll|`AJ2|}iZ@0gE0sg;jo{sKXu+^9;1-e_=zr&J7b%#QJ zeP+v{d&#-7J^*)Ht_yUo75z^;a_xvfA>52H;XVKd8?P5~!MI$#E9mFn966p^t0F@i zgXaN^cz7L2^AO~6&G$HOMOTp3V&ZrZ?`FQ&2DzCGKpXQ&8$tQzX}r8|g(Kf_oJ%l% z3H&DG2MFJ+LjUpq_>_vfMf#5>96G!g^SyE(Ss~gaSMvp9BlmBTsbFdM_>cQtml@ch2ZaT9TQl&OF1yuQh#pYcm4g-8>$)lI}CHM)-hveUV6A2M^_VEX;up#=Kx8S$0c*)T{f9`P(N| zKDi;UDcUY7qy5?Qp4i~Ed$7gchhOh0%R_iLr!Xh7H@aMu7qtWRJOc^5Zi5%8u0<*e z(^K|GW>4NPbGEu*KV!A$)moXOUb1#iWOf$2KZWU|(o?03S3PBaO2@o*cQs_QS~j~U zg7~X^W<0!nPc`Yk?p+IN+JJ&Gxru-+7QK-`SI!d$d(2eP-muVqppq-MD;0HFdlgEY z%2%W+4~L^Cn@fgz2B4fJ%;W?ZDr7pZ49`f%3n8vrBnJW)4)Dd-`b@9cCt-{}km=`U z5txpbK=BCY%;B&CUJic{$E+KBQ3FsX*0XL|cg-K)ziIqzye`m`GsfUGz`@2F10F{<#A93x9{t;R*J(a1X$)RFC>t+^ z;S%FRJlY2D8a&&09|g^~y)g#wDmd793E-Ldaok|=ZpX8Y_j%2OC5^%37Ojn!wBpCn zg~59m&o&Jl=%^08(Arx*q!Zr2a7=W5^Kj`4y13FhaE_U#;Ryw$=WALta@VFy(l1T(?Q?CXb zydf)o>{ATh7aY82L8o%y-R|IR0iJ2+$6I*ccJTfT+T<-^P5d5l@U~j%#bTfzzXOnC zJ2kVK2ms*Z8}s~cj$9t(>~PKV806^3#Dj9V%7fo{+2JN8z=Ns-iD&YRa=B)NRd7cd zvL@o2LBE?B;V#J4;Af0Uubl?+uA72#!$fK}o{7u!vOcnHn7qTIcnFUC-pm+-XJ}*F z?(fBn5Ye-YDGlYs8DE&so<1;~(S`XenZR(y7UsJ%xI%|-mpJohn!}$aXV!e@DZ`#K zFx-&~hnJA@L9Cebf#D8YSiV@wxBDXO`2xdlro!?i4!-?nV*HPGsN^R%K*`f46{n%z(FvlEGZ!nsfo+iWdNE0w;j~ZU(};#)U)WmBv3Z(EV~%Z*^aZ(vkfJ|!NQe$Lxr=1@lH+h=2GQ`;dt0?}wtu$8rTFn3WJbSeda`eTC5^#b49dp48J_8%qe%KScZcd(gyHd>#T zo}NBBeY_matlF+dHFX%(EJ`m(pMsIiXgwt(_@-!db7E&9z7P`S6>wL(oQa(r1?8n< zyJ;uWi9JfcAvHRBvlBZD4k&(7^1TrcyP{z!qVxB^V5G#`T5^q)v{Lqqdj`8#WOHsc z8MW=sc!`HXaTy1%N^nL+xb#c0a09|PPfAh$1l|lYmq+;(5hqRKApI*1{;Kw-*oKWU z@7TF;u*U;$VDQ25fLTwcAJR+lW4~&~UA1^l;b)A&TMP#q?-20NeMmfe-1T9&*?8Tc zIR-Jt;H`y&jaP_8F%v)9CVrdoY~x)6Iv3vc4qgfH*rzeQh^miw51wtjn>8PnG$wv` zg0kaRWyOzusfpjW@NDCK9<=>#HF!H5Jl?-*;>W($;63l)(I4Y)jKTX69PId=ZN-nc z2G8A_dR+5dyw@GP#TFj(+u%(`V(s+q(>z$xnE2&G$c|sLg~z$L!8<|YnL76rc)7-- z)sVBtqo;$m$1EVFamS<7i&txykT8$5OJ(1Z>j14$Xdu{@FG--u*;~j$2=JDgWQpe70q-DSsEXF~mQBAMx0CaE?|n6>4PCjV`0`zB zzyFnF_{zJ9M!aTlAV;_k5sVM?fSO~4M(e5{6}~@KFjDr7K_-g)2w4ppj1;icaG?!% zj!ON&ejJoA?_W~h{h@>QoBQJ*{h_j4c9r9EF6H9ri}c-`xe7;qXv)x;@Ldr{p|a28 zxcVfzV?53J$?-P(AiA?$#JbjIN)2JR3OW!3x(dk(+osL^K#oim50Pp}@j=u9pD z&g1bC)$#e`@nbQ&Gb@gHO|#nbnnVRh*iyf^`~qLa%g9V>iY-5`dsZE^j5jL%;l~gM(MOwRb^B6#DL1flD&`4!>BR08qlXuY zk!ZJf`%!XKpP#Olvj^|K+0s6Gd*OEP?#lMawk%dm^QBu}y4pHVS-S^-fAuS)Id9r@ zhR%)*HC-QBq7hmXLaMddE9BbiVH9{vetJ2QR%sC@~Cv}>T$IxVBhKt@#l1I~w zn~M8iyz=@#Y2CHTG!WQ)AJELj&mMnq{GWu|G5Ar2KaR88@Z);|!yjo@;crSm(=vE1 zc((C4US~H%Jo+_wSK-;l+X7m5S9l8W`tfYz)c`LEH{vl~2Jee_w(+)sW}j+|iQnho zVB@vv@h0)uw;H^Cc((C49_Bp87=uT58}BmUQI2>F-{Acm&o(%$Lr64fh&xBV;*Unw3GQZD&0OfFmIChF-=T2 z^Vp;nkK%DSoN7QoTaRS>#&&-%#_N3F2PRLJ3&(cK*d@UD7Rd2|;j%@s9D{aaTBnlW znV>L!Ov)#H0G4=Qct$8JAD8lh6kAAOs8=~GUnu1RH@gKg{?igBDAGvFmi` zji4!?!jJQXTO9tEHJ@e1`M|d|&79);_6wS3edYL{dnCkTJUHHGyElg68|@!TJ|T{= zDk%AC{N5Q{vFabjFfTfDmVyIY{YsUi+?=mr(fF?Pn~r~r%hxG`#PTyjxge8)Mx|Wg zs1X4rb4EaprLCw!J&^5W59kq$xmT9g#+vl1<05i6Zb?X2WEblN$JcCw5oBtTHeTXK z!!D}`_@v{YS&o#OtL2ig%TQSi4$Fmdbf+Ba5%JijNTX|#;jv{=jy2GP$1lz?1rTwJ z>rbLRTjQRhT1Gsni??IrU>`n1;9&#*TcQcZ^)>U~{W$}zN8TUTS27jJ#7d`p{=SFDA}NK$zx-9FquWw@qMPbY@m>VI7hnIJNBf8s*x%XX)GgChUx=<#_I>RC*vDOf zpNF3rnXJJxdBzyL<#4d^wgHd+iATQ%Z#|xEytSYihA{^3!*Ho^8BG zK~KZa7=y=kI~#AriXZ!KgZB`gZM^Sk9xQ1L-hH5KyjLwejs*$pm-UANaFDAhIhJ#ma;c@I^;`e=xmx3G3ukp(@k9!_+_B`%l z&}T{?>JLb1+svm*dCyArT(RiqFz!-yP zXk**%@5MZhaS04#7Z}dl!hF+Olnm!-VLn?%U^p)e^V#DBhV!s6pFK!mIPVJc?H-Qh zhJAuS98Y12^RBQ9TWnxBZwm9-0t3TuFT#AbsKD^PnlPU&Brv?6Cd_Az4-D_43G;&) zG^Kd|jBWVs1ZRG%1M~3XybeQc-w^8@pHjKuo^$GP_%}H89iWNNn!tJB0}lTQ&A&kM zV{+bSL>T_7hJa1_ZHG4dIxI=f8&9?>H08~=1S z5WiULbND|F@k_*SLiEw{+X0gV#_w3PQ9`KjO2vGu&62-7#GfhJ9sboJ{w#5u!&md( z4m~jnHm~$})(n;9q!33yoRjRFU`}vGUIVla=`p9;0Mf2)IbB16X~|$T9s;nO83!%w z9H+-5cQ6C3X}m--pO-7O`e1t{n57r5V%|7 zW~3jI^&LZkIRdkW`VK(O!0ds4NIt}{0uAN?A#uyu5)MxaLLR~__V%3nvsaB*YVB=R z!Q3A#5kCokV7RBp-kU)n>Qzo@2G?KZyi9^xCSKk?TZig7kooxKaRf1CY3b*eAY zRM9=NJ)!ppm26b%77u(tTipMSvv>`eex4K^f65IE)hpyU=cYa7IBo|HJDH6Ga%YWO zWor!1dA)sWI-siJFWwpZpEbwjd(@bSen1ln%`uuMsdq8oPke9j$F{o+KUQBes$=`J zMkC|)kuoHY>Wwn_6j`H2i z9XJR42jdAg!=j;W(nR`kL}))8IrlJgL#ByoHEF=3xEX~Y4+oHdF?fm!{@U*E#oQsh z3t@6kg~z!=m|q~*qJ#QiYMqgfIr1?nAB@OZa)II8B8<K!Jbv&4P$~r#1qt{OAwX7zRK9O!&hD9W_d14vsB)6)*_m_Z+u7OO z*)wO(%#eQwKk``z97A~qp%D2m;zvHqN8Omup%D3AHyj=vd~|$bdjIH9HY8#jIj0?l zR+7Fy-p3xTtV{DF3Rs=U%@yT`AIW)R8>F!{x}^FH0gtV&0OD97;xKP~y$G7&EH#W7 zEcWjtee`*q^xb!Q0V;*{Qii>T?*P+z$16zWGr)A#0ey~0t*B(@tItg%!feHC3}Jn- zZxGf(oAX@7E&c_|zUwQ|gD!-)JN2$9?4|MG!M@Q)CTymG>frFeH8{~+7z6G4Nd$gyWU4wnGBH+D zEZ4u9RRYhqFI-&=Ncck5m5_Nmvz{oM!85B=R-B!agG1HsC$aVDAXf3SHJ6pC=g|J@ zbX_s@Q?Nm!tNH6!n%+s{0{TlO-&?CQoeOs3K;gNB1n-MT z(B-?N@c5;b@=;IG*UN9H{&EZ64-DQPfXDWq_k-VK!TUXqHQoT??pukFBzW{=(&hV` z!lS(4%>$Um+ZT8U90}grh-tj}0O5UL`Pd&8Ji9g(bprB)1n+$~sm5zkc>Mkeo*fr> zEbuIz9T!-n@btI<=MU)X9j}8&yPGcGQiaFwwv_KVgEv(NkM?tow?g6Z6EApY4c?P= z@Xi>#H42aVnBZMDcu#?+^+dTJmki!I;Nic!zqHB<-roaW8`4O}@hj>paIGw;6q8N} ze@ckYrLRCgckYQTgs3BiDmiIpWuj0k5J;QF@-i9c&8Qh_?*C()A=a*0dpWVM5c8#V z^)ei1i1~cea$;W~=Ia)P*WYCLR`*|E__|lk{LO~Xn$3yh4DtEd0_4PThM3PcIwy`Z z#C-ik^877^&o?e7jx)shgOVIXIL;9B`9|c#afX<0#~spK7)M;Ai8a7ykav>f5Gg_- z^4jss`3*_8FcFf^b~@)b*7Zm8_?6`ICjSdj{-)%#;r}x5`6ST)?2m@;P9D-&p4(9v zmWRh2HEL%h5Yx7q_)w7dfyBE+26wvy+mxxj* zqV#w#p%Y?(NS(LBF_Re!G<=__E+bQ*b8S5zX^Bd6=P4*WUl z@ObHU`U^f^Jti||){NHQYAMRC!Aym?#m$VW#W z@0<6N5$ER!n*>$`NG_LCu9Hq+S}C}W(&VY+D7iQF?RDX*jXyoT*UdRvweiB~&L4I< zUr4cOWFr|^p+IIjmEkY>@1{c$!nu#W#xw7A{*|fwd&2#F^Wd?WM(0ymX?qi%l}&Bs zmzO{D%FF`iS$PxYKKT;!Z}YaF&n)`YLV9ARn8V>8X^{Fh57kHIVR*i5Od;klci zr(A=phvZbl+0shJFZ*lkYsBm*Y7uBc|Ta)WHZ+U89aCmegjL#YaijtN6Qsbr0l|Vi|Tpt9ja`*5sY%$Z-nnk`9 z6vTE6j&H58*2E$^N3bbvfV1|GSh9a&{LwiH;;b7dulfuOdO??Es!!FZE%; z`x%Zk-pRm2;7IT;BBt?1RQa@R=g*MSc&{SPa|sC^b#aX+>tXYH+4GX}Ee4pzqmEyM z_ihMjJg$c=^~Z0u;N55Nz6T!bMM%nbufaPEJmRo?cyuzn#|+*tz$?Og#NZuQc-pq} zC4+aR4j%g!`g%_&JnH*$y+1N|tjy!!3rSsm-{8FlyuA?O_40ZI?+t@@9C5*bSZ0s- zt-))?MauoqwjJr?NWIf{i_fQ!q~C%AurmA;i0B@?l;I8|N8c}=S4iaO!=>x5MU_w6 zcJ2yzZ2{oBz$>!tdJPf(b_zCeENeoqTGKNaIfWogp`fB`m9ef^n z4LEN`Yi>=F*HwbxWdh+qr~fa;f%y!we4eD%eXQQN@H!FCT1%0y9T(0-aWI#0U_8!> z^pnHD9g#gW!Ft}ehjX#!N{DNs?I^};g_o))zI&w_AJ#N*eL!2%Dkta1 zd1*`9rX*O~pEU8OgM24Kj6aR~eyB9E|@%$}#VffDQN#?kHhkAj? z?+<)_i#cvTYWPP?{OczEy@ z{x>52ZEl`1#2qpJ8-afu#|we-SCju;s*R!iQWIZi;`f{Qw2429ILqs=e@XHk!}qqS z(Q38oyC#|6gV$;^P1c!elyYC&gK-iYqm6#Nc_GiGIy^qV_kPF)uvyV4_jPhu18OBh z8ZtshqHlC;e|0MMpY>fE&vEt*j}UxYBUxzkwZ5`>2_o4%c~9QSvKOT|ETzg5b-HY} ztgBVPh&osWeBG_GHzvoeElrGD%fB|R?xYnI%yi?5%4RxmMIcth6g2A9+59onIz~V~skV_F65U z?>K#Z*>03q23y=3ukTb~tE2u`flZG6fJz(NAB3>kEo0ab<`b_C>!hbh1hv8!nBSTT zlrG{{@L}LrkL$3LT7xo{`3NK3l>_-G-wK;v6z?+eo?!di+o7^GNschS9=>}B%PIbVTDSWUb}ZlI!FNLzV$W=g z*sr>19rm>y|G96|60A1h{gCHxFD+X#IS;FhHg?e>=G_XherW&lgB$$5i7B@8lT}Ca zeGs$#2pi8dU_ZmPPPXN2hJ$rTJ(lNttn_RtKNBTD*PDOl%zOK8-M;i7S4lc|>iAnH zt|k@Q`xaj<-MZ-f$I_FjUmfZFXE&vNSG!83W#!A94PJKk!L)Bi)@{1+ZGAocy?ctx zN=z>{=(!xzz9p!!zmds?edJL4{re`TAA;l7)V@(`CNom?*&TBNaZ+_a4orqGz5Ar^ z7@Qh>0@f}%g^y16j8(JCxS{M{TAOE^Mndx%^>-Vae7nWAi!%JN{Y3NR^sokmq#gLB zJP0Isn-JIi=TzY_ui)*&G4(pZo5V3hGZMT{Aw}bLLWt#I`4|eG=>3BC8Sqm4gaps} zHg&1;@%tip-@>sj-&YV%@e>lfmyn>#w_D-ydIawxjy2vn#8do)1n&Y8G~T4b)Ap}F zK~CdcLOjJ!Nbs&8LE{}&c>KOe`Rv-J{{)ZsTuAWj+NLLfmqLj5gWqGpYeV69e?(p1 zggE|ZB*$DcpU3zdI-*>W9c4SxfyKwf5q)~*Vn^W|9PY&@B!>*kl8A6O<^{Cj1nke^ z6YH*n^~1W8YrtW06c5SM0)n_YBs(LW{@<{p@L9@fzFXy%krXyhB6Jnx^U{D^VdRbu>#!RMQl6MbxA`6eSDb7^;pQx+I`z6m+e4in2a8+qQz zoM@Mct$YwPjXJQ(?|;MYYB16=Va|RaAa3RI}Yt0%*%T~JH`hUpQYPi;twEB z`4m6eG4>!7qWlDYAwn z21H@htwF$LV zawabwaLFNY=8095EK7l6;(IEtpADynFsA|MciIc&eHY5=D+V#rQamCcTxtP?*H$z{ zp^g$thBa3QHnKJz!o0PB-QT-|OS)f$NXBRy0(w= zEZK&XVYcJ*O}`1g>719z=alJuvL&5y$NxaicllP=rn`Iv=}sOGzr}I#NN32t9g5=m NcK0&u@b4zi|1Z2zJ)!^r literal 0 HcmV?d00001 diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.c b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.c deleted file mode 100644 index 7ad3edf01b..0000000000 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/ieee802154_efr32xg12_configurator_out.c +++ /dev/null @@ -1,133 +0,0 @@ -/***************************************************************************//** - * @brief RAIL Configuration - * @copyright Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com - ******************************************************************************/ -//============================================================================= -// -// WARNING: Auto-Generated Radio Config - DO NOT EDIT -// -//============================================================================= -#include - -const uint32_t ieee802154_config_base[] = { - 0x01011FF4UL, 0x00000000UL, - 0x00010004UL, 0x00157001UL, - 0x00010008UL, 0x0000007FUL, - 0x00010018UL, 0x00000000UL, - 0x0001001CUL, 0x00000000UL, - 0x00010028UL, 0x00000000UL, - 0x0001002CUL, 0x00000000UL, - 0x00010030UL, 0x00000000UL, - 0x00010034UL, 0x00000000UL, - 0x0001003CUL, 0x00000000UL, - 0x00010040UL, 0x000007A0UL, - 0x00010048UL, 0x00000000UL, - 0x00010054UL, 0x00000000UL, - 0x00010058UL, 0x00000000UL, - 0x000100A0UL, 0x00004000UL, - 0x000100A4UL, 0x00004CFFUL, - 0x000100A8UL, 0x00004100UL, - 0x000100ACUL, 0x00004DFFUL, - 0x00012000UL, 0x00000704UL, - 0x00012010UL, 0x00000000UL, - 0x00012018UL, 0x00008408UL, - 0x00013008UL, 0x0100AC37UL, - 0x0001302CUL, 0x01F50AAAUL, - 0x00013030UL, 0x00104911UL, - 0x00013034UL, 0x00000001UL, - 0x0001303CUL, 0x00010AABUL, - 0x00013040UL, 0x00000000UL, - 0x000140A0UL, 0x0F00277AUL, - 0x000140B8UL, 0x00A3C000UL, - 0x000140F4UL, 0x00001020UL, - 0x00014134UL, 0x00000880UL, - 0x00014138UL, 0x000087E6UL, - 0x00014140UL, 0x0088006DUL, - 0x00014144UL, 0x4D52E6C0UL, - 0x00014160UL, 0x00000000UL, - 0x00014164UL, 0x00000000UL, - 0x00014168UL, 0x00000006UL, - 0x0001416CUL, 0x00000006UL, - 0x00016014UL, 0x00000010UL, - 0x00016018UL, 0x0413F920UL, - 0x0001601CUL, 0x0052C007UL, - 0x00016020UL, 0x000000C8UL, - 0x00016024UL, 0x00000000UL, - 0x00016028UL, 0x03000000UL, - 0x0001602CUL, 0x00000000UL, - 0x00016030UL, 0x00000000UL, - 0x00016050UL, 0x00FF0264UL, - 0x00016054UL, 0x00000841UL, - 0x00016058UL, 0x00000001UL, - 0x0001605CUL, 0x000807B0UL, - 0x00016060UL, 0x000000A7UL, - 0x00016064UL, 0x00000000UL, - 0x00016078UL, 0x08A00141UL, - 0x0001607CUL, 0x744AC39BUL, - 0x00016080UL, 0x000003F0UL, - 0x00016084UL, 0x00000000UL, - 0x00016088UL, 0x00000000UL, - 0x0001608CUL, 0x30100101UL, - 0x00016090UL, 0x7F7F7050UL, - 0x00016094UL, 0x00000000UL, - 0x00016098UL, 0x00000000UL, - 0x0001609CUL, 0x00000000UL, - 0x000160A0UL, 0x00000000UL, - 0x000160A4UL, 0x00000000UL, - 0x000160E4UL, 0x8BD70080UL, - 0x000160E8UL, 0x00000000UL, - 0x000160ECUL, 0x07830464UL, - 0x000160F0UL, 0x3AC81388UL, - 0x000160F4UL, 0x0006209CUL, - 0x000160F8UL, 0x00206100UL, - 0x000160FCUL, 0x208556B7UL, - 0x00016104UL, 0x00124887UL, - 0x00016108UL, 0x00003020UL, - 0x0001610CUL, 0x0000BB88UL, - 0x00016120UL, 0x00001003UL, - 0x00017014UL, 0x000270FAUL, - 0x00017018UL, 0x00001800UL, - 0x0001701CUL, 0x850A0000UL, - 0x00017020UL, 0x00000000UL, - 0x00017024UL, 0x00000082UL, - 0x00017028UL, 0x01800000UL, - 0x00017048UL, 0x00003D3CUL, - 0x0001704CUL, 0x000019BCUL, - 0x00017070UL, 0x00210103UL, - 0x00017074UL, 0x0008300BUL, - 0x00017078UL, 0x0049E006UL, - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_base_min[] = { - 0x00013030UL, 0x00104911UL, - 0x0001303CUL, 0x00010AABUL, - 0x000140B8UL, 0x00A3C000UL, - 0x00014144UL, 0x4D52E6C0UL, - 0x00016054UL, 0x00000841UL, - 0x00016058UL, 0x00000001UL, - 0x00016078UL, 0x08A00141UL, - 0x000160E4UL, 0x8BD70080UL, - 0x00016104UL, 0x00124887UL, - 0x00016120UL, 0x00001003UL, - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_2415MHz_min[] = { - 0xFFFFFFFFUL, -}; - -const uint32_t ieee802154_config_2420MHz_min[] = { - 0x00013030UL, 0x00104924UL, - 0x0001303CUL, 0x00003555UL, - 0x000140B8UL, 0x0093C000UL, - 0x00014144UL, 0x4D52E6C1UL, - 0x00016054UL, 0x00000441UL, - 0x00016058UL, 0x00000009UL, - 0x00016078UL, 0x04600141UL, - 0x000160E4UL, 0xCC4D087FUL, - 0x00016104UL, 0x0012491FUL, - 0x00016120UL, 0x00000000UL, - 0xFFFFFFFFUL, -}; - diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12.a deleted file mode 100644 index 57c1427a22d4a3df9b17055128a588c66677b85c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 193280 zcmeFa3w%`9c`v&5%;O6j~1|%+O1uPp(#z>9*FHz{5UsC?bEn8w^!J5GJZ7N z|F<4{ue~(FcGLFUoL?4ft^Ix9e|_uyUVBZ=+E_Z?|H+ao{ch8+`kJe*xn^ZU!y3Oo z$VK{JzrSJS)z@Cl`Q0UqS^vV=%GdHgp9nJ6`2K&+)4hkW-q3&D^F_qtf9LZ@6O3Kx zIo!n9g`TILXYALHod(vdHufL>)S)`$dsd%emU5fF|xs zZr_)~XjfxXq$?5|NcN;-*#v8Dk2JP+L77CSa`mVeH#E6wfAyl^ZEw?Tt;% zTe?~|H+IEi1Do4o*?!j6*tKP6HnlU`Hhf1SP0F{o#Y8rdjB~g2^<@xs$iP_{?Clv8 z0Lhuc5Q#Ju$dzpx?oGIycVyGaR3g(j)Y~zTj3+WuD+jkGZchwIhKY*|4-O6wp|Hg5 zfJW29gC7FMwQfmelY`0K335EejZ~_oj10u4*vM37V_Rh1P^@Qw>jKe~%qXfY5!=y} z$R^_1;q->&_Wt&rLp-z^yLI>u$qmP{8m2uqnCeUpCMZu3Mj~D5rsOIG6fHv<>D)P# zkniCb5;rk`P{<+xeZ1PVwQuQc-n6dWphO+Eg}gbispbrVJA`J1*{t?Nh61USts97? zGKpRayu<9=vbB>qX}30wP3?xQ!{+noE6tHe9u+pzr9g6OBI1o}Bno zwF$mk5mEvTb96YpJ(0Zu37n9MIuf_>21JB3(%RxuCySmCqC-w*vWawa`ZhFG1AGt? zZI5)dwIe~=uit>SX&{ki#L~$2#zj+9 z5lVu&f=!I@E{r1@Z;vGhczZ68og?9$eSK)h(B!!}q8U`Y#`un@K%1#!+qVgzNW;$l zbn}o>twb_cTrxDoBeKE?Kij8-OmV3Cx-l;QM=)kd^08QJVrV-?1#WB`#*HWkMmi|n z7fhsSgmyCImA8+GV2D(i1|ozsq9T9{aWowpq|rq-Jv`8q$i&kE)r{UxC4g3J(=xrL zb1ce(?@pk4I=PEVv@V^-P=i-0si-M2INZzgd&^M!NQRFs*CB~^x$5k+D0hR<6vxof z?T|QbQ0K^o;elQZ8(lz~>jr-+K8&~|&^EZx4%-dy9JwKu9;B|($ry*{Bt<(qip~)? zjwS*qAX5bZP5~1SN?abb=keU(>7I)ryy@EEI#}V4BXOdI5iSPi7>|TwJA3&oO4Li6 z-?3}3XLz8U=2wOU-IvCOXYCyw%@PC;BJB~X2Q-gsk9Mx>=)@3M%!q7~Pl*&o^Qu^H za#)o6od^p}E~FGi3!~c$0J!eR9i1b}1!rK;ornz@Or0D~IaFAV8>N>Z*A1q!yHLI3 zr~q42=+P3;n$57DM7nc08ynzNsWs7;B~HhVq^Mhp!6Ce=Xf7~dP$3i%g*TWNI?=?i zfWkrE*v!;$dJ31vPdL^+r;wl{Pa@?LG!5b*liE7gZSGjt)sYy&z!}N~sdZzD)szqo zm_pFxSIJO?+WWR-;xyZ}nKoy`Zr0uziFDk!8T}!5rYMZUItCJnlp}8&&SY7G)HoLA5~9P8~I5#uj0lySL>4(!bIUqCJ#c8;LLVX4IBREb z%IR@_msl}GYpvsz5}E^TNDQPf#?L3#Cova*T|h(yQrFB|UnB65e!C%XK@+z%W`_rp z@m5p>ml9q^n=vzSaWU-?_^m@!bzHK}5mi}rA5dj(PY&Yjv?x!&2riqc9H0T=a0v}C| zBzi9h;3G0x@73LlMyav47cEXEnjFCVkye~^h)nGZV(itQ3!->*FNoj`n(nzBzY98Z z#o_{icZtv#G$#^?w%AZ}Z$3dsKSmtV+kEoY;i2u*i1V>U7@OCvTel{-vf--LE|oHk zr;*yJJB^%1zcgIJx}KhPl8r5fDO{9NlA?#6DqA;_LKSc)30LJTNb33`u_08JWZy2# zH5t}pP=Mm7zUWG}cV%eZ*Udwh*4&CkR(p^u7_#=rTEH<=Dx%;fdUkH7UXypRwBnUc zVuZ(Kq9%z-AT)_-2o-wa?Fb?+N9YIzN&qe13K=Ddi$MAa3Bh!N2BrycsG@MSuCl2| z!6gXqGD72$+M@%6%Oy~a-Bh3KVv#2lysG8lBQ8>V9-+G$P4&>-5(ov9pp=F8IWf%6Uc<8JZcOkxTDPA$S-E4W?UrvZT8` zxMi$V6zOIvnXyVdhamp79+_ z%y(&*#?Aut=V|QoC21l|vq4H41QrVh`Pi5Xy0r2}QA`k3j$!df&NfLEf(w%Jai^x; zHEox$2nP4gUYQIDoD*MWf)l*FU@B0uGF^)(K=8$wHIM^5GZZoG%_HL zEh^dMW3N6BN(_MV2wVf8JaT;ilt+xRKA6nJcVbYk6=zof;dNwqINggSR;+AI30z}5 zo=9bRubDUGT+)Vp8{QN1Ja^Pn;iJ4tVvHw7TwQTKpzd0^dS!6ahTUE0!1GEQu9{xj z6U!u~aY!N=h44UP<))q#-x3ok15U#fj$C1)vI==qA}JP`INiDqGaBA2($e+~NF?4w z^GJqU*WJ*MwJq8lCN8?pu0&sY)yk3W4J*5Dha}yTT)D}K?^SDfm_HELa5WOAVGX6w zO8mKMHT@yp)xi&=z)qYG@Q9~WUQEM>4785>cLmx}aN$6^aYjnZ@+2~z4{Q5GmeM=5 z_WJNa%4w#{yU_MN8Yb|ugb-0D#P@%>SavDvMzE)c!Vd_B1Eh3nhff0ZhUiA7j0H$U zeUzM)^C<#X|EWYegC5oHt$CMB)s&Yq3Xsha!L>=-36MtTOwPb{_sz89)rDcYj5XFs z=xCCnWDCk&YW)=GNDqcUyqTkf*_p9Z${bS3X849=wx7Y!vzuo@bYe`Z`9`|| z#K7!`CkUab!nq)d<$(AIz)mCdPU z%HV3r>n@RtAX+z#`RIz_D@%CusEtw5eO>*r0g`A;r*juw4s8q$r@Jt%wN+4e>bP}x zuG2b-JCiP3QExJ~eF)o9$+*pOLPD&P*v^rz)BuH1L{EI%a@93Ke88fA)zT0QUVSxq zE3djneA?pgF1d4EYt*tVri{hvnL{yFS;Qp;tGQLrDp(mSYaW^IIqvXYQ+e*##G%Sl(Q)J5)u z4(0Bu+@0q=Yc8%oaMaUMc?%}Mg^C%`L?p8xqT&cBdbJz77xr*gwt7V3`!TUIl9zM*Dv^tQ&ce^b+V)>8|t z|67BBi95XuBY&CzA{d$22;Ikm-yA#0o{ww{6g;$Y20ne}2K zRC8lD_`v}D3P2b633>48*C*~mnjjBYusB5NvM73Sv>>{V$N12DKc6Ukk4?s_FFF;8 zUJ<=E8svP>a?fcBMaj5Vz7>q~P)(fY8vRkyYk9n^kQL!;sM$#KIjoA8hy`qYB=RwT z{rb&Y{hhk@CJHQ%bT7FY{?wR(x>!FH8#A3JwmaK&G* zOUjs+d2}&ouR;6ROc%$;)2Q0!`Rq4(@v;H~Utr)141A%1FXVVpCka|;;EN1=5yzL= zC{d{u>18tv{0xD&lWm5Aa@z~EJHBqp%Vx2;(#0jPEzr90a_tVsD@zl3=f_jdd~6MD zhb~}SCB2r*3t3Fk^Eh3^MkQSdN9BmmeV~=0ct4DX^lipdj?f>1tqe~W)riJfU6$4L zvPj1boskVIR;%OvI6a6i>%Z=+0_Oy%I%O$8U=U--j$JrfIJhCYZ42MarlAg6X2v`h z<10njC6_YxS7a|@td#5;#_-h^D_O`G)teGjU#dza3mBs`Euq4?BC~5S8|#6cO$)nU zy`hd}*$O&8$yW4aGHeAgR^<7nLi^%kT8#4*feXS1c`MK)xVRYY(E(Vbzxz9kd_eh) z#T1c9vlZ!KiogmxYgfdvKb*js!xdZP6kl%wd5*S*1XoKYAGMD2i#`8fq%0qIa`|Ag-jB0V(z|e7>p#2I2Tj40qIu6B&mkR||xGxzv zsz>t_2)4p~0q@jmgz%7g7EKz(i`oTheF#VN5j?uTCqPpjRz~UjQ!sRW&qE)TchX0E zrSI?YuIqaR1l4(ERDS#|7`ndKpsyZ0(nqbC(l?HG(x=>Affs7iluEIAV;AT?Ik`h0GZ zMop2(L>op$lNen!HAE&@#|hYFffKn64ZVIEk1)J(% zR4!4Up|^ScsE?{`APha!Ca=ds`baOCXYu4~%i6%#+p>?t(T8cvM&NHZ+$uwUks(_& z5u9XMFplAs${;-yJ{4ZQEn5vos~}TG=}V^RbH5MYmR)nr>JQzP{S@OY7`rXI5~C__ zz5mRQUS|`Yic1z$Y^>OAE%lsk+x7aBsr4Sb-Mi};-n>g^pFXwg0ldv@*|w_<_KcPX zc7F{U6XRX=;cUhl%=CgCg@7{gaXKci7AU*@cXCz|JGyLtPyTW^_vdoXL^Y-1MHyE0? zUa@Iu>kGNEhCufVxm<9`=6H7|`Ed7Rx4zo_*gzom)<8V=*l^vJhhzVk8x6i1`^)5y za`%h|dd}p0!FbOLxypuz@wd9+Rs8ig1mZ8`>Kfws+t%=K{2y~q1YeDRYe%5>v1GjW zA9H(y5BE|Uj`P1P;7|MwcxQ5<;H-@_$3Ka;H~J$JA@3XA<$E4WmU}#tsh+@ODqazJ zEXHTtG~XtZg553OS#hXr%*W@~Gg}ty2(gOE(M9u))>YM2`Z?GCq?%)wJ?)RO8s5YC z%P1c)cb~cO{v`Uuin6i$V}I~AYwzeUZmpO|4Zq80>V+*+Bm!AzFTL8A`_#L$Yf>Y z{+{TWcqddcqTb z>^abLQ!+d`>bWV#0)LI%{8qAaV_Zp~ve(~fln(8L*^fjGjb*0o+HCFQ4acRp{up8G1roNPYsLmcK6&5lso zp&i=tg+oOM@0y3a_uU))dbGg5WrEFI|FiQu5l62tdgh4t!N1S3hZY=eiH5PB<{h`9 z^tOhF@X_!SM+>69b0tWPCyqWG{mpvssq5;0{Gu=V>QBCPuE6(q=hhWMSLU@NKRdz} zd+wiku3+XZ>k9tob<1nd{Pnp|!T)n);dr3%=g&WWSom_?vU`sDv1XUwH_w9)gr7RP zIO@6AT5Wxjbe{Q1eYD^ZTBxsj>VG~q3oC(G4Lr^6Xa0(4Nz~#k&MK?}Vo>&blz!~@ zh_Y%#tA!l#TjP{A-a`{luNfl*J+&>htyTRfwKX^4Z_e-E`1StlV=wmK*E2tPU+;~{ z)4g9$-nV^0^O@xLa-*#B)_t-0o3`EB-~GU?DErnK{H?Yscc4yM+wix}dH{dhtTQ{l zmwSR$4m=d!HgIq3z`*x%d;RkV&kQJEmk!Xn?$X{@(H?}nuXeAI{TT zwMJ3;Q2tTwi+Q-~5BpjwlaXrgsnH|FPg9(zzdUr;_#EW%`r1vt=%dMf(fgtYc)nT7 z3ZrwP-cyy&d6yNwc+oh8L8QstanW{%s|!y(o%09Vqs_833OP@&)sH60#pr_A8$}ii zV2w9TG`sw(;VnP=#qGsMzZhP2v=F5^UhO+2^fjF=Y~rh|zscH)Lq#I3>x)knHUHL^ zzP$Tyzr^nI@Z3`Q@#&oJJ<;F)iY~wMu^y@#H~(4l6dKD4<6|XwDODs!lC&aui$>e8 zc%gX=;T==R@s2(<(iR9WM$K+~F~`$bRT#%5(O#h4_!5qp;#Iq5C-N|Ylnt2XdXN(g-m4LKHVHREM|L+f&u27WQe-)o~5+i&#Z#VV&ey)NhYdK*QnppNmfC4AmT9LiD)w7Uc^ zalm-i_kUrjk~U`rR*SN`rEQ zJ}v1-IX#noR?;UqJ!{JT!#BWJrVKBSD*`sr$MKN=Yw?t$KAwTC49QmH&cEox~TG7yKMmd>F=Klay#82JXL}%6L$TGi5Nqvlub3oX6l0M<=767)lALTZwsjGap z8r(1C+W8U!e%ky4E}IfT#nu@A!bBA0-<^*(drS(XEWpc!2QK zHkE8)Y=rDK(bjm-pdFKPAMrcH{y<45V}7FHp4!9`Y_w8uRdR#at0=jdv1(K_vZ>7= zyH(mZNqa=vkHaSasV!It9QOyCFZHDF(_%fb1fA?^qTA)Z~0w!$f>O?>0<1g(xxT3k{Cm4Anc&Dsj8E|Jl%R_x*(o=h>v(un?UKq zaY#36Q%aI@zqF6>-h^-~iH`=biR>Q6Hj*7@3{l{CKv~Il#_lE?>B;rAFvi2xFVcbH z_3vD-HZGELHaS(vHm;E~0Vuidd*;M8tL>VZ4)_T$lj*){Zi2nhfIli zr@G8e4-B;>rhD*It73}sG$+$Q_#XWVcc1l3Z*Q;#D7vWHydJ^g^_XmBsJxS@!9zGN z5inHWbwe^TG|DT+^FcVO$ELri#hf~D6NVo0kLs1`b;Um3D-#)zS`knw?jYk=! z?;sdD?s?FUDiCaiqxk9Z__pRR%^a1#hw-lK+XLbxc*-b!-vL9{_Z0N`!J~AUg-7Z8 z?|9esHKBm41y32J@9)6S^}V9$qnW4D_pf-@^^H!W@2sKkedwd~rSQ$gqx5;8OxO1m z^wmMGj0)dH25ua3iMKS5}n29=&GhdlvfYr9Qu=@81l4Pe32VLm8ERa}iKL?e_E}aDD}Xt#Gq|)AM%{ z{;KjEkT{~38Twv_J{sF7qx97q`re1W4FFNP&`e#W%N9f59(Y1+tTIYpi=nRxjh{;A z%K=vU;=oZjReS#^2#UWl>iu@kUt zp5`pgwc7dg4?34k^JAET)!eGbibN5^n)k2dsTGx86qWyowO|x`&8Si;SakMQH)^d{ z`cG+vYQYVaKdtE7@9V%PoT|fD<2_#; z#`MrthyM`thpEF~hw|S5RvGe(4B2{kUIG0O9;&nSOjn0#tb-%7wo&?0?keom;Whcs z!>w7fY9*>V%m<%`+aQ*a?K=E%%y=tX7L1gQRklVR8>zqSe_nz;QXlrCyCQ*!&*Fr? zui=N--*)I~(7w6%uPF%J``%k`%~+F9yFD{JZ!&>6=)@YRE6QPA~M$$)m5((T7t3wG-cyI(;>@ zlcDhOoR7XTv31Uw5>7w#&V=4N;Qtl)I)tYV=NY~%-~9+1eQn}*=_x?EdzMy-b znhMV_M0@UItR8#Ke$V*X!*ipH{8sIkL)OQ>hTVD=_e|bdUKJ^AxuQFCwy})TZ1rI} z2SF(qnq;Bi)3uTcK5f+$N5_A{LbF3EEo%^7YiZfooYO`1-ZR1%HeTef-gs%t+0VwJj}+i;kxG7kwt++C@C);IsQhZ;#k$OBi2eQ7&;p+n{k-@qUUFZHwcycH*pdf$FGQ*;G=0rS{< z6B7leygUagk5V{fc?>kkU19%XO8 zn>zfCCx|*QK`tws=Wm?Ze|LQVIa2mGeS0(amFg1Tj<5W@THamqo;znS>9rWhwb9JzS+H(=kjg_jDu{H4YgZd$l`>>XdQvS}%Dr2O=% z{skMWTdP8afz|I+lWi;5u9c15QtX@j#XO{KMIchqP2ro_ zvgYt}IfnXnXZgIy@f>R`9DgoXY15UBI5m-eDMoFND!)FQQNq*h+gNcc+L?GokH~W+ z7jYDrdU#xUn|5X&wGkAZ87<*{@fF$=IOTh1 zPwm7U)UYS;RoW9}p8gVq_6a}7b{B^#nuBAfb5Div1o8M!<3s|UHaum=-zo|`^Hx## zwIe^Q`rcdK8qd4dxvB+!{g$`F^RD-;o9D8LIn4V;tity$o4`S_vLNLTbY{jDZCZ+! z#TWIRvX+(}U3uB#m$C8Ry{z;}D^ST#7T`3(Dmo)@=)E^5nj(+C_p`}f>v7bas>9Z* z_Trn5y!(?mOFgf!rPfRT>nC#p3q1YNt9|T#>vt*TMd_fw;Wx`N@knniX`%Y``snBp z&moi&n6k0iIAh&bXJ-&~$(Sy3e$ew}TavSP$5$g4}2I5%oQB0Lw zSSQ*0zgTqFr894R`n~gqM(-@xxbpn@?C8bbvskmeess*b{0Po7jW%0*{~Bw*qo>)# zam@G77_NSt=6x;f>=^n{=s16#Yh{b>+BUZ}{O`568>*UPO2H!jXEmmFNz4`q44Es0FD_EoM zU@usI^=AkNcJy95N#|U@&F=jhnuiUr!_aX#i?Ar<7@Xlnt?;!~e@L?)dVfjD7z6(ewXw{@nR@&f~NSnP17- zgct*g9Qlu#PpGl3(COpjNE#o~#M6TjC9UuG3L*Z|2-7h%zi_)RTF@t{XZ_;>OQ3@U$Z67%x_c-1t(C5804X`;A`c+dnsc7RS?i zfH1Sv3%BX)i5owMKUX@q26ttGMl)V?18)5_9N%PPYV0?9@v?w{4{*Gb>H!14*uXF5 z_%$|avHeCbbk@Wjp36DjsYRC?_$3B@3CGvls3rCrz0g?`xBe?QzRgBmVZRCdQUkw~ z<40}OQu|HdmmB!y9KY5^(W;$eyjZPrhi3)HJLN~nsm&5b$Q^yO+T|E8X7Fx(K_k3D z2aGo_c1cwUr8d&yyQU7ri{8iaoA|5jHTN<&ut4j^i`^qPel=gGB+P6)ma)6!Wmg&a ztJo)`LTZ^U$aUl8U%@&YFIFEqILlmJa@3RGt3tkAGaUd-;2bSG>&8+5;mp2_#+ zDJ?c|c_~A;jc|xH?Q*o2Ka})-E}z5x#YLC#Zw3iZWvU$iDnSr^HK*sX>m)tE>5J^M zJVM_kY*5OnPL(5f?sU-$*nUY<8(og};TtY`5&JVqQ=3_i`u%;-%22s_LCXDjFGqb= zXL+bh(OH{!q?~$+a@5CSBqpg?#_1(&zNAI^UBQ+}dM}qRWosz$r6K=ly_wvH@RXx8 z+~A^Du!MonO1Vgnplhv`^f4^*@a4W(D(;-=!8hQb#g#w3fXG`%Qgp#kus1xYXzdrR zwhYLh@}l3Z+VbmP7c+j~Eb^cF>tga`le$?SIiUXr*?-25jpg|UAHGiW`(q+__U{0Q zMPc=GWP);jO-PIw?6aS-QTvb*sR?l$2+;izrZX{uKg zerj__UJ9H1osLhqk~<{6Tj~d0EZx(7UCHO zcqiPF`_GHBMJ1mV`=}*5r28~ux08HS#uM&7(lWn&GR4(^IA=4awgxU4zq8EwtwC`@ z1a6EU614g5-yO8sd4GLysz-FGoM`26f<~T=foHf{ZOX3^PIYYmE}=_gx)s;%^XhJg zjz{tXey7l-lsj<$Vxdbu#ZzisTnMcN=25k?3DKSUdxkEj&MzC9Y;{MQi?6pd>X!_s z1<0nzCD(od(Zz4qehbk~N@C{8L4_6Ru18i$Tp4b+Q!Wp+UrcoP?#7DW0s#X}f+h+dC} z#y5p{$UK6F+D~Paz6cn)z9vl{xmEh&c-QqE0-aA^m!Yp!(?{V_`q2Ek^wD^>6OS?~ zd}Jl)j{IJ|3m-9}Ru?Or!5PL*Gv|eYAR_ z^!?1x_Yee>zseAf%$tV3_n}Xf16o~C`siE_pmsffVj6ujfYZ}&9x_4cqtzFsZ?U28 z6a=l1D?>OkHHN-r(5K2(4dhB+)X-O5fHFx6q*409hQ8IBz5uXFU!S3GE%ebGQ5mJL z$I!P{(?_d2O5f)UeIwA9uU*@1=xfsSU9Rc7-_W-g`j)A{NgR>iG;oK2>&$~YVc_W8 z+ul65V@CK|5x#ohs65kZkc#h%hQ58!7lK?Fm45%Pfjc=3?hV7=Ec{jFidKP?zeT9m zdO0n|IDWtKRN{#A0;iYLd!R1}KE;DgPFQAWl0 z69(=O3Nx(@DWlwP1&+$O^7j}BrGv2QJtg%~n8^^1)_jzqAkec5IQ&m3{*{RQHHwfJ zBF*z>Pa$2tqynMgNT&)bx$B3%5d8ia-V=Bzd}VkjjWy@&QF!n*&7n%7l>AvSbqLKq zf3{|tvnvfN#dV<{;_OOJEXozEMp&q{uEDxm`n$BNdwq5FQEO#YcV)lYgY~vl_E#RZ z)>L-0Cwsmt_IcNg&Dk`k)vBrIyWX=~0^Q<`cJ^^XVIt(AU444SXZqQM#W)Z8JhVF*yD4@c1`cS%XvbaQZ@j_0YZ0plD=VXdZv~2<^lW6~o{be; z-+t&ih==)#T9!Q7R{KEwrar5-pv5=-Q0=zfoBC{@q4Qqg9>C*mDSmR>4mMsnz)F?> z5s&xW7bD)cYXh`Px&?P&c(J2wwQTDX{?eTU1<@}Yx-VMFQ%N|ISb@96eId*yB+Xa^$XqsF5{ak6|4|2@^a;`Gy{n~t-K=9npcT^wr9(W+^d9dir z%en5dxo3;#lpeKeXz!QRSl3WEyl)iwe5VVq^qgW#UOrtk-f&oikzC_yGQQ_+`3v~H z1lS{|JiH!vr37*6z^dG)=S5l2n(Vfi=b1DL6O7Td;9~hfZ%)Y_E^5#66}du`A8}wJ5K*i*!wmmGYZXDU>{(E0pGG zG*&#<=hBFHtie9_MLbt#Y&bp?n8@Mgk6eZC+zbzH{#ZpfbR6%y0x4-61Td{OlA@He9MM-NAFOVH?=Xd_SIyVm{u%-*o)#k#8X z(SQ93?gIHdFPFdG|3*LKbB(E}7or_m>SJiEK>Ob`MxKX97}bjkiuS+tF&T|^X)TZ3 zlN%3ca!>u5Flg5`L;K-w_r)9^vN6=7JBIed-S`qCd?gMTZ?qro#?Rz{ctyDmVr0-!)F`#*+%&FkqzmeW8mj-ypx`kTaKaqb9Z>kINonV9GAqR zyB^&5xrTlk-8hE!+uitbj(6ti=6-vHfv@2BQ?|+q`;A^`|J|+sA|pH)TxrIO-9R_~ zVvcvpt9y5m_UqmFOE|vC)=4u~$IyPg8$X}pol;3NQpeC;5pH}H$A@ePeL3S8x+}ts zujcrm4RKPISYFgFH-4cJ9;$tgq5XX~evyHv8Kz_C?g=;E&+*G_h~Ivr7rJ}GjjuK2 z0Ye_(`r2$%z<#3_FZL7N`WAD%Q)(9*_{$9ZWd{B-17C08>kWLpfxp7QU%~NCu3TZ@ zml^nF9PgADCnd?D7yFy;_%1i_Q}_Sf_!UO@X=djbFT2vvf2AYD8}0wQ^*JSvfL_*M z$Q!tSPJL-G^sO@J)i?*|7|O@1@KFEIiihsrh`?5cPa<0ATg0j)9prdFTPkURuVtT7%oCCp;aSH1-bF8G|KxJNg8f|5)RUK^{8nHxOz{zPkX{7cp*yJZt{tO(w(hnj>a3#2XQG@&)l&0n__K$?CUyY-yFl?s! z<#5}fxO7}2afgIWIltd%v&3B*Ho0yfmdfDQE9sX`ZD!||t)2V_Bl%tF`PlR`I8*ub zrMb-_kQsU#9hW$6YKoA3N?rk+ap@uwSN=|S?>9TfchLmEFQIz&IG zJXJ}%l87Cs_WVkem-uPZWX7$C|B#cd#SSFG;7(WUjJX*=h`2j}Y7KWr`uOj=*?Pdj z?;Ew^7yaa2DY``DzuY_PY{m~djnMV;Vpr0oR{W%*+pS($;0=_CA0u<4z@$w*o!Oje zjAxU#YpI#%suA14)=cNHTka@RKRiJ7+A|>953;GA(b)mw)0qLPw{+HkMs_75@?MQB zW8anZUyzMq^fS_?zK-_bY2-!tPr_cfORUWi&Gn6nwPE7ZjDYydB#venCD^m);kZqN zt0W`u{Yc6CMc|&}zBJY5{v*8P|3ZX|`v-m0GnOFS|GvF{y;*U#PPNv>VcMxLZrI>o z3EDhSY~*Hd`{?W#?%+ZI!UtKqqT0=x0JAVxJj`FwFSxHDQcLirTS=EzXz zG)j5gIL(vcYDy!O-?1!rQ!@(gMFTaRyQxJ}Z?L9@hPP$fSp-!g;L2{i3|H}-@`P74X}|Pw16s47F^5{MSdDkxV2Hv^4gL}iLlSOG9LdOBj)&T%55mzH z&GfetJY}fOBSUQ^?GuFXkSRsuO!}|JLl}C9j^fevwSu09M;WCr42G_6o~Dn|K~ z@4CKj(4;62Ra|_`v$HUj`HQlj}4rE8r&}o+#290FO^Z@qdU3q-!6YNhsc+2 z(fbc72u$8_W4BP{t&*Z^%fUoD`0h7wdx6WB zeq#piAaEPtk1{GAhmG*vg7A?(3ZH(~K%H4u_4hUCD^<#1D}CmkKb_TR%7Zia{Ii?zBg9x7=AWCPlRrtPa=zH7|KIiX6I6ToegGP0Dv4;%hI1%Ii$ zk-q_nBl?)(Z#5L;D_4~7db+FzE?+qvH~c-J`Fok>FE!x0z75mpd*9IatfsGC(^qZi zy9N6EkSha{n@ZsH^71_Nsd9e>5QL+2S!L+k13|uWu-U-vn+BIOaQlJFmwr@^^mKU? zI2ykzgXG}mj||+AX>iXPxTk>Ipp?M|$<0aN^mO?t(uL{=l^3iG*y-}B)The24`({4 z?@@-rPR~z)!~c}xXMp=Kd;agk-}m8A8PY|DY!!E+zYTqU1ekOV;GuX>cqtB=bN1|P z^z9l$=}YzR>e`u24rJt}zrE*wZT>y~l~=7gH@BRe)c(q>+m!4|N)duf>_u;o5d-wBi`ImZ5dEW?^;dfD1PW*&!Zx^T%j#7x@ z67i-)tQjlddwafUCI6)j+HDlO#LGCXc45~%of`8r-5Z{Js(3LAV0YE`y|>uKO=lzc zd6jI)`ozme8qfM_-aL&fX+QqPPl}`XrkXP3*L#B~kK!J6UMlz>RqF(Y?%HwhZlQ2% zhV};Ca@G1P_eF+W6hNhd_6FVVsfBY4{jQ~3PPND}v{&es>n#%1w^Bo{x0EEG#fyTY zaTXr~5lt!aVSe{Az;U9E)7?YYNt$+P%8`CsC5`3-bRpZ}qKoWtFZDsRR{jksujTX% zehC7#4b%tF+W2YM%1|+WO%bq(e$${W)v!o;xk394`byBm3gY2Aflh;@u2LQt9!_Pt zQi*iet;xQ=UCg=r7mH~0Q;!=G_$~OxOgx#?W&Mfx4t#T!%<3+}$!sQ(ZO-sTunjkM zZS8Ds?dTF*zV_ERFrXT%$khzpsB`7=>lU*m~L?w&G{e=suFnr|S z^1M(s$l16ZxQLb+rcBS0{4zUZ@{3*BlON*FByFB=hft-q>E4yB;!6gzJpRhA4J<>p zQ{7XoD9tOVoG7El8Joe-aZRA9y-`NtZUsZf^?;^!NEwCuA{aU@3pyX}4-Fi-qoS&e z(svRJUEjAs*D4Tfg_|&N{{WiWIb{^?r(oz~z=P<9sC}A?hgy7UtEuOpxx4Of4m`ps zqx3D7I5qsL2TeMZQSbD7c%)D1SOy~Bn6e3c=t?Q~4}$(MV@mo>)lTw28ud!H3M+}8 z2V)cr$`dsgEyKGxrtCz(qe=NS;3sw1R)r1*hj%4>rk`W$Jg=(6oG2dH|BR<* zZg)}bP1|FiSsL}#lIx|>!f|VP$?1zWUesLx2@CjYYxazPhGetHJ1-v>ph_T;l)UK=4IHNd(WMXT^W^bC^Qs4i|@P@;) zcu1G_vo|^zonE!pFwYEr9&X0Qy2(2u<+xQ1H=ji+>EtP$spAHEpf^W%vcdQ^J~vFL z=eF~knE3fpl+F;z#o4;ldht$YM8&%gH=gYevZYTQ^|s)oE5_RB`a={xI%7z`7MEK8 zK6fwN(EG2)uvG7SxH(fd;YWS~$nhc{ev+{I-x29&CtdhQ`2de5ny08j(1L#>8&? zECcTzano=w z@40BCA2rBoG@Tj3Aez4EW&AB1+u6HexBQikHtaf2e|%wmTl1E#w&V~wrt!10Q?2jZ zPdVScVg+v$Taq8L~*HjArRBeK<6j9oiU@$@Dxa4yA z+YI%L^$`vG5!fC-)>p{JM_9iLdm;E(Mqwpa$nV7=Z-55fh3GyOe83Zzjz!7|YLc(NY>T?3xl{~%m3o@P9{zSlrg zo1u)-w+;+l-$T$xYqzA2(m?6!#=EX>H3(`mlu`Odz|e7RAgF#Qqi_#`q2q3u26xoJ z^#hmB-~Vag_D-WuwPz}S@0|u$1wN&t%D01{RoKC{-#)&6ga(4fS4PaKd7(~;|WBF_Q#Y_uVkw-OR^>qWpGGs)nYspr!qWL26TO$7~juR zN+46O=~!=aSR0Y6@puD9-D2P^{x$@IS6_X#-@h_=)oQWG`@w6xIV#B78t?D0uYIKN zy68KaLirU;(4UIX7b!K-#ZByO%l{`~@2R<1Mg4s29eiUUzQhRzwne<>_Tr1DV-?7!_Ro(9`^J!@xlL=k;`^Va{j1MtQv=bMKeU zY(AblSk{3%PVe+~^mN=BnFzr49^${?87dAP`{$19cVCV{O%P-CRB>o@Fz(HbmAB$v z&8_kN|Fzx1?*oqp=O9ff1b@LAqR!V;Gg<o?-gzxZD z1t|EvcslVk;i%=r#d47Z%!=V{jBSUA354rJ9gOPjxTWPf-|_w3QHbhnOv`L3cDmjF-lB0g)&JzX0m4&of5aPvGxJny~K6Jdd> z==>=Ez2u{G$EugR^TG#lm$0YBS4;QXQh8@(C||gpm2`M3~YoFGQkVD zctuD*`h{`t(lbX2P8BWnp7Ji*7T$($tt>xW@v`N^H+0*&t47NX+g~_Rcfm%Nd+0kZ z`y0^Wu>v41f7K|(&EvWscJam(?$;guxRtxm(u$V_qQ+j z+L0q~Pu#hrsrbb$lM`v?FL--mC+Qlyt6*HD*hTa`Uw5p)dV%;AErHNX{yp2gi5YWz zr^a>Y3mw++lwvI1eiu``f(dLYar(zPiJztLAzL zHK(Pz`osf(h%=&b0>s3-cB*N?ID zHKJV7`_gD_^t?dce^cJ)%8>Ra6$!>p?LX7$VL-iU`w4b7ven?wW z67PaPs`16U;7@9NdZ%`0e=suP$DPglsVzc&2wuR&i`S>d3SW%8c{1=oxE?pmV})?M zw{AwujLp@f6k31P7mm~)p|{}Oe|QcfEB>Ck+fVzoFx2l^EtU4Y;HJI;(zlr0*H`U5 z;^(e?n}c^f;^?}o9=b@+hjV*Kb30+XrL|4+g<=wU^KWYRhxZ??jaEhP4tsw{{Jlp! z;|CE#(OWpN@@+o!c_&^IpQm_~%bQ+hV+e8GUW5#{(eu=SZj=n5xo*|glRx>e4`|^i9-GVC3}4HF!DGc34TRew z4<4b_QhdpbIw|fOFT~gE-ie^ce}(7h@wZOYc2r9QzgNAys{B8W~&}p{hUru|+(f2JW zK3Wwmi((xY<(9^844;qF9R!uJ12mRID^KkXJ*)=Lh0U+e6kz@%?$>q_N_>Azb03-$ z)Az{e=>#uJ7Otu*S!c$BROs&Fm@u zvkd$!`^z~c=$psIOz|#tuV`%-=ji1AQ6JjU6=KAYg13#A?lz3W4@nAic z@}nM)Ff^-n4E=Vz+rJ7n1~K_ZIp?uYTnIPxeXtvU5&NFRQ=WVHFYE~{{iW}N-S~^` z`*;POcGw+5-v_(#m+OfE^LFEF41A4&4;c7>fe#q?#Rh({fu|J` z$IyM=?(kgh2=PY074McWG4w4l@JkK+QUkx#z%MuO%MJW;1AnD~ztX^8Y2X_Se1joh zX~^~63yS|LL%xdp*J*26Wxvr2-Iwi7FZ%k{F?1icTYe4K=eHsH${6Xp*1%tDBk9G< zK5ocA&hh4QalBK1LIyr; z;KLkGZJsb;^}=m0PM5pWyUE@U`Zf?A$jR*kwyP%ljb6O?qQmVz%JFM#RMdVG`1J;U zJ;yuo$JA9bUYxRZ>)*if&ib;`QVIRd2EN(AH*4A{{2LAYMgzamz_%Fq76ad6;9CuR zE5|$e=d{cs{F@B?CPUw5L%x~o8@Ex^yF12<9RPRwwK+n(dD-=b{CY#)VaPiSd8Z+F zYCZwII8o^KpH3J$#>;LnTWmiNduoW!k;woI}H2|j(5t-4g)`E;0F!-pn)GY@WUMM z)N*|Xh|2G62L3jVueY_{X1~#kmt_om#=vI`{7wVEljEKCXQzR`!@%Fc@zpl!4*QK> zycoT^>-R20KaK7k<7K-I{BA@4ZU>AvFWY0__Zav+2L5vf{&O7fw^4Lj!ZBVpYT!pX z-pQ{~2aGo_yW7Cu&G8`{b+`RSFJ7FOcBju?j(7U6y$1dZT<$Qxz;crCz_!>I91-5U z?288ei;V6CCKJMAL9QDwW>1wm1GL)nqcUOf*_8wE;zoWqejmG3>i2W}J_n39FZ(j1 zGuhlAz!qq?`!7qOu)Me}<&&=P{+5CNEdzg#A-~7o0~P6WkAeRR>vrk?isAk%2L87V z`ERqdbT889w+;MP4g6Qx-4ai2qQ$;y;O{l)`}ln;ib-z%n{-b+q8~Tt?}H{*3Qsxa zhyS-Be_P7CxqLqJQo=|>`brF1{VsSvWOREL-PfxO;jacwUI_W6EMmyj{VY_b%Q4?m z_p=DPhN*jV1sz~tk@^I^m^~zEA9sH_d(0(Y!k%%_OWFT$(aYICyXY(J`&w$bz6OS0 zNaf+DF=jbVU)4zZ7EZ6Szflw6xr(iq@;WZRhTS4*%KviAH!?1LA7{VqqSvx-y4-() z{iUR-4K2rN&EHE}_!nY7a>>K&EzrtP`d@^Eq4ZyiryS$$<&vg)RgTkQEs`c|ImXNV zF1ne0!9{Omf9RrH*hxu?@U*fYNxF{f+r&HtGW`&Ua;zTB0<8@Bx!j|$fC22Y@T#jEuIv{D0UY+cSq-kZV9OKC!NSfBW$}xWYCrMwy z=^NQQk`8hDW_B?aZYcc_E#N=RmP%U0w~JlxqPy9Mi;l4`yXYSF`z|`p9&^#X><5w- z>w9vnkeMi!MF292vcgc6L7hUq*>@63)hdoSzm4?DU6BUJ6qWpZ0 zEta$h-zZxv=~iIM(VuRVG`TIOFO0;2lMlE&Nt|U1Z;eK7z(+dt6C>G3q$jzJw9JAQ6zBNWkrhEYAbhabrj4x=me?{$#2>aeFd@XwYRY z3Vs_u$vBu8jHh-nSQ%U9{9KVc2(F`=>RzPAF71~^gzoml_GBiTNF&9OV*@?0_zo6r zk94)QNj!inNalOlt{SlU?h%#GuvS~{bl0gHAQ1XI1 zJk*!mE|Y{9;a%B8rt$Vza)4hqC6Jvm$C1PmsyO1?E`_qQSqIuo9oxQ5ln0Tbo&D)% zTudetPm1KJOqUE_rlBnHJD?+ov>EVHb@-YLf#Z>};b7I6UYBJE#si-M2INZw%(w3q2kqoYQi}$Y^ z%BFX@5@TAFI%zB-+Z2z-2HXyb;|6t(Y#1Ks#cyc2fHv0+{#1MzaY>-jaiJZy8}3|P zM;U|Pj#59TqqTwuCScd!mNsbSb`M0nb z3;Bu0B$~!Mbno2NWM5?QeOdZemg~Djd|6Tgo4bQe-#`+5nY3v<46DYq5VI8;84JgYCgbm#>rkF7E0e z``>Uy1=(JUuiH@izE3ok&3HPlmH7>u(re*$vRs5@xEm~f*1ZILo}OWg)dENK8q$OG zBC`cVdpf?4QA}~3$%+XP(-z$?w3%wIqO-LrjHv@IjFJ9Sgc#hL zd}m-kMIr{mCOh9q-ofM<)4PS*nA;KL8Rxr&#)#h$8e@M)kZ%^?NU4D6!+%FIWoDq~ z054ZES@`{qPGK~LpN>KSQL_W;Z>N)q(fCxUJqph6*cMCoTEOzoDf9>_fE)zLnT3wf z<`-tj)Q~e@u#}8O9@DwYA74siZC zdZ7@`^kgc+n5awzhEVY6pW_Ka#;gf_RD7NcfaCIG?X^DRC2NDOV(#XsB4>Z_2PW2|zj zAM&+VJGn>cVYhL@xbK6`7mso9^>le$OBYPB?R3F3)fGN+ zM|rM{iu-vmbbTkZe47iIN@q;VUHVEvt1>}4Rl3xIuj_kO(^sMCGw&0o``{>ll~MY( z82*y}e7IW;+-lG%r3|);Zy)%2_@39ocZtMNKHg*Kdjxbh_{u1K`wV@rKwmvTR8HsP zQRzqS@!w7}A0pTfS{bG9Aw!=J^WYFbqz_YNTi;(9`Ua-a_ZNn~Cg=-FeRQH*h3^GJ z-}BH{3b`^We5Vb4S?HtmqVUm)Z>8@YL*Mu``shr9o*#QOeKndsy2lt$JNsM(8m|Z_M82a{W`YzY>B@KOa)*)Yh zBn*8AHGNAoeRmuB=1rrI&UEPM_lTwsuXg@EWa#rxqmS;_*7bc`(?=)VReAXfLm&NS zZ@&0`*U1f1T#Dcnr(_3}r*?R$$-23zGd{l>8# z-=`2h)gG*pII1s~8~W%TVm-df-+-a-H7&k$!d|7{Iz!(X&~=b2qr%r{==&-3QF}`D z_ZmD(U$3E$?i{9YE2F~KZRmSn3*WT>D}8qv`g{=R>8!%{2L`Tk8XVp0t>?!w;ObQ1 zq`yR}GdQZRY6Fhe6O{qU&C5nSe9N46?UO(dj^h8G;qL$hdcG-rKR5K1YWhN&zDwXh zj|cr$eZKHjfUlRUdC*7WI?A`Ortd04AKjzG_ zL6?ds^1mv4>MWEhSL49dX*g9sZZq`x-~d}awo&>9fz$Ihi~M*1D9Vq`cnC-Nakrtb z66@=f|H>$TzhmHT0uD>*wo$l0G5jq>qpaG4>w#AOs({M-6=&pf6v!f8M}#PJ^?MUV8p^PlKCp;0C6_tu$~W)8IB6xV_Wh zb{M#Ofy>t)Q90M+@yIl|ZyLBKfNN5jA=8=2KLSoKf43k%{NPi0-i}A*$4Nuq`_shZ zgrRSbmcL0&-#;7riV=u>?f5?#`u1w&Z-=Ij%CDX-P1ES3%Bsirpr&t7(|5U{ZxoK& zAXi3}?SP^0apnefzATZ&C{%ec_?P_kS7s)1g|ElZ zR|kEnT-^<%3g2!+UoZ3#P8p?dKX8=(7^ZTQ1y1!D#8B^llm{2$F2oZS@fb%O5Y=!$f;P9V?q--_f`~R``F3@olXTErK&uC^mlBF3**s?6-(Zfc5 zU?kgsz&u6|k0p)3vg{7Bj#G7z;ZOrZ!CS*mz-gOAMYZ06y z2OJ3lS@PPI04IJxqGYp+W3q{iWipG|)&KWZclA`a#)fRp`QLlbNl88R_`dqpySl2n z>MJr+JKu|k_z3^kV3O1EW#Ac+hmp#j)PJVn^K**!BlzZ`Jgs;lO~fh8i&OCVH7Nco z@cb$G2wy0X-jAi=OI2<=z(?5SIsm1Y`aPkDMo%yJP_|Lwo{r9i=66Dg_|Y1lr~^dn zLq0zUzd{K<(nZ>dRtvmI?B#eA=1dSN9TZDik=4W*CGd`tw zb8Bhw!4{G?bsE24j^(#P5(^`_GHDGPA~}=M?n~n&%Z22$1ZC~Rur&@IsNRNSE!k!?D2< zvAovT63?(rt^0Niw2tjK+3MMu*XF7lOAND3ZDZX7ZDU<0+s3yc&QVGaR7eY(;xIp$ zA7@KejO91n6*-=G$n#iafA~~nJUp-Cc%t8PSI2n!S1*oMpXyj2nzzH-cGr&et&ir(?Hq5J*XeC_)o<#25#c}9IlkRdzkl1Q&hc%K z2_=V*u&1Y;%!_mnL*7^va-4?Cvml8Lvc7x=JBp_!V$~>#gW=P=y3eWA-RH8aPq%;V z;%E(Iv4lbz>OfiBCY`plrRsQ2*WJ$Fp8)y@$#5e-X$`I;8#+r+q8r+%E*Me`K}#GV7vCMe zMrUAo;Kpx}tt65&q^vFpT|KcRl6`c3aDM!yq5RKBWKFLP96C{NA;Ay`UhcFe7vn1^4YT0>Nb0^+J>B@d<;Pr+8eK5ozcKh zDj5y*cq4eAR~7EBPH)&d(mfgSd(b*Y*=NtrVmZABLav4!Q6HpuLJSfuD;vsl#1^y% zvVQo`*(}CoE`cH>mif3uEUgqge&{1iQB+06o;^IO&4x~DiaMY_$wxvTZMR4WvU3^M zls%1jNInvMAE?8lDeVH2$VZdLVg7X8v>wznMz%jm$2yIe#*}vy-$N)tc z+AeHvC3o1lf9|i zF_Z(IhrOfQsZM93KK_Spr<~5lpNqhBMe!+xot&P+la2Znu+UpA_IoXM`gUrEUwY^~ z=|PMA8x}i#%ar;55qA9Z?=ab@ucvjpmfk$}JKat-I~(;a4Fg!>r<#?G`ZQM>&{BF< z=yokW#q4(7PJX=1$JXg~;`P$kPBDn(CmMU(`*ug0x^N_JBL=ptw2gIjw6t`#x8Q2A z=v9CLJ1qL2o&8Ige@%nIqx^`61;wW3Yqe&Z1b@98$^zC+=v?%NQz{E+i zk9+`3^KIGmXx_;u_WJ3WBz7mYw8u7f_k}yT-^TWBeGD!ec6Mlol7s_i;b)9`iLUuT z*@zs|vJq)YW--rwxacR#y637|T!;K%1+PZ}M4sE`y z-ibX8gtHDZpGm(#o4ctvTrfcPCdjcT9gF^hq@&}eHyVWlBc~$@oKF3Zx|%UR>APE ztf|s_R2OJVktMl=yJh0YfL9IFc2Z6UZp5Jo)pp zY|?q-jW@dS%*Nwk^MVBt*95J<+4--cnFFQY%B^d6`RA>hbSlMxb(73ib)G52mv-^S z9NWc{tt4yxh3Zu!x6fzSWR(oQvrqk>)%MrsW2MyZI)i%&Rz`ibSjqGyj`;%6x$-@k zIFgC@UX8mvXE!|3!InU}`ZesDfvE z59)}vMy&FiKPb&aUmg7Y5vACv-!pN|&@J~4I+d|Kk$L>ycjjxGn0?-%YO9Wr`(Jip zEO#;^t6+RjWO?wh>bz5Xs~;W-$U?qsZt*s#MfS<-?CV2ifr8NN33ZV=VPC{1 zT#G0sR4Z2290-&77jM(e43y?U>OiTyQ75!~#xKe~ab)nk%Vt|@58Qgv7c9C{xn=>+ z*#*HYtfCZsUT`w^`MDYL0($AzRvh zW60M|p=Jkj>Xk}X9BS`hO{@G1Lff~wBW%eBV`}mCT`k*`B34}7J`XG3OWKti$p`A- zHOcbxvkM*`SAVAe(W_pq$<2MWX4TDz@1NFp(WhO0eV5*Yw7yI4r{p`2dc>q6`S<4a zIR{_QqW+NlkoE3>%Zjx7K5Kg zdr6gQ{WnP^yqW8_gqO_EWX#B4s`XpqpClqz$&w^%s`Xpqr?hK|MpsEi>$gNtsywz? zw@}Sc_~!kYi{4GI}(J$RSoLix7G zV*jGWPIC#Nh<`{}pp*T3c&L8V;mJmMpU~|TUs@kMtJ^83X+8A!x}DC#(E6txI{81u z>2ugTvOtl4FY*iPh1wwE!z7>uHmtdG!nuYV;$X)-=lNX zw6OMFs{)1fgYL_+D_-n&WGYeDk(-y{#nu$cVn-f}3Zdct3*rrJ| z+f%RA_O+5c7aF#aoDmvJyKm6uYi9{%Y3%eUS)oVA_zlg;>S6^p?ewysS`!~|5^FjGj{HR_K9;Ju;H<6BbeU^0K z{6Xtq#_8HWM6QLULdk12T2<4l)=Yv_$z~GuDln5ERfd^Fy;{s9Xh+PA1d3{eC>Rxk z@%12s(!#VwAmL!}p#pJE(Hj2fg(2#Fs5v|EkV17dDKTXzf-CWfIfa#vXr!*emwG59u&##1q@C)$}4?ScL;F0kfVW)a2l)$TogN)~w@F))i-rX?E zcp=zp@dzdGJ^=?AuMQR;+$eq&FM+okW*P4(*h}#UCGdLSAmc@(_)$9*cz+4AjQ1++ z`|t=Q@aSD3<3(X9gB!(<-b4cL8!*dwn_#Jfn@|Gp@8KZh4Zz}q8{x_8LNCKE;|;@Wu=wFd@uToX{2*@06u+0za1Mbkl)#$}J{ix2LZy07c=Ec?GVoD8h<4NogTNq6 zVZKEV_rv%;Zo#8-UIIhLqi>t|H@*QAU#fMDPB4KKCBLNTJQBKoLlFik`nnI2p?pa1 z{elQrVI*DjHN;HkqbA{z#!=MQP+X}#P~ORSE@aZR0t7T+jPSlBT3;az53 zV`cdb8sn ztaJyT*pxPDOH;0$JFcGZ$9=$QB~5|X6B%B@et(x8v)HuvZ5MK??c@Dx%0~KeN31$g zMynDoWmVd;x5j5p`B#4HBD;M{Fo(={9lhAU_0$g6$iW@Tc}1B$LOaaxalhorOKM5M zNP4DQwM`t{!Ai(|{T*MADEpi0>my$54phdNZ~w&46J<}H#%+(elMefP1`1#(ZbhYN3 zr&U#-uXc?*Tm8@croS89fpgAn>(0$B8@%M$&Mvt=t=)=8{%#6rH)1YpyEb?_!HV)j z%Yr{hunM&pyBd3!wEQ5^R(?7W3H=}u@qZ(ttlZhQq-|lt&d!|BbphLXCG$kWHF`R+ z#p9joe;}{kH9ocG;&=vDl^%IpU3p)dQu>>>?XVG6aGUb@Uv5i3ucrU-9h;gJRBJc4 zsaQ+eyrX(jRX4XBjNIKh`c67~J^#V#>8aj-$OtOFyl6%+FN8bve73{K&QAUnYjXM7 zdORq5+P~+o#$XPL_6`a45OdeieZcGQTp4Fe+2j-bO^t6PGJ3uishRqf?Q5Ysf}3{~ z>mjNuHn)AUvmxlkzD~A}^0J@jBKF`-?Y&(M+%oq4cd#T_GI+_wSEK%J#~TTI)w*-a z;`(!*jWilIyIPN|o2vp2&nqsUX6zf)Op_|m)Q)k|JB5H7AOsefr#QA5sT{{!~% zha`CsnU&a zS`>4|vSLDOC}#c)NXgff#%~Ut_SDtrbc%ukyV*Y$>m@~NDzc(G0h=TTdXI(i5EhxU zk$>_#mfZUB5S`>H(4MGAU>1t#G!7$r8-B9st!TXP_$0h}V@(Yt?bd811D^`hgp{Vk z*uT@-TGJQntPZ#C+#Q9W?rqI|tu+vwOb8^ek598_2+TGR`D|v!%-bM0#o9M?wzo%_ zAx&;gXE=%(HHlhfNw)6ZzE6aAwtpeC%$$$bw8-B^9p@fhe^}S4ei1*7eaZh8 z(rM86hwS4>PV+8X1o}P*LAOp1g}afH(u~reC9{vu2TeuFU6SRhS>?k0qi2np%noD^ zYObbej3z5FmMelI@rf~;m5*qouE8UZcQ40R4nAwRm=dVKl;h2xb{C4lHWRLJ7Qn zILLTo0P(|(@W`F`C>>wXb&=0+!XPj}GR%iRBHu^~J}G)U?u0vzhulROP`GkmMl^b8 z4GE+uG_Hb(+((%&c#ybr!V`262hyeNXAc37_A*d&MVG+SOXWy;B=Q7C_8cng^JLJK zz{6ajFCr!jmeBp+Qn{N21^Mz$pSkipqTCB+7u5IJn=jF`Wx4QzI@Ua(RX0aeY zFn0`Q@8i32aBkzp3pq;Km~FMP^x+YEv8$L(*f4q@yrl3kADitzrk@b=6dzEk4UdoRy2rj74i!2C!ap(L9yQHpk?>v!s%3n}VIbP7#wO2KG6Y2NQiIh&>Zhr+n;oHaF`M83x zF;;%>ymC|3In`Ek?h7TLmfH_czJRecH7_(|Ex#x)xpn?ltfIpCyZ(iw(|lkyZgQuw zxHF)Ak6jU5c_(tcNVzU!qGK8t6yvPT0fgk<_omw}sorYv5alO{@_j|Y(F?dmc&dM%|J*EA-g?%4b!hOCQ`wpByks*t=LIKQ z^W*tPSL{+JZ&&l99=e&{_nKqQiJXS#Fek{5X9w+rPok5bSeFRGr(Lpp@dm%1Y`#r_Tb#Rustt%RZQGfmO84`sV>)``B43p1Tzi>}=ZcL&YNE>8K_#eGpbmFA?a za+L0BCmbl6mkGbbFEIDPjJwQ%gB#i7=|i@LoOYVGlRJ+yFF!hq0|kfCf8N1d86MxC z<{H%Z+Ib($^NIgxa}RoFX-a-e5&z8l$!Rp6K5NF$x8UbX+!X(r_lXmJvV7-T_-EcHZjKL)K9b6Ym0fdu z3N7)WmEWXFb^kcwCv$y4k{KpCzauL;pF{jfRh%@!MCWtN^b!lb)Iv{|Br)1>=Gg3? zzp4xj8@@W4>5B}S=KmVL)<9-z`3fKTlTA}LY1M&T=)Q6)VH&3qZZ>=^HrX9~uR@aU zGVL#>*6>N4zaM%wbK?fnq$2u5c*wsG54Da1x}EYo8*}}yLKlkopT$G`G_I%b>96Yc zT5k7XTaiY8hTD_h)5(+kJ$)Ic&tbTFgX3xG%VXsx`#eVTQvB=b&u3zdo=S%9KeV1d z`YRLv)$H$0_CofLy4}b9FJNa09EvnA%I|`1r}FWlylIamDa~HOt}@w+*+P>YvC;<9 zd?5nM4K*7+v9YFZdBsh*O6$&zbz7UaiM0sLUK8064Y%SNFaEWjv(y_bGZq>&KN^EB zEm;4=Ul))+@pGKU?%IxfB-q{+(N$~l4OO5T`vy2SWIi{CySBI2_u}4_4(uk-qRX!- zYV6pBGd0?|0u!O8bEnDGY>9-sy4pKQ&awtp+p)d58&}4d?mkLI5_=?cn)SLQt21Ij zfvmaXV_WHJrN*x2)^6=WF(YIH!VLXkH#Mc83xIoCyVr(0x|(qBOoHdb!tW`^lMO93MYJ$&$w~t>8kOu=FPfGW$J(f@bgkBynpbL;WJ9yk z^(HsNIobH+n5JxkmuC=_-Na$EB_TQ9SoOP1!%Xcv6?TgDc9}p@a2kM`2y$(&2(?4G z#6@*iiddUA$tQJIURo3Q{hqHBI7klc$5bM zZ#&E~UgKr(S}k~+Bs_|j!265^kH$3pc!VN8Qh$a=j$a6PG*YMZ(u_&qJr1)Rzmu^0 z@CYUF4#Pp_OTeBhn4k;3?_2mh@I-MGiqb;r6+CkM;!^zNeJQ^NpB!!kmRbVPl?eA= zVVCjtN%=?b2jZi!GvHswdj^(g;4YNFbHQE48vtH8m?-~f1}5;9S@8Io4GKV40*}r~ z$#|~gH|&-YpQ_FabW z2@BtsFT-b*3r^>xN<|{{_>q;)(#!c$j&x9YQ97tk5$QN%3D+v8SmcXU-Z#k~PLFj$D@^``qOeFcgMrEk!Er_BvqV_r zAk5o8BHz6qk?*g-M{)SDaKCQB%SD7l+$ny-d{oDS#uf32xRZn6`=QQ9ZHE-?6H4{H zf#kd+Zc&Yku`ht{qkM0uLwWp4L;{{gxTH(YY!rA+=$NT3Q6EonrFuqXB=Q7C=1FJl zddZ`}<5xy+ZQZq7|K?zPZ@}p)Z6lKQTTxzq!wvY-u%f*3Bkxa&r%}ks{YhTTQAaP> zitS50&)EVQ0q0oSl38QQlC-f;ChS34|8zB|6RrlFplNvNf_ zt#!WY&-61qKf>cW!lvRm-@4d;-GZ@MC!ZgpT}3On#ISsP5pY!$PQc~5xntkD=(}z{ zen+n>;nZwUJr!9K2yr?KW>(?l<_wrKDr^%%#?(s}TqO=pae$IrfjE^YE48l^f`{UQ zH03y!rj0q5&KgexXQiS}&^HN>GJ3(~i>~D>y9S>-FdLk6$7d6#w`gj*qG+nW2W#_1 zSU>kh*E-3k#oYsUeSH`>e_GF_x^2gbh^*|q-un$FY6(e2>$zrr2j_ptU=brc&4Jc) z&HOITUuy7+H@@I^Tln3azt-TV(MeL#dakT!y_P<@P`hlzL+eX4t`UmbbQvC^@5MuV zH88a^6w$9WY+4_HDI@16e~>O?I?qe|+jM#zr@Prs=t2=)yHB2X4q^?3%L_5~WatwD zv!k)7!p}g|1&jj_W;X09=xwE`UpJBVxl=kw#}t+o zLhmPiE@M8@v1mv6R7fw~|K9!y5;tN^a&nGmj=o6z<>*GLugE~@|D$Iv|99<;pt2Im zt{av?m&YI>5L|G}!b3dtkX_Vc(L(#-wil030xt*$87~4tCEN&){0h8on5i8JJQ@?1 z!7h}*qxK-<4T2!zN4mh<2eXVv>!x)AOy?u(!+2!8LlT}mcljpx2(KIusW>bYXQ7Bj z&$sc&V~e-p_)*3dhY{}g1elIRR>G8q2+Rk|C>*ITpuUOHOJ+)gJhqsCh2~{K5e_LF zfr_?XFtXsW4d+{$;a2@8(xZR?Kh`onsBF8N3xXq(|oP6G6g?wS8jttnBtQQnGNr#z-d zC{dcX!$IbYz%GwP1Rs`=IiKjK`e9GiPkjpRazFJu*gr}?6+j#B0qjGbz)WUOys2VKi*hbN3#@GHZ>mmcE!3CcdU-w zMKUW^t`3z44|cFePC$-?@(ASjPKKHfh7WdBPqLPS;Zp4Jd8oXM??u7sftqh@!|#Tj zE$eU!N|D^c&fjji1_SZw=X}H*z2oG*snb_ zVqcX0j*G1b9ImC9EO>u!;^%K?2iaq^4+Zie4w58`*$w-{Z)sd1RXM?gjCuD>C z3|}BkJ9&UUH52nTmp`;#%MiRt{UpcM1$oZSBWe*OJut#o%d*CgK}N&6_w2TV)%KBf z@1@zk3Hc57Ah{lFSA1-O;XDK8gO}($gAyFr)&DGdZJ4!vYIQ?tK}W-5yS)7ecclgM z`?<`GD3`MV9x4o>Tt_l!9}Sl_;ST2QRqb^n{gW-Y?(LHQe`>x*9b4Hpt=^HH+Jg!{%5&oTZ_Zy+=cF_N)fiG_k@mGPSrnFxN(~|B%?u8dQj>|HrMGu^ zimIS}^V2Fs(p>S!&x-#~jlD#B6g?aDEz~xJ5Yv@%mw*wk?#vdlU{b-@~v_+Jq8(``{plyG%+4 zxr=aV4lCom0E-`PLJ2(D>m=hfN_f;e3%u81ru1RF$rYWwA$*~P`5icrS>~hmDU>k( z9u6|!f59SX#4F4;xD%g|7a*h>3)6Qxgc&8jq`JZPQO3fZNN)iJpetb{UBrP%Bv-H> z54sP2W|{KEgNO1?q!mV1hN;wPGU!U+ZEx>_$dlHs(a0V?9yaFeD=+sw;D+n90|*~3 zht01oSQ=yDdsy!uB!?}^?|Uc>zPamQSFS%T;7i-GO+8`r(YP^pYA{P3|Aqa!6AOpv zRHrX6e^=RrMzeDc;-Y5`#(X(LS8)kmR|W6pJG&uwYs?$W@5;t5c6H1{fA_AuwKyeU8dqYBiE*yT*XWTocP#6Ar>nsK zZ;ofSxlUBW=i`w9TFsvx9P*U7CPEI+iKShq9BC(Zb{=%9C;TNlw>c+nLb&stwi7pi z{|xy5m(w}63T|(~tpaZI;Wm+W&53fPz&06e{nq)>Zr}JaaGY}3PAn#lj)Ap{kfzrh zo;N78YZ|Vpr&~O(X~@R;a29ioxI+sY@!o4BQS9ncu1L=T1G4wqz`Kie=5Y(=|2+98aJuR^n9kz*_s%f2EzZ&7w5NA451R zDIbvDg;V|4?@*m5+>}b-t&Dhh{;Z5V-dQqq^-x(rO0QHWybYcsuO%3rAYM`6AG9A& zxT>{WoWEmW?UQLXLX6xEa|_H=^B#w}#He>3|Ct?mYjKh!q~#&aC;h>nCtSZMjC}4e zD^mBn0@VfTJD*Kk^nTg}+vI}un}dtqSEow+>;TT7ybpl}`yyBWlqvgi1NLR>#^5$! zd*A*+<2jb`l|&u8rTT_e@S_%^G)| zS6t`cRvusUzHO3CE?~iPEd48qdhWjv{@3pNc_Q8q{~148lW}^J=KuYK|BL6)CjlX2 zJmb8QG5NL~zur0qoQw}LK(o~#o&#y+$|~25%D!*D%^pvGKkecH|J60> ze!KtOa8BMxP9S5b1~LGvopmEMsIzMv&@o>=K5I?GSXUm*Y{P@+nBwy9+jgQW-MwxjWMRrIgPtuZO)m(ra>BfK;A?^YDbdZfbPBH}JT_6CCKO8>yP=4}azyQ$7Ao z+rHf8=Kcn@ZQk}+m%HZRHrwHHI&ktfXjfD3Z_D zU4+z5ZT*1aV0_)hSua;(YvgXHW88_JcK#4imCC`ey&)$;w-V)q&<>f)---H`fycw& zQQCVaPviD^j*%}rBv`)3zdzgfx(vDb0`QGnbX+x%wHa^*t_l?J7^%yP#>^NAjzNB& zNaXnz2J?sVBh{0BRh^)_u>5L%=%&DmfbNH{XsD3psV*zmaVn3_L;UZy+xWY{4%!^Z z!YuIRN0nt6AX>NaiBP$y+!>;wJ?Z-9vhHIC)uHte)GF8 zEs)96V@^xdk{<$VMPRWd1sbO>5IrW&K+$`m@<oOv|we?Od8KPq_&VdKNND1C=~Q6_A`l zan>ZV(pkpOANKJ(t{i~~ryNV*+t_>4y#v*@aaPhAD(TOiP@b;fH07JyLZt~;de)D# zUS1k03DFz)OlSJgz*;t;$t-c`aX>7Nc!u0TrE-AFDlI>Xw>Eflz)RsfjGAue^_JGa z(DtFIyy=~-(5XM9#*O#2yYY3b94f`dp{oOI(TT*~^1E%06N^GBAA>0+C84RedD_u` zxV%)B83D+4Jvxu4>{|V6jBRP!_-l!1g>5nmGEt|-b9p&xyEIC%GJ4wisgV*Mn__+* zZUOvh_r;xiTdQkjLz-?L`%!x4B0V*{Un=m zz4%4kc1FH5oLb(ZZHU1cXZ486`78O|a{Z{6lpfv&kU!%59=VCSOLv+nln=^@5MSDj?H7yo+Cp*>`8MJxOI zy^(v#jYe2JjntmnFiE-|v%iqb4>?E;^ah*N;PxNfhE~!;WxF|iFnkKD;L{cJT2Hs} zZ+&=w{eJp_4X5=!z*_RoQCdqbclp)eyzbN8@Vi~JYpuYE{yr_Z8MVf#ZVqjZZ06q! zMVVI~$qii1Ti@t~bXA$mQnKolTU?9nlUerTVf!g|Z7xno<8<_dQtU^&eK1r5xib&c zl;9L~O=y;_CQ^0IUgWKrS5p;2t>XQI_D;eZqY{{qYs1&EQNJ{IZ!qs@UT9Nj0JkHm z@%(6Yd~=i)ABk@E!=z-Hx+#PY3mWIES}E-m0c^@tv1=bL!K$ zo?Y+cI=P8w-IQNp+!Z4>ujbEq+w*Y(`ZmATzfqf}_zNY*4sQ%)28-hlCTe|Ojk}g8 zrx@Pw4<-V>7PzhP{Ss~$Pd=Df>npzZ!9;`49&CZcXbN8epU4xX%yYzh(zZD3Bs*{4 zV7vGq8G^ygkI;{eJXaHeJNtc_pnTu;2gvns2g+ z{O7CFPkR!!iRF>Z_tpQ(^xt{T;aHQf?^IS|)bE2tsn0O}n{x!KoCnYv1Im6iFfWkD zaW@Uwmi_GreSJZ?JYV%69C1^+eArfSSj&f;BX;hG9Z&;6DAGzp_E&HCt2g;`l_>j_ zB8;fula;t;gqPZ1?~%fQk=u_PNCe8+f!P5!5ET6leA`g@&|;i$SMk+K>sM%mskMoI z-X=yNUx4bn9rb_Rdk@4^KeZHcWxO3|?ILM+2b2J>l_T;m)@*_&ca2`?$L>J1bM!$P z6>D9lWDbKqfyVdz<{zx|yc%UXc`ik23prasB~=hgKkyiq3kQ`Q4m9 zj{@Y%Eeu?zy@6)_49@=}gG*kSrFFeb3x6i(uQT|~Uz6y2ks05^zd=xRC{8Nqlz!S5 zrKx02ke$wQoBd~V{zikJN+YT0EVr3Im-7!AEXk50Cpyb*=EtT!NzvJDGo4C3sp#yr znV!$XD>Yc?V@gtytZOrW0q0+3uoM_3GSFFSGk+oHf7#%o+)FAO^I7>W1%m$&=+&OO$OIu!$bxfPC1zI zmU8}bgKMc_()h2n@Ly}8UuU6T$MNV}iKea-2Cmy!g@wO@^C!!v!ot7O!oQO9C-Z-$ zg@2WWf0czlS#!vvja_fyzutm(qlJDW$4lm~{Dpw#}$e%S9{xzJx(Lh~en8;wm*LE}hTF#&BMb}#R z>n!|r7XCU5f4zmjp7SU3v);nrVBv4z{K@n-Soj+){EeLdkinHqIXT&|o4}mjJ2`)? z!7uMNApRx`f3l=Byk-l%*+A0h8!hyW?BgKN>!%BkYTD^e;eFh~|8X9_WGf}#NoB*y zK683DS@@GJlYH6OW()sj3;*UMIOpGD;ooARf67At6vs=}pHEr%w_5nOa{grbZnf}- zEc_wPpR7M23xC+cAGXk2E%a6kz1>2WcbicDZMV?3TjI0bf)}yyM=bOm7Wxj3m+U`w zSon7uvN)&?DL4sXeuM9{@ON71o$NuK!_NJ8TKIQa_;<0#P5iqo{9VS`O)WlM7XMVs zlgfrK&F1)a)8YYFT70^b%rMzl)WRQSujw2bf7HTHy91KS#$xPWl2$%W{vGTT*XQui zSrd701J&DwMAQ}8Z?@Ri!%j}O;D=lAG&*F6~3X9{TWWrWq0UyszY=aawqIUQT+Z~r_;zc8{^ZjSm@8{ z^m0zmXFs;k&*}6^PA_277WzD!7N0jby^!4iyHFJV9Txj`i~U}U{Vy%{r!DqZV5js` zPoK?v?3Wh$2RfbljBFaeqT&$0kK0Swa;iwWqWF=VMWM*vYO&v^``7Y&A^WO@{&k(c z2!69MUVYg@e^aMZPnr$MJX03B1N$9>qVTV_*sp_~;_t_kjqz)ZZl{?acI>jv7XF<& zo!%kY>^k;23;l0&x>i3c*fSRTF^hd%=hyOcCHr@ieHF7IA{0L@KG(BC-A+AUHg=G# zB7&|cebpBGI*YyCVt>G5KVY%{y~X~##s1G0`@dN1zqi;OPAxrDOxYOE7Q!wR#eb~ow=&v?P5Gzg?``aFbvuQXjT;MJ(Cww%?q{cU`$lfB zV*jPv^SHf+EpTago49=qyG^&}a{F2qHreag=XARkUOoGUZrA#g2KHm!{wnw1$bJU9 zP~_*=7W?}ad+sd3t*u)WTkI7Ud%eZp3OnUbBc5!G=l(*sFX#3q_BGvJ&h5?YySiQL zuRhLxYO-%)zc<-8vpHDeAbgE~3%gdgYx(sl)}Y(9{N2hTx?Rh!5WhE){KFaX3$wo^ zgRY3@h|W*dESt5mADZm#>}}ny;caKM0h#bL{s^0|+kM>s4#wn-P<+p-d>;^`Ns(1Q z|G0L|ookxwYqmDk-L(}*_o~|3aJI2G(9zk4tyEpx?+Ev`MmC0VRXt11SsU&PvuJx4 z_P{pBKhc35v7cVk)yBdyjs())MObY$;m*z$$j?pR&N_DJ*YE@p9V?EbXwS{?2aJaRtVv95N_9j187R882=?wFLrG8y$i%66ujeLkP!qQLUnl z-3HsodN+3C3~g&y-@1En#;ddY(@9zqT!+19mp zM%!aXoV5bAWU#q*H@An|ID^GgE%vu-?y176ifa7>?r!ha!_>FJr{cE6YGVwY0mZhl zy=!}4#8iYLF_g>Zh{`USM~eEL?QtukwZig?=}{TvnAId@UB~OLe-Lk;pIC_^6GcB`3LE=gyA05&JMd@)Xp`Lelxj4zm4?cn5&YG`4z2d z(Y>BuhOQpf%5?w1++Jn64!=OT#ThXFm&D@g}G%{AQrsIBq1 zF|mq}{rlL#3!V7iARYWP=OH_N?^M4DJLx!>(xl@xkiQ=?_LRpz07qCAi!p1(YOh*t*D5e}_=5kHULsCLec(osh4i03lW5ziY)e@i>BMEtd6 zhtBaP^nCh-Ue3SN@uBnlfxD0Rf2HT&zv=EjM;?>=zv%8~b(~-8;r^?hFXuG5eN^5& zU%|)Y3-?v{+^!C5GLJ5_Bjgc)b&1HzhBq;NzYce+-vt-h0AntV*|n?ZQNEPkLX;QRQU3qEbD8pbLh_uXw5*VHlzVXFwJT4cQ?pv9 z*{Qj#v**-YGbh8T`S7;2zQU!Yi`0IMm%kWk^h)x9<+KC*!&p*GuTuw_YFeF|Q_L9k z$@G<(E*Ep_OgS~mj7h3?0@suW+JrQ0xS~4^Q!^!}gsJKBR4O&cjCs_|n2L@- zYdvfxgEU>5Nt`ihn#nSA>XbUJM)S2yqCSLMo=$xjt1+>f8B5cgz*uulksX(tWX*&$ z#^KhU>@t-)^`t9xn)uWyHOa`wj~J{e<(G+?InkG4O7_`&B|3HNOw*_AC`4ntsiU3=cv~!ma?4oQ}=J zFipz1jP#iw7r1lyGG7=tvEBNafxGt3{MMjBiRF6f1x>OYW_)${qors4-zC?O#=t_^ zbpy?F@cE06hq)65k~C(f@h|bvL-qh31rLq0Nj2ih*_+g4;!W)(FJfI1@Ddx7_^1<&r(=F$RC;QiKuR|Y%^ zm-3JDN8ovpAg~(k_ZHy20lQEFZ#MYk^4$cy0Wc9B%{2vHr3H`f9Hl-%D3O1(H%Z2u z1YQ%E2+xN{;N5M(+X6glKSGK4(VeeyIwIin2`1Mf_el%hUf`vw zr%zb$Hc5C3CA`-xc&m{3MJeL@I<~`u;A?lUK#i(pBGDb zVs93zCs)J3^Xq2P1m0EXPe3wgho$%})%lQB>_+g(<&l6Vfeo@z9xE+)uL6(!Q~a*Q zBg$iw1&=!ARiFzc;;Z<4i27ot3K)Mpxw_5NH0j~@^6u;GY zh>z0WX2E+Hg|Q0mLJ7RjS@=f5m#W-oFQ1&=AA!juz@Q7fS1f#Qg0D0M-@jYBfNkGuM>EiID+;g z@Tx6%6B6DUunIh}*HF~qmw}g?0`E~vxF;{e_gxF$Z@`zTJbr88`v83M_&}uN9QfpX zIg4}<9@VP`DINJpfSk{H7<|2&A{}$UC*vi6w^zq&l<=;%;7tIJ=t7D3Rao%)QJJZH zDSmh25&2AeBIWok%hJ~R1s+}pT!k%o1HhwlCp>x&3%tLu;B5w8IY-cb1m5Q?c!LsN zvxN7*EqGr9URMgdr!9DgB)p9h-s={;1n?>)JduC2w^J^U!xG-dCA{}6c;%=Bsqo&l z;0;T7)J{bH`7oZ6%Oi3byaMpa@f(%!HcNQ*7Q8_Vo+yts7Q9!12UcFbG)@rl+h)N# z38q}og%bJq7Z$$XfRE~*P=fE97CyT-b-Vnjg)bL;G|v)Bq~mq)$@y|p%9k*hMLH4| zyh7lihzuq0rYv|95?-r>mxsn6ms{y&@N&T?$M39!*Dm4RY{8>@?5RA268ZN@3*Rl5 z3HL5bxRX-25rB$(`Ev_iE%1CIP@RvgPk;~qI9H*mHtH*pq>OCFM)B;1`MY>1u2e6`t0)T?*^f#we!-YXD1mpK zev^?;S05(p@OoT=q_KXutix4^7nC9EknSgVQI3>|%>SdhI#9{ff!pwGRMmlDJX>Ji zfrs>W@x&E%;88r!;u*zL4xZao$3U}_CHU_vPeG1?W8hgA9=BtlAf3H(h$Mz^s$;;P z?ij$Xac=V*RlnmHm`oEK`?GB;_8ztUtU1=R=QAGl^x!`Ih_qCo_B2?_uAG0#5;+a|at8 zWG=sB;E_zbPsK0A*)ee1X?wFUCgP(Y%>5qMNkLHe3$Ji*B5Rv0Mvxrk& zJr57p#B-zMTYWRT$92XPdoss$2EL9CM{UO(1Dy(`m%Z`~&k+j49I?j$VLSvNk%1K{LPnXwsD!0cOR!&XCKI3tQl#?f84-dD- z9Rp7(?3H02AGu6lfQu;cQJ5)3S}K~5r&=jYRTKwQoEbD%aml?3JS zD!Avuzulv3V#f>CyZoiORa@Bca!Ai8%{g0K>aAK_ag(w*u{&>gcU<9Rff|Wg6nC-F zQk11HuE%3o$=~nEDo1`ESJ9zRZrM*cdbl6G?E23*V(LJP-P!7FRnEA3_8o2AqYgyU zoUQDr`WyCR?;8C6sLE>_wx7Bs=B(JC?K7kvnss)BJU`Em3jMyeW&d`;dqtT zb;{n;68D|5$6DjpRFu5sij9I2ira>(yv_>Lq^n%le+MC##hwK3;U4u=VeChz55*kA z>Y0olb=P|D^r?d}XM5Tmk0M1#!Elk+Uq5>4^F4zVRag11SK8NC*}|^V1u^^SB{5I^ zlUJ$NJ5Wb6VvxVsD&7 z@{hfE_0-RlJdZl?Rl9O#725OvN>k6|^?XoV>hYF&%NzseGTHGwl;yO~mCZ(X@cQ5k zQGSnRDyX-<7d*V=B5CY-_99{DUbQ~k+2U*&E%Gj#UXj`3-@887F%V0us$q{-c|qGj zuItekkgKy3?k`5jpGR3eT$Jmr@JyFy^w`5nHVY}I6Fn8ErR2g47v)q&EN{3kZXc#x z5v{-fOl=Q)#Mbf_FXcJ*C%ww46+P^DC3>OKY`d?_L*;HiHK)h^oxF0SJ@lVGWeK@W z7w6q$f71cX80x=oHXB}xnp?iNY40>jME%WlX(9@~A0vj(uWy<@Y4541b%xkZ&zX07 z>_yYXzlvowvcHBzodzktMJgaq6b)2 zrP53^5J9uo+YK6fK+w>2tVZwIT2a03>90oDJzYDjL^i||!yDp$ANIfRzxC^EKl&_$ zgcR-HpjQGUbr!EGP=-m8?0dzHh^NLKllA#ZNhD#bfm z=NOp4o9Aqr?XBXN{X57l)PLjw`US^#*h>$=Pg#yVo+!b)*QLCbfquFc91G)%;gd^Q{0ayYA;4SMztd7T~o zr`%|h{Xlbhk(NPn^PeJ&O&HG5{YkmmIC}eLX;0k?dJXaT(F&De$3VYp@^nTFHKj-8 zHue(XOb;tQ7q!VX;99dO$5r|P+L%(6m!njd<>0+MjJoz>WjWO&Acl}qk1eE>r$vYd zxul0`ixf3YmMhI=Ubv0=$}^E8c8{lNN~<$|*t3h)JHr_j&JJ&L8S>mQaIYKX4&Y8ybH}oa&H=5hoknCwwC0Y3!@pn5*2v zMqegh9%Y$(Hyd7b$T4u6lZ`&CbCw-uFHTNRPkSpfk9z%Ohx&)vi?xUea&?r3&WjF- zkkT@IzD0;#>+i5e>R)sS_TOl<(zx$8MWEcLQ<9kMMVkE)Zd!)M>jQ5V%maRxKM=2q z4`FoFfL^>2VX_zLY;~SzcIIqc#~Fo--CJIf4{99dh4Iq(-@vDEKZn|+`Eno(kgkeKuOI!fmd8jv8-3Ksqo>e2+>i3%<=Ky*Zz}5NO+qrx+%}|8~A3&Vfh`|3gS;aAHDC+`_|pZ23^Bl@jDNDPUay+SSVt*9m+*I zv$#neIET7HuC?5i&k$Zb3~VZ)Pxmiiw?3;>-}*F__w)zK&9^>Hem_02fRXEZwEI6p zT;Sc05g>Bm%{0eA$U$v(Bi=Q)Ij4r##Am_BmyKK@KcCe6*lG{mc8D3F(G=#^A?2o9 zzwR3D#<)#MZ1gaU8WoO|Hyn+#;VQfj)Pc`qZ1Vy}jZ_jFuUelweLan5sdSW0>&xuB zl}%M;nY$eWuchN15u48XNi=Wx)9}egc@0Mo>+Wg7IP&uu=)qB!b=PvO-{n1|r{6bS zPVN1(84P`gk~1e-;Z=5e@A58HTG@-!SP}59R+h5Sy~r|UQ$?BUp0wfkv9f5wN2XVg z6-M7Y_NLEqk7GDDIsx4|oDn?>-8F2F&O$3-EokX@KP#v6Fg9|bSNeR$qNuBA*`BgJ zTHKrwTZFy13_StLHEVi0H@D~(rMAwi4D;Rq?z!1Tc)wLOudn940q+r4<*=70JT8B2 zHp)e@Gv#KCyGzS*T|xHpCb*Z}e{2=D^TQ?Alc1hxlef$VmpEKpUT4VV z#n_WtDesABq~Y?G?`7!G-gDv&J4(H;-K+9`lKSP+J=8)dH#LgAo@|bRrcCd8>QOMp zB%gY}QFWDatFz77rrbicq-n2X;LjQRYm9>W*3{|cg62U zotg5x{PFl6m>_f;eUAT7;1Jbp>cM|9`;H+t`nRa2-b()v;uQ9foG`hOY8AHo%gwM2$NZkJ$^hBcO zqxKC`UQ(X2e&(sP$3P!cnl_-%yg8H7fp;p8k1MK$UX_zk(tN-FKBeh8^l*FbccUet zwyCb%IAYawziW6G+KDSZD{l8vzk%F8infLlL=WI|^YZZCMdKD;et2&>Lw5YyLMnch zkb++pqIaI%Yr{y)8J_li5c6W(NAEmxRm`vnw10i{VU#@f5(OG-x4nT1>yM0@1<%;*}L_QzjQ!|#WuH;~8~EQgsC#+_Uh;g|TtvXYgLXr!*e zBd_aSj&B+G$dAA$KDji7xz55zo~UdLr3buK=QGL=Z?Pl|<*Fp#I?8<7opVC=Y)Ry<$UsC$vvm!*>Tp{+m%8f;=Es)| zvEp@8{pH&2B_)x(ILVhE{pTHQV!I}D&NZaMhe|$1L^^SgI!W+`40jhvW*?!)b0iJ& zRlQtNE-Us1xO~#-jE0Q5oSl$aTv9T{T60=+cCvFX`|@f$t%|_|3C55L>+$mtw0r;X zVF_|kcaC0oRhMImaTS+*O`*DuX=YZI0U4PjG#rpJeWq zA5r4!;?Et1tYF*RlgiV|feoPpp)XatPS-|$wdIYC4@LfU%Nu#h%D;UsU zm;8@J2ES#1P2}Nj!t!Hk5Hfn1CSTQucNE3?N{>R7B2!JzRA*(XRH0CI?WQ2ie#yp=^h>*>LWFkOgY&}cB+}5q+QAJ*E$5vFY)JC_;Un_>o#_k zg?^QVKG#B@YoX7x(9Lga8{S6d_|CV)7YD5*MY2@Q{PK8DMPCMX|ie#ml{ri$c zm`GNtnO~F%J4By4xwa~LbBs#S;s{KoKJM|1C%Z<+83Ps`VG|@8| z?OPR!=zQ)8y$Me?V))k<`XP(`n2tw&N!HsBbh{Rx9QIQS|5=OOjsX%mY5uQbv=3A$ zax2#9RCBV~Ty}$n-e9qR%3_aM>|cVN!mH(Y^Vm}s`VVxv7N7a-tZvuxvw$gLfC&G@ zQwlrbY4k#Nn}yzDqWjpNTj)=j=*8>>3;ky%dMTrQaYFGpBH(2Bi`WW^h^~m>U=#O@w&6ItCXqrrE}|co!u8;-?e(#ma3@Q0=%+<=mgcJZ#;yD` znc+|ixfO;5RQ-sR1(6{LcE;&2`GDXIqUNQ&W%u?#ti5MjF)ZHh?238+UiL zGeZW*hW1Vr2&Ism*7de_basXzrb#OvEk<-ihCFe2{k%+4!o&;*vqYec-H;T+eNx!S z(4^76HIj&`lN$v`=z;vEVuPbti8To2r z)Z%3IUcJYX`6fSl9?IaFlZh)evR?U3;vLM#$C9V(c>b9%jYCu>|AwoHH+A^@6rIU; z>T`87!$zs-_$Kd?^GrXcY%zH=Q)c=!=ZVRyg~a_*V+gl(bc-8|leg)boT*E9WAaJ; zpNh#Zb!qM@T{c8Dy+>fL(asCFYqh;M?lsywf%xg&rDBT5{okz3_X{x);5hJ4s<1)V z8#TK7P91lhE|UQ|u@=Ie$ER6agK%%q?H|+apU~rlfd!raaNniJ3!CjK$xfT(pbBXL zfb_7gx9U0#K%fe@>w1T-@6`2O(3kh_+0_?rf!-I>^oTI^kqjz+D=?$8XVO_ap5t?I!EwctZuA{xxqey;`e?s2 zbE9$C|KID3q)G?S)y!dkS{yuZ5z%mefOdWW0Xh z5f0(e98uu?Z~gpwU#_#@y$U>0ZnPRB@ER<5t6(n!T_}MUu;7hJ`9iBV0xx30 z+X8#70D~^@+AMgJQv7JON8o+If;R}eoL=H1^$!-l!>|h)(M7o5fV-T}2`OA!6%ygT zX2E;zGI;-F!6PC6BA?}Rl+kD&e(T@Ls+QUf6=?lkjL2Oq9o8S@2%H3?8jZ$muPU@Tgu3 zyzf}>esmeUZ(H!nCA=jP-U%H~EGvuw4^_)huyXY-_^5sezMp|0Xv84QDj3Kt^QFS` z>3rqn8R|Fi)U6r$FJaKL7<~AT3KE^e#Sq<4#6!xu@4XV~y-7p@biqeDAPn^=EE9NP zt%S>McqpH#ol;py-dP_Uo+F~J1RjZl-5T4rH4^Sz-hG|V_hH|&R;*a5Z+!po?^z#c zAJB|_?~md`dFPo>^(wa5_V!Xo?*){O%;-SJPRHBYd7##g^>$`5)v4BY z?u`R&a*Um~X}sr$9v)cnb-$#2wY`+}us29K!8HM!u6^iSn7yMhNt zot1czvt!c-CN&m)`la=!tWRv*JlLOn=Ft9et%v3$${Q2cV-~OZp`o&x#71>q`M#j4 z^$-?lU;ogXV{00&e`qLO^Ml>cPPQJ}lz3=pR88Xg%~zA-L1~pfQbuN3fW#2CF zj^%6QKOG8gb;*H5^=MeYKBfJoqVx-xVeBdzNP&A0_UU0qlOgw+_gAy$TZ!9trgDiF z>KOXSR}#SsbX$|Nw5zIT9)R8N1uL$bc-_IFJ2G`u_tt&u(5J_qv@p0RIkl|)PP`5E zhFbdI?$U$z?1o*@4>Xlesw=uCc(inGFr#GZf9v}7!O;VWsbe6$yW-@!-~)56er#w& zW@6putLMC)oXqP$=MB#8A&syKg!Vi$nA_vLqE3$^Er~HNoT=l-xRv2al7qK2JpP8d zrTkz<+Z7%^@Y6)MpL#H}i1(`MqYc)ouCKz)B)_WD{2ADb|7zdJ`Ez0CJz@Q_?bPOvGo1l`p-C4- z+v93*jH-flWX!!bE6l3);l4q2^1z7a6V-_Wco&nC1Hoi9fD~l@*;fwh-^szQ*2mx2 z-&uVi^Wx)g)ZH@WKoQ*jTe1iE7(} zQr`h(1##E*Zh_miXM`>Xqx9PuweSb9l05!!f9s2F-?FN5a7>k(9@On_S zxn)mZZC_8{`MZJ-Zma*d-Ni3184OB-f$6y&xrbp1J~8lcjy^lLT(E`s{kxO75C7GL zxg*uj?GD}ug5bw>B}1=Xyz5AH(ScPJgJk*K{@ovHd|=&@U#Eh5c7Lw^;squ9 zmi)RXk?s#Fzk<^8K--aO*x5}yaP7PUB~u>GjT)$3IJ0s0kQ!i!yXMV1@XXMPfwBE_ z2F`ALag~By*ZSO9ut`2&r~ZyizJ`;+6EPjB1}3%7xO%Z%sb#!2my zw8d_foi<=fTxOSXjWz3_5*Al=`BBv$K78H(eC^e-jU|(#`x%R_&%XNG>c9H&k;<3y z;_DXNGR$_2Reei=|=9{nn*DZA= zMQ;bm=j(p3`>~;t8q`u*>Sl9XN5E%hZG-Z@5sO)Bk#nc$bjXG4Ah4$6#D&ZI_8+PX zS`N)g!tyKJO>p1EU%#hH#P3=zRcmeTjmU=g1fuMqb#V&Er;ff8`lNP zv&|Wk*X`O6K4+p)4F(EdQk2D8OH_l@J**R2+P7Q%jI6alNOuJW+DZDmTh#bKU+1BD zWe;?fw})1d@x{Qn-k#D)e6GaQqFnMIpH5|GbG68kQiQ1=%qAFy{76`2uFjbiD3f*C zB=p}+h~NI*#;!FH<(`?nXb1GcCU%xjVC-8f1*C8t#%X)hwBkmr+)yR^V5|4uU`J4u zxcknb6KZ(BBHcD19>b&>Kf+X2&3KBBm>AjkpOE``F)S48TKx57`h{$J!zA-0Sy%G@9?rs_*-y$zZZ$)IM z;j7iIQ&2rn*&ICZ(3_<-tC|xJe5JXnCk0E&ypOq8vN5w~+jYdv&fUKoF{vr3n{D6g zr1qlRByGJun7sXx>YTiX0J#Y@xK1N;Z@KT$I21M5l;@p->hc4l^_Q)DS8MyY!LH7s zgXzYr+Q$xdtv=!4$i|BHbM#%S=T6S;-@OxeW+>#+r}5?BHw|?&-(An1QY|@sW8&G+PFQFT+|tdavJCs*C1&Pz~I1xe+@H>nx8o*dlWa?`H2KK%x4 z+uU7~o2v0>zj-9S@8brKjA5Awblx?!P%2lhYbjdUPVmhkF2>e#R@-{6v$me;mqiYz zrDyRocAm)@yU!(i_HWVYf%N1Wrt!!F1-@C?vcn4BtfGT6Hk$8MC2EjlrF^k6{9^4( z*>6@tTWl{u4Qp&pldl?#^QeJ)Vse+)Hrn?qiKB@#YY2%mW6WRQu5{z51#GDv9NLn( zJ$d!Mk_G8ztg8yaf(DxccsE#|M^ zH>HM>sZBV}9_vZw7T z3}-)^V@8G;n~1n3ES`Q@eQw&;P$e5)@nSf8+N(pY%J9nQPx0`lX#Az2)|Bwd=%3-~ zpP}`m^x$Y(MDNzVb`;;K5g4wLYMOWdY5M+6q1LqUiWf<&L5ru~bgj?1T0_iD5hZcL zeO&(>t^Zam6)fas3)kKGTzPq&=dfDr`@CMW|96UhyIc3j*=`&C>CU^6xB9 zKi|H#tMG2@X~)ACwx1oXeEguRj`$b0hrKA&`fzx~i=--S-#RL#b3FZg`_`^PA$!(w zdA|MXxV*6a>8O+}aMcn2M(=%b#xA0yTI|Ue>-QOzr^S&nu99krr@zFLU*^d#(|FPQ zxXjbfw>QliC>v@m3$J*QRLed5<(~X;0d$fL3KlXU~y`Fxrhu`bz-{9%rp!K8g$qk-< zpQqpF#i!5H-{|RY^z=7+`Zs#|H+uRvdipnc`Zsy{H+lLud-^wf`Zs&}pY-%U>FIyc z)BlvG|0%5>rRS$S{eDls-_!5+^f!6>o4ojJ^7J=*`kOuc&7S^kp8jnf{%xNAXS6)> z{EVu%ObTwGEjvZhr24F<|5+t9@(Qj0*+>~zNp-uYe|vboYeMVa?&*InJV&oc%RlGI zKkwmvK8&G>@8>=JJ3Re6)EBLW(Z9pfzf*nP`ml)=s5`yzcY6AFdGfo|<5t7q-{t9l z!Q;28{f-aoo#*i5y;+CTemmEM2vL4m7`Wu4zLVj(HiF^H@rP^rXOOW({RJN1?D0Hf zT8R30dHiD@|BT1K?(qq}XiLN!51uN#<{pErC!cNQ>`#?pHaQpLGwRA14-3RGeuC-* zFT{J?YUSpB-?jLa zq5p>S!ZgpGd>K|k{npbz1sRX}&01co&bBibmY4`XIR-Yp; zwExaCP=%;}x0RRTn)ctn?8#|=p7F_Q`3Kc=mT%Jhht*4-{u@?q-v1nxEQX>b-j8R9 z5|6L7Of{$)Pu>`l&r=`s3A33}4qK%QG3v(BHY%3xBhf z*J%0W>P}Bi`}RVN&v!ij1slE$vNH64{?(Ho_V~<5K{L-od-hTMuTpb8`A4kWyw8uS z^`3lFOn!}ez>_~}$mp8UsFp4IXe^@b-;B4aatCjYjoGc3<_MP=yUT*!=X ziRp7mOn$Ap#*?p)$ve~*PyUdVF9lW^`Zxc>lmD%iU#;cq)Q>#*AuBiEk4_bgvXO(s z_?_tSQ^E83O!{1}J{aR+5!><%Tc&zcM@-(UK56+nEx$qi7w|$1^GGawpV}AWH>ww6 z{Eh1M7?1Wl5}xrh_rF<{$M{dG8q3dxPMP|YS`g#=RdY;#lj^hl#ae%}!kIZC@g5Jx z^lwwjU1X*AqPh0|a8QL~=+Eq0$St3D>GFBp@U?ao_K&HxtHes{ITzNP`yTjTFjKYpHhj8a5}qcH=iPv{<2{Po z&AP?fP*-UH#JWUT>9%)74Zg;})D^=7|vX#T^$7)!$ zQta3-=hAiHE(>vG`;~93T>SG)kS|ySyg6%Oz#DtG7PqbI?B1w%eZjXL#*5cq+1(NP zyBnek*vR7xK(Kl1S05`-0eg8i@UlJ&+}7IGaRV&qT7T@hli2C!&2_Jv*G-G@`j*T3 z^llaI%Gl5|58GO_PH5Y{tGlgb9n4bCZR^FJIe@O=&O2~5=A{4$8|Uy=EL@Wdhb-8t zw|j8c%e7`R9iB40VVm(^t$I4w^nRkHn;YSx+~6je7Ff&bI@&Q!+y9jbElUle15tgOb!@P9&hORL3%lcqMn8?0i;+Q=v`=pVru9Y-eX75fDjVKn1 zS$SReqE)?2n=o63wvu6=%VaB>y`Hn7k4L;L+0fhN8AL8*A~FOEZO!ZF)n?t6Z-m9{ zb@Ov8mNd|;Ja&J?c83{r+kWzxJs`d=HmXQP5Vv}7iZAwHMqZ{+dW(_P^<0dOtwzRdZ>R7p9?dpyjP>bn|yt1LSrJ-kC zOSET{8&?^p@HUtCGm?D>%Sc~z_roLDLi?`gyCd;xu6ae$`t&c9uHh$qtjPF>}_ngapXt27i z-%@O2u@*0FY3Rk?S^fNTRyJ_g7_YTVms>xtiKi63ND~FGwGEkvPpY*DRh`_^5z_~6MG$sY+F-bBs6iY@4%i*n~UR`R$|na zt-)ughxycedQAc4!&(WlqZMgIn>%&-H>`@iDU?RprVTUcs%hThr4870}@K(a7#Kr1TkEFeNpXdpcB*%NqE`uD}+4^9V>$*G~W&HgtC{?fgVr_oB8N zkeipzS!wEe?HAQ_xT2;la5{%@Ge5oY{aoL+)>H=JyE!Us?Bz-=yu7QewPQ_3D;rsD zXj;|Fi>66mBn->6JTwy-6^XqY)4$=$d>wj!BCfW)mu-fEs#X-DhEEnN)AF>eGfY0T zCLfUj+)^5^*TUSftk0&C$yK(lH(N7f!DD%9&W7GjeEnnfq4ksfp(ZlcGy3wxyu(t# zd}>ws)C)^wlP&UW%E?g04t!1y1qv%vqEuz zn}+enw@N;e@c^bmM)c#}SGIKY<~qA0e^iM~-q`!{zCSi~7!>>QZD`YTlP6Hh|RuP#oHF=KTJFmKf)O; z^ann>acQ{h$EML^zln1A&xTt8 z{$q3zFOEN?N80e|K%f1S9%b~>rGehRlRhEP^B?Ka1~2ivv1gU|o*BQa7;9|Lr!mH( zpAUvOIgXGH5d)lL4iK;29i_q&xY(&2M-5$-;^*+A{2i}2sI?oZ$*4w}7DiND9Z0r_WPBZT)m zIWXys@Qimwl}$f9{|fMYZjMjz{pfT%)23Useg0|Ioo?UDE6^n_-Z$SH!)sjN>GV0< z+=uCQ2KC@SlP>Ph_msxQ%@5JF>BI0#!6%S!G%hAF$}JB^Rd7Qn-Se$`L4c8agul?F zf8tavRuvbSd_p{(|8QRnuc-8g3|{)fM!%xYJWs`3`&`)gsqroeO#Ym2{TJHjZ8XnS zvB>h5+ITFr?lSA&WW!xy(*XuSb^83o^DywvH2%yo;UF(0==tqEZni8=u81;$SCrR4bH^8qp=mw z+YUi^zTu#Qb!jn6|I|6LK}R(lvWUWY;}nsg;J`#Ajt@LI{^4Ll zFIdHS}K9Sb6zYF|0lz4nDp&)E^#Zl~@b=XiJ4T4edlnq94WWgu3x{yP|#=wz5rw*tWJD1;)+ke|i$>Xu8n|yOy@ESttk_(}nz{ zKUqi?bss%x)K_HF-xE3=M^7Ss#lqgJeV}+B(FvrJ-Rmv7DUWB3_XRy+yhrE*BQ&~C z`R~Q#TQ&(z$1N{h*roF&NTjGk<_nn>qE47EwH+#_>otsqbh&&n;p2U`0vf}2uJV-K zZdSf9-o+{?_xe_OI$_Chvx767U$)yH2?<_3JY2lj96ZKF@IH!b7q1yS+rL7RE?oWV;tc|i z&%yXHUV_(+YZvck@LYc-B=K7h4;Qawrdh{9Jht}*?{-|fc>LhN~;8U_!;6tVQ%>fo_IEO-?j z-nYRQdcPPZh~eGu;4vQx9=gA=`27%kq4LIVv-^Ix15ffZ`@4dN?rIG0m*5M%4|H>5 zcuzXpL+N0!hNNjpXuE9Ef0@t3)|%(tRC5MNH3^{&znWW3q9`` z=(+i?5BIG`IHn)RC**l+JiI;#>L3@Q9%;IVw;gzrpP9b|uhGMM5(2LG6B4{jJiI4? z*AFGekK-JIx5~rYiNdiKav_K{@jPkwd1vFpD(PGU4Z-X4@VEw!m$y^*iyq2+D#d zYkQ?`d=YqA0ke8!PsDxQe6SUGlFlErdW>(a7r!CkH4(s)q;rjjN4xTM&|yC1jx~wj zA`fp7ZsOJlf;Zp8qy2BmS92V^b`P%|c!B{nCF!@?!=oK(c^?f9-e)|#wZq_T^6=F8 z5#Brp@2ehO*D!cr_V7v^yh|Lsr#-x0;8jB|B+tIr!^;3q(r*Ej<$e6n!-HMJg6Vg_ z!^=AHYjp5_>EUe$o?G4|ey@3W)lU4lqfg>D5*KdycoKN5mxbj07D3O=&sY=}=I13) z7Q87Q-YdY%3YgU+JIB*Y0engUy;YuGHT0zHQC;HqG3dGRTk53Wa_B*<^W!ZZUJU}( z5XchsNH=+SE1c)O9CE>Xz{6_>UYSNPe4{xi3$G#K8;8p6i_ip_DY#6*>czE|ac-J_1V~gU?yA62b zAs3Rko&Y_FRGk%UcksAFQsP(R;q64AtPMj)@TPlsJAfzkbBopE^Dgu74gk;nehA*B z9^QT@eytAPEgs%afX9B8ki3tZJiKRtC-qAkl;wH1d3di6gLl7&_o9P$t%LWJhc`3~ z-jg2QYYtwAgE!#emEdE(R36sqk%e{Q*!vv6E{CU0X()Nh2;H~K@Uk0=D#}NNq*^szu-;t@CJZaC_m5j^bQZB zx6;!q!F(L^fsn+n-_t9HUZMNm3_bTbR^U09&zUa0_{np8$-|otygJB*Z>*Eb%g-dzRs+J>fr!~GF1%~B!2F$2Q!{JUtZcUS!kM*3|Jdj1ZbRHa;kmj~)MRx+HBMnWFly1L#?jR! z`zGNevGk%ePTIY%{?uH_fuc*znXymQCk~kN&ZalxbTN-`cGf=Ff7E9&%E@oWuV_Bc z)k>Majj4qbn|ZF87hH|oQ_>iGZ`63%y8XKoIH8VViud5mM0BHZ zYN86hp-+}QVovoPUJ~TY3A9Ccrp&JT!~HXZflB;kOymqRk*Ne_3TL!MGMDh@LiFKU(Wg2{GN)Gxal` zzWY_9oIAcqoJOQi{Qn zu<#t$KUwQbeXcwU(6lKT*FVL%JMoxXBI0>r%r6mD=yhl0nR5c~G=!u&EmFl*Qf0MG zMDgU?aKF#wdqfDA{M{b^KfyEq@_w|L_#IFFvXwI|&rf*UlXLDxh&mU8kMPopb00#K z-(cm{xaN5U_j_`&!C>U0)eD~d|9JdpeCX)Kbf=BPGh=+2;utjL{7jZ1|E+O8jEv81 zR?cy}GUUG5TJ5YL|-5n>WwI%C6jS7rYyzVP4$lw6?Z&^=d1AvQ;M*TuW%{k!JGT2x6%UZrQPB zW3kk}$St)0^PhgUQ^+N*vt1MmM@Eghd@C%v#pwUZz$ofw;buIl_C(xhw ztEfj9@|T$LgY*J0?`j>bd4Yv03V%IMl#;UODl)XDS8zoNQcj152#Z$UIOzi17Q zSGY7CRo@hkqpHLT%274lGT|Icnr$WulX&`tTaP8vV44&m(Nbs(Q zhl_VV@Tf;T;tJjuaqZ&WVP$YM2_F0LF5V6&ez*+r{tDMF-d6C{_zCg8q`$z=#oGyx z8u&4OtRE$Quj1OpdlGyhyqDqc;&Ggo^(gUJUkVx&hqefARODf zLXs|Qi@SInH4)Elfm|!(s22X~Udc(KhCC|}n@tB86)ax{t`Y-YL zTMIp4b&2Q#@NR!h?(2`cW$_$0Lsv-j=sMo23(R&zstW#SQt0Pper1}-GvHEX(5_hG zcnIFP=g%<1X!h^1#@%MloPFHmZm*ciJREmB0WF@xrv>`fDWp!&bt2L_P`4m{<@OE0 z;yR;?GH=}J)~&H_t#vQ9ZXMk1c((bLZ?f(R>u#r8r_|Tr9$BQ+4)Sx9dX)TP+$f8E zQwX1dODcz3ax3ycO`tA-(sa0wq<<24{ zn|*U!Y7*Sy{mWDq?z7OF0+&>6+~jo2*I0Kc+|}4z)dY7A;;{lQLtG7aXK{&YhWp>a zuZBzNgF7eKUUDypgubvqXTfW zD0HQ8x8UQGg_}e=kM9c9TPO_Wa9Kf3qN~!kWwncRg1ZSm)tc`Q=EJ=hZRbUBpF+jc z1veQ?R=sdX)s(0{xFZG@s3RbG_wvr=9m_lP(^k?@o>k&5aTUxd$WO$)9CM`x^In}V zzJ+|DF;T8p;Q3jW4Q6wSn75QHevX)@Ehy8^53!D?!T74aet#^L^iQW9^H?MM>aiDQAkP;;gYG!}U6mN)VuJ@-bh zCs5CiW$o?^BDAgPK5u5NUC6(Py- zjqq^wUV{$vn2_kLhli_oG3x$8diQyHTcO8xypZ7iB|M0SDq9oRHy3IrJp(C3T~JUKlSZRRJ}-gb@?IqO8OYBC9;#X$$1&g;KYTXw+DW~r0v>?Bkl>wr;moW{$7(0l z)<}S3&rg0EZ9P!fPC5l2Fxcyylgf?M_In0S+rN84^~A+vUJR;eF{`{WS$Edn&57a{ zruR))cv9nt0pljDtEP{~jOO^tXKZqw)u+xX z*>_3qsc??7wi$NeK5gt-jf#!(OKL=JW=~OL(fnY_ByEK;rRO+l3o6nuS0!3cRT`US zMlUEZ7h19>r{_J3^_;2sJEF08Ve$Nl&74b>`BfjEyv)HW*pe)%;|wg`ZR5#nURrl~ zHSGqL?yDaR67_?L#7k{=zxD7NTi@C~`25g2*|HPLik^YXYxK_!cV+8eA3LX{0e;%< z6K#rRo*21kVAbT-vAJoxf+{t+wRK{yBnSJDRjXRda}#s0t=eerSW?HhnEZ04wyD>@ z?W`}n{~b2p;c-lykW%`r38vL{{5Yq1He8Nv7-H#+h~MFO_z_w^>WBK@BTV*p5e~@FhUH!(Bs#6e7_CPH^Di}t(Kp!`O)ez%kz6ri&xKh;mw>M zj=L-{*;l`49>%hTsa<@hEaMGkchIRSI^{rQ8W-q!0vgMWS$Q0`_S*LyV zsb_jhVs2YcYfpooV@7^wos&kv`xsqx*t)FC??nQGxwq1tX3ob-oTbzqryk4OW%#*xKLpSG zDwv$Dx8K2Iyaexd4{r*%pBzh*FQt4Kb#4?)kxn+*__bK;faCwQFia`Ae>%!i+l#P6Tr;p%ap zI^U6y=)D9F_rCLSU#17|EB#sWZ{bH5eQ8av0gw1Xa-G42uP67Su3VpC!^`s%kKu$w zuM+-l{FXZLV_TVe42R>}bbJJF5IoaONbr_hJ?3lDJK#IbrTz<6<6MmkciiAQ03Xk| z0r#D7j!H-_=}O!v`x==2xB)&7I=?c0eBXRlNn>29)yV8GIRORl+!-@w{7&Nrvucie zeq}meyfbdVcA=hkfG5Y8V{+f=|1-BV7sTpJJ`<0n%S&Hv3c!dKAjyBiw z4(#XYv3q1{j@^^4hRb!0oNM{fU*CS$YU|H2{SsuTn=Q||mVL>Ih38sQr4u>Va&B&U z%YAU$SFKoZKiu=PJ6GBdTQm~$=n zjs5QY!*Ks=*37j8EoQFelh^(0f9Kpn+c(GRxt1v?Oq^@E-OjZf`DZiNG9+^?C!;_u5zqge_3-0I z&C~Cp9@cZ-r|q|S8XvGJ$P1*S<>_ZrX3m@Y_E-<&a~~W%PyaCO=IMjUX$A9iDm}iE zd3xrYg-e*HNzBtE=4lf1G>Lhd#5~=PCXibX`*Yq~ZJt&w$2aFa3Jns@dFR)|j|`Ki z3(t8M1(muUF7f8PSr3PKx(;cN=Wz3~o4?;5<7Qhhr7Dp|5lKtd_;9W{F2_WZLmcCd z%cUnL;fp1=*@BIT`+nl#QDPiQVuBz`SI|^mqA@; zc@utw`a+CHdSE2L8L%uosUFv{gPO-XSn2A$tFguiARI$HMuha-d_kRPeDLTav98{` zigW~U^hn3`3cd}!ZexZL8HN%VV)+Pg_>v*_bJAFugGwNAsWA?0gvHR>u>O9@kzsXDlY)^luu zzpHl`0Sf6o;py$bXQ$A8|HIRJ0(z`Bg(QA33lO{Sv(PJa-zAX&Q zQ>wKl>GdkA`t5_6r_HK}QH>|J5AIpqt}08c5(sm%lp8Qs*=|? zT)+AHsk@%JKGm3P&QvA4yDs_G^+9t0SMB@N-+b|v6xPv{HwV)a`;rUQByqI$%EsX3SsLtjMiTi#!0{VkmGuec>HK}-5r;AXD*08 z-qRoN>AN*4^(T1x6SRIdj6weTjd*-c()tnVNnuD{aL;>O|70&dtT7|vp7*#uXW1g+ zp7*%?)JTXc?rCTGM0A?2m&r5dV3ao!;fj0S6VzpvpQQPd zR4aJio4>K@-;Z?1!k?^dD8WnHBI2I+2gq3B{dZaY8eEqlKk)orANVR zLz}}~Io->})2%T(9j&mX0JFPxNrGAFvc@c=@U2ofzUGpy^nsv*2+kPo+r&w+=FJv?u#55tPEwHHeXf#Uif zBM_T)xa$>d-950v2$?xOAT+mW)^|W7^zjtJAkd5(@d%^ndGjfu95?C_Di`v0EwkwM z)eUXk%pEKGtQBD&R8DC90LN=ky`$DY5)gx@Vbs znR0$*$P+iwVAq|996akB?gy`cTahzmN%n`Q=iBuk3m|-V>pqxZ%S@(q)>qhMbaSUC zMHrg6E$B;&xOsvwCwdZ_Uu>R?3k&AXe3b$jGGEEhns&hnpVY~q@o-VbWL6zc#$4*j z^73oGJf0WzDwWn)nKE9nDn@$kVLpA&D^vb(dlXncSlvo1tQOb&?g>eEYC1gFKdQ3= zp6$xIo8yG?ZD1Kf(TL%(yk+qd61;kNxOjCA9^*nx;;qKdjo(`E5?5S?eeq^oyLjy5 zF+Af(SMYAcwTs6}hGkwz;&%f)T)Y)d{8+~b-o3bX@jhc^a5M?t7r?oA?N0nkArrjE zaP8vV0iN$fh_Sg( zDR{PbgycCm7w+D7I~d9LY&pw)xrQ14!@SA$D}~Z!m4~;}c@7zi;B#&A@cO`?A(4YC z`O3G+@T3zzw!|fVU-9t11fFGINbu5A3RRI zSD=Ug;d2qMQ2PDK>Pg&x0>01~(r@99xOFiuB-$)Mb0H*%HE|3`o`D_%cwU|hH)6T`K#Z=In0s@&_nlYrl;~qnrG5f;f9z)u15jdDV&-pBS;)663NnC<}}5+U8*lTasO^tCxD(AKjFy9ioHg2zSf+Yqplf4Nni|x z<0$)gmvFRcA4Xr^KQ|Eh;SWD1f~*%3=ll4LU|z&jHTq zUzQUgxi9l_>|2Qluq=$hkMD**-fupBF5ac!S&oDRZ!SDsycdDTZ!htf27Q{JX}1kk0cJ`=eCKz2%hm{I+7m6uh2Jo zJNyx)E;yQCCi%F&(HY!#rv!q_dy(i$T*>o1obC9z?}XQU2HZC!&d)s`auJ^XM)w~7 zH+trU$AA7x7up4&@Egs2#r$HLy~QWwCge`jvo`JatK6)=wHM`P=FInYa1ON-*i}3D z=|KM-mrLi=Wctb%UB2Y-JHj95WB4UE=L9S4^bMv`H#k6Ftx^5v0rT~D!$kV<-N)ab z=2xBhLnx)*I3m|{lVL70zR6flqTJ0f1xAHUKa#rUZPd)*GqwpD3ZF%#&Ws2u` z3GsgHbJEMm$E#*fZrVJkfXv~r93yi~XPZ`z>tPghBj?JF-u5M3y%_J6J)yr#dq<4G z>h_MuGx{(P6|$yTq@e1p&9=2gXfO3jzZ+z_`QU1h46}@5c zyq4>{^N-)Q$uIe0oi_ey=+Sq7lPi`kn>1-(0DB+N`lKY*DwXdFW|udsy{o=y);~!* zKGis>In}5tIU=V|+}Rhcof4hm#*zi6w5MKACPuZ7YZ#?hTTR?0V|Z9?Wl8jLeov@h z^?D+a)*&+fx~y>hl<5N`5qI_sGCA50AtZYPJ$u++N#!zomkb^`PYop7gL_ZhOTD68 zweH1C%>_HiPuNwuD|oP~IkB@#k0;h?w4z)#T-{ckoBi~kX79q3FG=U$NB@H5Eus`! z(B>Yje|RoW72HV2EzQjPBODn~M(FyD`JQ1C;2EA}#SjXdLp&cZ!ls}^>!Uej$z*Qf zxGpQMpVs=-q7bVM8NX6bzf|i_3H4c9N5uY29DlUdk7B{vI3o6M;`$k_ANfU3&QM&p z70Kws+A|`q(~8UE9M@&Vef<7UxxRmdSgvMRhHoy=UzJG8by$2q5uL2+EMxRp+eMVr zHK5C%67JccFQ4`*{P_Nv#_S)lz9wIz`LwzXt`PPA3_r@JV>&_$E^S&V zXVqgd5LtV+y>8$)w5;`58XeGTi#oAlX1#O}peVr3x**3_ha)CNH{pFLj^t@uZF?7v zTEkkL(UR|NA`$g7oDkLuf|jv&1W^GmwG8l%$9uuD2AXQ%$u72RPc!eE z=dSQwq%qdSa+|1BDogitrO)`PzyN~C`3}?ISzf8fcTPQAs*1BCJ-#dIO|g1fA9^f@ z440rB_hZ|KdMp#fAypuwu~ekt>b}r9rp?9mJ*<6rJ_}1-`Yil;SA8KjYed}$Cx=9y zrjzKTt4_e9$aQWwiri#_qbNif;wVZ^K5(@1GfBSCWS4w@^IWTXdd~5RhhEtte&*@^ zbM>#7r-hi$NzB)7`}RKDzC|}(mj&uEFX!-MbtGTKMYwkBcfqTNzl*oc!DCp#<5;|l z*9?9NenNtGB|KcbuK^?rKgN&o61ppo!TSV!T)b}sk7bs4ETe+=Ag*1! zC%`kUgaq%4@Nn^d>BO%TGQoQa*Dl@wc*=zY?@4&Lc%`U2_?(QN+rRo3@Gjmj!54bJ z{|J8!o{x05hCw^}Kif7!ocqL%?-4kNHNXmM6 zTpu9uWB!u(UF_j~2t4avA;IIAq8qof!eyjue?;s{#pNtv5wY(Smz#_u8tf~@;U{`>x2B_fk|&RPp}Y(2 zD7wTwC0ItG%Q%{tc)FCH`xhO?<%7b&CBNL`J3OA_ltR?M4?pHH<^;}FJpxyV@^9fs z`K9==uk}N?LX^KI3|#W>czgzd8J=&FdqDiYk(||K?q8~SCYKQL+HH6vAFVza<1^|$ zPyf-FyiD!)Zk1`rasE&Dfo&g~^MWLv zEy~)T`m80X{{gzwl&YhPzVTeT(@o!`f)yNyeQWIkSG(v_YZrZL?Mfefw&e*5s<_y? zAAb5h zYqK~cQQIHcKi2Q51~`h2Vtn|`;g9#@_t(W+Wo2+Q$#X0O=k}wPA~3@fk7*!y>v8Sk ztpU$_2npWD;o;(~09ZBrh(}z(`#i2)yeGhq#!pD_J_`>QuOA@9As*`s!Fv?fF5cf* z85~W5w*#Du$Fm&-kF86=`!23syzf{U98H2pe;047gU9C)yr1LR#UnmtLW1|N@Nn_& zcktML5ImUqisAjemHBuhpy%RkcktYPysX*bJ16}Bze4e2f8WL9Sr+)O-^X|xhWsU7 z{C+eHUW13X)4_B5@zSo7_`Ng?-f9o;Ne7SL6-mF(dGY(FVemfV;q7w^apEvb0$O?@!JP$q8EnN_6x*YuRj58d-eP4#IkX+K0yhzy{ z@ZkE{N?cFIkMUzZWFC+@4VUU>j59py1Qfh;XUzJY=9y<)SUWqb>Dc28&oMI2I0Mg` zHS@KO%@uoAh}pT3Xsm3X*eqvo*tuP8-6aZP=63%yd;g|R(5ZqyzmNVu`;!rw1Q(wD z|G0dF9(#*=xl&q92#yED^-Huq>kUK5ln!xxAg<3EKO&9~#CzPOdMyMs7}Fp&^2+>r zLKGNR96y+<^`yU<((8#tiTQlKFmTB?;m5qqvdaGN8n{A~Z^VysrUCoEx5E{p`~mzZ zXZ+Z|<#$Vna?`(C-O+OG`p%x-j@EGR|Ejib(@wl(ZRe_%wPq@;zO9=(7GkRlwVx5& zUDCRx3U3oWwo)+kjp1SOq3uEG$rT3?m+Yl&=!xd{a25KRx+8s}`8HSJsO1 zJmwMNF|6RV;o8M(22VX9!E1qsi}w@YW#LCW#!K)xuI1wOSs5Hn@+sqdlZ*Eb@Q6b^ z=4rv>{1E*i)^s!eN}T8+*V0a{(OSm7RH5(s9>{^!W!2O#aB)1}^%QROw-N|0pOHjY zo{2o$aolUl`3IIg#*fd$XO(BbrQ#kDz2J!qNbt^`A$vZ|*ZNrV2j|Z?-x{ks_IG`S z$#~)X!RcsylNMYsL^o`pGg2zdtno zKpAI2vRH#qb>~nfo7xdPawld)?i>ngM%+_;FSSQ#?Gd}w-r#id1LhfXC0LEdJPW^l zt8wB0|0Uot3ggmsjf+%W>s4O}-}(FdSy3)hUVFsYjAOYmB&FPN!?llUMLnz?ML)lN z6sqFlc-lkp_7Z!v5wX1!m%BAQ@iU%0dNQJLz9b$#f4(FxXU!53=S$-9cGgv%UFep8V?`zu)6u^!Q(Td|08wpZ70E z1mZw#Rd=S7>&hs0D$n*RKA@bj{;SGMNdMU<_R&T}ljFR~j zzIm>#yU6*75$_uCyoHgESN)#+t1b*IuS9iDd^yE6$!ib)X zfSXZqSAr2@?oDzg5MsIo=Y66W#B?L?mC=~Gnd*r|j)eD&1U#9`#<@*)hec8dm$s~5 zAhS6!!SeRbZV75TMlt!K&h^(?r-4q+X)uzrO+#dy=EQxN&Mk zPeBnjmK%o&fOk>fjXlhMO6!5oLQJk;NYnZSL_~L)(4CP2`~g+i zPC^CzH4lFs4}_zB1?IbAe4WSFn|@b%uHDCn1p_)>A2xMtdX8D&l}5*nQ)k$FZRX_= z|Fz^V!4L-B`KE7^UVv```B~NmVipXjqS3fqJNq8`_|DtOuK~TTy`w8u{~~*Ue$MPM zd0@4_U(W$Sc8IEz;qMhz07q4cRRu@YbSs6UDtd+g=(=7tFuZcCKo76xuPXM^*Dp%; zXgQ>|IT_!4?KHggX*H+Q{T|FA{=v>$M-kEAevWI9Sgzd`GRq|iRYYve;WZ32uzgd7 zA9eU+9dI>%Y)c3pid<~`Qt(#5-yOr?!L+O%h{v#k_eos4c>PueM^nPO9OHEHW&@A$ zAs$`9dl=U)-mT!zz)wi<9)gF9R|hFTO~{xo zLW0Nrf-WAKcAP+BY6Ml;cW#k7*Gq}$B#WceyAls^V=$TNhCN_!*E%tEnWb< zq%*cy1^#%(7Bjf-CD0WDye7Jix4Ih4ene^t{HNi^_%T278F1f_CKW67oZ}&QdTlZc zf5;(m;n*T(2F)U5^LIu~&8%5C9d72V<3A&=9QOo;V~ZS-F!O+^#-MUyR}yE+l+?7I9dJON3y+P%?!Mb2>HZh~1=6`>_l6fl? zD`(7kWAL)0I*vIpB970w<&s}R>PMqQ@?|w)IDZ+}FVXr@nT@U(g5z~@{j`Vg)*jR^ z_4G?U{Wu!O^Wr}I8b!qMJl6jtmaPChpD!Yo%7~JBHo)b}^!OITGEF#Mg)MO*G4w?t zXUg~z@YK)Z$MLF_aD}Mfi67;RH^-MYSw5@zwE7}kA?kl!7`Wu0#4o}xRp0mI|7_(K z!_^iDsBDSh$9wz?k2m8ltbF9q^^TtUwQbTH(0xT12shgfP1hA-(~)Hxm#uyGP<8rI zUj|Zi7ZxFe7r8fT!61Zc->8k6N3*f+;p~73O`eAlGofZKUezU?aj0n)64TeU;2XN^ z=#U-;TH4axvQC0PwP9HUpXv%uHJeBmHj5q#uWaw=ZCj6pp}dd&9;A_JSoRY5$TJ^S zoNB&r>C;SpqCeXc;!mC>h-*NZ-@q4l6eAtgyJ?yV8@;vF!QYXQ2O>);}^22uaO79Ug95XiJgFW700A z9`nk4{8+T5249NnEPg_QHy0i*-gXC%VFhm$u3fw?@NV5Jcpvldo&+A_!}!q^yjyVX z;@u2Bi=U9-`SZ{Fo%r$VA$VWHwTrh6d=@_;!FvE6?(@Fr;PH6`?`d4Scu#@97(XF2 z@igtlUl(uC!E^gYuRxE_FU`FnToYeNu73>=Ue{Ow_4v&YqKv;I_yLQrLDRMHJf1de t30~?L0$7quy7EjEZHLEpcwi}u9xq_JWbos&$}`|n)j`0ujzV(z{{TiHfzki~ diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12_gcc_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_GCC_ARM/TARGET_EFR32MG12/librail_efr32xg12_gcc_release.a new file mode 100644 index 0000000000000000000000000000000000000000..ac00f614cdb9d7e6c55d7a20a99099d5dccb9365 GIT binary patch literal 221840 zcmeFa4R~DDc`my4?2$Ac$+muMkbkg88X1IboUv@c1e%OA(pb{SNRi}Vep1b7G?E5O znqg)HGLRsC(l`mHg+LPmq$NOFo+LfB9oz?capho|keuXPJ0__UNTa0mKx~@ISdamy z^?kp!_S$>xt&wp~l5=}`?s~Mf_WHheee3`Ko3(4Mie=)%AM$>{XEz%+Z@FS)VDqMp zTYSC%XQ}^vzKxqN-L#q0qh7{bTNwLbW#Ol}ma#wd6T6YIL4@;%cs|*{*zWxQJI~ke zW9+}m^MjWdJKOWhV~m~cdHn{){);`@`H!+c$n$|?Oe^$!xRq)0iQLY#Kg1LJ4b#-; zMx>FRRQDhD`O}A)=6t^RcT9UfKL7R$rr~kvtNzbDwSU4~|Nrw}GY`J}E9UxbpQo2I zm-L~Ucyz6dz2{T*DAVVAs&h>LZJ+vSrmIij8K(d5 zJdInJ{@Xm;A7uLcPviC-T^${LjpGwNiCiu@Hk9oe8R$b258!sk8)! zQe!tKGC4@=NHr&K?oD+khCUh_QP_jYq47*Y5_)p6OpY~e4~O~?d?+?DLcwMQ1;PZ{ zLBA%G%q5z}2L}@w0qjo122}UfM6M?tizgayjwMH8{UZqh1G#BeE|GPRdnX#>JB4?| zK|mE+cOqMWT1Zg$ge9ead@$ZU(UZ$0Vx!1ZBc28T5wR1LFxtkF4yF@|v{EYUmiH#;&GMQ9{6MK~$YYX=^Hi!C9_R0QC3^8fz4mEc4nU#WN;%ymln`60{ z!9($F9ZB`aMnLY}m6l!*WFayYwvfs5T)g(gZcd=iqFz!K8?;1@Vw$*VJTVsEC5cpX zyC+OnDs4GX{l@#Z4&SP_BvX{ZvYL^}8BZJ1dNZ-H>8u&26219alH@#bYB^cg1qUtgErFb3B(G&vm74Nn}X)P*+S86Y)5;b8rx?h;kg1 zhQL7or~nw0IRueObAepgw$wnv=ABbJ5;rGC40&jG$ut`J*g(%nGM>oJLk^`zM^j^{ zEO9fU;Y@1O>AL`o2iBR+B}Y-K$@3gPhEOGEj7V&YP0S@Wc7%BY0EdsmpLHa6w{&R zL^hd83`iOY2=$JSC5&V=#gMs)5k$+V6X5f91bcgW0F~FM0z;wkOeQgwL#d6UPE(cY z>hA1q+t$);c#tkJ7??~xu9&X2ERr}zU8zYDy{74G8HuH{i2+Kmh3W0w-b<8>U7A9s z0mzhL(s`E2h=oE0L|l`JrMHcb))Kuv+nciUEuKvC+zghSxp|BlZqH*xGc-8FE53|mb7Ca63z4`5wIF0g z46$mxwr_iHTSpI#R5TZAO-%Hr8nf|aQsoUN;yb%yn8@r>s7=XSHj!%+-IXavP(xH7 z8b?Ovz|r^h5o|ccOq{giw)oHd3MG&6~D{cx)ac=8uZgGS{<1so%Ok#P95y|VGz#JmU=SE^) zW+aEtw@@*2nbZh6_;^Ol=-SYg%YJ+gL^OW~fIMf7jzI*8nDU97$Py#G=EP`ffcMj# zW8D*3RN?q=3qs#z%lvs!_L6OmW6ojsNEAD$ccL{lGJyGp4QNvB;E%>rn3^U~vNp6u zw!<+Iz%(b(JJA#yAK-IRqcRCP=G6u1nAPqY?N5z#(=68J1Co+Cg^X^vyQink08vdI ziihGcbQH1CtU*O33WXYbhck)nFj8uj3sMoMsUfCn$<%-)Bh($D+D*%_?r?8QPj6pS zBGWRO&h0|s$I({Aa7|O*EbGTexicx25*>*_%+(W_-c&9&!YBPU3NLN$Ljcfu$pHB9 zfcdZy9*w<BDIfn-WlpK)X)O$rPwDhnn$X8~~8p<8+t=@|ONO3Oi1ovF0tLi+i1 zzz9;r14Jv1yvlMIWr`WKbSjf`Qh9uYXIj^w6pS@&zmk=djpz`QD2D`1UwJR@U7c3iVujH98aS zO}a2__KYMFX^Y>L%I2<#?M!S>GvIq$`??27C~BtR4h_@V8WS;#)aHQjwZFp7Hl#Oi zMI?kkw65;h*ifP^iz=BMkijH!n6GqTLYN&V$&pZ_Z5Lw6_HFP&&7neGOfq6Y?ahg{ONrb(Mma{E1lWhF*YU6>Wz<) z5~27-Nb`qgF&#b-jro#^4FJwmd~}~JV=QJtAGVAUTLcue4Qr7VG{qg;S$zC<`mlB;7>7RB`0K!Yv{Nz%K+-Hlf__Ys~(3Ys#c(!0>JadJ;0 zG0>Gs<)|j1D;Y?QN)9{}W^gar#P|U9Jq`~ld27qnE!}OH-(mV~%)Mlf&Qu;v_|Qie z15c`0=6JjgFmJ-Rb5#{1YFflILLNV5n zg?(bI$4INDwgpq1h36)Ji#4sF6T_)tF0-CgUCG zD{Vq}1#H7C-$pg@+sCMPwefn*^|cxTdexhgsqw6+=r#|iOvZSodXN)w?19_R&DfTS z({_s7VNpHF8dN}@k@7j2#7B8$zM+ca^B_@vg(S)i`j28IOZ!#ET0@m!*4S`zA~A4Q z04BK!zHO`e7vomrzyJoNY&bcBwHR#zsSsoIJS)cBkU1-gC-f)No+VtAwMVG>3B|_HSdxRgaLmK7 z&4CIONAtxvG1Ql(?OQtyv!1pN?3J1e6hSarkI@P^W==yC)I|UI5KXN3ER1%nGD%GM zIZw1C(FlYjF_WOP3J#zSJRUO_cSc+$kQ>Ij5K-$&jf^xxEH?WsBG248RQQ`iQwVgJ zfI*egi-2i!S2!s1Z4Q)#1(S}pu^jfej7e?+8!mjTH*ts&mdbn%C}_3@qUNKG(X`8v zB{r@(i$#=e3^{}5iLr6ax>+C=yuBBoBR32g1(^1>JU2jlcO(Q*0jd+3^iE88np0zm zmYZ`74w`h1VnHq5@wbYB|-gSnOK|`4^?U$8QHdtW$VgdE5WEM6jAbnxkWeC>#PxHnSczRqf%SV zifT`bU3Ao$@pO)1TR6iHw6L<{5uo@}^7;M&Pd|@nM}LkS-QiZbv=FZ-i>_RfW_77} zincH~ALDTgP8kgdRW)R>;q2UrS$GCVXb90DwW6luXduPMap4L1kNHSPDn?r+s7}b2 zPAu2 zQ60M{x?{JR|zn^rFtV3~8pP0=(`Cl&WljBC0f>r(>|x810f! z9jAji;~iRj&+Hf=F8ar*KyL*stxd^F- z!>9_))P;xoWt@4sQ1|&cG?L2a03x*tl}_LUk@`~Fe;vyv)tmtti=RSd>>k;|;>9br zlnjZORI6?z0#3kk<1*hN-L}z3WdRr+zFEhkRs`px%XZe2PQ;Ug$#`fuL`M~&Ch3)? z_virlCYFpGDr4xHLR4c{&Vfg)#3bC1**Km{VQjY5EQ4lt>%0sMqSB+QWLp**P-@;{ zi`yPn_k=jF5-BjiXeo*8I1P2G*xo|W-hxmxkSv!=`*>6UhG4Xbf^?j(VFy?!ve-O` z>QD0(8~K`8GKX>2qLaRa)e{(@5eide8;~D_^iG76gDFEKS0pG*DA4qI-6h}3)P$!H zRZNI=GI%4H#|K8c0-|KERETGGONE$b92`nNBJaQz;W^Y+1eebM92t|9K8&oQal%%) zkT!KSBP3Z3dnAVuFKy9S}N-QD@Fl>v6 z0(^B5QGkv9Vl?1+Seb;Ci<`eISreAjTM<7{ zHqN0aqXziRiKN)Sr*5LDqXoMId`8!^Yb<^ZG7I@8#dow^GmK*c(tRK*rhR=k!=33* zHf);{<$1ZPzl~@0XXkQ%&OD`16dK3O6B#>Mj;o<_!`4)LL=Ym|4edZYI z2b=dHa;5-~lW68FZ4O!?86(Rz$=t9lJafdM@Q_5T42&U2C16D_re=mdpA8}=1>yis zc;XWjGjlQEN<}hWo>%vpN`NR8*}1}Jo1H^_1P|6h=b96R7($d;W|+$v-Hb|7q7Hyn zZ;ip$?9?eG22JVE6{?!M22h=yC`fa1Vx!5qiH&H@D-^OhW3kZ+_*ds83f49)QRvF7 zM4>vS8^qyLRjYvE6p1&B*Z}aUi{U|3Q8VYAt21>BCLgv54H4A&jNNUY&JYjrm@{cH z=yRqfL`SR&;z2KnpJygRqUM{(*n)A+V+>~DX$&#>EQY2=qS;x)Z=aYqC=-b}2ssjw z9L1xf5-S|!o-);NcmvazYRqNWry6tlwyDNkwsRg)0O6dBI3V_^hJ$G}ZF^en^AGZb z;aciN87?&sIoDMG!L;Nz{e`0ZoH?r9t7{ZC6f&Pnq6DYtABXP6{)^~`5_)j!L> zF{!P&AnFePD1VUoWE97xCWi_eU>?To9dv-8sv2e{@Bp zymonXdBns26ZO_KNw1DfBKDoLlbP$H%Z8V(LvTcFOTU_a0qAk_V*Q>Q< z+H!4$w#r?ru?^W>qq$f=>|93J!}1N@b8N!^R0W7V;eFlO2CFt&o#ZF)(sm2Y(pHH{8+)U4anOK zu^iO@`=S1mrD8iLvjQk;&&38>v}4Pw%XqDUO*qlq8FS)fpKuW{o^!xasXD{;fhLXH zcgF;gWkF9yQ#@ z;N}FfVPyRNJKj}!kHS$78p$KNl=pqS+vLGX*{R{X->qyn}NGrI$%qA6c1Tfi2XOf zl}e_9Ba)08;r5^+`ar#!cIxBMEi#VRrBTSKe;WqWXRCbmrcF32lR3LQJL_5C3 zA)jihWpw1C9lwC%UojzSjiU6HI`DSiI$Ox=8+oTXrNONlolCbUIz|-P-}peTM1EcY zo63mVU?uYFqlUYVyNg-B;THT7cBkPcPnAf|=irux^7TnPB#+umC1Sr9wlqB7T;}ZfLVR%*~fwcTx%3Cn7sct-skJ}Ew<6uTfan*zfCZu(K4}T7qsw4Tf;j#xi%xM z6Db|8^F$x)y@2sN@UCX840Lae==Z#<7^6Pciy@o_Q!g_9DzaBH{)0nvGKg8;d(8(g z-@NIZ=YuzhDrC+FH=#!L|k;up%6Ib^+%SZ+W!*!18cc zzBagIuU7Y9&>zwo+-u)HQW|~ZHTH8hjp%bzzP~C`)xKi5I#?AcpV1aqM=K-MQ&r)6 zN?NBvGn(F5vbb$=2i|8VpoAr9)umJLYO3Up?49F z`2w=bJ;681Jy{^wJKYvNZ zqEZjjHkMA@9s4c*fAC+Ad@S!io!)xaH-4K?Ldnv!w(*?*o1p~!J3^EOiaopW;Hffp z@GX{}+?U=umy_O_-|y|v{4eC62`mbi@LA*)m}fSGbsxp8{E`S}BsXUwM&4Kwtk z`8|xJW0nrOJHl#rM3+xi@5NeR)>sQ5&nbVk$c|w-m-p-^xgMaGPnJZq+J_T|^1FRc zyfxWVUi~z;Z=cD=6Ku_e(f(+>e|2QdV0>_O z(Fn~FG&kOmd1NGsHdE74!Ydj?`pH@R52g1Uxj8wJFU`DT>WZB1R z1L5US;x1O|spfy8pYnz1A|KKR5HHFDhY2#w;mM%>ULGmme>6YsJDPtZxFmQe|9UW9 zQt`u0krfliN*4aGA+mg!V%V@Z&|Vb{L{<#17=CE0HvIv(VnroCycoFaO7tJD1?LfP z;(9e`%ZAJS8~4@&Q;+zu?&Z;i(-*d0)ZR0wM=y+2Pn7Rnmc~kBu+HH6BmUs^dnw+J zLFN+3Tn3p-A@gO(Tr#s@arxmD5nt`Y(I?&t_Mi;y>oa|)E9Q`;q?J&q<-XmxqLELIdktY zuvRaeC$>QG(@$(88>+iveZ;xyodyb-b~TLyVugy)&#^^lXF5(g9T8FPHo&G7o1e>f z6^#`lkEG)B>_NyI1`5cREE>TbK}(hqu03n{_MF25ew5d0`~c6vu|&z+66OI|_a-P= zD18fcJ?r*_0uX0D@Z~hmEGdK+A>E{4^DT4$MbSEC*c0A8A+RKe->fiCN*s4A(CU7J z5fL>ozULge)l#&+$`U_p*!0`$GJN5yGVES5}j+g*T+|v%+G2m#uB8|lT5Ck>cH{hT=l}4ub2ncF=-I%k}8k6#`43A9jDZH!l zRw5wES7~Ip{|MyB@>hrF*tUOhl0Zy6pb?^%bu9bl;W zhv;&%-y!cMCI8T*OnEn{iGROj(n@PN=_4!q#m*Pj|;m1SaQoDN6 zA#VnZX3(V}9GS-)@@64V*1t92OL^Y{j^vvCIJS*~a7#mZM&@S)a5607%lBUwz?q2z zPRjElz;g-LR{$qvP`L8_g9UIhPK1;1UFV1!1de3Ow!InoauW$M4Dskm0f)b|q<;mt zbJ??e1-LulQ5u;JvXO8)VwK5Vr$fN}#KN(a>osw;|j_9_bZKNOEr9$+@3(tjU& zmQ;q85qp@;CPC)9AkZG99WVAIyG*OjHR1ED=+T}U-D9arDG9JJ6rVO>Gr0^Cw@H9eNMn}oo!z<_VEGbm-meH|8YR6Y_ zyfr^SyM#qf7&adbF6d|bP(|NvXbapXokp%Qr8r*jO7fUX;b&Qlf1|wPbTq5i25(oYgHg3ZU{v`&DMl>qh4T_t> zvtl9oCo2?Ze`NV25jy(-`xDsIUZ{_xGmVD~_Xu|v^SL7Nhq>FszG?7j%|T}vM+`U3 zu`1Euy>7Uvj?)MC42>Y^UR+bd}=e5=#S)lRfNBk?KAj$IRAY19Nf}S7(a8k-!bqsXp;OAUa!O) zwG#cqD#I<(e*wGHaMN6<679d+aEti+*qF_K4U_XX!LMb1W$>xyRbpoLoZ)Wf?ltTf z++--46)5?CgPYP%{waRqfJ7b;@vQ`9!==#HLV;Zc4l_3t3>P%EjZLjNn+0?B3Ah*R zBUw8KoKj#njnmbAG)_=<(71c<-kBsjwqZC~+4rEmtWalnOCK&HfI=g#?n=gSrH&v? zBy%Rk=}~NFIjMz0lUqg<6m78l?_VG)ZW-dLYsjgy-1b!Hek&eT85em0s3qadl0s3jPZWf)ymkTNBv(->c+Cyl2Qpy2{Y-T~{;q6S!9;L_AmZ8R<%iba=6lp#ISdI?Z^!7*r_U z|YUC z(b4*5muq>na|UNUiE^C2wQd~Xr&tW{y&F4cd`pY#sv-lv3yf2%qxsgF&lTS=wYYt0 zRJ*G4`1YcIKXNqRTLay*26w|DydBE7HhQ3?N2f<5J(TZSzXj)6v(P!CvzcD#?BQu{ z#`FF@%b0WZ?*C`?s{*JuRE4PSlA(HZ4}TN?+{XKQ*y;>t1dMWnMi_cLc(&ppc_f$2 zGkDNMOhY_+y6|Alo0g1=K|GhWb`-d%^aPt^ks;f~-^9NO2tSBdukld)WPHIg%@!~= znJ!D7LgKG79CG|V*4h*=%ec8ljF}lcH!Uu$wN*p-`-E?J`hh$lN8IXjtC zW9O=q@Vz@PCbLOzVyZv`+v*Xw=Il3+8g zs`FP=wO8G$t#cje+V%Rg>8&oj-M8x?-t={gjvU_g5Z+27J9c%!UJ!X`R}gkd1v--Bf`b5RL@Q>F-nkJT~@0z$S{rtqkY1giw;6}jZH{G?1 zHB?V&wb$MByz%z%O|Dx7?I$-i-MT#EnmB)L`H%0q{mzdY$jtM%Kb&!W{3n^Fk2f91 zIr^R2C!YWK;_16?z4JB`aVrqF0dbpwxczzl_LDoCZeN~bKFFQTgwO2nL`w_Hkei7T3tnFXj-aXvk ze>7iR^Em#mtoa50`)X?ANAqtA_nEGkR!dTK7yUxj*w^q;c|?h(e?*M{IhrT z_-8&0E$?VgXy!wDdjA6hM@O#Tc74YUSFc#Oq9`#AL7k^;r zfgAlZQ;6$d>kssI8{skkKjtR`UrTnj`)8-K&~?gwE!KlHl>k?y_e9$%$B^=u^3@w# z+x;`a5XJcgxH@NpA)$Z2#8(Bruck3l6%5Vpj+4(9^1h8PLaa51;9Ry@lpIFk6iJ>RRtQQWg2}MDet~-gTI2=#~SEBg=Lz ziul6IC$8r`O=x9N_~c=#KSCc!3moSz@=H`5et*v2n2+XGB>%(pk4_yt8DylVa>+0A zq4Jr@#nn@H_$q{5vuN%4;RAW!WaBY^$4ltBYG?nmsdnZLSJQD;>qUNDRa4Dd&dSJj zw|+5P`7GDliL(nY4Q~!#_HN0k3yuUi|BLwrfzaMB=1T*A(NubrVxwK^ZZ4i)Of7m~ z`OeQ3|K^AP{u-gGp7oMWPh7j~pI>8_ESahgYrY3h&&*8j)25;Ol4ko3yq>>XZR7a; zLFXs;Od_6J_PFl9Km2gGsE%E<_3bm`FPsc&-`VGSY*FTJ#vq?aB1@cMhFYVcc!!Xf<>2-m*F@7{ar;il)N z)`af~Yn!zXk?femC$_BPV>c$EkKXuvzPj-h{9oC)a_94TU*iqx+N9bed#{oT-==J$lp1;=^6xwr~^GVy-JE_&nD(lPvNxxgvI=L}PyZb|yn^cF~_T zb-w+dH+!c3q-p(BagbdYU+F$9BsL!}ZsxyK`4sE&1WQDo*Lx0^w0-8*&wlzlpJw;F zxJ+3tq+2Q4+WUOn;`l;{r72^6W5fO-5GMeeLkgK zgCBCr`@!Z&W0ZW!fXDp4b2R}~X^44V9MiBq(36Rr9UlX)OQm1)TK$(Y}H zsrz3_FKK`VSi@i`$c=NY`vx|6XiY^s`h=l}*1GL@XbmP;XSAPRhDRDHk0uG~+W9w- zNB&73`IYi^;$4;ZB-~5zNF(J9fuPEB<0wqVkK{^uyYa5dqqR8gRY@b|Jqm(~dkOBR zBnY;|QTo(ymnh-Va!!W37w@XP+u=9}nlw`0-+-XXtAjirXp}GX3lS;r|Hiv2kMugO z0!^148m zM#j$tkScFP$-gRqW&D;ovp!luE zBlCsy`S54<8`UNF)+^l7$n?JMkk<@(^#GB)8az^-h6t$gUVuDGhcr^&QU~rO;CvDU zTjDB!v(;0CE9-rofg^XoA#WD)9x5Pjy+d9O@>+qTbXrlZFp?_LB#eX%q$ew_|^ z&nfv_53rOs1RTXv?)Nm2xS@42eRWUINoXxGy++M^nvX7Dvl4D z5E@}DL;65={8EmuHz7`apz|E~^EmzRXXv>hkkDXt`!+X$#)R=GdqC3G4bS6RlJ9Sg^8*S2;_#kZJQ=U|!{eQ%8(;T-F?R(g8Qy!3hOU7_N z#oeXsFXSy{6Na1SaFv*uea?Y@(%?rSs}k*NkAr`} z;EViS&W;)GXE=TZd(DA=%iw>D^DkhFP*?2mVF&6mbs>y3;RFtwNvp~o3noJ z$F3S;Yxj7_%2}FVY5c!peK3qHL{H&tQ6RIlL<#x3(7R9?OB<7rC(+tMjD*7UFKT7Tn z==~E8_z`kaW=R&9WoWXY!zsJy@>1E7EZuqBu)w^A+-MrU`@VwU=^y?V= z74biY2aTERdc)pq*g?albsX`jAEEe6!d?Y85BF-Z)*w9=(pUHH5dEIFo3S9dKPu*^ z-s>3yiFt3Z@`3s@k_#`~zLD&H@mm-QXEV8DjQxdS)69YNergRnVA$vmc(^_s5KdiI2evS;)N5=RsC+Jda+xKLyoV{GxKfB-obhAd{e63( zl4$g{&m{lO8;djpq->=6LPq4Jc&GnVu4HQP5Kbotj1wn{;@p4lxE?Z`;mWW`zI<;n za8$p^T!!Z+{wDsB40_P?C~j#%W$drZ?xN*AtAWoO@G;5J>yyK$207i>EG$}C)xn{y- z$Uk#F&flSBfP3Mpp!HCKb8xzmqKMm{2)VC3Xi)Bio!_5qjtBXYi)gTK?(~W)bqjwN9h+?J3Q$>7CM+ z-@h?(!GwOv4TrT$KG3n~NJ+hZjMaOlG#{HT@zoBmBi)1JEbfm^?#myj9j=em&b-r& zv+l~K**m(MW;`y^cGn7X|5L6+J|W z2bu(Unmzk{vn+Idg?8n^QwKLv{MgKDR^80%^`D-pe`@Ls(yRFn?xQo#)wSibcXaw@ z?+86``pq|8CpGr`iKfaYPPp_XQ_z!WWHq7V!E#TC^nUif!vYUAJ%w~WcJf8NzLtD+ zHJpGOuzV$Zq!sa;rf?HISzHP8jp|nF~@ep507I>q-pq2{y87oK>V3axGl%f+i?x^yE&&w zTWe;21vE{bV|aXc%3sPq(}gFECwg$-^QTJc{L8<6O0Rq%_{~!#O_eLYbxN=KOt8Dc zbs}C>G_%-sUr;|0EuT3+verf}-(MYF8(G`_Nb=CByQ-?vF0?oII(N9}m{#k0S3gxX zQ?=N0#LsJJG0MJds$tF3Yh2T84V(V_8Y;OnwNxkfpawRFo<9B7?11+4=~Jgx?A02s z_xxbryRY@^Tf9zxg{^yL3d_{##r_qp;qWDHXmI>F_YDa}yjFNSn%*qW4%F@p?K%DC z3|hvif0-o2^lp7mz|h7K+G?UK7eu`1A4@fTHlNjIO0;Dm-L20~`&rSl5Sz)Pls%zp z^tq%h^lR3*o|(!~l})jFoc)?>(6xSp!dXqVE$W|G)$UqXbmRhP zbnM<(HOp2nnbzQ5X1Ifk%ckSco*!A-cKwY<^1CZ^+>UiO9&L6~D-9JN*8Np!)TB_) zBx&0DhpVFT;hyO9Zkc;%MU37{B056j>EjxC)P{LZp&uj-ksZAMBfcl%L3vkBP>Da> zRCKsFQavpEAx)&m$m^NNWsG}g7<-ZZ=08{8c|qxo2Tq^aGkHf*d&8MCxykeNyec{ZRk4@g_>Uff|#>s26zy2O(g_G0lAHIuUcu(HTzKbQ<#aQR;f7XbH_G0PB z1E2!~s(H^#EFHHtdMsUquExI3@f^N5Zr+D)<8dlJbe@HV z2VJJaHACR1Au!NCD&*Pd^N_^`iPMuAHwfeb(f1D&p>y~hiJQe2m~C;yUH{2+B8!iV z_lzWQH7<{k>emSnA1Dpcr-97`@$kdA+xu)_RVeqsBShaW7^QFgoi$b>I8}m@?{lKO zEjDpBc4Jpa-2ZM56J+_V09#zT60x1)Gj6F&YjS9qJ|ktNTw!*kZs9yNnoY5s=|`n^ zGKCRQDM49XBzA5lNRF)*h3LzGbMmAK*D&?qg5$V)sgqcqpaMCxq(Bj$ zoENbX*AZ_(BM|vEU=W7r8&$Y72sMvB{)~%}k)z_~-*n8l+uS737b5}#O{0?jzPeo~ zNFBOiOIq)q4)^GCa~qc_9#J#VpNpiagqJkn-Yq zr`4$3g_y*9A$fhEtMXn@KQz^U?n19{}18*$fI9EQJs-S z$|J2CHD6Xj9_`#xzEtCp@}?Z}++Zw`!VDZa|1XEUUL}5XmMi7G?2uPIkGy|!$Qw}P zQ9YFM-gU@Z4+h0w8p4rz+aWIpd4!|%uEHbbk@gFqW<6-0N8Uo<)cm_wk>^w7UF?u| z1LSppFO7`f8i%|mAy3v*yqfU~JLJ)=Mj)9+z7INZUk7fzi4yY2NvCpZI=)_Og}VlP ziXX+}6ApRDz$gP<8p4qwZ5mbH(~7){z?bq!BSy{VSHY;`62w0#@2d`+2OEHe^6v!) zt`|5=xlJSG9RyB|-*dI1pQL&~XWE3L^#0f(kF>}N^^^bZz%>Im0RPg+a8EeG{SCsE z?Uzn;WVpCL*p@F(LEfWMn1Lgw4xE~fGQarc9;G8-;3yrd9rBt>3a4X*L*7-8=YxNe z*MLXH?@~h^EN&(skIGRR`5t!QcFlw9GjPZrZf*yzTnYh2=3m-@Bkiz7h99z||J??T z@_@|4z!lnMzaKdKr3H$yQe@`2?6Nlj_hopLMn;uv83*Expi`bi*jM2_frrvTos`W0zgdPedSY9xnY=3~77WMuGa1W}wwE1GGZV{@c9)%B#pPN3;9Tu4JASDp3~xGo z+xh2ldCew@O5ZZ1&1J_|bNqw}v2ub)q|If=FXwow|H9CWz%n{!mUjF~2cAZJ%jg)f z?f6v=JdNmeHC&$0MA1lV z8M?j6F7G0aw_3?X78q}I8u|xjF4*XgNeyt;YYaRG?4*WWf|GJ5yk<&7C+mby# zmvDT&3Ax04qZb`I4R-tnj<;%|aCe!$XvDOPj-JZyKfwL(HX&9|MkF00njPQZh#!r3 zmeDctFEgCfM{2g20Li=50^?1`Oy7z-u`V;`HZ-k@j6DY#Mf`PLX!rwXiL|hwU`nLD-~?_i>xM zl>MpUrarb3Qvb?uQ%kKxfBBr@ex17)v+o=3k8*bfzioxWqcSCJITz0tu|}$db}HQn zLHu6MKaYLbaNo<_)$AI>y@b1$v!u#UsRT*x|mrBeuYe}$S zD7;G@?g-p8XP}45=LW;S$nQ(ou;Cs6zY^t7U)Yg`{*3K*_j_p-Y z?7Oib6x@fE!tA@Rl4|a`lJ^2Ttp&)+{;HJn9y_ZNX5UXOB$_sDL058y_6b3myJHHX zwNEM>a(5K2LVKcyT4C1s5ViwlY>tAeY>C1pw=k)Q45zgPs_^;dr{boF7x?5%Z`-!E ztGD8Fn{lL-HYF2{BO`36Igw3f5(6?Y3d!6i#k;aODpJvrYEIrvQL^ul3RkEjV(cHo zt8JgOz=o)p!@72ee$F*$+0+k6_o^Gk+}{+X7HdZ@)*>$&xO&*~_9^n$Y|uXh zdlhh36MxLmh8xAYn%pVIAewp8LVJz;-2=DlkHsxjuIoh~Ot(l;nOYA+F{^6#XAK}--CiwxfC(+$xQaFl8 zWTc9nc}v!OdO4S$``3nEq)bz^>pp~4EpAfiZ0Pt|{`EjNz(nFa|Nfhl#lxNmmRp6ab9bgedgJwI(eKe8-(ex$azI$9il{Iu6U?5Xp5PrEl& zo?zb4NmjZz90_-Yuf?|+DWru!FO0Y@tB!6x$x6QA2_64bR=e`Wd;s5N%>NnAOWi1u z3XS=`T*87)_Voo%J$?z#&;Pp*@oy-(=q3}KO|ze~Y5J9X5x?1sczAqzM0{5hat*#K za%`B*XpHL#0Iwqls$xAcXfw6*8+JgWaAt5D#_I6GaQO;vWavbZ_P0%*smGgE>@5Ak z^03x`{L+y&{Y%i^Y&rh9akebk2t5Fj7x6snt7X&lMNAn6(iEwAwyXA`_;rKjwfgj9 zwL1o`8w?7B;b+HAHeEf!%A}v7h)b(#hVBJv>tyxzyMsN0oc9sj&;mbSM11aR(vMCq zkD)An{Tg_zJOHf>t$K%=zVd)J8`YTRiZssX+OjSwU!xQCA-Et*i@4f>NP_R8T`_j#XX7wOa5=D$d?i(chgJ;k`!#yz9EwM~KW72#J;>)K(d zTL3w`OT8hwE#tF$&O<&1Nx+Tx-k+GSJ|F01Zr)TjUcq-!yo z`TXRz$nu@c-?b8XtbPBNh|(ipV(gJek=GB5KY=>)$*k*vuX*$bv|8r>{x99QO=0r3 z(swHEL*Xca$L1zjf8 z1+5YB{8JV_e&5Y^vXaji-~ZEJ7HibLDAb?+(xr*gDmi+72AjT?S{z;yz5uyjou=IPwjUky&*X6vO}?u5bi=~2e~phq zfgaE7WW#krKL>I0?Dv~=W~0}dbZReLUjlf1&1lrBr#lkzU5~tsyNZezFPYMO{F}JI zmg1JEMd4+`kDb>1+Uep=l_yyfwak@a)K5@xZn8!{U0gveG%f2V+P4SalJZ0X`&SI3 z{F>RCe>u%s)`pq?=ck#!JiIJy>d630H-gAo?7NRrNRJyec_A;0XHjnY5$YlS3N3Q; z3iKC6+B7EHYdj|x=q2qdTp?(oR1F1jXN&JXBbT@GT;};qo6OmsAJcsqoM8t&`*uxAq*%2fDONDb;kh z3DKGV{xG#>(N`Bm4(_W?znHJSuT03m-9oqzX9`(@1&=4VW&iox)(_Xsrrpi6^n)i?Bu2Wue_LmK+;W)h46|^-EM{a4jRTbT%#Z$eh?1-rCHM!WR}BiluY- zJlLE-@!9B1?}XGTv8N?O%x;ru>43;Ek0YOd2o;ne4N(a#iN9p)WJgU5V;n)J2G*aH*gP`JG zfMbaS!Irpxa^UEfyuJdsw;Z_qJo2zCw1r!S3Q|bkdIyef?x_HN zTrY41^VxwL0ZuI0Mc^`Do^ask=AJ_3OZkdFvwU|0*Q%sL$~y>Bh2)Jpoqx495f9{ai zfd()jg&8<eWPsWJ|^8K9xII3sT$oIwYa4z!v=ZM>UjyTe( zqc~7rk)d=H($U!l9Fme2D11Q=k-c0xV9RunwuHbo*GR*`IX?K? zzXMt{UKEUx&6Jn*DNTicw z$2V~NV3~h{ z&*33FwOrDH`m*8nad!#(TfU8!%b~o{Q@7wl)kw4zYIRLaq4~l!*Kh!dm&qj zz$iSyUu518Cish4(BMKUp)WQ|L+&>W{3Ps3^uI1lj;Md2hjfn4hnu_v@l>L}Z7|#-{1vRla8sMCM6UK3 zZV}%L*iCRtL*aee#$U}IvAJuQT!#tye)dg+FWhzPM}}ME=Nd*j^%Or*9v3pHJHH;Z zO7tJJ&LMu3yVtTmQs!_JpKgQS%lY_~u7iK4!5`rK4eWD??-*N$zf7e`olo zFoh14RBDiSm?^u3d}C2@)8?SMaj5JW&bheC+zIAK3S2KHv~7D|Xe1TiX>5esiFBVj zZP=S0#on^w#Fnw?vd$Vzk~m>7o$A?wNi>fJ_^Co6GVP?#rQ0HA?z*cHvYj570t~2i zZs6p|69bEGJ1el0%}r&KEYAi)=W?N%>B~$2B{rKH%-s^pB>1@q{Y#B2IbiK)%M%1s zigk8ilCXVkKQ&M}qCAC$R9A0XU*q`1Kr9y%x@K0MLxwmxu=`c>8W0E*Ck1wtaYmpL z&C>ys*fsaYG?Q20B*5g!yfF9w4PCO{iECn+QOY`7HIZ<$)THX!JaFSwzzohh3ouFY z1YpiSzxa~jE<<c3n! zinXZsGsewlpB4KNM5n%q=+uvT?-t{g_tWAQYqGo1!4Q21+3?qI*b}f_|IPS9A^6lU zuDVx@$6gG6G%l-l0B(xUX0j1K>c=VGG_!Ic-n7E;K0@OPefLzkyCApjrH|Imq z1j}iT>oEAV;v`+KGO{rkbKNgwmXF+!*FZM%Eoj(XWJ5QN=4_M?6fZC2QaT7v;}WG` z#%C3|A-~z6r-yg-jpvdhSwo4;)FInc_-?0$&FB85#WEd%C^}?(bv1)qed{+*1^k!$ ztDDnXCy$p0@%ZqRvzf(u`0dY^S2qf+qR0YmX0_Ip_p=v+hMv)hJGDET^ux^Gn0Not zJEVzJ`zyt3-af;K)h)nw(J)g z4DN6>|5}!%xv-wQ54^r52-?(^1L^&)=KGo|4tv%xzc!<}zj=zC*L*yrw|R0w?T=pG z*Ld7r^X3tj*RDMA8t&ma@V>lfLY#TFUfZ|5x2>b64`;GC;>)!rCVEqi*?2N3k8dr+ za3a1Fzobv*cFo~6C3D$Cu1(zJ;E*hM{7jnkVvXZsQ>ZN7 z(-bB9GG`D&iLtKkrk*RBF*dOG)s1`9XG()x%;wqK9#U#Xdl+jS8E96pST&{@D+LH<1E(_%5q8(clX^>t5u! zV~4_1Mh%Oqju%dwY*c%^*xICg_4-co);R{f!C<$SZ1=)1xD7oD2M^l75I;0!EG3x||?jxnU21y?278Bm#Zg%5Nxd#Jm-E&iV z1ivH@zZVEnTs=X;GKXKq{XYL{xV1QU-1lTLY)Xt4S?&&q*_=ghOs5lL1BrpQvBA_l zURB7vVr+W_a{>|E`Q!_(DVo&ZvSZ1?LHb3W(1zpArr7vE>#e{0l#_qyiTYwWO41rp zHJB!FgD!>l*>Zm1#E}d#7vZ56^xF1DZ5))Tgmd9bp5dV*M)b1|l4V*M>)x z_Xga(c%+f?T0l_c4MScvXe5vFK+22aU6mJvL!IkNc@qvC-NQtEu{08gWxq|{$UL|y z2k!QH!u_cO_s~4@PCIZ<&4XJGx>|0}z%Anr5#~Gnj`&<~9|R76<~*3>6`JdYKu29k zQy66EexGxh>qdd=p#TgcU&)qrmRP?*p_U_nC3s(hhtfplLv=vbQM|G;FUCqK1a9S( z*rrkGzmK`DefBB7`t+n3npy%B-(t*ORU^Lo6f{Y)6$=9C7})XRt51{{!ca+ChUT_* z`~rq-;d2auQdpn#(sR z077qdxUX@zhu|jv)VI-GpZXtZ$iJN1i?xA=Jq8-#iAQH{2W)OHd)aUcd?`C+eBzOLjL4RfSXZpk?7`HKaUBc?@BhiX+w zAK%YchWY|tZ6mlM(l&O_p-Vwj-@F%!KF52J__C?D-uO)~?5~6G@)^GgzCheZwF>k_ z=k9eBsIm{+i| zpETZyN_>6z+928NUwLksdMJwP51Y++C%x@_{zY2 zl;5NM#M`fA@2C|w z0e3LdJM8Fr~*dto1V-NSc}@jEkGkKlL5 z=_1$zczW^B1!#46a>d3S

vy7V_Jn%kcZzL-_}hF9+ifZld4mNWy7&;}@4FJ?`GT=c?;go;rN!lpaH=oGJ--=WEKp zv`^d6a$GA~_~YKZ`(BZQCED{<4C3+4NhCH4@wSa#8ty?S~XAJ#ygn^5FG? z|8q7i!g|ESmqe}~M#|#)x?}r_4wtOc59_OUH0@|at@qJ7jPhq;%G|xbXD`YAsWbfgjjk z*5MY2fvs-QKJ3qWCjE|W; zur}-uGv67$x@KR{KJUUi(RdE*nK=L(ZI1s27PWxFHrAK3la?Fb!=O5o-by^>ov%w- zx6R*-;)Xw;;?I1?_ZTXC6a#l;#ppo~YEDyE=#hQ2dPePw(r-1(Bjs%mkKQoqnkms= zIMuxLf86l=sqbsrX?@f4r&^k>XD+w6h3|$CNgT#4^0PC1jSV?e zrsD4R;>aUOeJ0@Yt#wTuI`u+r&q^aSe&=~*}aT*eh13qPwwi- z4a4r4^uW_6*&Xh~?vo#Hj5I|Wf%aFn|M~FaZw0$sPJMc5uZj7aeH_))+tf>_x|P)8 z&#c>5^%lFsb%d>d>4-j!?N)q+;u9_P`*<3INMoAvi+)*3Xy%WGDmst{vzm{+tH1ep zlm3J9b>|({Hog5?S^Hw_d(d}Ks-j-x$IJUB*LeOS31-!WLdZe{zzV>_R{KUp)I zuV|c|+<1Qs?=urOHO{h%`(x$PtNrA@y|MB5Wc0q+eM#Ren&)vn^g!%^WN2n0`#_B0 z7sxYrYWzQ&`rA`%l708#D=EK_Z(*{ju6%ZT3AvjmKmQQsO|)O5)mFzI=4}zT@&~D} z0I~+pS&i;?dpz&oqe3x{x(3I8iJo0!@*;LY73X$y$f1!8HhSlfJ2P`gJ5qCLbUi!| z$UNyYq7X~w!ocH#`$BBKU#tAq(u^VG!P`(G$J0;%aZ|w^D(mJQ>sOvaW?{Iv@5zbn zP7EcpxkRQda}#bA8tIS4cPcRmcZd4Ay4(8Nx@nnrz(zi0yC>w&X%%w!1U{6Q9HB$mj>Ond zZrC{Y6`r6dHcFos$YoL^xJfCVX&N6KME>DId3iuQ4^aHNn8O@3hsz{kS%I--ax<1T zNMB1PgDdxWA=u*6oES|F@Xh|tvF?d1eqbFRZb9sJ71$!27b}+@>TY9m9M?t_5<>Js z9(pHQQzHYoNUVS-lUK+izP1@ojwMk43iz~`rdLPq;gT?Xbt2I_LA#n6s71}mJ_FJH zo`~Lwo?WB;sS*5OcwQ+8Cz&eJCwR|7Z*v47A_$3 z(heN0$0@$j$Z+olK@E2Y+=XyoaNweFd+|sk<^3%Ps=OQFCS5OSB<^b&8QJDUT=~{}YcY?;f~i8RC^mdEdpmD(^RtNB&73<&Tv2D&AFj_rjgSBMsrmOyg1I zxi7Kg(YAw>R}5jQJaP38eHa7!cQ(Vn*| zZ$0D%0U~*oc%-~74td}Ef4F-W__&JuUVP5(N?NaEd-br9Wn)$kgFpu42VlTW){?xI zv@(`u(-`d3tCx|mZ0iLPBrPIvQ-{(UlaL!hXd)7B>!dWbowzk2ROXeEgtRu`)(?^> zlon!WD}xPNoO}KMe&?JyXU=E^{(qW&?!6i5?96ZGJKuSnIdf*_%meazxGSajcp|LM z*8{#vfXG*bOYyBX_+q#LENec6mz{mTgl;TSnd@q7e z-QQw>6`z_HugVC|Zpg%Uufg|<#>eui`2MF6zui;tJ!@w@O^IzzP~Z} zUf1|I*HQ7A>(LKR!Dp^Ve_P{=X?$rTelJeJciM>GX^pQ;}m14e7Ej0K-S9tZy#c)^o*I@94QK4rlFI?ZC$FB%{s{HXeQG6+b zuLyjZ;`b>7w+y)DjJTszI?VO$gTTcU2)e@kjluUIaD3jBQn+6kxEFy#Qd|XRss0%T zJ-zd^{3D)xOn(Ia_51q)WEB>P6kj&%b-smK{#65~_!by^bYT6cl;U1%;G$FD{=mS+ zfXj4$|A&F&*&&&5e`(;BO%d)-3|##bxHk>lhAG0$g1w&49aG>gF>t+*V=D8YLzIf^ zxb^$7RJ$M7IXK?m27{0LNi^9M@>lV#H29Wl<%Q*%IPz_UK~Kl4kSipU{X-npEimZu zYtrKPF}M>)zAwO_^I?iz#wvpbaF*&hgRe)6UmXy{F}<(Dpr@C^>wNzyMI2QQ!qIVY;F@URC~{E+fz#75h;W-> z&-XM2gxzq<48HqwGC!Bgfg?AHwN#G)7kA9mRQ#B)jE<@wh*NRWah(S4G2mhZI7;!g z0;i|rIiw>F4Aa5#N*wv`GWebYAFN!Zvglz4$GVB?N5Ey81Mp4YkXE;dT!%o;XAVFg zaNpGeR^jS-!f@-*aoK~4XdTRKgEJjbTuiIVV;IHhOK`4{$_&Vgk8Zls?SB(<0Q5X( z>{w?q3`T`#hv7Y8EzC6V_27dfBq55O&vjhxR&N1-gBXV6T`;42J#g@Lay@E05SizVJm z<;4cR(!f_5{FMg&G6R2^#K&CJWv+>aAkISYr?*Pty>@JsfnR9g7aH+jXy7k5@Rv*c zQWu3zho-pB-ya{mR5ZnP{eE}#wy;55$M1JvEW=}6XRF1^AoUxtBv?vWAI;N;Pp2nL{yk$A6utTFI)2EI<>*Sjb$CA12Pgn>^;yjM#nT%R_6m4RO+@s)f* zNwrEDq#ne~R)72(B;G6k4FH{3Y~RVnf}I(U|m0{q=StbhbzP{6N z=eU?s)c;E5NFu&-&ae<=HokqV0Z}c+7F64d;`yJWNkEP;kKKUxK*N4Aa?mfov zZN6*7&wco1;*3weR!m34h>yweuM-OxQAd&EYR8==zX0{$4USwP<&TLjM{bsK98*SY zzFsNUh(C7Z4k_1(Z#pttVg;yQegIi1hWAs)oqf>)^e|s@WV#h_CcHgiP|nh{KV^C! z*KHY}oz(Yp+d})GZd*8?(rrO~M7JgN`P`O1;s0oETiTz>D>{VnG0XjkHTlC;h7VS? z=e1FUyFf~6Cv?t!4-_DA|{o!i=b?-0-i zTsQASy~LVxS8W3M&EEdNjjwsaK6xj3`*v;>!q1nT+Xv*K;?5UR+r6%~uC}Ff5W6ur z);5>(5!pPD$Jvu%U1uNmZ@|{&GDzD;rda?PzWrzT;!i8%JHPRDKhrmT^Gm+*{eIF{ zdnb>)@AXc!Cw-~6?LYJz{S*-I>%0cgzsWn+{x9(|A^5H==K$DC?rhwYpW1zQYD$#) z*6onBx4YlQH5)(3{lxAI!L{{+y|3y%v}f&yPyWR2mSVM+jUBJaU)p{4zVGXXi~6c= zTdQyBw#27V|AKDYX83kKX>T4U5dSB1msIco$xJeD4M3Is3pM(|Ml* z)9v+IfjM{`ZrMDD{TBy?W94uYG+T@q)@)Dz!?ip}s`qV?Od|tnBn~ z4d=7JoPNwPKL+z|$GjWn#~t(IF|1f^uPA%C4d>PLAII+_{Uz=8T;jAm11XeP{$0*& zys)vbt8lM%ePQat@wp9=u7W2@l5>Zi+Ft5U(P@RFdM8D5YajusDC%m3kxnaPr_naP{F?yFfghMiDw9?rDJuXg2kMH(Nf zxtcah9!PyDmFB$H4^iR$S(r^-IMKV~gTstrAQ`}%Q_S^^hvT>sg_v6!-EYrI&rjwz zshQW-*i59Qd}1P4J24&%j}@l!c!E|NIojpy?Ch%G;duEsWvts}2xkvt7B1GzlAH7I zQ4->FlXHf|rHc=jG`^I+S8Pb_>K;iQ>OPu!DLpKTTMup9(E7z454RRIHg_FujrJ6` zHE-R}_ELIOjNtb%aTLG1MREH}>Bq%}_FcD*v>&?lXnS;PaYwlRQ2Kz_&~a$TNXMb= zM>`I0!93|+-V>-4(uS}ZkGaW`A#vH_LnVzjbv={5H~LW51Fgrp4!6$fekMH}y{Y?f z=QqwAtU1=bHZ|wg{EnM$UEBW9t?WV9T+d!&`7pmL5LBK6frh6k?WtZ=fVq(D)_JUhX@1Y536I zGY9XA92$m6lp_|^q49FeYp$Ib4t}Y1S~7z548c=>P+QIWl*B6PR8FH+UWnf>VP@(9 z<}cE>DHTr46z9;j3diHZUNd0Nx6Z zT~`qEy|bzUhYPoF%z5t!=NL2p=#OP6j@a>-S>;<(MOeK-SD7c^_$SQPy(sukt*@l-tws*4 zdk*?Pbr+tFuL+FhBAj?lNlKKz)iEtufY3wbRUMceEfwOG!W9k2M_+mQ!l6{SZXWUj z@k!+IoVHY6Bd`1}T+mm{f1oC}ap%~MiBvqAiZmV+pM7(hC>%h(*k`%fr0y@)Z(QUG zFhuv`e7MBSpWOTAOd;o)OFMf8vweOZPMVXs!gUQu;g}dhzVNl-S2$kG3Iu|@0>NO2 z^9z1^rwyZhep_$zcFeq8kILPi7H7}PORQhHZvEz(&i<9#dI#@7)2;Xp3CLUym++RYQ+i2&LodP&#N~dfQORpL8t);VfNB`i|?lNB;YR+wJ zVAa{2zV90Z3f@H;JZHqU$?MOMSSZ4-6CMhxqYPiRbfcE0zRLaejy&Um)>(&TM7Q4=FV8g$6$cMl{9wB!2!PiTCnf zuh|&?*#>^L#Cz{8*1VqLd=fu@vBWQRAznzd;(QW6zC_}^Tw%@WDb6SH&k?4e+_lED;<*nAhDe_N)Bi&QDxaWxZJ@zs>I*NGJ4jG1-PXoWV5@O5K z#it#aWsv&>-|xtkQjQ9)8z4SU$^~MNBUebdP;eap-D6TN5(`r2~et*5lk@@5lpgdpY$aZ-1#45;C?Amy@Y?hF9H>Y$_s<>Ise9$h zJC6~T{c+vG?S<=>=xe*8?0Gv%R`px2f@b$3iDEsBIEf%T8I6cZ{q|R;=L{{2$N&pqlPS^)93d(0E zfJW0U>dS?Akb1okBh(x0J#7L@>}N8PwA+o5)%Jd1ksF+E2(a%Z{#sAxqYy!pAWXf< z(LdpQli7eZDUN#&{b8yV-!lw%8Fhq{-wu{6yLNF*s*m1#r^#+Ax!(@v@eC%6FGlwlrgE{P z!@9P@*22_UjLR2wZQ5HX$44eVx_A9|ih@1L2Noye=a z=IAfp6cagDUww51*K}M_F()~%D?BboQ{}H^n-lZCTU6f}j?Y;$kz=hmC9E=MKZUF_ z*AxcN9Bt>08GlxD|JcXpic4mekG{1l@Rgd-OLOr(A|5`m@4Yvc^v3G&y&#r;DwgoR z8^j(}yz*A50vF3 zY_?1GF28d$$2xRJ*BrSAj)--P#}d;|Wd~$9*unJOLq!vLGv^(?qw9*~Lp8<6b|U?W zk{Kmm+nX1gekw=ey7qp$YXtVsmdq{rZq3KX{v@4K{m1F->bi-%P*$Qe`6ub@*v+Xs z?|f-5a-cOdkrxbOcaFTO+(V(N>4!_OU&li^B}c;J7r=CL&ILz;)b#Pd#ewnA#bP{sF=Ncqu>|{6(EQ6cg4hLy z`7+9mFUtqZhEmA$^#0LP;b5=|Uzd(vBy*Gg<|k)jZ2y0XAaXqG)bPr=$!J;DnJo*j zgU!V&-U}2~b%s6&Ow3MZe-L_qcGE?v_{0Jc>!i=Z##p(vEY(?@Yddrq5_V*E0 zXAcF+w`^<(+VesH>dZslh6;a(r8wO#ODXjf~U@%q zjQcIPv6zZ(ick=@mMv=r+BuuRUdOJOYTKOASY_ejxPd80g*&$`P4u+h@*5bT{lDuh zZ@fNT#rF)=LR=gNP-+v#3Sto0>mi00-+g!m$@U?J5u_TzFW^tdvuYx2FJLVtT94dbQ0<+FHiUd9mJEaugYp~Gy=3%&@7j?_lk!g&5wsQjx$`GrAZWbo>9xF}FH|#W6RI zQm`#+EB($f{@KPDNVX^ika66FD*$);_eP3rc_-{_rJj0Q;+m~oh@}~{iOS}D?j2iCWHRKl{vwSq;;u#VD=*Wye&u}>D z$gE>I2me1DnRO)3VpMy4u#V%L`ne>7qW^s4pWD&0XDu6TAq;w`)`QjvQdUmWM~Ss< zLbWK)Ysg^Il*4s*U_-5KO_xr4V|%Nj{sAg--uB=Jb0P*mD!-U+&E5yVB_|S37g@772Tf;T29lzTB=u+27_n zg?ts%;lGkP?CYTiV)%iYzu3W}fbj{BK<9fXf{IJx@es3oM4%t14nDr;$j8DHK>R|~ zV=M!(hyNz()u_9vgQtJ6y?p??uc;2VJ6G@O%yadYR9}7G=Tr*c2{`pkvMxO+;tLt>{uv1JgorxX~y5P79Zat=P#vZ#4rEV z`)ll(I)lmV1ok1_^>Vs+RKzfUZdq31GHXZj>l<<=f;rZevk&Jj5v31rXintH{SCX4 zS*OB*6Wek=2)t8L6FNM+vT|%Vu`Cf7Uxqyraj4K$S(pF(@U+wMCEq||iF97`tcmQb_YULMO?+;6ur_q&bm=$FhHuG_h0g{*Wu4j8 zSJSi?J$~jv=u~!i^lbR^G*=}8iH1a6rXe>_dotP{2s~L69@|%Q=q0*e9Z8(b*|O&3 z1(l;`vu_b+!=JKu1icpisuK1-yFX6Hn-?Zeq(x~-sw(*t?A{tE!wjc^AE#rnpQJmg zPo%qgf0FKMM(nFA8muKhPS;h#PwY7KT+CjxW?a-*e8WrW@WFpbZyGK>J$zUA@adJO z4^Q8loBHE70!!9)SPR~IBNuzG4i5}$vA#O1;jgy@mOl4ZFgN!t5nR_1C@*ZwO+C=n z(o<1#U&%LW&Yd3k%ju04Hl`g&VK_Jz+=KlczaW~!aj_Ox9CP5XXC@WDXGw+fP!Yo! zCs3FFDqVZS>Z&0ueVO>m@ai?IlmD2`Te0T!>w%I~QueEp$%nfFi*N4uy`F|-K4yN3 zUCb$a7vk%?3QzC+cpy=G=tpm5i`{4Oq{v+?zklmLrbB&ePFj~XoQ!tkehy^^s*&?G z&Zta5q~>I>?Si^$*fcnHYfcuIeWk{F*{U8ZscM+ndN>^}{mHF?I%~TN0=W9-Y_t^0s5vnIkxvWMJKvdC5TO zoVI!B%RhtrG#4|`Ubp68-dt7hm%HaQ&aqlHyp&UTWM*UVR9GC|W|e(59;wMaTx=CK zJYF+xL*VG6HKAkH_@g!1N54hWlB}wK!p_j?dx8y-E$_cUlgv-#b+|d4K%Um|S(A47 zfn6Q%K_2hJZ+HKHeQhmPg(F?aqGT2^=Q*$MN^)PqA{7rSt*)HcRKij#nUR&3; zP;L2A2N#?IM-Hk>aD{Pw6b`SJN#W8?DYieT@T&6lvo_!zMt;r#Achy^W?XtYIv_`J zDW&+jV4>p%A%|2VX?8r&zuvz~A>0kHW4Nqoh-0|-;?ntsz}2NP!@)rl!?<+51K^9p zj(oINd|!i^yej|3VW68*%De{_=Yt!|fYYKU<4*3wxM;8L0mJR1gQMuii|q$E^*YvK zEh2P2{l%TYom8Hnt2j{CvS0KdQQQZM?GS!{WqNrZnMW#5U=)u;gm{t$M=3rfD_yt$ zP4pM@6tUDp`0DB98~clwLauZ%>TcN<>@WKLXG^?ir=CKE&oS^h691~3DCeE$gvU7= z9v3aANqpSJ>m`u+nJe8L@6dAP^G2C5w~XE&`-@DUr}Es>>utP0bk6Chb-;{*1=;T( zoqkQRzo{$E@o3g8SPoiok&9-Yv#|rZQnVY!MRz{a{09C-n3baYpW&iApHY4T_Zqf# z2S-)RlPY_3b$pexS18uen6V9Z*HIAn#_HMtFEc81`O(>ztO#DKPv7w zI+s;@Nkf4;Es#^y0DR+7sd8u?@BGSsjiCu|{Z_H9Qd& z2j3Mu4*_jV(8+W2*fz{Yi*ClFhkqrk#j>R>7TjBN+gny}`iaGGiAWdXMr-=s$_hR{ zX2q~?J9;U&?ET2Ex#08U6Tg4_acWWQBTsxs+4s&)yerNY*0t5{J3BEUp0KXZ!G7xh z)|#KXdEUlwOW3;Jx^AvjdooZSz$ypye8#G=CInZadjI^!|F$REwYIC^PV3Ku&(3Wq z=?!xNde5t;}}|>q6fuOy@2yYCIa> zbM~EgB6YRzox8Cho!b<}DvD_1tdw|bZD8NoQ}0;Up;fzNdSmU$d&>(`S!jn>vlqtK zi>;7%${7Ef_=5P{&4rX7LmY9*^DL$(?6hVl?9~(26-8r}jh8lFx+V%v=0at17+=o@ zYip2~sdm$A0yW}gk_(+}NBlIix6 zp^_)A!*2K=50vy?fE7p&#$L*vePmYS_s+g^x@4#*89Ey}wXQb)&bpSy+NO8%TCKB1 z6`?afDhi#sv4dYzvy$^V(bHG~KCJ0jwj!LsRmbw7(&*|eA6IX;xR-p`Ilm%Q^&f{K zRqr3lN{+P8*&94Fylxn4ZEP-Cp1@forp*8Rs{IlsS=&REjgFW8%!N-VpEC zL~z-`eGU&Iz`l=$hu^5{HzdtC?O`Z)Z?Lhjlg|atlBkpMmg(SX6ew66{QFyf%fI2- ztGZjZxGi`0qnqtg+qJH@wH-^hIi%!$k+U5eJa2N9hi%)mqptgQ3D+ze1{U`&UB&Nb zMgUm<+tRxImd=I&>?hr=fAw>sCKsDGVfpyrD?YXZ zbv}L*eoT=$IEp86>3olXk7c707u(K?kL^gE?+}F7;jR>MR1w(gd@q8J`9eN4H(kC3 z1|Rp0W?558@s%2U6|=qa$NQqEEJQk(zs#38xKuixGWaUNmnj|G{~G_^^E(AD3-Q)*ao}R`rTcUorhQQTc=Z%3 z{N#O2{dg}V`pC3TDe>Mn^oULD{BlghAOBn#f99{PFmR`-O#7OWzuv`A@>HgMO^NWn z(VJr+llL_x{xdG67c*LA+Sio$AGmndyq?OmuPN~rE<}Ihk$>{Oro?->j>`Da zt$R^ppo|yK&Si>Nr`U3~+;7H{!*cB%Go=E+3g0&Srs?ku)cn?*YUL>ZkN{< z-OjEW)a>c#z8%}eIRThmUMJYe9bJ10M}0z{!Xd+VJ6ulJR)uq$KOo0dCByCR+7=l* zx|y6*uhDUHyQj`RUZ%CvrCquD#?9>KHf?Wd-%*28#MsX@v3}|dJyu^B8Qc|t*4xa~ zBW?F}XDR7DUdnpUR@T{p-?8iN!1a!PtzB*+c!BYGjG!~e=Yl%RAJ>ZT-4j?Q#4vUE z+esZf_fv=e5$Yco@(k?xO*Sw2_$+YE32P+sTuptAa}G1~Eso6Rm3%K!2j3y;2;(|86Mv}^MBXwQxPY(Tio2f?KWo&`lH657X!f2=kpnVe$#GOx#Q3I z_;zs+GgLxV(ft9Ox14h*t7_UIt19b|S`QLV2FAlltO!Ux^KNJn&(AE{%hQ3a@gPp5 zEy0K`=GwO z;`iW{<FINeN>2~> ztvDGd#d*^Cy{mHQ)3A@iUX6_+{lDFF30C0HLH84p^VEAIT5|h5*Lm__rQaQ2j0W2M z1C|*8tdIWFBUAr(&EH3r;wsijR10zG?XIG*UGK1MLJTih$z6^4x>UW2VVHN~QcCfm zn)30@gJ)EE@_R4+D!v^s>wKKQUkN*<6yH`@=WXg{%sO8+gnHO1rTFfL zh0eE0<71CT@%;tNp}y+yEBiOM|@V;Ca;996!V>B zneIDr@jE(Rr>>&=W>>QBQ!ixV$y0!m`-g`6LymjBbdQKVhP(DMR_#!KW#v?cZtdsD zevqmXRg=-32JCuM2){qKs&sL#O$H#VOh1q|_MF=JXcV!X5y8(=M~^!?^P2Ws9DNh? z`H+XHqnjI}KF8j7b3VG6n9SVU-rD1SA$Qv+Xoc7x!tLKh)zw%Zitp!(mg4vP+9%H5 z=5G5W7x!#BcIPYTI=1iJr8$S5c{iu_=6%-U(AcihIpx+kf3q6{v5ot_gzwO~buSN; zm+u-_H^A?Pd+r{e$$cF|*ewvVaN7e_p|Rm|?n>zF75Llu&Xym#urGCU?TV(&_S8O~ z6&Cz$+0no4|K)e+hQX1^Im5HA@lM?G86J#+{0~{;t^s@(I|nmSjE3_(gG<@0un!TmgHf6rYlnuG{}6 z-ZlOaM0=kf*2lI|xoJz8_Vt+oCsad@vM0|giSH&|ab9#jESQEkF1`!cZ=%e5$bCxO zib&PWzGANgRp7BJIzE&SoOi8t&9&#>t2!MiO@taWG#99 zY|z5mcdF)ad}nT?HoCvKp8o7PDX)iTB}3J(ThD|;Z$+b+3p24HRZt)3!3ulKmTVDa6Ny)C}I>nHQXCKo0ZR1{pduUd^$Q@X&oD0R*e}$xW*XW z%YQYo0=o&{@Qd_khI8Z^eS5C{n$vd@|W#HWKk(?>XnQ}On?ax{LxR0l*>tKl;zmZmZ2id9PH!8VCHLjlf z=vSq4tH;&majDr`Ol|Eue_Qro&4XiQiIT*wn&2_|9^Mxmf21asU_JzzQlF(=>OMOU z!uzKsH+0Rt@8GGs;^NF*LY(Q1Beechb>M7J*zqoI;|{*q#ly+hY%O20#$mjpBAA>f zSz`&X%JLH4k9k9%XS_Gmj-I(QWiuV+Ucl1*L%C!wcwCr8=iaC2ex$PEUfk1A0_?ph z=iV2$+IaE;-z{ev!8{dyLz{=UcYBgr7NBvnHQd)EIdcdvEZ2x z2EKdtop%qGs5I)BjZWR$5M3m*S1%GqQ6yNg^=;w3U4&RalT<- z{f>1!3Zs90cl*{_>~)|`J#sK?AK946ZtI6W(b~U_QE2HzYq$Nj9(#k>&K`TZkwf9Z zEzQ#*uD!{=Q{|Y0(MF%zQ2Tp&Ue3-e|d0I@jDK)&iDEheE(qZJ*MR!dkBi}KMcMw zx=IXBDHXpnu+Zc8JuUxuUld<4;-kl}2z(Wa%)wDC0!ZikftFr<_SeS^zGYMJU2pKc zqNTUU377Zz_Y6MH7OG@~9Hr9B-3;~ky{^R%gEnq@&0UP|og#kbF2=vs;>Vtr%D?Xz z@!LH`{Jw3(FAv=|^054sXng!SjDPp}Jp{hxkd;#DJ#6q*fG-9R`S=A*#qYGi$6c>k zM<}KECJeqh@TupQJxs+n7x4kqjo)(cWx5}nsifbJ^%`GH3RE%!FMnCSbljwF4p+IZt(qJiu7`J znx236YkbUa6~7-CeB)EZ?`Hz-7vp$ADw})U!>#Orv#w z0UZ8&WuW-^U%;K$XdMQYo`OfE7#0Mqz89F6mj_GL?ahl^LOE`^`G0}%PuJ+e!H z>lyhodB-2(-J2y_Dms4hjz7e+{7^fAp|a2vXAk=EF^R8mF)`Of19#2#EzkGT*p<+KXoTsJ@dGK2pz*QbrIGVoOff0cp1+`#h< zi+O%P2UC@x9jPK11B#$gBxDd$ir> zULb~ja*_D5BQqa)YV=?G+=~U<-T0UJ%w5U<&5@T&{5%oF%aHEXQl2kjj%@SAj9tvj zM2pY8LfqoWc6=`uY*&)cPOo<=wC#SG__oizN<8n#tVwtZ^a)4i{VzcIKIOwN64SJI zF!OH#WG_6FM`uvv3i&n38+9?qAu$ux98*!lDYfUbqxh#Vn2Bvs*4&N{u{}FJH6Waz zG91I}e$4k~2Q)NocFslRP?X~}!%*j>Ij0U(8}W1(?B9qXBFrmj_adc;y}?a=3>4=G zw_ps4gJoJIJS@k*oZvi54e5<$>a30r&rzfKkO5BD+oWMlHwu{sGbcG}q1oekOkRfg zd5)S7Z}c&P56>~94`0T3BaJ?+XRV<#4Lhpb@DDaRwxHC97#&+M`Ue)>a^Wu%>vv$# z(evXUYQ*!zdOCu}C7)mJeBJ~-aI<5-$sT)(eA2Ej0?l?k9f3XTkH}`b?;rU+d)8Q_ z)!F$C?j4T%F!|t*Ezd|hpK<8G&!hc1yDt-I6C&owVMqT^{1y+daBNwTSMjjr6v4|t z$y4EE`VlY2hw+o?y47wYF@CJ4$jkbXGFw=Y9y`A%M;&*S9_hZ_b64q6=~gL_g+>PyUX6ZRXiO zi?3O>^t@;PpiYKzXaCGX?3W}j|JA#zUQWLdpPsl3U##t2&gv$5g5Rv+{&VZbvGZHk z(VYKyrONp(j$PK}oZ`x4W#iYozj@|h?V5?y+LzP!?#fREPKkbeamMZx74n;OX=A7~ zpZmJiJiGN{(zB-iI%lFx%e}>-T0Qvl}1UmOuRPwyb2ya29rb$1WTErV0!* zTdDB=Jnp(6_pOg4i+2V>^<%>mZCLeEGMv*`xN}aZZtR}Z!|U#u$PL~k@`pFX?eCh( z|G)pu-+l1g{cW-((X!%(y3MRGc~s}h?SuV0da)wk{pRNY)^&Dvpw)m@0nW|9qp}0D zt>gzKkHB=!NHNfPTL-sakOU?Iv1s-I__3!~vtcZ_PrKX)U;sk3W?uB4|MY{2fWpGX zdV`AXTwSsLpen^hoc(A|#?g)H5?rjCJ_^Tr)eLt6c1p1xrdo(gA3y6w#aIcuLR`e~ zVt8wD>3kIsmcvdd#kU$3I^PKR=%0Md1I5R&D4j0_ArE#+DZU3`q2qcWFl|aH+%8z? z;f^BQ80;7>?Nzvc1+&h_)!K2`DW&-K!9wRdsPVDSrubflS-&5zf{*-4Df3&fpjq8F z;?%t-R+-;7a6g{{7lb|eR9=ijV4f;PH(uNc7-9A*`?Uz@e8%^70ymEYj#5VIDz0>T z8#i?qEZCp82p97uii>%t(h8&a3@qNI!BL7&$x7Gl|EtFL4ynLoY+V8Iojjh$_JKEk zqn={hPo^EciD!ARm1m-y>6AUoF zo$+nAt#jJ|`ga+opR;R{p$7~P?RZPtE<@dewf)_L-I!3L0^obfcpZ8{XLgWYv{#*? zGT({F2efr#&Pu>iXXRd*y}~w9E@YlXD(rI29p!khBMY21_XSQ{9Svu`O9H3}Sn4Bq zQL&s-=JOK(j`t)0+%28kJNvuaH}`hkA=}4lX8a;dh_~m&+rMgNJXh}7OZPr{=eVQu z5Qx?`9ul`K4*TQZt?8dVe!@RL8 zIMLhw-BSm5R2^Ol#Ifw)k!m8k?eNB*sKzR}ow0(6_{<9vmTZ9^K|8r5JNK1KlVR*6 zb}7(>r^Q`GW0y2mHe%1@RCzKE`{4M6JdeKr<}K|x;Ukzc+Vk_A&?|F*4#zek`~^9o zBeNl4mOrFaD0rj*(g}q7D9kfqo_p)asv_)|+`gA-tbZaeS=l>x=;rLukuY4X*jIu5 zW_H#Q>?_vw)SJEWjornodgZ*ra9rl9`iY0*QOp69?Qv(gMhXZ=Dr?Gv{Zm z!6R2O?5!iKx{*VRVg4%2-?pY9FTOf-0(O_fZf=jAC);6v8SEc{{Uxy9=-5}nz5@0) z!M>Cnj{U6DcZIGwH0$*6mGf>0ADRb5NlxI%lCBeQ&pQ3-&_4yIF(-yTiM(He{9w8& zP7f~~g*|5a4m||EC0$XOPZg)d($@mvBa!6Bp|47ojmRaSi7qLnN zjs#;w6`dZP894kep(RHa>|KCZ#1dcKws72b3rPe~ye>jcW+!rGS-Q}TSJvUV$&#VD zNozq#Z)lu2QF-RDnwh-viCOTq0VQq*Q`l|AkXM1=kz7b8wvDX%h82`$aqjk!Rqe$a^<9anX$HlM6nu zPM6263Y?_%PVkF)r?LWnhi#zp5}}1HhklVhv@7`ahtl=KR@pb=*VP72hQqs7UU>MS zbfP!#m7j2L_(Hvx2rh5CK;WuX2#!XFDOpM-)Su@ z9xF`To731-KURzL(X4Ffr-y5w$$D)&O=8_WCj(aLMAVAJFH3!6%ZkR_coZ|^zqzF_ zl{Y5J*8q`~C6NQqp&tyt?RST+ZMb$db~`VV_U&K@mBIJZ>2TT7#&Y^!1M^~=Aym%( zbM1r`%nC~X<@cg=BIG42vM+0pHcLJ$Ll`cM-1>ZgHeEq-maiu3k6X(c%U74jf6`i* zDr*Gy%oP{|V5&kAD+-^sE+o%{82GGppG?)T8>hxC7a&GSq-J*G?53Bo59M%b_+-$^ zjhCms)Lxhj$9J_Cr>dV~e)b4wcSSr;Femuj=Cy_EaN*Rna6E>35LcoLJEw<=o8>wL zm=k<{m-mM2a3wCou8q=IGviA<> zre1yn;~u{h<4iYIbbq8N)fL6Qs@aFR3+7z;%v;MwTeFkH7|B81g_3$T#4m1T(dsQanKAPuZ3CzJqp7NB3pZzND zmMp_usc;>7hbr1~f9_!4Qe24g{- zd`Ow&Q|j4ezA^nW^YMd`y%pJsnTcHzIXN%q%2a!KNj_dkOS$$Y;KY&l<*xmg;lz!f_2eb;U)Ts(CGS z8Co;S{+C^FSs1B(E!CB?Vk~gI%~3Z-+p@dAm6LPCau^C=^U}0$^qmAQcAzn z)!m61PC2@^DJ!w%iQ)3{lwB%!@3nRNEk8q+sYPu6rb576nY_8H0B4!}%OSQ!-+x2J zocg7Bw~dY#cJUc2OkI*ZM?aUWktd6Ut1n4CfhTa!^H&O`cHww-*WT*tg^78C5sxV!8UYb9eypZzRY%tz#R zcz*E+}U%z+Z9YuTRq(T*ealBhw=cMXzB90iJm+BsB-TUSc?E3Ok zvAv>{E+M#34}^BZWwyJFZ{10mZ7&)7r$h(FKCTLjSPJjC zl>PoY2y+;t_$8@nNjxWgH*ev2u{XCq+B|a+K+c2C&&0seE;0LL1*lJ>p_ma zSBK+)WXX&jcY#(IVeetUC50&xx-KK9)?7?F1A`>t}Gf0l?TglwoLi7VEnyvy(>;;mF`N-sSP!T5aXQQ zXlhO>EuS-T;!1GMm$jTB2a?adn;UvWu2W;Z7)s1vy+PJ_7s{tq#c*M&CuP6Q%7?0Y z+lRLHit<12ZR@%ZA5s`s#a%5k6uo+uy6YqXZwr^ZeL zW9>n5TB`%K;Eu%CGp z^$jtedqqa~0CrM$_CJ^S@cyQ^DRpR@y+@tXNFyIkAhReo@0T*N5^+T}WH|w?mpg{1+!dosL`d z8N+Hekx!G_smE^H*mVF?=vQjZ-z$4(B+G{GN!P``F%-VcIwoS#r|wB7Vr{Tn8G8+O zXO7;JUKK05^PY5LER<}+S-}j&0#4>#*LLvnf(rvfhpt?iR3{ zkk77qu#<Jo_i}C9H@J;X4>(ruB?+* z_WZQ9@yqe6YUAn9#)&s9)MQvEYX6GD{eg0{EMnqI)&pe;D-o2;8}vEm+)eQLMT_4+!NZ*X*xqXN;V+eK9lJIQ;LUuq?>VWP7N%(KVDgY!DR@81oUjzFq z+20oxCL1e8u_IIJp7~Z)@Yu5#ZK&C>qIZ>LpsvbuE;E9+X@da%{F`xR5Cw>QGOt-n*{ioUo_2XX?7 zlW|i)nvtoUgX@QCcWm3XWBU{VD$o?p>)N|IJ8tXgv|%kn=LK62nEc4=i}2u%UOHq< zwxX|V9c-=d?CI_7{|MlU-rmmb_@>*ieanvX@^D@t4%=sr;JU%qe#{M;!WC1A+zt9O zrVkU^Rt)ag*4^H;W9ov=59tjZEE+bJtA6&hoqf@~q#Z)~(Qv#gals99NZ+l-x?aa^2$!+Px zml?ZMscfC$>m?aMJMMWKBD^-|~^b4+q$p(6Dml%4OAy7hSbH>!=ah8ELrNXTkYuQ}Bx2=IFY1J;vRgtL23l_0z8$Z} z3>>ws+fkczZ@FUyD^5=A8E{@n9W6smI~Y4T+ef|)Fuk-JQ-nUXay!DKb*ujV)nC4J z?A*==zC(MB8uaz8{T&|F?XBHC^kCq*C2Qw){bl^0JwxRGuALe?EVgEC#d#l8{06Mg zVyMIi{d(Blj*A#x{65Te1oW#rI>Fbv~Xl!SCTpDZU@V zLg(8Jz9{S%Kh9xLeE$ry&bJhkZQg{PQi|`Fu+aGqfRA}Vz8Sa_Ule3I-#j>QEx1yO zkMoIizUnnz{xP14ug>6GnuXm6Gw{U?zGdK3>E*lx#kbAi`vGqL0Tnq1N3q-Bs|Q~( z?3rFnMR56c8GM5|neWH_246}`?`(~4zrnX>3ckGtUl;hQo%k`HD!s25d~bt~yN@cR z?#Cg6Zv=d!05QFoYT@#oHTbv}R|@V*$$?M^?;Cu}n(gO^e4JXL;x`{27#;Qeu1BF@ z`BX~9?|K850xqUN&{eqCz@V3_od{Rmw~K&N;dU5&!|=36<5S_L48Bo~uTWB|2*o!S^^RT+LYP9e%;BJ> z;&%aXdi*LizABCH;|AYy@MWrpt~dCq!Pg5O=AXWfe51j)9)&bhIsJVDmzo0iCkCzu zxJ>!?kP*L8Exn7h^gd(o4T3KYccoPR{f)u58+@v~ECE>EkJk*o?}1NokW<~?pBsFK zwD@rqq2j|=2H*WX0KTIna+J#rgMNRHYVqTIQ^j|Q!M6)j5~~%NgQHk);0^+Zpj|~i zs!jvU%i%pbpWgQwHtgDQ}Asz_%>*K361ZM4Zb??Whw_x z8MyVp@x7*$O2-pMxLsPf4FIcj{L0|#1>b}sb8r;@+29)j-#F}94wASOUkH_ne&13^ zL=)VVQt@M@qu;j;>%8~nYJe5rQiJbt@bUgCrTD51zFzRDa=Hd!#kaxWdj))%o}={! z-;lzRUYlfidT0v~@@1)kdu57rR0F4%mp8R=yR~p{H27WxUo1m927$vr)&$t< z*T6BpN-6W_&l5MA0jKUgIhFaT^TfTJ0jJ_bK4pF@15SmdhZ{uZ0qRR{Cfpq0$X!j( zP|TM;+bDnO#;XiCv$dmZZZ5SrP4uNm07xtT#4rh*iXTH5EtXh=Zap{ zJ%dr~t`Xucw8@oHd`ecjZvUHD$Aj0Zrb2SfLfj2R&soMdTb{h(dB~Rd*If(!$t6B) z;KLGM@8WqUJ;i-_{PBrMyw_esr%F>iMbMAW6SLsX=(9~3fIDuxTL%0!0pmBr@IOQ1 zUw|K5p>d}vuDkJv7nOZlhR42C0PYOW8&A+{P=;4v_~$ulLU{R2$x}RK&>vor#6Rvr z^qQCavkg2>VFT7{N6dD8(!hOt{QSid@4eT(oVW2M2EIh%PrIxf8SxbN?eX*LEkcGr z-*BHV`MgrWRqLMOsegVxj$n9-r~LWdOC_I|U!@)xrl2S{@a2a40>gcQ=fB5C0O0_ww@+1AnQ3ztnKAGTf^qpLajm!}nAWJ#>HgmrJ~Ne=hgHFmWFqKmJOI z_wxTr17B_6s|~!WZEbJdx5v-F$lzOIxG#}>9?KE~f0cnZ_vN|9aKA?K9dudPWA;=K z`{euMcdf)%xR7gI6AeM^rsv0BXQcl+1Ao1Nzh2_=ToiY2^HdPEmY;vQ5g*oSo(iI; z>&Jgg;+tFud%~UyinxJ~OT1T$#62)fL9D*_^VdlHu#3V=OH)Cdx9!K*Nxb*e*J)_- zCk%YTz$XlRy@9WncrQQe4Sa)vZ;*H|y$uFFY2cF*|B8!ZkJ3{?vD(0|mUu6f>@j*O zh;y|3`Ljmiz4Erk1H%-=>To}Pt;AQlsI{(%hM-ty;Md7-HGDs@?-zi(u7cu51An9B zU+RL`WAju{e8Rwg!oagf=Bc2#$-v)a;MwEyR8VX*@EaxGs}IEcK(!hUG;=S_5 z9+RhnIG@R%pPLOldqkcJidF;PD)C-;5 zL-Kvy!1Mc?QgnaT@!t$H*M0xekz-Phi2r5aqX9TLivG(W6Y?gm0<^zt4fhR(yv>lg zkF-+cQ{S1G4z{Lw5fm;FE%MTguqmKK<(!E?fX}G`axNnl~3k0?xauvh-wILT^d{!yCmqTX!>v0vJ zy?l)$v*%bKE)_Qzc#cyO&o*=cc4fT7aKF!SXa9@)@QoVodky(H2XE)!m15i{SBv)? z*^bX5kq-mIkIV3vh)d|;D5mEsL#{F8-!N0C1> z-1&W8DdJx=330hkzDYDWGTV3sXm7PUa!ksf6vIAw zv-p}L+xM?k{EZ{C4PAit&JoB;5%ZSg&SF`B-SezmJ3e_*-Xbo9tQ7H!9e10*OC%lH z_TMeGIC2cw0=72vO)k`4B9kVP>yzfZX^NTVgl9&|3618gH+%ZCKH+Vuxo(rDxoK2t zhFk08$!(M7wds*Fr|#F>n5f0!Fg3Sr+0xl>PrF^AD230l=8nP60ng3OEYPj&@88j1 zj}5*s|GDk9E$z*i(C2J*DV>BKytyU-yKpvlwr;KK9K_^f&~)F@g&Bpyux{G%DaW>^ zbx>h++R2LubXRlfK<)YLaH~{kW}`2fnuYC+@xGyR$bg}E`ERR@%PMpyZ!v|P*C3Y@=hb1HQgB`%aKrXa zw`?BhzOz%kR2(~B1oZ_NHmm)F`#_V{U`S-`>Kix9vzDED!<1JwH>}y*+|Ak6^4u>y zDJmZ`1g0(4(0xo=rlC7dUYw!3x^c-Vp{UGDEA;5dqF~=o&DgxYVY73yY`2!qTe=6ZkgTD<$5C6^q5GM< zIz)GMOX?K9on{6WxlPJ#yC~^oUYlf+E#3@t<$92T9a{!J)!N@F(aLg?2emw8l7qJ> zM0fHn2a$8VYTG&!_$z`ZLt`VO)dy<97cf z@@QO1@J-|=_BYM>FFNwy*>kTVe~)nK4!zOQ zZ=iliaJr%Nhb^#01mENDq>lK1jyiboF9L^!091ymEqhKG4g37!aeemJ$IV%{T}gfFQEMqn5iTF>^4RI(XmJ1{BjyWIx46m@M`L? z=NDVzr9JQq9s8x!5n1;0BF6-JV$hEZajWA#L>+i}f57t?rHp9qK=`(;fM_ z5KJ%g?I?Bd!b*n!rlX&R&U|3!lKB#H?xRcx;wRIG@MJm=UK#x%Ju<#3J>Zq`Mtp1N zKJMHn;MY@z&VC>7OO*OQ*>mqA$n-qQ&}DwWK1TUp?71KjL{i$n=InF+&yM{`hvzLP z9&gzDU`F0{&LP76k?{vk#vAtY$&2(Xr2e8akH9H+^Z(sR*D1#zaMB;rEz^tqtE4~Z zS5Tj@%P;e@nKIHX(+T@Opp0@T@6WqJp65Y-57PcL=2SWP`)`m{IiHXF7pD7vIQfnA zS3?e*b@qh(wUGOU&i??GQ1kz{lW(|bMUW$wCH@EXfF=Ia(Z5d|WS)pWz-O4)!-Y{(7LRcS+bsSc5Cv{XlcD`ETvy_pEGJj`TcK*(`?EJmJ5)acIgNCEj=Q#OMVu{Bo z&$Yxp>e#6F2h=aL#19=^)&~cj`rt=Seek?fZ~fG%w|*?-c`NhhTXLL_@mo&+CHA-{ z)6Mi##=q1nsh3*zb9AqBe>Gj^J7nVK$0pw|nUAQZK3^qlq=?Y;BrSs zdA-u!3N)tFN9`4Q)skzjvauh%SLiZELfb1e7olf|q}^}DPhe!32#kCT*Utlik+*|^ zk>7*42N(4>aXn`RMzGPy$b7gj#Pz4RUI=85To)E;`TP7R_PJO;D|_V5Y1t#6&CMQp zJ6Ama80>8K?2%|*_Q=(_wiJCL@crzO{}EJ(2MU6VcRmsPc~gJi9gjw1M+^FVJWp)s z70+@XjirUdC+78uXLm=#@kfiIO9M^yh2jVGg%1?vbevmSUwHqMZJ&-G4fn0RLwvvY zj+|S?!BG*8XOBEGGZYKpSH|=y$l>S{!B<0l!ih)dSazRvv;v_%W}Q2l*T3_?sv&Wp zZs_XX2cqGl*?rrm`KV7Ew%gN#S0Fm|G(k8a_<`w!F(9q0|8_+I~`h2az5=?{W` z#A15I^Sgm%XyW_9S1bEN3&g>^wTzDlmllbGMTlD{8ZKX&pI`ZF{AQ25H*>{h>t~f- zo;~vOX@QZ(84pCQ8-rJ^ZMNo!QR~3n`NPMG`^3|E&Ea@aG*q3}FP^RjUs2Sm7Nbm? z3{{4&QXrn+gE;WM*o-!csm$&VA4m;}XYdr^K0X-ao!LEe=Yi&-wL=f&hmM8%>xb?? zP&1^Mvw>3gk7>$zHPWx{A6JpVlzM{#hT${pl@UXBjHU6mu?jTHVs`euIFsk<5X*)DC8J-t_k z7wHQhxN9ho_Xh~`y0Dez-K)VJzaQoDJ9)S>UZ8>cROY;|= zTRfvLzH@C+_Q;H^6}95Q75Q+xm9}f~)YCSn2lh{M&m%ku*B>Y?%3l;cSDn`vYPAZ` zJU^c9TZHgvBU~Hn7@zW?p^%JgVB}zS_DI`- z+U9d8-HYmSQetcL#5;YV(sO06_s?t+Ulv~yqdDz4?beA%->xUx?_f%D+EKT_XZ}k3 zzPKVkcp!9aet*uQ2MWT+!Ths={-WN%0p`K?XI3u@<5^^$0sG^u1J;RxzS!{@ebM7@ z_glv!eSdKv(p!FfydSPFcJ|6229lxyq|0C~R;Hxa|yzzO? zIY|zOKu#`d1dJyaF(Tk01RE6HlM9ECpo9<=70b!xKvF_-azPJ5YrNHTtF0E>Qi@$_ zZC|`~2|_ohG_l&&?G=>nqP4quTX)sg{WKQZO|9?pet&a$o_QuGXy5h!-*@{CoXj)x z`^|TLbDw8sp5Fvle)TNRlJp+`&x5^Id1g<>=7FE*_1r(aDal4>WM$4s-}Nl72^l<9 zKPn5=vC*`1{0-!v9k!}wyxP(e8f4FX50i$_Grm`6_99n$s}6fRCW_xIUX+)%*?Kj- zCw---K4WvnW;RN7q9XWg$n$Ct{mbdXuVNfX@7ZxUqa#1)*@Z8$#OM$lI1%mnEk>4- zne21kmS4QO3u(1pDMS6OKxzRaI84e(XSE^jg6i@js9WTdHX#fYh9!?eQUuJ*4s$qck&yMKiTIU z%+4*z4zHQ$N$-r5_=48D>{8Z#I>erT5G5c+C^kG0vMx(+DZHU_9zx#FzV`xXICil= zqdhCUekeOHtK7;StxezcFvg?Lc)h;}_U1j!o=<=axxeeuY14i|t^LwzmAT%3rl&h* zF!-eJI(z2Y{R7Xi&Ebkb4|ve~TsD*KUB5pIqg!xrC_AHL;FSQzzX9|k{%oXkFZo4Y zA&k;#>^ah6otML&wO$LMU!OlMf;Maor|+trHvVd6FM81)4|ml*%bq8U)5BKCM}5t5 z@GW1L>n~x?RfMTeW#45n^!{gsmsnfYR9cn!xmHzaF6J7;XD8Swvrr$-7vsA~{O;v**T7pFW*kG4pVCq;%iFFng{BDL|P#Hx8b>VEFR%9_r!Q z3x4?5WM?;=4qI#Tfr|r8Y%Yy4JjH35q0n5Uy7jk=EsD(D2lv~8R+0?8T?oo{Npa$2 z&jm2&rg+mZY7AUd7`gi(~u96_~3+Y}|ksa~p$b3cau+h6@ z&al1V;Yf1EkoC%Yy_h+T_RF$^X2a8kOY?(oqny}x;P@@M<|H3^Cb9kM?W?!5z5d~@ zn+Mt9V>J1_^x%b>PNqw4D!r-qj&0|;@ioeBzblL+Ij z*>~kWCpLPWzGBE)dc~vu;cnD?YoaO0Ud!pRI8y#_0`uldjG>-g*J6fqFXq6Mb4?h} zPcO-6IbBA%X{}pR>f36qD=eM4mF8X;S9?!q{X-&uxECSWD6gsLeb4S`z)Y`e27BJ$ z;*ZSVUb>w92YJFzI++KgG; z#a1hO?sNuf&*j#|Y?Mw|S?d;+`fpAfP97;uOoZs^#UllY*N(gvO20XMI4>~-6coyuxKx zO>MR{jMsJa7D-U@atbk5r_w!eKXZ+%L&)$-noYQ5`7yaO73YCXJasIK0YV&XNLzFddXowW;LVKXHy$sdw=t^aQU*c zFQYkW{^9;@qW`)fD|-#~Dwq!=RNJ%Zot5j?%%@Um7);+afCFtbM-H9H#QZy+%pdMS z8T*Gj@ji7!^7`bBsAZ=j{zx*p4Nq?)K3_1hFS?J~0*wIwH1nzn#`Ek|`zBE5&dt1XsIv0PM^7E@+t!yv3@=Oo6Mbf-KT?$7b7EHW zSaBvjO~(^^AqWaaJ^b}Ovu;OP=Jh)=OR_RAc|0w12=4`XJ#DwfZ=Ex|Ex8?X(%;yQ zQzezTqP_HPUyJsUmf4<+yp37}nR$p6esC%u3wdg&gS(F|sL6Xa# z5b;;$W)?T@h-|kSE}p;tw=tt*EZPEL6JU>T5zx-QAsip^e?Wp~}XqLd&XE{V$^3(7YvUC@Fn z4_n(qq))D|qq{3qR#skCQE?NiycFG3bG*5wgIV+Om{tuHTJhw9tIApWjEt+Mc>?J< zzC7zJ>l|;sb*?qbnr#*MiY&IUZ`+ps<`&rfy~1u+Po&;T+|oosS%-Z;l}%44o#YM_QvLlb@aX8^m_dyxKR2 zp90@UcnI-F!tpz(z-OCL@Fi`Rh>M)WuhKy7ajY{Rg&n|eI)0Q65*J6uC|=uOiG}@@ z?Q-xmFaD_HA;*XD4dS`32vjZ$PcKVjZhD%Fo4!fZjhAKcy(01>q-^}P^B;-M2Af^q_Njd7p1;u=_5-kK~T?bmY+>ZFs`Kjg1vV}7my-H-cX<_)o;)u#r+ zvl2utZqHAWF6+^sevFN6TEb&E{}3y_Z^9G4Z^Db8FFd`_Q#`Ziz6r+eo3QXphi^vk zzKLn!X@&PqWQN=|75d>X$A)PG3maVJR;>&R3;)WJh(g}!LE z&_P`ohzjk#)9R2PFb4V%b<&fk38FY=<)<%>BU z*Wu0c;)r-=rI{n1kdlV-jSUh#G!Wx`4cy3?Or8^LjD^Ha37&fB zv1S&RFArniRJo!2|1!src&EIAv=TRn^TR^oh=8UCv5`pfXiIA1q(e529#S5-Cf>4j z6Wvw5HQv>_jcz#a?P$|=fO0Nz9!#8}67ld8K8Ctb&Wa-i)ve744zIjtT6`AkupMeh4Gf*{BBaVQ%E`X&hgwRb}yOc&-E-0N4 z;9j;?O4}O;2TbV+V6ykhuKo?sYK$|mea-#xXm>9^29_c$QrAxh5V&qhcZ9CfAgYYH zK20uW6 zH}S0F(K!O5DWmWngNKe+qv28f3J*sYTzJ2eG+5jyJREUx;jPl}XiY}pVS?ep`-7yx z;zr?}f=idLNyEc*&c?$L0TB-i5bb!=r6$C12RU`;RH`<{Nlz8XnbG zh1X!<;m8H2frT3-ADxrZ)7z=x(HQ`R*Ja?PPl5L_1Fv7h%h&KeW8h`NT_Z%}e<@xv ze{JCH0A2|GRG;ZAgOcy71|FrK%1arAH*E05;7(QV55iy1mpzD=@F-q1c{|>p8hD*> z>+!05{-J^QgqAPoYk2=^;O&50$qqKVUj5R*JE-9mYIxHj09ft*bO4T00+L3_mw^X8 zz0Yd-Tnt{7&leeZ`+yf!V6YY51qR-0TK-+2;nf;=t38XnC7RQ_!@@a9Z`cZ-2nqT$hMm%_to7%n#~ZbHDL^edyDzaitLydpzrr7 zB|iH7E%@+1p-7~c_Jgd!ya>J#C4|Hx48jD-HWg?@Aq@Cez-Kvrln!|Dve1IFb?B7$ zXiFR_9bk1C-T%W_gTXStW_*0Dh~yJSubGrj=~!jaO*-eNzE~JltA&g7K)Lym5t<>r zPi{KRWE?|!p4@bOgdlll8g!azIEM5#xx+gtBQDa*O*q|31^a~6+jW~`Wy-9BT3yt(#=rH5SixJb!uaBTapJ&i%WN?fZr+eMu zsi$|07pHgKbn3Ys7^rnnj6|=+kMu;WgslwG+mr(~x%EDk z+ynS2L+&ps2W)cxEq;XGh#%>Z_%3W^i2h6bh)#7n2dVoH>87422fpVMQ5xdE5^nMm z^qFj}K_~t74n4?{2K|#RdJg-tK_7C_^Vs(d`aikoXS3fKbehkRmyj=?ou>^BB!9W2 z*Wj7-OjH{5Cd1t!`6(>viMUz1MSh*f?lkxxG~D}L;m>DB4Ej$bUC3L=-ZJQF{z5G; z2kk#s8^lPaQp0_P;chhCop4kB(A+f#n%eI+==U1#1Cn2)|3Y?Dx`n)@>@9;o69gy! z=droOC=FrMx#;uRMuV>OT$6VW`iDmh`uAMn!|YcE{aqKmjLp)cB2$KXxzaGjs00VbX%G{@Kwa zBA0cFHC|3T)5@-nEHVOLvpFk_JUryB)|Y!5qqUWMJ=N{Ym$2=nUy+?^Ay~*^EdL4| zb5U4CNuTFxE4ui;j>kF4n<6#Vg$1kWNsJnxSRxjzlf8+VmV0S&*#0X`>F8A zYjt01M`vdL91E1`+cJow`fPuAd0lhw7J{WTo%u7$6r55cLQ}W%fhCvSwJ!DMBp*vY}l$l!l)`M%_lf$^OCB^5Q3UG2rcb>R{8YCVT72UP`-WYAHyt;-Os>_>( z&Hx5B>gPQXF$chH*LZ7zKPFc6wh^eqcRFNap*l?VDzX0NiHJE^;A$C8PQ(hh~SU-BZCotjku4N-vdA5=M-@h zI!@pLRq%>u;qQ_6*76vD;XmZ#X8_>Ft;;x(%Vj~mI+RzRx9Zho_sKgvuO{-_iB7-J z0R7FvIRMC+8yK2V$Hr#V<;D*Fkujo7ug|QT-QGQZ8uEJHVZGBMxiLSF0jC5slaG7J z@v9-P{DiRmhq#Qk9N6`zRM>8j0^Aw%*7%CS{nkFB)zr^PzHoBDH)lxj?ik}CCVUOJ z<-G5qs*Gsg(FL=fJdpNICYLWg`b1UXOTKpk(_Z*ZS|A)<8TCB&;|c#>3g!9oKs5I- zxpqa5O!$KlURHG1y(j9cSs4vS{UfaCkpsm0^EWD@-bd*v^TIIp@;#4vzDO=#G&tn> z^7MvxJFm{#_HtKlSK94&jt_XBKRKG)da}|QD7JcbZhUAWC+ykA7Uz#x z#jPjt8Botd6WQTv{7nzPbO5~GR^-Q0#y9grk>n>B8Dy|9;#C zeGl#_=EfhfO8rMYr8AFZ)X#2zH7)Qn)Sg7zm=CTmr+MLGbb@0<+;bd0bcg5e{kYBf zXB0=V_aoe9rHhZwuAjYf{pMMlk4@Ygj1=#TSeHL{^7icA2hOSYUNpNM=R1PFcUaSm zV=VNg1OBB}O?D){-uI|gV}<>t)WRVmX}Ci@6!9G$J)ll{1dmYLp=_csy!D)J z_5^=+A+K+FsIR+Q@{mv7@!P7OdWYS1?y>B85Ae102 zKflSwr+d<;v7+p#70MW6MONXvZ&*bPPubBR)k0pA&Z)lYcIf3yua)JoQfG zw!))num^5C?F)o?&I=~b_b4nxV#j9u-nVyN6WmRG&*sF;;oQnHnaYQ_V1kZwj4X(b5U9p-!aYe z9;1Hx=iX_@{q=?IRQ4?N@F2yEkL<_1C8fNThN2Z5hw8$Dw@$9WsiD$akB$yL_(yM$ zc)y-}aDv_6np`ksT~WXM-wvd|Y+Y!LJsMpd{Xz6gQETi6QR~9JgL4PJ_3kJCK>RmP z8#vJQln1w`pPskj-8=uo`;O(cUTO6I`y1azpEd31>3Qdm%zWqc;`~aq7w@k8{E<5j zl+}M}%j!S)*ryKMUKOtOkF5Sfnq>`Gh1R<>-?5f{DZYB#KW(7!OPhj-GcZu zy-m)n*og@iEK|^O6|;D$P#Uu9=d{l`%yTM~J0@CUa7frV{R9rH z#1ow!We*BJR{G|#5WgQDJssK+gIU#pHU)G3A#ZfuQ=Y-Pr!ro&p1AAH40dj^dFaSQ zfIam`e0};S%k$(!AoLJUnl;X%^JaKr7V7Z>k=v`Rm#nfszVYS3m45aoZ}zdsO9!6B z2!P%VC(+VEIIT4%MsDB!AU}b&;H`;jUo`*lkvAu*AtjwiLoE{$vyy=*l=xpre$%5U zpF&aotoTb+{*lP?z)M64{+`|TZ%5gI=gzq_e|4o*{>B^2P-~asM*3f!L-c_I*4XM( zpNKH@S`&9x96GC>;jCU>{qByu`n0G&DsH&8)S{Zkm##rR;==O^*R`Nt2<*ydSq z&;HElw4;9B^IWhEN-LvTQEDyL7^S^FAqt$4_Tjyyp}nKb^*d zd}yau#pnS~>8_Ei`e5Czk+l<{;LeW05ms0{9$P!TdS~-=nL~lP-0tG>bZ_;z&zrl+ zUypg#nsZ~m;_pn{73Sj#WkL*Ry?K84BM+kQ4%DY(9Keh^^!&tKY#N1WoE7u_{=K!n z#UkHVkH_Fcd6i%^#_(`8Rz3CYl$VeXC8?f+hi0#=PmZ39cv?BCrZ!ids%qdg~L#$r!MT z6Y2GkoR@$YALtAsB}tiS=&PSU>2391JpE`8qiNnqdR=vLD_hFk;LRpSv)^U3e$>`uH2_h@!AW-!6=*;%h9W+fq8AuDV?S?QUT zD1tndo}xs0T`(qQlBwl^3|V<2-a2ocr#LspOJGFBE6-h`jP=u)$W7kwr=gB_BMzFW z+Ot?*R}+Ua=THsuT!gVf)|Ldd;L|heUrAPud#qOyX;C57G?Ys?D$cbQ@p|ZsidJ+N za%c2Ff{&ph_e8w-h8^vKjaea@k?{HlGSKZ4syGWfFQXo3I2q=S#nw)1pH=L6z%8X{DNBNc~cMBmC#GqhiO13wG3SI-e?3dJgp9C@=M!uim0 z(pOoiGwRlEDL!>uE6pOR$J@MX z<7gqL1`xt771V!9Z&J?v>6ymEw}bwu$WuCFOm7_uGtETcc>?~L^D!Q`^KxRli(=O9 zhj3E1CFa@vaICmb_0uBfNY*rrG-=T}L-cGF?p;wzqcO)q-^SZ3i6UfB(w@nMo)PiS zh@LG*snS_|<~g%If9Qtxobg2WzaP84J$pRS96T04Z#8`=6y3F=U}#@^2XB$3$A(4NlC}~<#yDgAoW4S?>{s; zNFhA+k*a)@GSyT1)?UqLviRIKYl>OTm%VAnL+ypz2tmwd(!gIT#~&I+Fqe)}ze{s! zkz>BP+;*C!=Gx^h96`z5InL^)`;U>{UT1RP=;%OCb(RWas6(X;A8QnjW$x}L= z=8xeodp|l7sE?pGr(WFSY2v-nO0@SXHczq2Hl_n|gXoj$NMa7Vh+C(o#8QznHq6z*!<3YOar8zO>2Fj!2 z5azw1OrG|;s=P0YaT2r6&_$SK5FVwFxGar}zh&b+)^c$L4}B7EhZM%*Z@s~~LjG3k zey1(u@3et%(Kg>M=dJc3ob+$)De9rntT+_=RZlu*QR02Xuk{%FF(Z0#B)_^EZ>A0L zhApEfr}J{9{sHS2A0xLFM%v)^*Ae&HkCkFgge9oYu_~z7893mrUfY70Mu0EE891Up zqWVI8jz{(`(p|&zXoTm%h`-K6lSoSXVA;;lGzNAmgP?y9tC`LRec$Y;M|Mx4Luv1D;_*5Q_u4CA+NtQuo+ zF@O7eE16T5b5(J2&Ee*gcfc=Jd~qzRK2msYjK<38;Pi3dT;4B>dhG#^8fh!=4ygJ& z8pml|rFw>6l-_4@#xp$D(X@HF$HIqiXfJ}RYCO$z1JdZP&nVje`+*IZQPTQTgSWn_ zV0Uw31=d#*$N`4$?SM!9*8h)&mKSNeIb_CpK6zkc*EjK({nbNab3as>c6Y^>-;8hT z>@)H3rp<*dP_}IPs;v^ue`7}{^iVc5_w{L>9HO#?zWUQYPe}B}o3}udrqIspB5fq) zobV58D9Ue<=GU8yc5LjvrmIct*=Q8L^4%C+yZq|4%V}S)vjrQ48a>h5-M^(5yMVp= zw+X_RfBJy!G>yHVN0cJL*ni}^IkX44N&ia0rR7j5Gjy`Gx38~5Zgo+fYf*_bRd#Oa z?(2_k?ZokTyDWqhg0y@~qF)ysf*_fV^j%5cr1G0wti4IvYa(@w4m>_DqmNRcN3;ut z*t<0WBLDDVYhSz=&p*A4<i*HflZB5-=39yrJ zK}78*b;sS!dL`xc2z8;lZ;M_Zls8g0DH7WB(|2gic+5Rklg@Kk+XkH!0g`+svPPTq z?TyH{*7kVY*3LL|i)eB4ZB|KXa#467XojVd*F$iBv5nQ3Y;3-zTB={w%SdiWO-Wb5 zbzRl2^0Wcm9Cn)!W!IQQofTNF&?t+>cECy zN=oC#wfJI6?}SA6DZD2&2Y$Svx@B?>@d}|Gq7aST$q$oGTKDzJg1o@~H8tK2Sz>x? zr=oNb4Pb<>iuX<-6|cM?yX!m`h!lXQrXUkRK+yiJlWPy6t8T2OBwkD3Fd4!iX!X|K z-iGd5;=QZlH@gd8MEgNFRDZZO5pV6-*wI?uUfmwYiI=KL5mG9e(Djp=?i55c-RkSk zOkdki1M<{7kQakoSBj)mZtd@`Y~8HdpOF=kDjTw^z$MAvq@N_XWSF8*C6&5tal^z^ z;Tw|;%^1X{CS#+2tNSBEUPdy4rZWd`N~+*mb(KNUG4=7d(TXNhn>1?bT)U<(-XyQj zm`Zxlxgh^j#c*A7M?b!UYjF>cV%>k2=FqOw~{3-_NQuW2Tu8jThNxuYw_Uq~Nf_BG!eZ^Uf0A>P~3E&F<@ zPNP-Mo2l~?3O1_OUe{DzyKqq$Gjj?|6K3j@x;CjUiRObR7{ACkihgWbtckd8h|mz)D}8RXqH zv##cOYl>M_{e+`KOL`A!=rQ13h%3U*6|*MJ5_ogGVuB}JUXkT z@SZjBc29vfY~bzC@TmM0-cbW@FWjl*`w{&0^xmc6(HSy@_d1^S^nPOsyfOIec=u{} z^j(0$Q)lm$OixUK_pX8WpoT|Z#3($d#dgVeUWUI`5N9_4ez%G-T>UG>dS8oyk)?nevRZS)$r7}9SVaq z<(1;6jLJVR60XZv1H1&72yY&KD*p<=N5K^yeXB7aZeEr@m29>DU9l3KgluBWK)*_cblvMUs#5 z{dObXW z;XP{L9S5NVbY+N-41F`Im+u4!RQ}3<%*_i%ymuj9RsSl$L3re*^3?H4@NGyNM-YEh zyzdx%gW#inUKzzV6Zxv+(f6pS@B-k|^W|R1R|+u7mu2`79?5sHfkzd475tS^@m^@) z9RyxJmo)MpHM|-PZ>NEm2|VgIlu>we*RWn5%YaAqgz_(npGxmj2Hp79(oWxK>3C0Q>8%5^lJBH}_udqEzcugTbw9q> z;9Ca1RQ2FFgRgc9zBdfMCh+YLN#K7$=7zqt)64BWq@xrRO2_s15g(=Nw1IaNc;)a{ zM&Zptf2Y?MACxAh%D;T@>G77}TLu*`@vC^%w|(fQxQPL8j(jFd#oJ)Sy90a>(Kf1{ zt}^0Xg?LrDZIF26{+NOHN#N<_q3|{ucul}l^|V>TyTibH5O^Wbl~L*Vgn`!vJk^d` z!L0J-Ap`Fq@YX3X$w$sF8F)K@7lA*OZyY~`cgVoYL}F9r^N@k}td`zQ8s0GjuM~JH zjbO9;jUO9$KLVaAj}8s*w+7z)De!({;2qcSHfwm9s8D)64NrmR2cKR~U(@jL*^Zrm za}B(5;8A^6My0*TzrS}I0--}c5{l?&XbBgr7VaPXMOE0q0md}rQl3xGDfv3+)lzcw$>GiK1 zcoo2*_WN-Suh_tgLCHZFbY&FY`37Dm@IqiByxZ_o<#C09cR%omPZ?FdOAWkxwe;Q& zW`%cyfwv!cN+!Zoc-I8F;S)kJip{g+JBj z2k=wrjT?CFzzcz{j4F?218)u*naaPNU{-i{8hC?K;N526&DZcgui<^gz}p8ridPvW z--y9C3_hxV$|$~PjChwJUU>0**#%pr;}-_rQQ*=1RT+i%ih)-HJc^g{c{hFv@3ete zl9hTM@h1asy_PR~G`s>-KE0ksrofv8KE0lHYItAK@UArQ)=ze&jkniXRW` zx-qW>-(3i+jFOLRU7okA;ZelcE3npqNcDy48PzG3cX(uP$1zT$Pf$kTDYvq9{|`eq zCZ-#jQLRXLkuFR(J)P@wK~<7Q?_nuDeuJNCl4D30rW+4~ie^X`rkkG0Be;PV{)t+(v9h+>n)tZ=NNQ!dYU2KnC|d->@3i!3@GIu*A5fmoo(=+4Q+2aKb;hC z4C&5vJdy59H+_~tpJUMH;6@caJ}2iWpch(r+;{~>c@`M>A%j1}`BC+y38@Ee zdr{Hd_(hz*$>u^s(2N&5h;IH8RtGxeFO`(XwZlmA&o%hxvKw9e`pl2`OAY=~a65){ zX}aT|$K?&#jclI7j3?5q>E@r$`5n~x2LD2Xe<9}|w7C}APxL^#H{JMQ13zr=FEaQS zaejwuk-@*%;9t!7+ikAJ_7gpLu>EhfnGyan9zJGsU1mQC{>u&i%Q?T(D^Tlkj2An-ZuyoO_{$t- zJbAH`>*l|b^Vis1SK3eX;AIhmKO*?;`WG?ys|@}sgI;6MotTNyi=9%pd{HBOtwFEl z@~pGDYV9X_@S?T4@#;9gQ-0K%9plB$xSM~K!N1C3#*>#_ZSY@h&>IYTgF$aJ=#4x+ zr&nw=_?ry=CeH7q+UdzCpqE{1@L$XMonGKt1OGaM|2iZ6*BSil4E}Wnzf&?op6d<% z>p6eIMx`A?$9U0uy36B6&R=S?Q19v(FLnyu{OdWtlk4jpW;}V>M-Bdua(-w0_^83Z z!QiJIKgW1kvq5imh;KT-D1#b2gosAw#}e#VD{#y-xY>sQj%eEW*+ches_u~fr;~dXv zT@c4!>qWw#srw>v~UdD)!?{Z4~^w?V(#pxA$pZ%ePJ@4^k=~sK|K|<< z&l~)-!tWR_G-3I?|&hLybv{LUFFWY1A z@8SGTf3wG7#*>$Q#o+&n!T%M5f3Ly6*Wll4@IP$uKWy+nZ16u~@IS)&o&0>n;QzY8 z|8;}^>jwWf4E}F${)o->4f}~6ylkJrzt7;`XYfB}@IS`+gErS=_7gpL+2aQPF*90{09yGgPh+P zUk)1lhYbEhMtTkz{NFP8zh&Ul%Ccj;Y}nu*Ht>fXW;}UuNwT|r9ya(78~jfj{7)PF zPaFKt82rx|^dknHR)ihng=!GDd?QBsM;vB6dD*DJKWgxg8vM^0{LgXz9X8i<_7gpL z+4Bbf^PGQ~&Go$fB=}$8bjR}rre-KUcv|cQhlD3DR&?DfEZ?=yymfN^?;8ByH~7EL zzl$LzY9ki=zQO;Z!T%!PVXTB zVaAh}{m9_|5mPlp@c+o*|FOaUW5g(o;Qz6~{}Y4%C+syB|4$75pR#wP54~bq?59Tf zpBnr}SsF3I2>zo6|4~7df4%IOK|jXm?m99a{4CIQ<7F=y{4cQ*$uH9TlFp9&e3>nF z$@8)i{$+#zxIsV8A})E38~i^r-2cED!B0Wv;750fY>?rJk?P2;hWm4d`x|hR7xB_v zBL@un4vyidy;_Hz)h(*7HEe8l^x#;;& zdkAJ}NTy3&^jU1VbPIV4n0YtH7D=Z$NDd3JI}AMf?m!vBctY~`<2eWGgU=fDpBrxT zE{@+D^h|BhobZbc_vMD$yo+Nq=uUo>vTX+c1CmbPxa44c@GA!WpyB?J;eOq4ziYU2 zsA5Y)@-H&nD-3s+;r^uI-UT1~{T8M{Hc^SJwRw#7wX#s-Y=I}JCTdsK$x z88O_);U@W3;g^H;#D6j9e~@(gCM1VNm>1{Clp(xx4fhhmU2C{o4EM(k_h$|F*Wo7l z+VRU_RcuJQsT$>A$N2jO|Cr$(m;4FNA7ymTO&OB^9K$^yZi-LzAGNI7pszFB>Ks`n z!sK9m@>UsMxL2_UqTeB+WX;%{dEVbEt$Kxv5oQn*R}5PmsWZ(AYV>$p44t}*!OoDA^` zc{Z_681yenx~M-L>~VwsJr{j5d&QuibkVmk?{q{a4aqwTZi>GYzZ}-hE;Q)nk}l%! zVO0iwjil%E@O`XJx~W;_u&wM?ga2+xpU3I9u-yjzF~dD=l>$RwzFg z=@Id7XI?5eX(+wcMTf!FBzc=X9W{CI%{cctWw=yK}Vo49-IfvcD>J9o$hC3noDViMiDYjF( zXL9$a**6S+I+sl874-Yq4-ERxUG&eg-y8G*0#bNU{~utp2}l}}e}Un?%y6%f;X~lf zVLMse<^DXoRk{f)2kTQ0NVlkuyV%#IyNT0xvm&J*A7Ovxa(|s&C*2JQlf%Bj5-#^Xc8_!mc^_kcBi*9^dYnB8w=xvR zcO+fJ_ays;bk7AXhkcX%*5%$WCe{*w!UXZhDUSnefpm-Ze~?9`n|O2BA-2Iq{}xNS z=)>#*m-{e#(&c`d{Xn`!dwhny>2e=o>DfY_`8>W6mhWdKc_#(E|=~a?tb2V zQH;6+t=CXsDD-ZbY72$lKU@2t2&8EU6m(rLprO>I)mG%9DR6P=ZgFdDF?6+NYK|lZW)D_4PMz zNyyv1s#`XYcBj_Oaa<+_JubSsODYV|Np~G?rW0zwNCzS3u}ec!dC3V%(d8udmP&zT zn5m~ljLJZ%p_I`G%s#}|J*^o=!q>@kthzm88Z7iksNj;0W9y!t(#&7td zT+r3snA$1zkV1^=8ZzD--_K( zretRr>0;7rzgrh3v8_yTyB{wtr5Te)(U@En@7mPgPAY@0j-#Y)fkX{yjJL)+Ziezp zkzlTluA{Stv_|r9iode6v%3|l_O6O=>4tt$iBc8c)X~LtXGwoOS7iiT1!Zl#GZF7q z!IpQmyS9Cp7!=NRY}`f) z#w7E~<;#~>gv%B!Dc?X@BUO@CLs1eGC$UtzL{Sn=Nn3-cXcJOzsC`{ub+uk)YgVq_ z(9pDUL*>>aX=YlzwLbyLZ01!}O`>jdEpA*5;o5C|{qZfe(RHhW!Na)a3>3 zc&nQG`lY5bJ+nl6YD!YI>+W&|;+?7EV^=KFZb~(P#3jA1cJaXNXp<9Zs9aH9U0rGW zl3W`$G{>7;IyQ8+b=)fF! znb6BA0*MCa(ibZTw&p!e)2us)-VI7LJ5UOmt}|8up%@))vBC=)8g0e0GPd5{?p|5r zc;0I|VH+wpRMVBCR3A8v_gQA|p*+c^4%My`?#l1nK*|G19kLEAMWUAi=Mt6MVNwe0 zCNV04!|G_2oy6>rIJ;ZTtY{HvXy}5W7SbV#EYQ@>8k~|M*pv=hrL)`akT*yQwJ4#^ zn=7lOK^Se-t&3Ka5E_WO#+Re4Y^=r=xdM>)oEihEplw=yRReKA10wDu-ogaG+r>*% zbi1aKTCMKr>S=9nM=5P%v}yU;rVYFaNX4?a6jpWSy`*fGw*$_#7HSQ7m#+pAelIcD z1=Vge+=-A}AvoGtYh_p4H3^K0ahkC@_)5vG1mN-0^v{+Fx96sgkS_a09hMS96|Nm7 z0iEvB+l~lBqoWqr?(ua$o?rkP3UbkS#5m5C=2D}vv+#_ZsJ*=> zLswBj&1NXk)mbIUM%6^MYcgr?rIfoavDTZTOr295 zrJh;QZOR;zeo7gpNT&33#(0;v>d<)ENLEd+F7Lvdl9=U*UVKvgO2e)T6ur36tLySr z+H?)iRIHlzT!Y)zs_XLCwdJ}9j*eWHx27Fe_$!^bdX}rHggbNHDsn|=T`{ikp^;Xq zXceO%+-hdTv)W-uF+w4iMPPfPA!R@nF%{v8_z)sB0U=UDsqxmW&sLz>qh~6jEra=1 zrkb~i&wRy`sqRyP$`tWFQRbA4+)-g`r%hL0OWTQo>n*-t8o0s28W7w!;?6AC1vgoI zpPFo1k0hJct#p41|Gw_H#L;Yy-!9?_d<=J-0msu|@qOWf&B6|B5&nTLi|bqpbX)uz z+5nUS()ym~N{g>Edg?5`pWvyn_&$v1B8#v0dR7Rz13eZ$A5qXN-F?#CFXg&f%8?Z5 z3v9E*{mj_Ru0T8iC|9KT0y`}BF|t2yu>rC_VX?m^8%i2?kq!F0WDfuji*7`pNjC8E z$iCfTA=sWui?6?XpnS3j{FHxKwr7F6Wd7f6u}_fulhXelk#0|g#dVAnARlRcE%4Ve zpFVA|OUVtpitKwW)+pUAunPudx<3PX$p5nz*YOv)-{Rkw1Rk*XH_?>ebV56TO?wI# z*lBUyS%C*Fu6vL2dk6eI^F{hSODuL5xsjd{*acq{`5E}KlzWd%&qK2Oz9Qp=o9Yws zg~{G)aUF62_+z<{1s=9ogzT?b>{YTKL8ejueI4P*#vuZpum1z(MQ+4H`AYdQmu!S9 zCwrg8YGHfUB7J0EZm}5QeH9Lvg2!ci-<0K!aFmV!++41|wYV-is(*AcJMe_8H*iyZ z4GhWph(iofawGrN!KQi_BOCRwoov+01lhT-l>G+e36dM}5?;Zpvi`j$%k>wse*TlB|5C>Lx@_mD z?+X!*@`dLE>U9im&%at+7b4{&$zAX-GTfW89KcWMC3+Fj-;(+D8!7j{N&B}l+&ePA zekb#>Ox6R~JRg29MhJ4g76#Tp4{-X#N_>-)^yJbK1p3LX}CCgReqFg9{sC{u< z&CS~(%1O0Ho)1u78Zr2(z87fW|6I49@a~p!YB;7p?*}0zABQqMqCU;^@b(hullcz2 zfbh_7@bEp-A2#>T@reEr{WtA+_JE)l;1CeyLjiEOjc`1Fj>vlatZe^tJfc0G z=V4tG9_7vZKa@8a&pMHBojj?Yqq2U+Wc|KF)?XZ&qW11-7V&tX44B%B zr&aWWo=p}%@8H=g+smD@UVciBb8WJIZj|-2L-sSBQm!&_zRy!EzFqcQBF+bT&SmV9 zvLzwiEGn;9x+q+}c+uieD9j1sFLcvidg-O1Q2COjWr9BzxNZ5WsAY*bDE(CX9T&d0 zr%J?F8l{DHm`hk8zdzHwFP?6J^B?lm@_Xm#)OE=TOWE{fXzbFda{>!XK#hrNG{Wnec{xmhkii&&V)ZO0c^|RXZhN?~tlv!g% z_$zL5WONIwyvI@8sHgathxnLhD!w$jIq}qZZuPHgs>MBT4wkrg(NmlpnudD>r`5eg zH>aOsVed#reXwX&EI*pg?>_V&$&b?gk96-F-4UqnHN;(-kEa!RCo&g!_IY+%#kjFF zOnH*V(|r2$U-oTkV#?|)h0FId^Zo~iLA|U^&EdScP0gb%7?dT-SJd7*=@t$rM!YLj z_2TN3R;-{_wzc)f`}%Nk!PMB`Z)omX>ADVx&*oi_Yum9VAmPpowyL{p(+6V23;dRj zzSgbS(Mx%|jVpeLSl!*-+t$(5j0KG|NKo0@8c+1|izD7A)tsjx-UZA}X8@$vW!eUj zcV+yg-3=kSNb1SZ-wTV61==wquJ?e(wIck8pMKE5gvtAc=Yv}j#n#bu((lp-Eir6?Z8v=k*)CPYaktO72LXf#7Bm{O49KXntU|= zE4=6NtmCbRyA(fV6drvQpyLeyFCTuCUK;-u-bp;`cz3}~=h~D}>HRG{bi7?!dTG9^ z@XiL9j`tPNQsL!*Nypo(;Zgo5yoiA}3>xLHGD^N>2HrjmkLFDZ57Ppde50VH%D=dQ zw;y<_zR)~R;eEltdvglB&lz~58XmnjD7^0&ctN;JKv#zN$b8$tJF4MPIV(I&n_cOp zcfbe%NTcvDjdzvDn3jK3ehM!a84gyvz4gOE^Gjt^d1T>1FW)ycJbG18c#9;S3P<^* zo(YrUBC}NTg@uzn2ttp1CX4v!R|P(=rmH0l?vD_IGzt&m5T9+9fv*uiWfULTnl}rh zF@_*KrjfkfP&%kyP+E1o1~iJ(T0n&dHkZ-;KMY+hdRr5@>_kVpTHJKiYYHCH&Elr( zEsfF_Fz5kx9)ePTA`JCZjv-wwZoEv+Ut+U3A<2t$wYd4IXK@VaYH`yk=N&`3THJJM z`Hmr7EpB?AArG}|$B?cTH~-lNKeb%PkggUte?I3A*(}sD9YeZX-2AgRzpCTzo|E!t zj=?Wq`XwakZqbdGov%9)K7@awolw1{Z&mcRLAlu^>GVwBqIAMmhWtLO9I(m#Bz{zf z1)ksawH49dkaU3;VAHe;Pkyru_hoRC7xl?Gs6R1-j%7pJQ1~xNe#*xj)Sm+`caXg# z-Bgq5TbFl?@Ikau@)GgovBg@OCH$!2UgzRJo82niRHt)L{$G^t2zSq7e`kb0D(O^G zIVjIJ4LZ(Yb#!j%h{xmdpiA$@4eiaH3)Qi{DQ5rru7Y?WaHg(u9o+FyF9i1D_tg7X zI<5@n;7kH`-XrvIw(l82PJX-Kd$5`})AFRXyFK2EGj$tUySp}aY}(M$j2jruoJsu> zq6-F&mB?uE>XCxrdf`X`F9N0@yk9{5{Uk-aIynWp`O;E7`S^|S(hu3B!g0UPm>jOR z7?X&sbG^Ihsc@g%GT!6Vs|+vR$-9AQ6_`(4B>I!U#bRtJn9sdg!9wXDmTNbQ#F^~C zVllT3V3CE|q2~h8H<3TJVe+T`sh~oJzfAP3fy<|MQ_oIxYMz0=68FReDzR3yWRY0< zk$>NBt*8vmSg^kTT2a3E4#r+9nt}0l{Cvy$EA-N*U_%t7!(!IJSs1A;uIoFW_g-`s zTXbw{^=ZCzhoxOE?Pb!Az@~d%YNfkL+Uumfm+S~*kH9{?is7qxxGV9k9=YjdDui`D zgb%_dlMmZ}7v|<+i{*kT3_E*ekd?zGjtFcrdm|RR^+J|444aL9jh%uWLLrq`T5JHF zbOr2xy$AfTx8OFS8rY-%+IUqAHkmeQx5K8{OQ*E+Vq$$UA9m=ExxP8DGe#R(2=RM_76(jAs|1MD`>Y1Rb05^}7AO(E99-k;%TG1&hD?l#zDlCUeSz5X4rzx;e% z{{ZZ9OaSka^g(Ig3)`}S;rn4XByPLyLFvCs+IytESK5zA`*qj@>>oei9r86>>>eok^urEOJAplj4~j#uy~yXh1oq<+ z9+nTAUI^!qjaBFnw~vguF z^^WPO>Z}*>P@VlY_&x0voV&IMs?Q98XkAoS@db} zpIm1xUT3p#37cML|1#H##g)3Q8IvWz3Zw7|kG@$~hUOMz>haV0#=xU! zL|4yU2H)#b@a;DE=v^UIyx)<0=7Jigo3^|k6M$pGR41Z-5o^mT&_x~`~Mlh|^j4BP`GJwuC&!c$Fij2F2gr?otvvJw9ZNv1N+hVMtEnkW%8Y9YcFk5Y``I4dUb5mS+$oY-hed}jpPn7Mca1;oy@~7Q5&Tp zVeHv*`4l^=mzIgG*3kRUmfsTvXwQ}l*lf1ot?|mV=($6*8@RAOKell7C0AdbEKlYR zEv#F((i&S>cgadNKW`*6nipMAm)(AE)&0?eqhZkJ*3GTA#^%;tSkFrHM)ISexm3Be~H%Ri2|EPJeNNMFijCq2eq4?SOYd=863J8*iFEcEN(Q zqjMKzj(n+j^{FrPdB+YGTVwRJtIGSDe^pWY?ke9e@}o!I9Ir(9k^8H>M@5XG82oOR z1${;`V&o!v7<5UfueVsi@;zGzl`)>REdR#BFWV`lxuvFblO!WKpSh+{gBV>B)=I6T9FlyxK8mp(AhlDc2$WjJoWN zFK@Y~w0Jzrn>kWFZh5Q6J>Hk&54`);ckX|8?|6EBM%}C!8&5>0WqRLXeU-lsE;=`s zSixfc$a^t=&FRxw%wK<^<=obJNFNK`&}v0UC0LR zDqsV9F8=Jd9{Tv&zswm#ymMhczEfK$Ui_<8EvG%&_H8)DPUnO%K`KRW zinizsG=6$M1zt_OqpJgGZZYs7L-UrF&iLAGU9Hz)Gd5*}tCnBa-q9cL!mcW(xAgTb zOtf#qG3|KUs`#en)@`L8-@#iyTQJ!+%etCf=^NF&cq z%cIU}_T&&~8(7TAZBTr%$W`b5^f45--k6LqL~J@1wG!kc}(Ju z8e3_E!=%7A4`MoygiGxJ5g(04vPw_d{|xfI@~47@SmQ64CxXpN_7M1V zytjdeEaZ4J%Tn_Foq<;ZfExHIqvZQ1cK4I`Z0zO3}UXqE-{gO}BrG4P*5hVVX_~=Kw z9Qw@tTsS_+%)J48j}m}1>XB?jWt%6E_!tDF-8_QKFqW{q?T{9GfvJN2|H>&DOHC+!JB;O9Buc=Dn} zy7|w7&K_Z?WGv7Jq?>ZqV&_Pgu)J`)!<+PccCQQ};>R+nX1ol`pqimw+%ITuYB%3B z-19|5I>z>QHI<}!~Hq9$t#8**4@}6 z2K}Jn{)yxdbN&E(&7k8jwrwcBSy~@K?gelY3ypEKt9ylX*Kqetc7t@6a(5QPVxMg& zyx0}Rd}@Qf9XiF_6mPqeCws;`Pchh2Jm}PLW_QlSP0r{Xk3Qzi;6(iRTFLl`aMISL z`};$hQBqQF#uT-;rK9XBeH)X%krQOk82I|q_Eq)pCAHu{{AKB|p(_2FC2 zXm@W-yt8>5m&qOL)MCor)~e39J+&vHwfOb0ZfTvceCjXtNkF4YH$Ll*H}|%-)Az=d zOG11+O}#K5*HqrIQAU-bTJDfG~zScfj4fq@&fJU$iRWh&$ zyHC>YCma6XCc8|GMIH>MKZ4s6V(ci{vlu&0_F{1}m9 z?D>oxgk1nUYBv<$Txo-q1u!5``yu>VvJsBtqIep}UMfy=P(16%eVNcONAc76NqF<5 zO=HU>Jm7FV;BvfW5)YAcyelLg!J{T`KtBe;sKolSgB(BV|Jh z+RV~-v5153V%<((HJ~TMe|_hb`nC^q=hZ@i>N~I2O83qy-8@Y@uMm^(yt3Gl7PRw9W<6{gn_{s4;oG13 zjJ}KIM}?tXEHVSIN4&FA@4WglXVK24IzO`NdaA3j z8`rL&x_apav$LtL4!pGN`&3uAU0Ys6bu}Af8P(O#`lGHsw#-+RPJQgr4AI9vAnWQM zo96J-E$CyvPkro~YeXNrAB&$KtdITr6m>OqADdR0x{v+uTvy-!B-Y6@*46*SeBgyS zC{uerp!(GhIv+qKrGAxqII62t%?FZrr`!QLnE}|xKlFa}!##;Lb-()O%?GNdsH=aO zds1QtWr~+$wZTHelc|&XE9!9C(%;IF^NlmAxELw~vm?i-XY=$7y_2Ro?Xm^_ zI^I;LXLcHVbb3a`MX{^rzcu*Yo`R3={m|nb2VW}r{>|XqgM%cg__6?|!l2(`{K0EQg8azDF(>^XdjxyHS4{xYs7JC@nGtCa%gE#K4C0wq zOez29+1w*YW;6CH_$#CElv~-l|A(`c)WmX zhV~5H;c0f|7&`6arcvg7tL@+51Xo2H~cvE6vDW@S%816)4OqD_az~2-fvxMNqF%G{ucaM)=Kt`9yAM2G^dCM;QJ17KepXJ2+j#pUjTL`P*tx%=V-P?CjsC?nlg^NRF;YCZrOUjmpN^u@1 zj<29D3f+hxm&9d|1?3x-E@>Kgj_$5dSy_2mMa505l2(zqW?5#@Ae~kX z{R;8qf~(3|`izXLrg;MCIlesWEbAO^zICoO%bIN!_==zwsBhbr{^l0g{k_6&S5I_S zhb<(%$^6WWeiVol5khr0KhonI9wJ{_-|z2GOZ+LqKx1)gU(#c&og5NTkZww@>Cm9a zO@iggjy~wFbQ5Vu1R6G5H@kNdCNn`+$&vzrc7kv?sw>{9PA!o{*T#D(+d(vf2o0m8 zcY^jh+;KUy6yd;*-4c{)AG9rZcbSQy4CM;M&p_AJ-SIO|Qf0m^Kb?bW6^W6XA8Pu_ z`@EagSt%I~+Ml70{69TO{jZv%(%g#XBWl#AIV$-ngCUa}Y9{)~J%){$eE5~(N8L63 zXylLLr{lH3O?=8IyefF;coV>*IThiNEDDdp>v%gP9TqnVF9w&6=g$@L5FW{;@NUJk zj&}##dH5-#@NR~Oju!-;l80v9<-;Y@G=3Wv-!l`KbI99-X7o@t~B8#|aj0lze|>@D0E{M=`-x ze01JQk2i*RRXtGe0#v_lH1PJoohlvI8F&dT9p}n;3GWsIZy(%q;jfIUr+o%qQj?GR z6qPSuH1OzLLs)^qR(LxNyg}fpc8={z8}IK7y#Ih($yr&Gjy;^$D*YJ*kkJ63z zIBq-ufR}C5GimG4`F!Bh<5kZS;G-}~4&qBy9@F5j;{~U{n+<=$Q+Y;wsoq6P;IF@n z-VXN%c^4f9UpaotP+Vm6G?04-UN6FUg}VsPgiGnA`bc$D*sO6NO$*=>f~jiVgl^hsfzA2EBx91|=qe=j1&3 zdF_=4a*=y3yBs#jPW=XH9kE}u;HKKsjGr>(?o=&V8uZ6d9n{C`Lj_!#Q8fcbSO0> z#_NLnO~Lg}AP&Qc7e9XZ%za;yOS?ROJLCcAdLQ}T!QFVJ(ccl}!7%lvC!Ge5eB-3I zN5P=3zEL8{n{cGlesAP%`649W7RhUhcSJ>kgzDwV7RUCG!L=7e9*Op9$ld(P3H3tg z_R;R7P@4QX!=!gXJ976cqGEQx7~0IKy!o|BMj`0$jdoz&(|$Xovk?4D8P%u2QZfGw z;0zkoxxg~fP7AIOa}zrA#r}e8crp0vcn<=M`Y6I9T!ptC&pKW^+$H!a zqwsElhmQ9MKva6EFH?9A;91AJ7jA`tNBeod!S@-ssgF`dg?R!Vdc4mfUXq{EF#|sp z?@#bd@rLmuvm3uu?`;1Ff3LQGI30oL-AWn4AVYIe@Y$vcgg0!Lh>M)WuVf|nD!i}J z`yyU_`H$qIe5W+%c8on?}{+i>ZmafF{NLH&T~f zV=@KJb$c64B3%Q9J?qi#b0a1-a*!Z2Rh%>*)EPEt1B#G*qci>F8q*90b1>o4LDQ2) z7||yNF!`Z;3Y;a%r$Bau1?ZTlJOii{l*a{lRi!>OfLGF)(x2){0VYS>AFrZ3oBRKa z`Onhu2iD>6i0B~f`Oj?hoHWZJJr2-25IsA39-qyu8xpgc2xc`)qh-;HF|!ex6Fkrc zFn)XRP$s_HXN5)Z7rUInLo^HWMg51#4n>1Ugw}Zm-TKx=!9(fC1Uv!@X+z-+!4ADj;GJNJ_bJ>uN`ihgD9i$Ho`;4%fzCWl8v&&)TOV5$-T?z|z9t{_ zwF>WL1CPRy{K_c2pTa|zZ_>iz~eIC7!BtFMyV6K3WPseLlJbZhg)ICpYGNlrDU!P(*O3N3xZy6!0}v z;{EWT`H^ZPl#i4KeLi|GJYot2H0=>C$LRil`Sa1qdk9WWQ2tHcGjP)8&#ahk0`F|UfGJRCT&K3$q%`SQQSHmQmkv~I#N(1 zjUK`7W0J{Ga3KamLOT@bxD+}WPm-}SHDGXR7gC1ll+r?A+D^h4QbGy&!!Wd?>0~DS ze!Kgf{dVuUw!mS?m`^%)&+hl_Z}&WQ&-d-qDKsvSZTu`#dCOrums7XWDR$)|q|xtx_B8NKBnJ=lgFZ z!yUovX}qEwxU}qd-Fduz;1p`=3ft69s5bpfR}d+^p{it&O9DA?t2-0Rstfz8GqYxA zmn;ufnA_9Z=$Y!^Qplgp?bZk4U>qyQrrf#dX%l;I^&t%TA$6cK;kTlMhsrvSdi5HH zL!ajRNqw7j5X1RgOE)|J%194i?ZY9Kbae3-?pn@;?Lo_+~$<*@Fg#j$aqeW-CD>7<5jc6~DIV%dC&%nbw0dwz1Xy$^doxm};y&tw|8T5n9` z7Y#It{Hu+PZ9}4~TU5NyY8;-`=o<#wM>DAll$$yGT1*$2u*Uu_HJ-BfIRIYwEu*`0yI?|XJd)ua zMUiqHNo>RT!(dY+)(UwE`ZI}JbUR3X9R_;ii8-|3sgW8Erv7jdrfs1MVQ5fVIxYrOk_M>*m#eZhMP=Nj(? z_&4DYlK0>{2+(-53Xk6c!TSNuHC_oGoj<|*_XzJX;I$%*`J*d%93#g2Deo26j*)9b zaCY9lKsokp<3D>xh?l3YZ$>!MoMIXz_E~SXr{v-ud zB7pZM#ldUhb@Lv}wc<26kAQaz2>j}l?2L5yo1w3_Wym~fG|z>)ohAJQnBOL&9|)Hv ziqFxP8!7Epg7Zs4{AMGcW&nKRo;XG*lrI^1FU1n#iStK7`4%JZ!*mH`{uf8`e4{;4 z|Mzhj&L`!GV}y9Up8U=|yi<8=N`>-o&sN*D^6XXc#4$yhxMmc~D4+Q%9JCMiDFNng zIP%ZIPx&$q+6%`c{^uN@&y4oKA2~no6x+97aDKk8)c@H>LOkY!`aa9O5YuP5C*R7q zChwrf5&2esAFhm#VL(4SFSEfI(Z^4`=DSBv?q@jJwxDf8YNKbcXnw{Q_b#ldSsgLj zbd-+O2xbVOHha}R zJ)e}nfU~CZXn*OBr{{}hi^N|ZUHuKG%g;3&?R!_@+wfn&?4O-9k-jQW=j~e7IORp70jubxF3t68JTOg z8s1vtHP)l<5n_EsVtuFeRL=8dU5KjF)P1b~SjXLkqkuy+lS4QsPe}0gAVA}t1|H)R zk8uTW0_Pgu$k&3g;T{ z&m0eqA;EhRK8^Q%g-2aL@V2%hL4d`6^i;K;+{+LRiPs+~Mv-EYA5d!4_(se?y*LgO_nJbptZf3y)a-rv{3 z<6L%)*Q)UNtrxt}2=BXf@J1rMWeSfvf#Cgeg!d11@P0AEOBEiP4>P<|5#B%5!TVx_ z*QM~N`$+!2=J3i0BfWwn&yM?B$Z0$70Q{Rx4EqDGq1cZ5RWM!_CM4vPuDpwk_!?do z?v&Mu^P6!nf5@_VW>!ss2lOHe59g8#37+`H)!}c39ml+QV(vWAZVUNRTC5E1w2;q| z;fZ!x$Y+h?iFR1XXARI1TyUf~Hj74yUyI_ztYcLA#FaYC^<%zj)x%ACGeyi}(*m z{wLrkKHmh|fu|z=R~-K?!*4crpNKHM?~4a6{jW!U>DS?tq}_OndZ8&Va|vwvEy+C* zU+OW-Uz~gbe2Q3qtJx`8k|f?!0e?wyF~a-1fZvw98u*u*xdR$+Im##@YgI2b|>;&XvU^n&uA7k;hR;M{qw04vm z7`9f(8RzCAbu52c1ECyg2M%pxaLhW(F!2~y@Txf1cth}OjY#k+2-kSCz)KNE zJmyRAsGDfKBaR2hkX-M_;L~_d0FOAtW1S;-pTRl9MeqK&g^;^v)63h3gxa%zALOkQ`PzL*DDO3LJ~>acEyDEqq&?BL2(|SV zGwzKN%xM99OTDKjBRD+Px&nxEg@{vM`C1WF!&#{7Gq}l?NsiIyb#m;!(F<@> zcwdTWuVEQrIG=b4fqVxT&U?TyN2CtiWHVNu%P+avidi2*o$q>2_ofBURorC@SoU3C z4GTW6#oo*?G;R5J|L_g$cUa(hSXXS@=jeSqFEJP`bls1`!T37PbEdK$w^pn9&rv(} zfoW_Tvj0f`*x|`I(qOeRGI$kEFyAGDhGJoX_m56jXGSN-YqDkRD<)l60`K=#Fd$(w zSrN%420NuXYw!HED@|{u z@kIJdCEwdvXFBiNjaQmlIIm3;|ksg&Nbfq>fj9_ zT;qLR;W1x=7wb%Yjt9q(TyLy1y`b>4&J>SN+71+^B_w#ii2$9y7Zo1Aw30vSDf)W( z4b@+6!TZw)?|Z;w{md_n!)n@`Bd@FpYP}@!%K| zyf@&}c#Qzzb71~x4+~zrHWhUO@`MEMW+bZdS`;3?e}WhH3q0U>F<#s+(5CRH7YQEc z59sTisDsCLH=VzBg~#u<;K^QFQa+~Z;IaK&J7{KO01xhQ`R)xkR(;jL46)W-zx zQiS(W@U)&N&x3n@>HPHo5C7)*a%_X({lMXs5k@+JBhOagT3Jvjri>7N3h*z)R^T}I z#gZw;a{zQzaMH@mB2%m2NS(#}G8pM*)Cx8C|DvBE)UJ8=JkeGN`SSKy8TK=Te3mp% zv;{)Gu2FdXEfGJ~{TD}kZB;XVYsBZB^~8RLFn!hlp4iV2@>!xiv7aI2>o=0=FN^pr zah}-E5XN^(vJ+uHL&#@|@Wg(Gkk2>VQ$vz^56-wo6Yl`uK|V?LL!@wp$m_=8`Ax|d zVZtS!^|a?V*By^$@k_}kqxhc=;G4)V2ZREF zIv)#%Oh(Mn@NJ~Jj7)*{+Pd_q#9DlYl+Va?>ej=f;x)nhVZ zmcPh^urcd$T~vE7BC{fkn$KlaZ)#X!<9BAC3b6oqqhbHAGEUO5#<^Y2UF%#Z^nAtH zkHD`<$9t@P)`5zNwLkY6Br)8$;@{-_RO~?=w>uY#IdMwpPhk1u8cy%&?se@6wznW_ ze?aenT@=9nc9+YWHetTfZQZvmcy7|~v*2Tu>K@~CVU@W~^efc%6TIEc{67|qW4vKc z>*!C9{#<{ssPEQV#;;W3CUIpuA?+{COJm#qW&S{c5VCWvqNUiQP;MM z&-OmoYsNxKn?}}?ffWj5rc)8)CI7qOP=t{7vC~X>$c(Q{&F@L``|^?F^UY>VWvTo! zMpm|zi%+in)YJ2e&B)3{nEPaN%-_~Me>LCs%_SU(nHD>fmB;5>)5a$Yr;cM(=JEML zx#>4!yo=N-Y-)< zU;k}1yLar^(OcfoeOu4L4O2ZkcYSoQGBP&l`e&mC6ea8S9<49n`-khxpjO^8GJ>|4 z8Eo`&MX`OAiQP4=H7Ywmx@Q#2yF0imgYBK1xPL){NOjxfG!SlRIj-1jA0+O2?4`pM%NgHt zWVv&sdCiSGZ>6>!ty$YDw06uV*Bz$@Ep`&+SO?ta%DGq{yWn@90i0P~jPAWSv~9?B z!YM~Q#udCz;GFe_;637aa14nG#(n{fw+nd85Ao;<-sf?y@qPjRH8_L>?{^WP@%8~v zu9y0-;Qb}eHQp)5gJVeWo`+B4jjH_Vww-^2oW^?wex@ZPc+|x;o~(z>>!sx-`MU{V z8jm`D9^OwtNaJxmY`K5@Rtw&p5#Aqy$NM5A`MW*BdjxpIVgB&yWOxrmc;5go5ASe< zcS7Omww=#Jc(2sKqivzD_oTw3zAxANu$sz+$uouG68p@!~Zw>f%y(Hf0pE~TVK6?;T{psYDcd ze2l!dq%I?8`+3=xw8x8^_vj;$|6wQJ3zz-upN{xnjQkfP|FeXK^4pR}BK{Ww{!%l~7~+N)|0Tyif%7Fm`Hv|6kEuF_^6inoC-Q$F^3O#6 z$KYpv?e(uno{IRkZECDqty=>*;wUQwlGMpjNKQ=yFoesy(TGPgIO#6lfcEe2rS=ui(V`Y6716dz@&>LCt zMJWz*sp14iR~!vYYii{%0s||DugxlRtHMMbZf$Nt+*!z(zK&s27fIi8s1+ z(o+P2IxrTP-#&nLoHCY;5k|Pl2jWq_18sVNzc2D{b!~s!ZGKDd zclkmaAnVxD7CX$C$ZDfPRt%*g*Z{W~#MiS91Dw?k=nk~~WPCXC&KTTJl->KL#t z+Ocevhp`*75c}2I7B_DApO0-?fz=7@ION8GLg$L92COpL+{YF%JFF1vhwfc@4`Q|-Ve{E0>}R;q$SymV;b0w7i)Hy1D?L~6DNzD+t?}p2{#5^s1MNq+ zO49i=Cw_GDa#CV@-%XbbH@02)V0tRGt0UcVZhP8)xvx;@EMDSl@S=Yx>Yw-1Zhp)n{*55Qveg z12Q+|zVzmkzOOP}c@V8#927n_vvs_hUB-3Q{-w2f)@dYEuYtYW++yo3)?Jk0!TJ-` zlhMPP;F9*?NO|H&@V3LR?dMeCF|Obp!a4Oi!JEQ4L^Be+pGAnq>xB^W!~D?|Jkk3F z@8jU5ID`Z*9^2HX^2hcC!TST8>-_x={3#A0!TUS{bpGyDc)T9LdmiT+?>zh|4k5w2 zhyaZ@rSSOO6TDY(uJK-kKgA&=c&{Kp;~i6Y{JsfZyte7<;PIIY30}Om=}F+F5aRRT z_gL`C$Q+-KsO#I|$A3n0&NcISj?bYX%H_4A3?Lj>d`%2-OwU5vQ8)*Od+`a$Dczz3 z!o3&s0?J5$_AEZJ<~n$Pc<fd zKDMKT@=Zp*UBt6eC-Tjae6x|~^Rwj7=x4i1h+m5ES&}?)j7=!t63K^Lw!4HOizE5k zc9>AUHInC(^u%_VP@XfhtX^iN_$GT|JB@_!xfbB3yr;O`1_Rj@u^or)9*oOpz;=vx zD?W2~N94a7e#)mf*p6`!t`OxXagfjJV7tSk&Yv28Dft{+A<9239=P;hz~S**vNf7g zgmX;HWw=6=FGASM+clZ!XC1+I2EEQO<=O5bM1S1w;gwj~NGtg88XLo?6x=4+8V>j_ zTLXwz5w!`mRdOaT2Dq8lfEeOuoKQu{qU0zhHbG-&V_1Vv-)Jw8w>D6$uSAG}mXck9 z3C)49+KPtA)lpo|u;%LEHr|a7Vcwd<-n(NTmvn_;aL>_+;REQ6G|AXIv3JLTQD|Kg zm|x3KQ}=P6CF_tPn(g?0bKC?=I_G8bJ!LrGYze2|@Ne~e6K`#8xQUk&ZshUu$2dkF W;dE)+AuGnV;}8qlcH7}H{r>`TKY-o< literal 0 HcmV?d00001 diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32_iar_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32_iar_release.a deleted file mode 100644 index a089e35b1dab27388f23b4948aa290d8d330a2f7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 378444 zcmeFa4SZD9nLmE+on$fugz%<_2$KLBRLBcS2)@o_k|BWraT3&8Yi2T;Fat?un3-Up zzJym1t)gwMeY4iu)^^*i@71mpv~RAp6{@?nw!6)`ZB^{HQPHAw&HwwHd(NG6?@TbZ zhTp&Y;eK-S+~?&y=Q;1^o_o$S#pj2T;pl~hWp3+LQMIJHvbv_Wa;e*0&RNF)nyM;} zRa910)$pfaA!FJrj8#0I`(D<iYx_bYjh3Rzv_QmY`NRa9Ohi}JM zA7T9d{*%n{Vc&l`gE>yzS$U9mTag% zX1VA8iRHiF?fU}DKh_;&EdPVv*Y&e}^}e-;<$sX-p?a2|xxH&HYiVw7_xAO-M$+k6 z@7h#Ls5u@_bcDj|Sq^4*x1H;Y_jbkB_9Y`y9E6RLWEv`)4?IodZ$!<-D zlIaW*Pp~F`ySLug?hAFtI+CGugf#_x-sbjSIvZCq+S6)*bH%bwfwn zri3In^~Pk7mPoQIp6n3{1lHQu(bd-*PRHWCf)R*>Is>UxOrWiyjS*N6lhcuuq(x|E zWI>u^y&zUXY^{tMxoL{zv<(7*et$Bup)b-K-jtDrP0OO2l|nEQ4{^a!O2B0GArpC? z@yreMn^-(yB5g3SGk%p!X>$}Z++A1_U2XI z_Hd|sRZA!xWi8(J^3IMPqhKh7AXH{iye+=^SSr-f9U(rjhF*!(g?c+%Bi)fO4_X&W zH^$aR1AVVHL;b7!(uuxwOZ=)xQVx>yEk=wG!^^xw-rZuTd@P_VCA{FT*12aVAq+zp#WR>BGHLYk$p^o&TJIsV= zu50skt>qafjRL7DhSGC2}YzahCRQqI9t>I{-v#&c6=r>zxHp^ZFGEjCYz+!7=+LCKc zLEGvzZM*_mQg2diVHLVsP1dB^;?@MSmd1~?uW4&)Zf&oNrIB18RT*!0cNT*>hDeIq zBLuU!O(`(4sOU9v1@T2A;q@({WGuZ&34)TL5wJ1R-xl|#!m*gbGi$7A?b=9hOQ5cG zsnYAVv^BMR6Nv~q<<6$wE)1hae=3@$jVlUDVfOWRq6^Ov%3zEX!01m!&rddFYsd=9 z+l_abue~X7aU;6-?nsi=t?^rMe;^BO2{fr8R<5pZSg8`ss;a0Bczx}GR*M*sS{p7_ zLmJsYCe&@hsO{YtigokxC&LgeCqtlNUnH9X5(=5Lw{=r*SkQgVD=cZp7=iIA($-%W z>g(jQ7DHWz9!m#kGGimRZtCfXcUw3#e-dK#VGOp`T<0W9)b){`cqebst9t|eDb(_C zw4pbh+++(ll9)vq%BCTi#AwOOPMG0OhA2a@sb`ba9Atn2IQiX@vbc&A4aF*4OA zK!GuwDk(&x545&62`#+#7&(M4w_o(727$&>G1u_N`Z2{Z$briYV?<)xqRFOSX_Vv{ zDYUX8Yh$T2(vaMMfwr5^Z-v5sLt)P95)jP#WIVwIq!ohhkM&~Ox;cWm19fLsjoFkI zOsgYld!3Y#P`#r_Y-%Jql|@fwMVZNenq8t4+v08g)Z40z=1A|_bo7|1Hbf}qRgwNo zx>|W8AHE$#>V`FP%gHkm>NB;Wb$+eO6rRZyA27&Gi z_(+i6FO0lzLnT^&jHD@iV^GWrmazhjo7elCHA6D3T8sdyipF?%CnkW_w%OJ%$d_BOl-mHK&OKa5VbTyT^ix7>tmufQIY0ISDJHqrh(HI zPlvi`GDB1Yp&?DmaSHFeDT`YhR<$^kQ1g0&PBD>qk~$IOhQ*))G&pFAc4atU)Jj(vp$Z?norTAm7&5?u)i2LSfV% zs+f`#>g|nmQ>_#PW1ujQdS5*T;xy`?uX}w)CPS7j$}TRNlpx2}2I3f}4NbNn7M>+o zQx|2R7|Vrq1}$TLQ>rpiwG4S=#I#~#uMC5{;#JWaT@C?DoP4z;quxxr7(R_y3~Do8 zL(_6x6%1~1Cio@ccp%ifHqw+r-x%v;;l5P0J#b#1~h!z_#_ug#RW9ArwIg)CRiyq%rMlaxQ!jmZght~sUTlqHp$ zjrmceQw+2@!y8ipS{cj9z65VDG)K;%qCSS#$~1Lcq8_RWLYATI< z!a4%pH;=)#w+b0-#2^?qv!iM2H&*7XtYlwUbW{D+cE7O)Kt&t7hbi5}PZbm0;4JJ8jdZ~l9 z@nll$WLXcaoeX-erbr~x9PeG5t1Sw4OQ^T0)2@)hwMH?c%Nda7TbN#1^1_%gsU(_! zCL8(_=!UHNIRo{IAVzqL9?r|G;brOLbGhsge0FLPHrK}x0x$bXteMAXk|_!qOE>7W z!zc)hBx{)!ZBNlsalqSz&ns#tU$-gK8)tKc=4^)OEORKdcC|SK%mLbNilrmX5zy?N za`1SS&p}6pkj2dt;WNfXHC^?Qj=r@tLEw`OTCq&VFfr!hS>p|-qMWT`IOVD+d?Oqo z_<&#_Mq4sQGb3VKmMgCfMu#>r>;*Kh6R#lZKE1^nL z>X%BUK~D_5mbe1_P53;CwRL2ODj&dbO)Ks;B5G(Km6s~oHi8NoW3yDW_2*KtCPk}$ zd||+<`_fP>jYW#AEFwB;k%fi6mVfL-UqWA_3>*2ooU9z&YLru*@iyE??|4)kAo=)Q zo=-Qe#LP!2L2twY4!(xO`H*IWr^g0b(&5^~iyZFCJtbY8Jm;#`R zz&MM&AgL=dJPM*2eSlPC60*V~VOeQFc$%lj!}0FcL?j&RiiLeqzVPm=%V=y#$D~w- z80gP**)sp24pRlQCpXEIQY0snIwJTkZNu^he{DDNi)V;f1<2xvF2G1NhBB)g*^-aLkT;@puxULs+!R6@f8- z$`usfr?EiShZ(L?4Ks;Ew!NBa#OqeLlGq$+i$Ljbb5;KCLQLs-7`p35q(Fx^82^3e{Fg zL=B~+7XKOFoHilU^>BkML8@yhWyfSvrYK=}dTn@a1(__sFpFlv`(>k> z6P>1@BbnJ#APRs!2%~ED>`0Ir`tiL2m61kqK5sCJ--4RMxGBIhm1F{4MxUQ~=AFJk zd0rdOyv3V}5Z=<0k_>3Jj#N->{U}i{i6m1P(?}nE0BFbDjwiv_f$@bmNQ$p7l`#hI zbmH?6SuIB#9)tOnTFhmX{*w3@vuV$TX}iG9ERfx)F{v>$Um8nCX&XnpS7a>-QQgfH z8uUsMzBr4(ZRlJrA_hSUpc6GlQnCw(=qgOpKoX&O-vLyP{`@PoXfg`f=mdFqdkAI7 zRsv9r*=p=|WY6WuU`bU9LXgZpS`kw^Vuh;C*%Y!mWwVgQbjw1Mvn_?F&etsD?C_b{ znj&bKtSNNcoQyc;T*j?( z8#z*3j8P;sNz_bo)*?h~emd&;gYdIybEWq24)hx`_tixJ%Sj(`+RbWU# zS7;0rBu{uIM>r-I-HbSigk<(5M4!rwqa}ptRf?6_jyAmS$%g7$aTFq0$h$UWSWI@c zM?>9<;$?*j(HMT|t5iJMj#(73c|aOpG9fafO%Bm;rlT-}cg8|%d-1^~7B)$lScw$s z>u*nVlR1XLGG*n}xzB7=SJf;wB!h+5H8lG*O=I%XSSib3jQypEbMmX08xN&y7I7D) zqN#K;9qPc-rXB+dJdAB<5qzIt6bmI6CDT1vNA6~e()3N4NbMWDBJELnNlCKy_WI_g zy7rcaKwD#=!CRk2Xy+x*HKpkLWM7K*TQ2IP)r59FXJ(6%k?w2)#jS?$239T#rLpO+ z17C(xMj+FqMbNZ1hD|pHox++FnJXq#vnG$dKD^fC(8KG)*C@DyIoWm#KAwG2!5R3s z0}q%qC%e;pX3W7RvTp+~F(Y-dhb{af_Cw$`3jY}ke+v6G@Z}2szb*V}>$#@=6@Hu$iuHdESGo|ljo*ycIiG^Rl$ezqqz#1)l7rWeo zk7FAYdgz!Jz_z>; z$J;SSxFQ^lC9a5cB^Os-k?gvHT2s6iAc^XFg>2_xv=nMfsZH46(vzAu&(LBtvl>eS zsi|VH# zMuPTKUm}sj7sLx%Lgm%vpwe4vsP}^ISUTMuaWBN*!f>MR0w1q53s+Y8-3#ki)i>0w zS>|52I=b1tuqjjV%J=|+!uN94Tv!VXt+(w>i|2TF93bu#u{ar*P%6ik1;WM|#M*SZ_E>Z=|O)xv|U`bw^}U z`#DDFG~US~g0CbflPlC7%XoV%OLieL(uc@KEsG%3c1IT^*+q*raV&h5iBAiEYq-BP z+7479gryg>4;*!7Qu2NpMwyEvSzu;TCdT&_#jMM{Fz(J-ZldOw@pm-5!y3hnE~yN& ziwKrJ%HkdC&_2X0E4Pwd6-AVS85DJRVP_;k+kAV&u}JEIp4_@Vm_eQHh20;9p7^3} ztO>Ta8y#pfy|5-Xv3fkPg|7~I^ZY0IPxjC85C7%8;rovMWypDy9hvdEHp#Vb_0Vwn zv;$}ROZ-dy<(#jdqaP$W*Puf@IR*)bWUa@)_m!b73tv6r%kvMf9$w}0Z;Cd#n%Jh` zbpO)m@bbwX@8PKC9V*wB2Ji51SYLej>QgCf(;?)Ai9 z{?PuS`y#bb&(LyK8|(+vSbvc40pNg#8Q@TlXQ+q`LC!toGU=Y7JUp*Hyg5N}47d|` z9!MmDej z8g526E{B#sLucxrL(|nr_ za*cBpy2ckwa7`>2&RIyR|#X23C^Nv94;qgQwc);6oPKXW)g%A+zcpzDA(gAh;!?Rg6o@4Z~|jz z5QN^d2x2~YHbFOIW0^%rj(O1(wQg$v_JSSGo%z@2?Q+~8GpRsi5)wI<#vl*Oi{{fo z-1;~XH!|?J$Bh!_l>>!!yyB*LKTr2bB5q{L@rs+;2#}jP!#M=eUaAP9eO*Wp6|$Zn+5shdJQ~~O1hHzcjvyM{0AQh;vELCy!)7kQ2dqL6w3{K}>8w~*_$D+6xV zw*pF}K7w@R()UrwjYi*36n%VP96{eNN2$+;zC+q4n^`XVS|K+Y`}QgNPUfjK(t97C z(R31m#GZv5t=rhI{UE62TLR-K5S6cN3uNEZxMiKiBfAZ9D3Yw}1yEFdUxFOfani>p z5P+nwFxJ(M&&=kMto!}eWGk0eRk-=}{%f-TOEI7ilxwm@WcvS^HCdiE^`BZUwC38S zGJ#*M;I!tt&4Q0-w<$Q4`lo?s>YkIgcPZk)jF$MBtAKqYgP_j2*uPltaqJfgPHpIS zxXI=;Zdx-O(=|a+&pz;y;5;nXeTa*0SuPz;EO(t)?h=dJ${M3}k>td37nWT!S@OPX zSjTm_OAcVUSC%qXXO>0fYM1PiKGel7q4e)v>yoJ&d8w=R;hD{DS~Bu@hFX|A=*F@U zYjH=4+`&kvn-+A#y~-UmNmdBul>!1-E_&n2b z0#eleW_AtasC48dRomapUWc6Ik*s{SznQ%SIrWk@+271YlIula8HV(boSZqUdhKsW zM>y_=$9N#$b0C+7Rl+<#uf%`#{1Eq}+%y(5L44Av=J)<@DT z!iTn{0uig9jWc^ElyAvw(b#Rg$n_FH)fDfks7g+D6CmCRP5e$gQ#B(Q4U_zD0m_SB z8XlAgpaaW9PbxT7_#Xi$-Nxl)Ka-Du4#e~u3tnIgU%*}hf0ilZWQWXW3O|{>1DtF& zE^IVV+MENOQxWh3k_~%iSoqV~nZW7g)VQ3i%)&o~T?qUY$wqj;g?}nr1KefOoa{>T zne01_^#K2xNprG|<}>k6=bI$HXVRSPX7ic&bJ!Pw<12${Uq%=4i`m2Ae@fwh-x7W< z`x)?O6u!E63nz1$vK0RUHXV42!k=y7pUoBmACP@4 z@~_6iU&xv)_#$?N1utjof#0NrPh0qvY#Z=r6#h*Xeii#X@HW2cNm=M*_gMHf>_Ol` zh5xvPU(0?9yjS5rZ{eTI{u}rd*$+bhA1(az*-_v#6@H$XSCoGjvZ=stQ}~&@CccNA z4gTj8ew8JB9rFQyM&UQxa9SumpztpP{=9;RfWM&N>wy18!BfBo75r-8zfJ5aaW3O)h&JO!T)yi~zw13yQ>&jens;N`%p6nrUgc{%V+ z;7K4VztO^XF)H88!}a|dI9-%Kld0j3<;FfS$X_+bm6O2)=RzNHYMR5GIC zWZEF8(q){qUr?pXNNw8(7t2^HtQ#B`%V;aC30`c*YfbB7GhS-I^=ah|Zu}bEVph z*P1IeX1rEAYs`49xl&`sYt5A!Gv1|{t)h#iajw)FT%z~(vfy+>1=XzrE3 za1VXFoIs!WY;)qX&56%8wBsCKGe)=9`~PR3ZN%#3-|*SS2>IdeQ5G}Xzx%U|NY%)n zZEj%NYn~$Z`gV^VOe||Zf>(_w7VL&5vBa{0hX)?i`imAUd=B)Yy8gn%*8b&*C;N9N z^i5C0FJs|`t()}wwUXredg;jrik@?n791EqShQIyEj*x?o`gNT zc?S<{D!Sj{E=p^~E`MTK%O+O(?g7pH_RD+l^wt60{rbyfsVkjWR`f8QJnpOM!;|~! zqP+tT)6;M%JNO=#dHRMMZ(z6W-mDiBUEhm+)vFOA;q=!=cl&Sk-@*4|=lK(}Px52; z^?8m1p4nQd^H-{f-K`%y*sr@C*f&1=;N(pXcWeKYe&Xi)rz7mN1N2EDmbXP!LbB;_l$`*h|6X>q|nr z*LQ@PdcPbZ`tJ2Fg$ko39cM*5I`nmSchs$WsblN9lJJx3I>G}zcZFR&gW;id?oP5M z$p7Ef`O13Qcm7Hkd&Y-6tUQ?5TO?9O8plQdRd3#R&ugB%Jlt-c0{3GSp6o0_oiS+4 zO=XM_4ExCsv&mYJWLW7@ogvMEVD?H=Vd!Vu-7F3#YMS4W)8K=9}BQ9ugkhEjNt6!Qnj|yx2Q*q2>*5 zSwHTiarxfE(||v&ZGjJ1ZRk4hWS_Uo8@plL4cNi|buAMMbKezqN8N`96CUiZcL!;2 z{J*;Xm3fEqVMA$jxXFE(xl4ohMm-E)MTZ7F_Xc0VXIPKtm0)Si%j>QHh?Th`)7+@l9?0yg^_2VW4Nh~@ z^O1-3(h2_Q{@MPM53<|oT!dC^^bQ8bcv~&-OCH6s>=1Lmv6t$?8)(CCtloNGzJJ-< z!~M)X;R~NY3Ek@dyx;HN>d!y3me(B$GiBcbzveeu!+mv+?{oSgnJ8Q`Q1-`Pe-UB) zbDV=D=V^F+-+=!C|HfIM7QOvIxxeZ3Ep-!qJy2TsB3tw(Z$qlS-@V*|*81LRPwAuk z_P_37`yWUw`{EH-5&INd@KOJA^jLIygPk!@dhfpL+ye`y`2mZI&RIRgT=(+RAQ!$k zynJ}|^ymei2Bgd7D+SU-Y<-L|H|g;>++r>D_rjm z9N9SQx>-Xn4>uFe&MX?#+;^eIu;_sE=)c(|N#?p)s~i6Kobxg5j7N{YJ;WYBsch3q z^3kT=d%4!=F(HMs7fpH;T37B4)kO<~+i==sYVZfq){rCC8urCL8QvCa?HXSG13Wp_ zO%3|i%?)l_H@@Qs>sE9)*5BCSTmRFJZR>B0Jh6UqMC*RFV@tQEn_{PXa6M`*8w{7? zT!@F2;`2VY7ddD2*zB?QUPhiY?Wr609OsNC zslqj*#pOBQ>+&2Ccph_kCg6Em!sVF}ba~2gLWCO2JkW==qWuHgdsq?V7r%MY@bIoT zhlelPKZpf5trju^1H;3$2v?4qJ^i`!_HP-SM70g06)wvu50~xe2gh~%=MSz@o#p%! zIts9hA^Q)9N(`by%QG|?{~emcM4r&Gm7^Nsva3zu_~JoX$E6U0L2 ze1hPY65Pb_)e9GP{huZ9MFbIF1;K5`+A1yR($)jEld*FN;+sBg17R_Ss)cJk_JI&g z8f(w&RK^+zhn^;a*e|i1AoQ&wh~3&36CA+zEP~q^yOiJ#tZZK zI2NZn2qHX4jP-C6_=5F1!f`SIrf|J+f`}g`;iH$>h5#b1^|B2-={!?56OQ;H%F6>$ z@_iH_ab++Gr^9*DxqZ6{&oeef_^8# zg^YcPAoBMs1g|mH(pec}UlsT_2wu;OZ`CmN+k~TV{#no;Ah?(r->wn?4Rw+D{OL`2<1me?-v1*pCS=W$Y&ecZzK^Nc_(UUu&$(Q|3NTIP&w~2%d)n z1O(HJy-4r^#+?mN{rD~63C0EqUe4Hm5k%(yUf_Qq2)WAuj%!;i6m4|j?y*1DO>0@g^v6%zL$GWnOo4SBmAH_9BD zAq+ZYYzq-`gMqr2&WdPEw^vv^w0dvRJ0JSkx z!GIuc{R|QJ{IQK2d2C+v8QqKX)%iQ}b~>&{P1HXh((<^%do~D{xohUW~g6cQv0;>t|`yGA~)jxpT4s8~Hg{L{}7IfrTASXN~8o95-glcg+!An1#PAq&UW5VRZf z+J&c_!;N=pItZSQHqWaS=D1^-Icg)LXC8N@h`S;??y;&BnC*#Lfu_zAj>-C1CLAM( zdEJAj-0lHtgfZ3G#*9@?&_vK^AGIQKyoQWrPN)NaKO(md{O1ZI@Xj-qMyU1BoC=>W z;>P>aSjMdmwW#{aNOz$y055D~X#mZ?<>kbK`403^5kFoGy~qT4paku5bO%bbV|pui z1ZuQ={4-Wr1jJ}(T=L=hlbvjWPAf!jY7?EAVK77gq^{C0)||w0@*oGZf*AByN1zXn zK>vg#3d$rM!v^&l`dNlw5`7C_fM7ZX;t=SgN!jU6Hj$gTVB&=Ang8=9ds8kpHv+ws z#fWQ!5$Lv2XrnUXR3}yoDSLY+x~v{bp2sd?gLSKB=keIlGgxBZEMiA@Mf94B4A(0) zUcPq23a@4CW}*W>AmEDv4gwaY7~gDPxRG&hhh50W!-B7C;BUgFKfszgETj=0W2};3 zA2uHn#KH$=G^}tNW0w%b6#fc=JFyT&5b|k)No;T?2z$N-SmR@iHnA6eoUtDg?!|^= z!n?51m>?!gv`M{i02_x1Zii7i;8xf}a0~1Ktf_|=8iEbjuuIU7IT^uau#;dT7T5?j zVQmkvFo88Cf<0J(A{fV68saZ!>^{ObF!l&R*!e?(y;$fWKEl69cphUf5k$HV5q$;h zB;0}g6a4oCeFA7T&5TU}q;Rz9o9uBDT!{rkg0Mdz=$8;&h5RFk_<{si!!E$_NY{RX zEyy2&7egO(7It7EQowTo#|IcYpI|FokPtnL^b7tfqPL-66Zn;a-$`^Y@&#~q6q`^5 zyqox_-L$!v;Nt?)=H0^UvEiFwCpK~uL_M5=j)ma)1i|+Z1pgWEX`yZp@bNxugeSO$ zvAcQSQ;YH&V;jxuKme zb{7zwYU~N7b?kA3p8`_}Vg@{(;AzI5U0NT83ce0Jkzlb{Kc6es&*zKv^D|LhiNC-& z@<;2i(+EfBhA8;@>d6Gr2_h=Ko;rgdx+O%(*GXp*#L$JP`MM|85g0?a1QRf(ai>w3 zdx>>;WUrg(C?1%^7spEo`i*Xlp_t|oj$(p|e9`<2f@rQV72ZX~dOeyMOlAzt>MVk2 zMrRX5^Erngnhlb|7uOdNL^DB>xL1sFf@l^r#M0TgN`k0%NFrZ+uOf)zt|o}$t|53i z{j*+N&Pw8#hX1@Q1&`!TCZg@4^5SJL=;ZllkIM+#C1^!}C~}Lw7g6w;vl&7Vfbw6B z=1Bzp3a?BV8G54pRplZmXkOM$~JQ9@8C|WKj^X5@rp-95Gr0pLAO3&{nmlASDXnYTVzC#jG;5M7w-KfCS zs_oYv5O~`YjES?2Hbr(!5Hu7c`!a4-ZZ^pwlSq!YRX~!n$GfO_bn$);a#TM^-z400 z<}$YGSry6ovVtt6vQmR~M?XG3l@`SKY>AJt*Ha_Rf}DD_R9o3T&U*IfGMLXOJZ ze%aG|yP}WxZ3vJ{-`5~Fn*2LuUdBG&H;$n1Ovr7q8wcEO-@S@H-nWjR?@`E&rab1M zLzVS~_st{dtAbqLDD3-&q7N&j{K}Pok3sILQRpj2M=$L|l^s!^2Xdn+-vKDc>p#K+--WX+(YXkQ_2A$c@In(@{yJ zeKg0QE0=u>Avcx8SQ_4-mCJ&&C8)+UF61x$Ij6xzY3+UsCkd z9Yf!DAeRt)71-^YgNd=UuU^sjYdkv?6=jfXRTYV6dpq9>x$otWv$yl}%NcV+j@tP$ zAy4^Y*LMZvB7(01yS^tBeND&E_g|2^QdK0L?fNdN$k?|+(f1mj)$(nJ+#X~UrNgPn zy@hABzxp#8H_espmjgnozB8)viVPa*TP1`kU%Gok88;kmcgBa_lH8s+Dr;&DM;z|= z_r&3*2oxWBlgRRaa36X+Me0AbFvxRWSY-lNJAZP5F`)1rn6lrZ;8fJNDL8q``-+0o z>GrQFIC;u@)Pj#=&jKf#sG#Z4?wB5`rP?#niCTU-&w8K{r%mUj?Z@-@&sx}jrzZQ% zp7<>aI=~~1 zfA29Wo|uu(P|05efZKnp1|FBKnKTjvaqD^Ft01No`~u{oS0PqZF97Akb~`7cF@by! zF$v;(aL9>KdDN+Yjq|wOrDq$!* z>C2}F+jT8)she0AK`z%j$&KKtbIgB&9OXaROJzkDO##1vTb274MNXC*$%(Q|;E`WH zh1?p6C@^82vS#M2_%T6aa%%jqsj9+^7IWI_rDD?h{&UucjF)fId)x}jiNA5q+8IiR z?6aLL&jVS656ykt*g1ylPzr;7k*^>4`6w(ZL=AJ!t2q?kn1SB}d@ow$azJtn^jSbd zmgEb#gB$wpMh@60{I|iMfSVcu@qYkFj*_Ty5&t@oyJm8;G_~%&oQ`vdIzp3zj7XEY= z0RDi&xBlYZDJ%y5BMN_mCH$%U*8rbU_%~Sir?ESL(|35|aE?*?qvzHEB-v znE6cnIqWImmzgvtJ7_)=znBdIf6=5l*{kL=@#pey??Ks%p*%G6nfUYREED^dNpo^1 zN77mcKGD&)c=}#0?XNJODf|NF0bXhL_)eRnxU<=1;D1Zuhb-Y2vIOu46#ga)zl_nq z@QA{{)xxh}cL9G~;eW%zU(6l_?v%Yc(*J~oU(F5xuUGiLvhbI%SAf&^cA5UyE&QdF z3G7;hKhCs;Sm&`Bz_%;>VhjHQRt|icITAS8QVahg)(HF@g-=eRG<>kQ8yw-vnL-Kc#2D+%fzE0s! z0qqtWey0upwhiBJ!=D9C3skkxMQap;z<-8kT39Ch4d4$VehS9dFp!tu22M#N{3PJy zT+JhJa_mOV?amPR0^mKk-2$)1^MiPn`j!K~6*#4o^j!h`^LVE5g>Z7>SO8&Ks3m*{ z@CM-11pay8-$omh_C5)moIAD%KGnsKAbnc}{wnbA;`wBO4+H-vJkuCR`X?h{(?Odd z@Dkt)fqMjA37pCRfXjRFumd=aNff>X_+sSGW`Re6Qyh8`~{30fPk2pcUYG2-2*CV8Itxg&K+i2FN{M0JkOerqEuwJRmNjk`Xmh+iwvoF+%l>U*=?ASR(i2W>VlCeG^3IMP zqZ`3b*%P5Mi{fqZ)yGmH{HQ7Mfr;3G)P;IGTk*4{VIH(Dlx~czjRyL9Nzm8U*BcQ^ zSBCmm_oWkk=@#mJ1W}=oxd@_AgiMRlhbg*Ma&!DD5hGXbPsV#%@$2h}NXiT2c&CS- zKgKWV`a<1diiL|cM>a;fS0~c3p4eudt_)R1O{T8IPs&@ehl{Q5>Pkh@LM{;MNmxXP z&=%{7$oM2K5-Cv;Jj+&LWft9%20K?O;||`J{O$$k!bmo z@FzYO{3CuYpyj_0{JzqxlEw4i7*x*;&4~gg=+>z5gBN z-dgwQz9Ro!uRo>7ht71|cJ$3RTxTIiO0?IW)W)5zm9B{1{|>xb9MvlB-KV|v?gsi1 z@B5Dq4HcX!&kTZhMsav4Hic0kUzvBxI47>l_Jl3FDD)*$5RizlUL-KQQWUBn09ah|FQE0 zL1*!I-pJD{-ibY4vlb9@S5-FkOHZ zqYgjvjvjOzs5qTU)G2;|{jOc*GlK)A(LuPOgR8Y-IG<{SW49!=5lY#V&6@#*_F zEjZ=ZdVF}rOpm_ylS_w}Pm9j=ObzDGz4hpuuaB#^fjQ#d!s!l)r-n3$$(SA$shbyeZ*P(8e2J;5*jTz7PhE@-; z#Bh^~JIESt+8>3ZIyhS^#!sLd^`CNyQZj?WdrE^kh4tJUGNc%!$hFq~U5RB^BS)Qn zH*e3k&vzWqN+;~Aod3}LKip5@QMMcIqmuO9cl50xk4DdMcvYbddR$Gj$e~`-14Rqq zuIz9knExVMaM?bWuKn9;IH#k0KKLq|`!n2ZPidaEhuupW>CWdl-&suB>fR{Y5c5%u z8ypziwQ=uoQ(bg9N`K1uDUL!w7A^9TgTwNNhntqe$=8bLgy>1pUp&C_@`fhmv5DiN z`n!3Dx6b_0n~v$H>EHC6HgQ~GVDgNa+R!9Tf30)ME|30Nu&8{mLmOW1ID8~U4#Q^n zT7oW(!OfjERDj;E2>J~NW1iX00|RjFIN?{u|A~Vr@qVrJ)O~ry%$--9=PnpT&+N_{ zbQC+>+F)VvBsj0jL(SYji52hiPV`_wg!LxI=ZDbs6#MIYbGDp5e%;=q!}kqbm%qGncsM<9 zvg6PSoK6{dSUVG+6D}HP(zgEyE8_zP+0YMg#04Ew)kAdDWd%F*Fu7LxD>9rc!ZDgH zmrZW2dw2ND15f8`pBWzh*uXly`5t^19=KHdIzBB_4GgmHKaFEC12?g!AE#q70rv1? zjBz`(r^a7XesuVs*sOfVM~8<~_z{5L;JaNb`#0_T-=R}Gr)s}@ijKm3i|zRdZR_o3 z_d~~-%*XuT->%xB^-TKm)^~@mWluOZVgL6U_B-wH{jh^A(SGu;q+>sO8amE~kEFjK z{xh(Kxcgpg<3&EcH2nJTJHv2hm*c`>mwC~VNjNHVy12JB^}paKF4Ba9G^~P39tGv$ zO=oM`1W7XJs5>M2Ni#wl+UUP7gz0zbWDJ={2VAllf0AcLr6UfQPM>~{t9vJW*X=}{ zy0J*imr!}$VxYo;C0|D5i-*^VPx5hbWUS9vU8N<;sU){fxK;~^BVQ5WVr{ZG@`Z2J zD1I*NCI~(A2!31~;hJu&_L8f$vxt6*II7hnj$}c;oam>DBUy;Qn((#a=oP;G^KFyB z&m%g{E}T!Wi}6)girh;$zJ)gsEas=lxGS#Zgkw+gN`go<-%dG~pAzHrR-(@ruGjD> zl*)+CnSF#{Qn+4QAhwI9jQk`$5#pcCP2lN77IA$@5_e&iAc*h?!vCcSE)?63V`7_m znXw8?F3DgzPdti(`*GVw5b_HjC+QN`;_AsH+@~=>7FU#KK1y;T_fY3CE`Z^dc4ZJR>qCb zS-iZ_mmjaV5v7smZV@-ejj@ayRoT3Zen$O$*%Dy{2CL&`#7>ywoqCP(Be(N}5p&1Z z2(`sG!-yd6BlnjXCR&OYQcjTX}aKA?B_w?~F7n7kcSkF61ECBS6IsDQO1?j>Uzx0(TGWM#m) z!U#;sk9$qTyA;oSO#8<&ZnYEI!!uyBr4vG};AY@$V=T>3>%a_I2RtI~i^eu?wGJRk z+hANLjKFKt@yY-qXqYv5h-B1KJzmt7IgHQAy5^RGLE`n>|42s|-Sl!4&c-$`BWDhym8jt*%4OrM=IKLuiQM93w z^!SBbGeI<{%L#r2&bA059CwC=a7n?ZO}P|qr+~Ckval2R30Msqxbv&4u$h$T{cuJl z__P^!{N*@!ARui>9RE=`VFN4-V=0Aj=zSWntJ~NNs}G>CkKrr|&ZBa=iptAFAwezQ zMa&oQU<7xz1Lb@H&Pfo>3Q;e6qO{(LY$oI?0Qu`q~v6SXQ@pyDkXbBL1(uNJ~P9HSac;0sH5-{lKR zc<1B`MzaWdg|8@|@DAx!0aCg%}EX~JZ_x_1Uav=*4o z_jqEa&wW543A_oPMG&ZqaN9Q zZ3jW>Cf>7fz;56A;*5P%hv~{?-^U?08v9;W z^vU{~OW$8csV`iTvF{Yayqxx>AU7KOeyix?ec}k|{qrdGeROWdK5E-^&pv@J`^Fpa@qIFDD`~|0|)g(I&LJ1 zU%B-4KyEbo_bWvoACsUlm%dj=sc#JiG-)3n(?-x2fgC0!S(iQk{zK8XKuG7Z?|&e7 zRhBm6LzCKHb;2lVA0JZ@CYQc6`OpyH0|T}ioWV&*!LFXMw8wUCQQ;k8pG+zmEH}I z8;yN`Q1oG1$gf=b-iF+0?CU_KllGl=41Gz+jix@os_3J+2wl1Cdk1o(u`hB?#=eUT zbvgC*L2fkpcSzCaJ%+w_A=fSVDzNtlU1(%7|9r>Lw-IuqvF|lSUxT8L-hLg5FR7!D zYgG*s&p!qnr_fhnLcRx`Gxg6-L8tOKfLjwdf&VPWo2r7#$N$8Gs&5(^?Og~+`kI6g z=}RQz*k~U~N(W07RZFTXtKmRt=?Lf4m)0z)b<_3!=hXjnK99&er`|=D|6`t0$H5Tw zd<$EYjC3!`B97f@_NXW_1H6vCN5*T(L_j+Icrzdkc6ny6O5m3GigrtJ3Nyv9Zng}<25Y4t{v=420;&y@aZepk^uwMbc)}%R=llsJ8%ILKEoeKY5^O^YPF*>dOHIwG#p6+FCIIvM@KKSx- z;7o3<1^2LJ!2ekZ-(um{v3B6(jo-MOENbD`v#WqVuJ8ved_TJdI4x+(@ON1FjqK~d zX`xf{X;D&M4z#R&z-htLxSZ@M^O@4$%zg>H-lX9)wE0Z@RqW5eFEMFOcEo%pehWXT zoJo_D6;a0{E(eyF=K!aLRO528QVYM0Edjn;;d?CnOW11Qdldd<7XD@Y^!S|$KVjit z&QC7iqwwjM0p#UiS8$g*|E%!uvhc5D-vRzdg-`vLia!eekivfg_+bTq8h9qp;5`I5 zozOQfCtr*;*MQJJ{2qK-7?%7$;h7eQCH@yYPf&2$JD16GCmRQRn!=v~e1?M4Y4uqO zJ`cEC!Rh4pJO!@-o+&dYy9oF>3cnF}xq@E|oPNzg+Iuvg7jGu#*{As|c5A_TF znZR#Fd^A5HedKxPQs9(U!dC%rQ1Bq|9l)i&KHxVh_-^3jv4d7SDg5VwF99y~KMed! ziu^&~zl7`rAwLNGI@sqH_)*{&179TY>BzY8z-9iF0pAN8Z(}?@5Ae_6S;oH__=CV{ zS)c6r81T6$51F4S;Q31V+z9+lE^El&4g9OHSLXMadcZX2_#^o+u=_7)TGiGr&lS_N zI90srk|tlfuR9V-wnTb6W4&ve0vFQ@1f8f&`nu!c_3Lred1S8z{N%dzK>G*wRWPqp zoPf6;Xg}euAo+jIU4iZGid+`hNtITo1E^Yta|D}H1NcNR=r*SY5aV>4Q-dY&abVD` zP7RhII)iSFcZrO5vDJyg5*hDeYn@+W#%p!rP;16(b>dKK#%rzfwPw85^wyg3TGLxA zlaUSNT0k80Z)r@pa=Rd4JCW1 z6V1rBS!gYR)oo2H8v^YKuPngHsh2;dlc6Efz+B*q&bvI3oi|3 z_?BcO+?!s#F_P@+j$hRlSF(@ zuna5Mkx(j97VlVBX1*bepd}oQCCZGT$u5ybfFwrkOxO?Eb%p#e@pn70kcy7s#zHHG zLj(O*4_pzrJ>%+*xQi0YtgbDRkC3ASEjsyiZPKiLO|!Hhi*hFpMXu-!xLt4s*};xS zgyV)5t+=IyJvugqSZqKEv}%3Blj*3!;$-uczW@0BR}LH6-WJp-ryD-4j*1VHCj0H{C$_r z+B&1i4}1kHE!d}(th`fSI5K0;mmALCch76%SpDo$4F~6EJRh7~QrF`4L*}lFc^)EPul{JT8xC_JDW)B*&m$_M3y_2bp{0EUnD>T4A2+pmUM)7p(M!gA}WV zgY84tv(h66jQEMh+=nSGn&&cd9|ETkhl4m)&ou9lL)+4lSat;II>~=BkD25P{BHiN zEpi;(TUWae>3#0i)AC-&w>5ouxd%Fmf|Zcj`^pgD$s_R0a@yWe1ZNxk4}2VmH~-^P9EHgKZwYP{AQsn==hm6|M`~<= zfac*~KD1ko=Vx336hT5SGPFx5&iKPxRih;V6i-G8k5x%i9-i@sSPfzhs|*hWhUu3f z+s5j=Gp+r}i@sF`aqDQeodmJ|#xFo#c&H0}iFUmB+%DGU=(l7+;vY)+HbVTPH9ivN z-#@XSIi2v`Vyo|$j5R{?0WgQ?S2N}&2;pLa_%J)4AmTfNAU@chN$~SxYcA;L5I#d} z&4oPQZUcKN1)Xn~fjr-q0(z~W^KB)!@Lk6A(S@&NlAeo*j}OE?f}qzE#KL6*!5hVP z04!`SC;ZdGR{$24R}+4{*skCfz5?zv4oZ-oj}X5^{6g#(g|7h6+lfBU$Zt9wK>1CH zjS$?%kNI;u))8LH=omhC>l!DR$K40;{N>v&5Pv_>5pEN~vxM(}Ey8yIGV3~`BOMUo znYW!F_`3*Vf%gW21MtR6u-y2SaCV3A8Gt}YGLIi5EFv3Tc1bBr=b4VAaYqDSCRinW z24FGxYlK7o8w9Tv-qULguetOw`a49g6+QzX{|Mn*4KKSyf0S^@eP7V`5j>Z%{RAQZ zLxQmHM+8CtF+s>bO%U{-61-4+w??855biP7yq^>N9Ap1M5Q!cn z2>btwU_HE-6GW!{fuJAX0|?&4*lPqK_a}l#=bs5S;(HdsPvSckK~$c%2;RcjI|Q%6 z_g;d{_^v?^^>3IU=)A$LqV5yVw;Ai?RG;8xgqQz#g85k6CkXjT1Y6MV2<|~sA{aos zBZz%HrxI*Kl_rQno=xx)v_FEMVvN@1>0}Xkz^8PS61*I{`w8wuJ0pmCRxbDuJuZFH zM8p%stxphr()h7GgoJ3!>ts9yaqBRmlOX!J#nP{e)C@r&E6g=He{MPnN`8o7C0h$rvV z&D-;L!SsTYcR)(huqbnqK8I<;?=d}4?$!epxGQll z#$AQG8g~uuCAe#GFLgTt73K7=g8o&~zs2+q!u92PeT80Msn;*o>#OwoYQ4TjuV13q z*Xs349rYFExGQj1;$Doq3U@WVTH6vB)kZoNUoT|c&Qt1mQukp-Ezs%63maE@07n6J}K zBJReqja$tCn%D9-x(4}1w?Y_!b&;{mfMXl6QW(*E{ERT)ZJT9ItQJPB8e1dOuE?C= zT`b~m`F{|1tB5;r{Ngs7z#0)ZR>j7$_T|j;OGVsRfjeGtn|f-!h?V{!Zd|80+R;8;x~yqJNL* zVK~qMB%jL90F1}f{pWyP4rBd$d<2eW2*1i$_a5J6tZR>7Yn-nlc^&yf^5kfUaJRte z{M7g;;vg8qObW0Na*c$qgWZJZ!Cf%HZE#BrShF5W$i#;{{eo#B){%cf5GC^xLCF0< z;BjMh#;K@BD=}q62V6R$&MEZ zqMYbFj=mX{<=761;FCyRIeil$wY&{L8{*+#Ft}SGSd?)!jtN2m;nR%fLZAJ{5k3Q^ z5S+<_@-{Ys@Y%vMk=tm7^qCE-#2$IIXE#f^M^}z5bL@v~;38&^v5Y=)CK{R6|nSXP{%OyW5j-=z4IE9OK zG>`KMNA<@m6plxW�(Q_6u2=^Fpg;ye9 zJXPNc1l;Em0t%q=Q==)IhEI`bF7|7lP3~b-i0O7A;FQ0l&nb9ML(ZeKAbQ`d z>sC;B+ZCMeK#t0Z?BHz|kc#JS+^XC@$k7oylB2Sxi{$L_{<36r@%qrcV7CY4LyFGi{F z!ZS1W@v&h9`&L12H1>T@(N}zo{Cj$o`f5ru_Myu1D_45`kQ1YZUA_Hn4rdH=6u= zT+z2s#FNkIzjYoGZO+ zAU7KOo>25vAH%+bki*+W)@8S^5rrW0kI#(|BA0!aL2fkqo>lbmxzz~zehay4vaHMY zuyqCIu+qNsggn{z2yS)w?uHzaoORjd?tt74SyGJs1hjDqy%?2=;-PW+0zuD}FAE^o zqlA->_I$n_axxvBW9a)D1j$c@In+Z27x$Iy2- z;#T|T0=&TQhY-m*6}h+Ztj7Bjyx3nP_$tVQkgCs#!Q~auNMENAq<9n2P3?W@Sa(Xe zMw6b=@QK)sKU~KDnyM;})l^l(XBu7a?-}j$Q+Y(DXS8`_`QPXn&3c+S>*#V8p*=>w zHO|k{r_!PD`o2_XZNzer-tcbL8R_U-+ulWf1v2i=)DUCm?JOpW!2quhtJ78TPPS9w zJMc37X$7ZBaR=}zCe6w2GM}jmPvkqZ&oOCE_FeOt_(goDHENl-oP32@Vh(8j4t}5{!F$M_@@+p zorOP(T@3vD3jcBoe>RI*@B+43!D*rL8U-hBJGWSHqw&Zop7fS;i-?c#uPO3W4&Sxm zKeFL3*zlKa_}ex-4{ep2Ht8nsE2jfb;dz$8&jXHGrs@5KJiS~DyhQMOfl~{dDR5dL zrzoVpyMR-j!kY-!{{ZlPc*Y3C@v-&RV)i>DxohFh60ANVDk|7KG-|^=g{3iL7&gd& zN|UZI-6&Ye(wBl&eWi4$VD&&zDZMHnl%l&*MrrjwQ7NN@BL$1Nj1!4a>ExEf+PN)Z zaR1WYUfAY36`?maBsI^*CTZv~TsEU>vG%{7Cznwx;IR z_PSUaNBp^89B+3wYq2pJV{4<4R2nDsA(+K&N`a9@ZH`}+D~K-|39oMnC1dGLN)UJ> zfaig9W2C<=?oEYbF@w~PsbEMc^=)ZV2JL||n95lvn+XrUtt}FZnWXnJK?pNM?@ZD{1y3am* z!0}og90R=fvXpRf34{Cgfgf-#9pR?~);J#j|FQQa@KqIO`*Y3>$t7%I5hE(zgkU2A z$xT84EA?g}5DJ0`C{}E4mKzcXNk{?$E`-emcWd1jY_%@6Ra{zaKMF3j)>;LZ?)}8t z7OU0|EGpHO{GVse%(-(;LVDY;iNEjv>%h%>o_XK%zVFPL?VK|+2g{QOh=5#*&SPgm z_M|7BCC}jq=+5wt*2jnM72|?g^MdCT4NWc_X6?5IB=5J9S4Ae-bz^6~bB1+bk2qv~ zeq`B~#)^~wv?o~Bx&y-y&-&b+*8cVsm+Y)U#$Vj+ILDa#k!JC>wm(+ka(orV&rVWP zV{kty1E?J0og^3j$@@BaYnQEFkK=x95CuLkxLY$#i*=DLoUobX{@uTG%bNPz|7`QVOXm4-WgGRYztZhqZ`{zy z>y3-hm$qfQf%GzDDpU7;JNK zoRw)!v}g#oWWqur!w2?~u!QM;fGZoNQ;^Wmb4$zx`Q$s>Nhe<_4d^a%) z>;t4|pdTh3=d6eyi#F6VBMVRj~zj_Mnk6_jflzZ1j@dN6$<4~?T--QUCEBhW$REKWUc;0}3xl6fL;h)AM zckY#m))EfQ0+D^Die3yyWFP1i>o$#N1>`<3WVG+>*Gzp?$Wzm-K4yPLIelI&YVN;$vXW6`cAV)qirX}dU-p(lMeCa5ofDyQ|4GW4WxB;*qDZ@r<9{T4${`mRn; z-=~H?GrU?$Tk<0`d+|K*LfU@)6fqO=7BH#0@&1ty$@V{nM#)WQd>J3^~Y%B+Z6Y` zOIW{g@xFJNnp==31rvDh@;#@8blI<2xNF|MF$cH#~T-c-+7&N?x2Ix5d#7Ci%Mz`2c1? zzYNUA+X=~Xn|F=)X_-F)?A8%D|9$tE1%IUYJMeGZxMaCayN3Lf47Zort0Qp!aYpG5 zh@-{Hz`ry2+=gF=0KWIimoaba2%InH^(q{|ENi}uIb`r_eYhU@Zw9{wI9|h&#TsC~ z!*oKj*ns1pfw$s#uz|mVW4U#XJRw=!1}wMGQTQId1SF`?nCEwV-@{)q=)m zUJbq*@@^@vwubgb_OQ=*Yb!p{5UVS1u5ZyBO&hzA8(dRi)q?mI|K7O6FhsG zQ&D#f-ASj&H@l%prKgw9EM7D#G--arx+A?@Pd+}u?w=u*=?zPY`bRT2rqiN%A*alqlYrPW^atXwJvjA@jHRcub+><#l_Lg zHBUcjXQoC|GOVZ=SABly{G?2tlX1b`^Tjyl_^x%)bvxcpi&zfcnYP245ZIF%#a_+P zclOy6lJ*RM1`Fs<`vMd8?GZpWc3nP%U46SwAK%d0AU-#HyR*0M$_DZ78G<`aN5-bu zw3OS>Ren+=STe076g_}Fe65Ddf=E^L@IEV(ueQcIJ4lxgY!D}v?sWF!)1Y8*+yOMFWYXqGnH+$3;k{z4Whi>S*U<)%+w1lwtN4~3oT?{Pp`As zOb<$TR?4SNcBYjM!ZY3w;!`I&QwIj2&Bmb^be!7Y0?mGue9%_Vv7mR5f4uYBi}DW; zL+^u>L!12rQuzEV_rwKWPYm zEEGrdO?+ZikG_G^h)LtG)AR-g*w6scd>8>WaKd@|!ABUfYeV_sWo8$YLW*i7dwvvg z`3M&ogi~Y&q1l!F7*3V_7+OD>VJxC}c;xI_fV4rC?BCEz$c%(a*`=W7s<{|EhzGW< zJq0Am@mVn`$MpLH{gP=^3~v71iNrF!ylxEiiS}h4FaqK3BqZ02aH3@wP1`zr2N`oC zWc?uv5vJTcWDHt}Zh=LWax$MmYamA-b@0ak`+K=2281 z&sB0dZ??({MhPcq9p?h__#er&D>>(EY`y_~XJ}y1O+L9_L$1l->%(hsV7?}pg@VNE zL_d&4GBEvj;b+R71-TF$rkpI3pp^65Jr7;vdc^yK-|k0{({^zvLr?mWA;c%-{@~ZQ z9&%crtOGcqCw*5#D3N^m)X*pE&=K?vg0V#Ood-GXpDwRG`FBZz`u<|*V>8RplRm!o zO2oew$Z7xd7_29K>l4)XuAvW2vkX1y`!qp)OK}mje`xlOsP8<;C6eB^41IbCO#dFo z4{brKV*wwPgwtF|?SU+@|Lwzsfr|Ucp#b{i7h;|FVMU1I$0_3hi z9QBP;($v>hUDw!RyuWkb-r*fxPphU1rshs})=&N8Ra4)-RvL2O-hD{V|HV~P^6lNy zww6_`VsdkfyCll^E@ZcNcikfXZ7=ii@YsBw9A9o_JY*J=`)<8eOkF^S9OydVg9r0t zCPo68K8zPSCj+QG{fCve*vF5W&wvvD*d8MwkOL%D)IY z9zWDgiGL0{933(XAo+g)y$nB$wIu!!G>jhbI)zhFZdTwJV>ihk2Rt9gP6bXDp9lUs zY6&|{>YEE3hJIEY;>Ez0VJ`;!P4IMj)&f6i;LCyU0_LEJ=idSRS400pz*C`bg5p09 zd~Lqp$a;DLsJS*)e_ML;ZgF`dT-{vwX$1%Y1jxuX~Z z^OLW5mnqEru@JisxD<(T_{n0E;*(hL`Wg>DTHLNM*l4_x<<4U~X5cHvM-4tx`5j>9 zr4y3HPJL`DTOv0QlUkP@n&(NB%4+zuMqG4L)}@)bc;^$e%6cFEaSQ0>9J1 zZ+Ya;5g!0=Gx(o+_~#1lrum4$$JU^32;lo&nZVyO_$Pb#)#4Oj?!@SXWKrVb*NO_@ z!3O^v4?iZB1E(4M4iA5+*bJO&@UQgn8^!IwPaFJic=*f3cYvQW_&YuP72;*!*9`tI zJp2~%Ht_EZ{s9kvrR@7ZG5D$IYjp@v`QjqrH3t6@5C1}OBk;opf18KDUOWu^gu#E(!`~o&4E&10f5pS! zBz_0{dxQV3hrdO93d}O-gk+J#frJVHe2Qxn@KA$)yoZ08m;^k+;1_!Mmy0ss(FT9M zhkvE00v==V8$A50#Twu&gTKMUzgAoee5%2}#l!!KcmTNA;6Li&e^opKyxQQu=;7Ze zegk}y!T*DYf3x@y_-=!L*u%e748@(=BL@Fy2{8z#9N4g5>sB?f*AIBMWO1J@b&W8ek@TYNZe;6cEx20jY7!@ws1uQBjR zz!w-eAGp)NGk`Z6coy)b20jD$3Im@5e2sx)!0|RSS+oG(WboGl-)7)Vz}pObB{17q zCnSp-f$uZ$UBC|-_?y5F8~AbH#|*p^_z46582G;o{3`G+1OFEISp)9_e%`|UNi78;9nT{7~tO+cpUIv15X0}y@96!zir?m;P(vtMd1AgUIcv5z*WG9 z4BQC(Hv_i=%ZEQQ!;{5@z)5Z!nJlUJKSmULu=BV+rcU7VG=?f4o}v0@%|Bb+&uILN8oz5iT#Z*X*3TR?zS*bm z=RW*PAO5Q9Z}jrGdX>q?gb5mKzxFRRmvR=|KJ#AHLp)zv08*_u)N0 z{1+ci<%2&JXm5-Up9EZu{ACh2#eEv^N(0XZo@d~*fM*(b8Sq*IpAXzo?-fPSAtAIbn`K1as0lx+P_%Hcf1NK`3Ukm&?uujhtz}a@DgC|88#X}$}a_e3&ym* zHNZcDET6BFe>L#y;OqSQCiw<_4)`?WFHB1Ly}*M2wEuqxeiHSG>*A>ID7>Va3S6vk z9`Mn?y1bMEzY2`gqPhnj9|6Sm3q5iR1;rY9P zk2d_{OS3=V{1X+QTjlefP}>gyUyk#&{Q}^%ke{aH=K`M%d8m~7qrki;ov3gJ@O)f6 zU7j`q^99-x#lHo37Os!h|7~DCgVFi-67V1Zef|FcJRCTr&i@2>m?3{OUdBC&>!I`W zWZ>@uFHrI`fd2>b+TVr1e=_hgVBX_GtxV5m;DNwd3f~002l=7X{~+)dV6AT#a5b=& ze+^g$l(*qXqsed@GYP!PC`S7~# zlqJhz&C45`+b6X*Rj-aMIj^N{d3$ShZLEFC%r&vvRUIvDlX91EUh{%yK)Ld7&7Uww2H;NaPmB_8e3|!u} za&~od9hOWOk!N9-uo$)m>nQS_?J|t`lBPCnPG&^NeZ!Qt`E3THqNrq6tfOL0Wk+>K zObH-PLNMYn3)gtpe>nS}8JZTgFKnsoXj~C%Ti95;yrjBGC-JQ6#*VUB zTUuP*9%~nEYtE`}Td@$yS=25%OwhxEs=Vp(1yx*!WW46hcULTV*G}c@J@vRs$&`0D z)$^{N%0I#yrUEQol1sCEYnTeO-8^S8lWC&>wtcUt3%p(z=*3su5zz3iz+Ewg^;bsx z6usn&TLqf&dYM+9SN{~f=!<&@n)0xVH~Cx&=Dft`f-iLh&FTo}s3T;GbHvoEBRApR zjGf}T?#o z>gMJaR7%+lb)ccEt;S}A&b7|>=H^t_C2wv{bzSmi#Z=cNZ&plmUGiqdG@TVJY=*1T zwA})4R!q}&SqM#eZMVRi71Om{7ED8ax@*^)-s!GgZ+fS@cD?DH?%MUHH=OGl_9i%- zt1VCQrZ}9dO|!%su7-29?J3?ghjX>@Dc(efxjUw;xl_EU4!dg`SxZbC?h?l--gJlE zm5x)q2@i)|I`4XS#um!zLc|y zI1FFPS>PRpFXj2JabL>wUE{u#v#dI*d?{z4l#Hpql(TJg7`~Ldt>jc+%H3uXmD!V5 zZaX>EmvR;k$A&NEZc91UmvUZe=L}!U-G*+eFXe7a$NFzxLAR-!=1aNT*0E*qoS}_R z^QF8{XFJ;r^9;ASo90V7vq+|ct%>Iho$b?nDR-MSwlkhHT;sl!yA9hkU&`HRp4-BObG=E=bDKEXJbKR2S3R8TO?;l)$jO$|JjZS2!nxk$=ef|cBCHg>X=_MGG90f#0Yj=lzLz_Z*H z>+uEZZu1?EFHv_}?r?mOdORr{)yOgxjwiz1qd6RR-`$`&9CtjvJG0wBhx3p%N}ua2 zhc`}~+boCUgI2di4#x+qZetwIcQ23I4u|6dRksNayMxrQ+xmvx0czN7c*E@f9beow zH(cP_aGTq3ftwDur46&EcFuJh*)aQJ6{lO7Fne1S=N2>erz+09yi;5oZi5ID;HK3$J%DDXzf^wo3UEl1}|!@!%Zh|HQPny*_8`t&Z{cH zje7-F(YIsRORH5?aw$;Nir9+UrnUkPZe1&iW|dTxSDc~mmU%O6;`U+e^AN1eim(2a5nYC5iO<`3>Y~dR2^wAc-X^+P@c2x8bUAcBeO-qx9!wr~~ z_0n40UU+ZtWt7KsX>3JHo!m-&esjf|_E>dWZNtpwj<&VF6OSb3QHE&tM!%QMjb1hbITgnU_!YgSFzY}MkRJ(Lt8oOjF;!6(94P~ZN#ecHayh9Gm)km ze4#_1w8l}`V{xfa%+j`&Rw>{+sjRWNx~Xwp4AsbZOruWf9H=rTG+C14ciWrVLq!lLaH4RT0R~7*0_c%WnuH{>&eDKJ{06; z_>Lx5gMOT2=8cYv`&b!UX%r2_BY*MiYH6%PKATe75MNSJLcueun^fGw_(P{2lVbxi?Lw$jHv+o-qS5=+ohS{3{xEJtDSSA?Xtk-XP=C z3yz26r#2Kv2Q~~GIMA}Ndrs%$;y(IG4t{A?_3RJ+xUwiZ|6s7%it5;+=R>&&O(ix5}OUYV_4_mlG z8T!D-*|&V1{$Ot;~VyC{$)Y>|C!D?9bEs_~wUswUs91UDAU6)f39BP;N~| z8IiU@ZTKz7jf(q*zBqK(;8U;9$d=~;KR@)@Q>EvT;_TS^9i5L`vJB{Ron4UrwYVK` zCq?A>D67e3$h9Q=1|;nrGi>3Z%+NKnf`$1FBT@Q??0)7if#{+`A#w8~&-^8&I9Rf> z!JhE$tMuW$eJs~F+KCi|bjcK~CnC}y_yG@cM5Iy0EpzBDg?B-Q{7%rc$8)oyB|wqw zpKLhr)PZ9x>kM&Ban!!~n3AHJv>o82FT}itJ^YbCY%kV*uvP1X;2+zjT=g%*FEyR;sKo(M`v}Wyb_lD9d93sSeZ$a{_jGK98dVX73~=PAX29$D{TS92VHk zSpK%9I1;1wr?m`_vGh=KEc^8xZx^6#3Gblyj!#9h6gzE$F4JrUct#-mxSc84N!ivO zD`evwTjuQSDE7AMOy6#0qLx;p{L1U%=!>A`>tt%vL@3zl)S(@3+YuY~T2cFx%AD3^ z$04y`{zqM{TZ%{QhIBOd(v=MpkO$5gQ#yszO%LfuYeOiSUACImk&7aV}8;tCGR{vZUFvn z%p6{FQVFYUS~R<{SfZ>Mv`Hy7KlP?v*_qb!B=`wmv!Wpj zo`z0vJm@NCnS)H`HN`3=A+a~DtZQzl^Rd5T-i#|3jD{{v!@h4!Q<|)M^d={^19AoshmWB1(gSi349v%1YTQ8pOf9t&!|e zJ0JeAbG@BK&C!xHv~kjglW(&jm9*t3nTrwrJ?cZT-rgf7zPCs0O?t9xUUpgDj;``c zqZZmnw9X7^!3h5e{Lp7cp1|)Az7SPV6pZZpW99JMfY*Ia3=8H4BiXIk-)==MCQ}I! z5jg&x*o*Ch_r3=mgHi_#x+xlra1Xq}_(k!15qfsv*My(kGcO5~q)PGQ8n-(97UGwM z-)8(&cmlfi;wMr$Axwz5A{Z$J-Ucc*b#+D0z}zZ?2ch$B{O-f=3H%<$kMXyGZo}^} z{BongNIHJOR-B6q5e$J+kKAnse|rfQc$`v2%Bg>(m?KGgt6-%G|9aKgOE1k+04zBFVNLYg z_t9ACqWIY-p{*e0gh&QZRyu(>qnL&&H-41O2Wo37@g%kB5!Ok_soObD#pMQEtgxKO zET>q8RmBD7++2Z;E97kYd}ppRC%}dnKU}pIQ=B=))FWMiez+zC;wO+oK9>~nP%Ss5 z$RmY(Au0UhJ{9~kjTG{yk|KTv>F3pVlwq%!7?CBUNJKd)(mRLrG=Wv)2$&E$pA_+& z+bW9GW>aX577^p*Gf9tDpBx7`hj^pqtPfc10{)72^*!6c3NT?DfF)( zg&(b?kZ&h#v&3rBEtXhAiq`RbQtZ)x5$Oe%*g(3*5*tY|;dc}1jTTn5A|PM3lES|$ zNpTUbA+58-wWQco;yO~;xq&oli5n$#zM&*mTXL@y>iHVu&$YzYNo%m4hZKI@M~cF8 zKPf)+{B6>uLVojFG+5#>VkGi$(k4spQ^FmIzDK;ma=shg?0oN-{AU>t{6ocmfpn!1 zKOx1p3U-rrV16*^a!dS-^gQ8wmSL&o?0c}zng1-7S>ku(Ux@kVq{z2@r0bo{>_oFA zKljc|{4?XRQOW_*J1ys%Maay*DEu)g%F`#LxK5vvZc(33xYcqh3^E<{R|wz%r1d7mwU<3j@--* z7kNA}{6C2l`X-Pf{$x_<$x-pSq*tRJk#4rc6jBt5Lefo^IEC~ps4}D*EO8ns%29;$ ztEdX3S6N~vDGE&)DeTT6g`Zzk@!ZRXatl=a8KgH0Q9*i{CC((h73(WVue8KDq)7h~ z(%WT`!(uf{R1-rliZ1-L1THnog~cKUyRztEk($LKB{#pprNyE)i$z`zInULk zw_Adr!=OI6hD8F%I?`J#akGlYp{y({LgE_KHx<8)bUTtldbuU;A$?Rh-#SOVe}EX3 z>YJonEb)-S50irb80mK*LV6+U9Vs>m`W`6~`2!Wdll1#S>{9X1lI}qLBW<K#n_Q`ApV=o?P@GO83Q^l;B3HbO^}Vqwm)q_3i1BRxiNbSUj) zkiL$7jdUc|fT;M-k^UV09O+S5%R%}}bgiT(pk9*x8f$7u(NPzY{uW&u>9MGnr0Cba zKsp3n7U>(PpQPx7OG&FxKS|$2{Uk;EKZg{RN$$b)dkp@Gzk&Km`ejS-+x6V>vw{?b z?o86RQ9nshnE5#q@eb-IDb9H9*o zlj8jINa4>K70=J6@cau^{6(bu(Ug{F!H#UlCHAE zPZj?q(gBuunG}uQtBU^`X^JIYCtZ(vN{Vvy8&Z^`H%Lcg{VM4|OT0;Xv(;~V?!vT) z;%84(W73oRZ@*u3myYep%J!tbwS6?~=|J25?`Y;KH*)&c4P1RUaF`#(&(2e}!+mSp z%mR!~x@AFuawETQ-8dembzm0YtEx#`0vBVm_hNo#^|_a#h_nlpGgF+~6Dz<|?4+TV zJ$Q&nL9I%$QvxZ2Q--Car3_CQkuox6RLW5)qcKWE&5c;-OHL40*I{8-Oa?-xT}`@tca@H2kKA0u|w0{t5F>9{=R?4}?o|?b5JanrD~h+oc6|=@h%P&@P>7 zmrk=wrw2;Ix%h?g%fl}pzXJTG$n|sf^zJzs#0R~Cb}$f33JwS+2UCK<;J{#Na8Ph? zaA>g84sNi68|~mGJGj{nZn1+G+rdlh;H7r(GCR1{4qk2tudstx+QF;r;MLrY-VH$< zMWXm)pQ3VZYIoy0-~7f?U_7PMPT63mY_wB0*(satlr473#dgY(jhm$j_nh5I6K)1^ zt0L^r_pKWkp1Xm^>Kg*H_zi(5u>A$)$Be%9!>rh;uq$mxlpsYiWvJ`clV>0ip|IPq%I?Phoj1^Cadhw6u2HtH{tRs6 zvS2(W>}&hhwt4524tw!Cr|XpiU+G&1%#3$$8*fmyzuJGc-I4fB%Jz-@XWQ*AZc(;x z?pxbt8{}T}a(z>Fn{wjTzIDR9M=h2m&wccW?n~DFJCrB4_pK*p5u653r0s3W_MQD_ z+bsrPQ?~EwTidK|I`C@5A6i6#?7Nj0U+-Hl%od1aws;Hl4duW+ed~ZZZap!c4Kfez zQ!e0r_+qg7ZHSlNE4|7^R@ryo(axA&iI zHvY1lKc;Ly+JCm)4);6C_TznP+k8cWmuqs&t6p`@!h_4<2absArl8hBhQcD zmFb7G-&4Lk+1;1E8ga7|bVl6&rHp^SyYW6BasNQs-qE+V%_g50#C%k-OS!PKZ(T44 z9q#?_)5`W!{b$?lZk|=PpXoo_Zn~dSwtv`vw%z9Ed1V_@wEC-ycWu9*Y-2iBzuSIM z+5X9AVEZLy`=_6Q?cK`u%l&8Dtz)k!+j~9(+pj6xuYLx$f2M4|-hZ~;o2g$Y+duyd zZ2wBx{^e(2`!~w=ulv^avFJW^NXLQu=x~mFk{Csl{ol%!-}bF5W|!(Vv3r&6H~QAL zIii>#v*Du6`l0UclnZb6tqbM=H%q$UK2V7Q+J8`P{JwA9=md&gC^z=^ts7?R;8e|c>+l!l!Uz55!bF)9aTh*PE_~RxF7((k98$JF z?pxdD6;MwZ-S+tt<-%Y4)&-i?f!)){_yzcz^5E0%9`sdJWb^1$#V%$1@7<06JFB93 z1xCTRdCx7JWrFtMzIDNT)U0m%)igm{Ie>Kri{V>eJ?AwY80+MLav(`LfCUYG>413= z%6u0gS-F6<6MgA|`SK}Gx?sKl4=N|HP@^xMFqgxuj&SYaHN zu*@^hT8=GggI*$4bjd2$rK94kFJW@vK!VdZOX^mI@3a7arR^WnFg z+VGkib()TnKI5G}-?h6w-)YG&LD^}_=S|9IOguQFo6pQNH{SZb=8SJ z){K@;eBbB9MOa!&r||6cU%6!IJzcW&9xoZjKAz-b@fTYq8;iZ7zXqg!h+Ic4>QQMsfD4CMa&b559pn#m7G)O>brxk4KR~%*mUx0R&5|FDFC1=( z7l=n#VlQZFttD_TBnn4bT<0eWM_F=_bKy}I*P)3*Oyov$BnpqV#EGQomdGVN#uBH3 zrnXsf@o(W6OD^h7ZE+Uml42dGAiYXathW=XSe$x?qF6sD@wXLy1hnv2ENTOtg3No7 z@msLyoAJk4;uoY?0lk;;XjlHI=zEHOpy)@Sg=3Kp(i1Gy1<2ndH}MdKAxn$}F3iAn zVLTRpP9V;-9*vL!wO9SeJhL8qXBw^1*qjK?Mlp!EL~(6Q%Q;tQaKIVhK)_46%J zs_DX$0i7*D6HEQeL%%OLJB{A09p^fo+X7J&w)}u zKlV=gdr+1ee!RV~0RE%xV!HUTcJfCN!w-I(o&1oZ6F`~10`ft>KzywwPFMUT#4AzH zh@q#67<$$aPeHi?tq1>E#$yru&q$k5K1jEsQlMeu`GZ005uc{$C`Hp1?J+Z5`R?mJw-oI^b=CZ9aeN~3hbkOoD9nLG7ofYl_esegQlZ=lV6SNPkaj6 zC*m(#qLcXZNC#;BS(f~`H2GJMzZi>z$v+k41C%=z+`xF$>#r&LZBocR20Ca4@*k9X zUIZNr{jZRJHqu23{5wV8R`h+)L0`b86U5MaSkbJYgR?;gorZP_wEjy-4{^j2a}|F9 zaS`gJijOiL_LeDrGvkXCRkDE>9%mmr;>)PED>vAFm)#+PEzGI2Z7MLZMj zv7&>K_o=I}7@idQK86&JeL|pv%Fur+Jed^NBf|Ju=r2fTqrU^Sm!RB`-iysUNC)A% zlV&*|!L`R>Q9j$Q&p|KgiD;Keap$mr6rJ-z(i3pkM2e9$KX7j2?kY-p3~ua5G3aj~ z<)d25P9P*DAk<(*G`?$(G|kG=*{l9yB3x;~i9C?Bd~k43Ps46cr&boW&)P0}o`K z+yDnjl^fn5JLN_eOYbn z6IC1g)ToVp>YQOVH+(^JDF-OXZaGjxF~;hCxmN);j!+x^VBmsoM{d}H%ZH63UNq_8&9l2q}EaIOEF`M*dwUN;twUN=QY9pi9xyu{E&+%bg(qF2v<*(HS zN554Y9KE47IC>KsKv3@YLR6Ce5p|68ZME^yJ8I*j_s|?N{(a|(1vg|koA?7+gycpG z=MaA^i;~<>;auWR<=#VbV}vSV3^b#p7B+ez4LD<7ZeUPLjQd~|HMt={j1*()dQ$W$ zOG$^KFC-miiAK^iwXxE0ODrcIfj*LSBsPd4#TXYwQ|_|ULOL2_7t*6G7F85xY#c+1 zF>X8Q7)y@11;(bUh>uenGhr-x9`RVUK@-NBYl%bXTS(EDollCfG3G+mzyQy= zH{k9*s3IuL=*vhk#<`LdV~wjwF;+m8K__lG8$(T18$+Q_zmDeaW4q=qt97qHjRe zLt(a@4X4J-Du~X5k=`Kdqc=(-3x5MfJmrwh-NGQm*hVb6OR;y1b1u3*8Q3O{#Lv_> z9rtaYLm%f4$0EWs6U{?&lH`|i+A&kE3k?antZpHU7|JCp&ZwzqR*ihnsu3;Qe(hst zk?IT7dA-RoeLD0e7tunXy~%YN8LH*j?hQB2*ZxuTL6s4dEx|8{A2#F(a)-%Fk&Y~2 z9h9it(9P6GIi5#--#mi8&CquZ z^l=x@ZIH`OKp*9_zHc2t-$CfR4|0k4M>(zUz9Z=4?xGJvuBZI-mp{rG#lSsIRPKvL zUNSqVPnRWPeS8j%>8`f*805@A9s}F`MC3LqIiABneSgr(ohbR2?V{Grh?`3t8b|AVCZ`m$7Z=Y6><}Ox(NMp4Um(4zE2iIK2Nzi06FFZ z%YoM0Q@;Eaa&nC1)8|h|JqCtpN?(qW?MdHi$R(1`e>U`md(roI$gT1DM(Fo%6$Y%@ zzx-bGZGl`Oe#Pu)md@>PU}VA7Rbr5xKF2FUzec|O}`91 zU5{alvCo=M7olI@X2|L5%drhZPx`KhoV*usMBKlAeIsyVrS+kUkfA4inUG7QJYQw# zllPF&*pt3H64aOarMQ3Pz4$ibp2WeIFS5(1aXOAGg#=B>$Qr zr~O0KJEFde64dvOp$|p&i26Q(T)X0%#9!Z5d^zqPE{zO5UEd2Kmq>d5WaxtnN7VP% z1og$L;{M_Ai27E6`E|uNi9fyR(YU^9CD>DXvmuvAdapP1)%K$A?gaIv!6{u{V!h}K zK`xQ@`KyLL`3wm51?lknZ^y1$`kV|BI5UPv&r{#O{FBfu&_;;J3PuKUJ^gWoMzH}5i zoqxJ~^`tKwa*6nNy`k^CUh?m5$Z2~@OcHdI|_}c&c7>r(KjA)iTHP|q3`Nm^xc)9z9BHG{kygoeaAyC5&teT^nIll zeK$i+w?9fu5`XP24=g*g%bIv}Uh`%o|XHYccWzoBn?FZ%c* zHWB}tAgBF%v=@CBB&hFgL*L`Q=sT34zB&x*w1402MPCQx5=rk~L*J9V=-UrDJ)Toy zlK9)xpNiR zd#V?G79Kt)lHL`N)BZivi@pmXmxzA{4ShfCMPCvI|H#5_!JpoBkkkJCs26=(A(x1M z7H%rEz909ZZ#d)<>CZ1R^!=n4eOEy)5&s6D&};vG+KaxUAeTt_yVTJ4axeOBN>JY* z44SlmdwS7#EaVa?f0r2gUhPHSjgU(uy{Wiq)Be5Qi@q_CLs!!+_{-lFhQ6QoqVG1y zB~o4nUKIE5m%Zpa26Bm{_X|-*0=-cRb`0(RY=h?~Pvc z-2u5o(mT8}?%$ie=*xf{x{z++PQ(l}VsGe->w8PZ_cWgT2ILYc&m%U(_5H!n_YRH& z>brT2&V*d0;+y1I0LzG21-UO7SRb-%o9TENa=D1(xbtl##B})ebwO^k;+w>;Z_~!O zKKjnklfFkGx5#08{`&O=H#zV1>EC-wvL}7nkV_=J8zHCD`+hI_9)Vn|$1?}`{mVqA zM8Kkd`yCOP-cN9B=5r0?Zc1_Fk`1{eTr~W5!zY)kj}N*r&cO%>nfmUy0_A0Zqwg5xDa1lVTh)#pEsYII##sQ z#hS$Aj@TMR)wH*Z$#vBo)skDax;|Fb5UZ|>wTY^#(z)fuRSRZTESz02v#7LNL{(#R zqf*-5QC+)yReSZ)7?j0oRxPcnZ>wGb&=zaz9zi$EGm0waO|I_fXltxlg*s#DlEi_orJ5n>fi5)ia@9#1DAs+*l}$WnD1J8ZEucr^H(22Z zL5JbTD@y(kK>10mQxw)c`~qMs9dthbh+~ETNOn#o&P8`q{lb!S%_V_60sgyU=jQ};vzACF_MGIK(* zI1$GM2F}6pGz0VaR09{`IAY*A?lH4zps#!k6z6#OsiN6~2T3>9tMbA2;$nk80^I9; zc)Jfj@58_G;rD=9M{x6x+Mg_jCONZF*KY*wrz9E{bQ-EufzWTE3`7h5&O%YmSb z_MI?IMNjoe=jEzsu#H|nFHc2J_eK|}=rB$*#kI|F*c-2nhM~`p&(~Iw3{Si^8-^iM z-nHvZYd+J6fzLFNRi{1kCOhBtz?<#@*8^|D3tSJpDKF3-FvASb3UtczyeTixcA1lg z{1k0B4=IAjB#@?A9kG>?Rmb|oUb+KYt76rM_6li^Cusg zS;FI^$LZZhi@56k5v3eJ;;K7k9c8?tva(#4^EJh*>g!`|#cNTli&mq)$s(_+g<@7< zq)GwbITbO~3|Ny}N>r_gt*C8XTOcaR7S60(SXCTro4KO3V=dIz7B$x`YDF1{v8uEi z5|te-ts0iJG}kvS#c365bW}yG6;&Kjp7W&H9wO0%#44)m8e1GqtJL6KrJ=ZOm~87PId7rsjEwN{D?8d^)hm25CTwXn&uD1{uO`-3j+A0dA7d**T)Dil zRbBuOm>a9_kP$M|Ahxijqq+$#S36@Jz^kU^WX#OAww5+LASf@Y2o;@PSsp6MDLMJ% zP)W;**2bn-Tj+T2PpCR(@WnzNIaM8v`+^bY@vae%|6);l*W(=FSaG znpD?Vy|k)*RcmWoti654g6iBUxrmK5Bffb?Q)5R*Q!F$I|0mV9u9^|wL?kq+^z_o1 z#fxTzCe3eH7n)QaZ_jgdd!Cb1jTV1ttoa|XbJ}AoAu>59$52u-ud=){r@XngX;mG} z`?#gC)s3~WoXW=F|@rLDfTt)-)- zwxuZtS0dKd$V4Y#s{48Ws@WP8A)KqS^q(``7>mWG<>rN_6#OF%3FhLF67ObG+~PkJ z#i$`PsU_57id4zZK|zxj-nrap)^l(ZAFFPU<+Ri+!{t}cHF{RkQ$bNz!95k1b5dQb z6%{ttT-z9HpRuB6UH_azb)iX3{|-GZlbbM>s;a7#qqVurjJCC+6bD%UV7(hj69+a& z>}cyOD^p~2%|5)ZYc>{z4i)={iPl-2k9U21xJzVzx`%Yf+rbF7D3VfXk9W=ODi1Ya zjiDWiTA^T+63N*E_H1j2?2m|T66>?mc680Q)--;dx2xwY zE3O{6d_#3td1}Mc)h{f!Yf_gN*L2Mp*|4dmvf-JUuQUW|Uuh_=owICX?bc;a*S@gK zuIrjJqM^8MYs<#Et<6u@iOj9_R)*EuI*T^WezdE+xZ#D`jSZ>MryJ%(?Z&OO#f@`n zy2_t!OpV&hUZ^czmRh@M87xGfSymYhEdNThWcjPnjmx{fIH%_6$nHD^x!(@k6Ju_6`vksGtEhJgbIT2_>KwV@Wd(U5U)@5-Wsohz+q(Xyib>x+sG zuD6P6286oGgHr17J|`EuW_QgI8Bf&?$QT}#c`b9)iX7fY2`h5|G%~+v!`h!>4LHf( z^VEv+l#gGxn0pNw`y;S>cwei$CIiGnA0#Dr%{^xCn~mb6q@9@;hzTQhc4bjGHinDiGWp_necTD5eo;Lsw^SWj?)bQN5mxT_tM&GW<#??MS zWJm8?9y+*p!F{#a4QU4>^8x=>SO{|FJPOA76+4e#hG7nyUaw^pYv zn^Tjv{owC#6NR2*UEixlxJBxM=n-fiK-x>{e;Hs9VWy0dlw8xXmXqmr| zJlgSg8gdWUp(W#BXVHeGPf7aJQkJF6gPp~xC}pH`qE^OJ(X0$BIv>}m2!C%|xdA0U z7zsv_@WaLskt_j}_5>Pit29GBup{&7+8UVHWUY~cGChi#9rEkb}l zI}qTFTCd?CZv|E0_FNYK*jTwO4+A(1%KuQP50nrkgYpl>$(8512TBd%waP%6Eu8;| z!GSX32qw9v)EU-dxYbvC*YSp42R*=AXlw(;b>jy|CL z_N8qUV>j?Ymi#8tZ2f^QJhqcg4DVYfP}kg$>p07TqY?pf-m=Z9(F~N@?R!}d>tvAs|T$w$Cwo~6=TO{72iqgPVsLb#(8`}J_rN#$3W{bc7B3X1H(OC{AMaMOSG(*kv7_WB1Lt~o8_>|k1!%`v1XHgG|fQH&kreHC1h zlRnUo%a^ZkNtWFZDJ~;ilVv!Q6qjWjX|dWB3E2vl<^31BBV+CWffEY!fsb0iGA~s; zw<{ zAg0_Vi~`I~NK4}qNI7}^aeNcx78;Id)wmS$J-cSThYN^O>jo`{8Y}gga_D2-pyhB0 zJpPS>bDBqCeO#gBbRMSr5~0&ro1olUB?lq{^q10aQG# zPuATd=o<;SRW#-c{(QOA&?oCYbP@XX4MKyU{Xq10aR4&A5J-?LTC#Y`#lxY8C+j#_iM?tQ` zbW9!l{kzQ27g91k`FAtq61g4&(6DR&GJDZ?6yy@gzl#lhS-t4H0dk4>#~VlOpX@uJ zv#0cqfZTb?o=LjppP?_i7yoXCTq5;tC^|yzA8s#X=*hpakV_=JTMc~^d(n4Gg8Gs} zasO}|AVW|7jfUJB#W#sR|E_|ZPH(Of>`C7pkV_=JsTpy7d4|64;~0HgtBMk1Ah$>Z zgZ>1^W_#ZPxxK2r*L^MhdmTSSyJ7w~wHvP+;~cyNV(MEBxooAcP{~qXTYY=1xjmNn z%^k$;*d1t&dd(e^M7$>wlgVP&d>JFt?4$8rd!0nZDuwMn-h@YQ?QL$ zNn&#U&fgw}EXEUIj0=+GtrW|K#<$@Z&66BElYbwMIev4>eKI#nmi_%YQ1YJxW#Cu} z-=C0kA&YR#@=X4lpzLc$E4&|+vReKSj&V#x&{ObnJ z_hxxT^RGg(F_)V9MsVX>Id{?#NajYiZs7dxGd(y(oNHjdKk(w9oZlUBH6$BzvuSU% zI1lHy8GJprl~J4zeiita8vGj#dz=sc4Pe`iOBN5g$2|WydCM4|qn#{%KmH?ac zp_#uXj)8B^k8TF$9A+mZ%elDb{OC^b&H2%n0f!9v>wwMq(YFGd^P}$uHs?ow3)q|= z&0A=5e)LXYbAI&mz~=nuJ-`ve{;z;b4g41HYybW~9_ z?x8+WvnpccTuc;OQBc-Yz0{d#>Ya@H@0_&Eu61gB+OKyO@Bg9c%W^ty82RMur#Ug# zALW~ptY`j)^<>_#o+cdD(}dmW-JG5*O}Sa~*-t?B4vGG$>BcOqb6aYcmtaYpn&nki zQ8K@z32~fguj3Z`qZZBe$mt2jtD5Q>S7T1UTewm5E9&RB*Os-#R=Sa;P6^iqzP#d$ z+11T;nEL8U$Qq#eu7cU?T!BiCTkHNahxR{nX!SxAW8$)R=4JP}ut%C3`j5{0&m3AV z^vTI_r`!HJ=FqA;(4Ob3dasBx**ZRlR`uEc<~g*E*8lw+T9vRw=g`Jy)QX1IS#96p zyv^YUtYOFPEI-bQG7hss8`8H&#s;HePtA8)XJH=gY|Ji=ip;L^IW?)(snKDXbE2gU z3%84mB4-XQblg>9MV;A>X*<+x(sGM)ZZXG{KWj(p<7xW`iy>vB%aV5|WvA>8W(Ri< z&K|gX@ZPT3Ne#ihoHdyw|60y*+2AKdsC5TsIL=8KH{#ue;_RZ#GBHlhuq?OUU1)9p z^x%Q}iwkzH7$e3H%e3}Jf)!)8y?agI_G0^$R~``)KH8Jl8cc89G3ihHXC;+wd|1!T z6cfkpy#7#dTOc&%9WgApySgE~T|BTr&e*JaM+^+exx^xL*4{Du2M-&&r@8?%IE%-; zT0XO2=l$;1G2-Y_D$E06&Vx3>@=haq=r0%5KMF^eb_zI%ogj z)UNrr`<1lGBe7YyzZJ8N{Z|skGZ)#H!`*%dP##z1?RsvK zxC?J)lMw%WWN0KEG7p1BqC+D={1)K&LHzE+ZySCEr#NT2b5}V7)|oYnqxj@kIf*sN zo$xAWyAH^gtACeaC1&NTg{6t$Fo3Uyw&7GDb6e9gC;7;C!Mc8^96t8 zRfL@xjEA!kQs^roou}r*hH!I9e1`fQ7j7Qs5+i+3CH<`+g&z3;7XF<{3}??GJzY+H zmFF)ZhSTSgLVq z?>gMTvaTi;oymzs>NtvM8}&=Nlis)PAgA5HXS(s3mUt;B9YCG#%ltUnHSf#`FB<8c zY=?G5x`8I7FWr#Mm2!p8qKZeZ*&N)Ga&ht{11?RvEU*<{sV*M5ItmWIcPTwWBh{B4 z$p%(=#HU|HBiF^hC@vkzP>zK9))90XZm@9_#m^q6Y$M_!Zzc1;0Z4rs6jZ zzv-bsML3s#!u*rRKl%Iv;nG~YG;EjV*`@h*X@Olj#V#$hOQ+hU)9ljefzog;eqsFb z@XN=q0KX}6AYf1Eo|8d*g*<2n1Hq)=fM9YkB^V4245kJL1qTO*20QKG20OUX4sNo8 zo9*BhJ9x1jyu=P(Y6mZ~gIn$3<#zB2J9woXyvhz+tEt?2WJ zP}3PXB1mXDqvcFzWJ`jFV8TMrC2TthUZ+|^EnXCB0RA{bAM*6E91D@d7#&_aHW?#1 zj_ZaDP4%|{uN?!X{B-?MLxbKzfH8%zk%Xb7CpojyY;^EwxP*-korQuk049>6kl;`Z z0?1Xgm=vR-Iixvi(j@$@A%;*hC?_FyfXZ)9Gah-w0mC5lBpXRFYWf;!0ls|>nmQX# zv9mGfqOpCoART%~DWK>g1$K#&;6K zPfn67gx|Lj!_Q~Qhu<%e!rxyoei}YaN;=({!IX;1fzh&@WH}g=lORVC<2;P6Wj=(6 zaefvl25Qqtlbp9-^=DuVNen+1f>Q69pqzx-z<8viN%33Bho2XaqIg}zc*t!eJ{5b% zffmldY#|lTZ^v`8=-tG~w}**OQ2eOe}Bpb`q?I8%<)p-xVll*Jqa7-XBA z4vEVo2jx&N3nH>n7CdB|5Fz+OnkiMu!LF>IC#pBH+3F?$Wi*X)xW;m{fV{*wO%`03 zk|Xy~q$q>3xkee}NP;WeWao~umQIW^Ci^s$A&e>H3{8wNON(p7y1{L^ z8MKbt1m)H$Ijw{GHfdnc%Y1T^ zaDkc(zCOGG2eK}xh?^nD>q&ogAI0?Fi=QcXKjfZ(^OQsNlYw%6yVa-&iP-%q zC;#dow^H#<;@9`Op-;9k5bjCeA0T(0sYo6B^(}!C?VoI;j-amzavKxS_r9S|wsA+$ zcNlUksc1+CSMw;)I^kdkN$cxxRlf^o5l1p7aHf8LRxx0sH-113B$qW-t0K zh1`V+=o^5BQ|rqz^nD-4x(#9UQIMOc_$Kko6+w=5)gN9&gjr5sfE@FI^&H)y3_az` zE09~E_$Kk^%W1gyIvpn|LF#)GKeV~6`rP@DtJJ`t{&ai|at#JwANtdgiVigwOr}HU z5A7bn&rI(rkmIcenB2I_0;sI6^Z z+gz)s8oGPHVxw1Q_gCky-UD`O?$mHdhJQTMaQ6G9_h+)Pb16Aq$j(wC?+J#J(8>$BRup}eqnK4k}BzM zsW8^Bh(YJ5=1d=6YvAl+{Mp%z@ja|Z~p|Nopt3b}SCa+yccSltBeO25V<=a=~GwJB=kn$?w z+G#Y5P3mn{G>7SIq4oRk^n8mD#Z-n;Lp za;!Dxh@!a*Dm?{PRz9zybncAu${F=lP1vARQ3uQ4-8V<+;&rw;X{@ZVrS+_;rLhID zx9Em7$L80^Vi+fUZY}V0Yk`i*-OqPA_08tu!M1t1+m{ZlwLtwkIEc-`Ubi~wXFp?m zfm-Z;yxB<$>cwIpZ0o&erH5cU4ZD8kUA2KbROHT-Qtm+!2LkD|3b=E>Xy0&PZ>QL6 z4_IF(){3#PESLX4$-F(O>1F%V(ydOc&mW(@qpa8(`_s5sM+vVjOWhl?cSN2}nYC3M zYwz4pxNd8(Bz3Qq`q$@UA#*=#GvH3r7Mg+wg9CWy+5A7m9b=o7Nw& zuZxtFmIOP74o=4;i z+Xw6o$lWZZGZwv=y)`o9oZkq!hbN_EXqdYF`VA303EF3bBYRTg^Y$D$=I#R_%RZ1a z^wl?<9aG=0?kZi}I6K-kd+`!`^n+EfGuOPh_S+5j)lQ6GG4icy`?w!ezqRz{Xi~@4 zkvB)JW8bQVM%!Lr)|GtZF7VZgH`DC9-yC4?seb59jLIQlPhDZBZSSc%A^zsl-+bZ9 z!htVX;ZT!x9Cv%AcHA6K*=r5nH{<0UV#2QNB5ZY7$8j&t$2X%~=621S)+Vx7Y{&kf zIopx)_3^H`k$ry=>!Z8t!WdfauF8(LkKA3od+B5G$QPKxU`ZHu`_`OxL&YTq9m}>^ft}g$HYCjak1kms z4@>Ptcv{o?x&hXmXa6H**si}Vv-XCP{~38NWzf!VW|Yl%Ic~r3jTtGwu{ypn!+K#| zq5Xn2=Ap=#+R~B9$N%N!ExS8!%E>4liF)_8b>J}AuH?=-SW?V-IuO{2>2?||TCR>b zd!{xV*w>l91!ps&*rjw=ifAnhMFf5kEX9VxfrzvUh%qMTH>*WjQ9J1fZ%<7Z(_n|t zsTavIe{AfUyZ1oAVroYTLWo?hf&3GQLoWWy?*wxB z1Mxux8UG|g5c3HUUw`IV7UNKkla9h+7p+dcI&@9SwZS#X*9ERmx&hk@3Wl{t!DA0p zc{!keb&~n0bmGLwv*E$fNUAefse_`(2HStPsn6P&s>()zO6reX zZwK&yQ%}J+^^|ryWtE+BrJZt>owC|ax!O*-#!fl-H+9)?5Gmbg{LD>6ShJTZfTurI zz}E@avHfumPr_0aYQI!sOuu~IuS9&_&-?6oWbZ?rv}fl?+zleX>R)Z)%e}j`$EoQF z>McD`*>!O{9E;XQe}#_;!bX>a1W9v{0Ac|0fL}=XbvJ`JnD_-D9|%ij09M+O5rQ@- z76PWBKYExrR*<(5qJMjd;Q=A@q4`bQf2N3Oe&pXP^%ml21)yiaF9CUy!Cj&{rn zQ4g*$*;p>2Zp3*uk$#@fq+H>Ax%Paqw(*R7AAkqaoJB!){_?$mOl9V>--cZIty8{2 zka==B8Oo$F9EriBGDp!pN{c=aAwOxeQ25;#qU3jD`949W$WPT_^{E<(kdFmH9-zW|@iOU0l?^LTyANQ#E41t9*PXqJq>LbnRUWkNN51 z>)>NKQD2=u%(uIIeBS}zqlyn%Bpvzu@m50EYDG7JKi)rsPsc0kGMIak_YRn@Fa;^U zUtTjBfR-oQf|9oxQ0F-xy%NN6^!S{g@B84p&c{Ra7xdpL99!2R-mWXNNOPe*w# zmsC!g$N z0m=6+er7$m`|zIojU+Ic@*V--Iy_5xVf^SQFAd-ITI2e|9=_SR-}a{T{B19HQeK|( zaqpAA?JYQ7#^Zk5E2QfG_P0H*4m&p-{eS#%FD7$R|JmDhDZDgzz`l+j=h(NfUa*^{ zfqk$LzTja;U6J35#Za>s4{CKxRBY>PNzi8mBv1~`W zT~Xej4LU#Wy$w9NocvWHMvg*;Q4Dk^kc-=fOA0SxS+f+ zQe#P&{cdt;Oz&v%a}S;+2Y<9fsh@w<^^^Zt@ps@IZdg#f>-tI07TjydfuVkWkn1P? z1Thl$S~n~x#=3se$4Q%(x4B_Kaf<6FeS(++oLeuo`~|L`^c+zG{0=uPD3-Z?((~lD z&b!^Pp#0dUr6pkxBIAD4px^2G`Fy?{d;P=>3yRIIpY&Vb1Y zp!sP)By8Z9!=Gi~*TT=OubO`?{NoJ#cKCA){BHP7gDnraG$u3T>pw!`aSuIJJm_Ti*b)Nkj-PcwAX`CO7>4^W$cpgIzalnW30!r;T&KTvxCj!qzIAfwglS1HI5&vj~ z&j-$T^WzGS0{=GR=h%n*7Xg0^xPJa-;H=XczYq9Vf#bjAe**X|Kma8EDm6?M`T|<3o0On`FIlj>N3&82u_@9AOSB<|9oQ_4x=lk{JzBA@I z*q8m&Ds#Hoi0OWdrTl1(@6X2P=-$83`)suw{9C;#QGZ+aeTCN_*nI|H^jCH~WeCZ0 zKec;rZOn5&xI>)DuOsE>dn4SvWRdq(`gRZSx!SZwOV?bBH%Ah8Q+hKw zaW|zmPu#mHY5&F0+P#~SdmhYi9j|ZWL*i~qZ>~(ydl|Sh!jLmX?`WVY88ck(Yv7g% zGu(|=7YlbW$Q=-Ff#kV7x+wbPrb`*Ao6nPVrE+t4vaU~V-cHs!ySX|UrGSF}lv^-n zU<*cZQE}0nhVtshLYR@6@0zWdRbrT}(VH-|ff|jw7HhB*r(#xRQG7mbysc|kBCX%3 zpsI$3SiO|%1jyU)g!2I7E|0ZhpGQ&s(gaT;Setk9vnv}>D!6V*c_VIocO>~9@z6Yv zmDX~{5HF6zvq~W+ETMjBOJ39DnJ}H>#B}<~2K@|7=*a6gz0vi+;E8iiV{zTegm^dY z&W)Zb7AJI0-7?&S=_N>w6OS*fZY-~ASQ0C3Sy)wHS0k!dG&j3tATcLBD{w#F#S$-< z5*)myx~AGyprWdI3CezDb>qycx`r}j$me@zKEGiT#;ABr_2+wL{u}qqsFkIE-!_mM zo_(g4fgG9t=~fw)q`q1O;%*46qR1OHyJkgb1!&eb`L`W^oqY;V58|DV*73pZgI-8F zK4p90g#i319ihx%$H2@$M|!5+5zZ7HDVZXk-kBnjwr?9{WhebU&|$q<5U@L*#XR*! zxr@cw+rT(~nk=P?r$a+KQ(%J#G1z5APlqzL&MKk~&?=R;TD0TWG;{mrpxn=ZJw34I zGP-1d#Kdto7Y=&adgYqJv=_|q#|i_lSTAoVw0IUo%jF!($i*gr*U9t(`ZE>-$JzcE5 z|9~y`R^Z$9y0Se(bJ{?=|3I1y`^El&>!(%av}HWjcA@AzP2@B&RojBYcICEVr^oEg z2Rb{?EW$yEw0g+h(7=^}ND$8C|nC9C-U}@z8HFtTE+nUx{ou@J^?A^US0l9@xA0^if@< z1LNZ&MSJYLfl=|juG0s`L4W7GBhPCq+;i3F(M4%8Kc;TccVGVKK<8d@U}#~@m~)FZ zL4WaB>8P$*cKn7>qxb!Dap@>K`n2`3NKLcjN2PKvO487wMOHL@i!~b7d6bnNYqXt- zTQf^TxN|j>(N)TwTH8i#+k~9oijRw+S)&8^+rC)pr^^d4ldND^Zn(i;p*`Gu zBTfH+2Z2B{+wV&r~sCp>&@NjK5iXT7h)(~=HP6x<2G$+<_ zN{x>Ik_04;;rIY6zk4B1<@YN5;XGWNtG=<~dl5br$d4KLd@DZ&$#vYt>Ui&2>Ub}h z!lW-zM~jY7dwHOYT=mDpCy>5WZYPp_xx|q{d4yO@m_)cpeFud6lZZp!DTH_~LKs)J zf)H;B@pIHsUVJ>6MI6u1QQ>n5GoAa3co$|lain_zA>?rFgkS$5O5$LV7h*z$RQ`O0 zR}q2xpAA=mtW_xtVaH^Nov!k8UH5#D0|!nf^6G$o&Q( zGX0x`koPUZDMG9#jH&f-$UjtdnCnGR{LK4c4^`Z36Ebczq#Ejgc5%q#M#GbFqYWPN zxUmQ-<3@Y$&$x#nZ?$9l`#;#`#A>G9Xn3Od*&|f)(T(+I^3Ax}&C0klRNUw?`!jBc zcU=TNX`<|p{>A&Q@kb|cH+xI-7Wt>eb1PsWW=V1H)4 znQr%GK2F7r!PFs-dxDA^1G7UFH(p{+dFQCOF$g?Val3hr(Y!2g3^WgU+>=$@7}WM> z+!!OdE(5-VwZ(j;07lXMU;_GHoM% zinHS|4W;xV@l%EP10eAa3Bebz0GHycF(99(fhWq%B98cvB|J?THbc&wMEYXvav_|L za!~LR@bYiDA>OgxL8Z@?_IExQz3$BEB|K{&v)I>*o%(^1dx({T$eU~L6v zX@I;RWgWwzFAbQ{z}R}i1u%`kaKv*T;T-1{*#UE55Dxe#45c4eeBAC${%6PsInM%e z+xT|kc>cG9XE?iAY`!U-?cUw4lJ)HWHV`~6mk^Kza!VmZ%T)wqnOs6(J>s_Q6hgcZ zLxdP2q!JzhT?mha4uq&zvg1a*!-PxD)>+S3=`abBvv3ZRxwSzyy5qSU0S+CyeAl9L z9Znn_9iou4TXuq+)gmf6o6R7cs*IK){j9%ST0qqD8rhMAs9#V)E;XR)OCx0%u}LFk zVZw+yp;X}PkPwAVyP(^$rB*>uACLrTDH-o5 zxnzN)NDISkN3>v!BpEw?h&T>?T#pXbPslP+RPr6cK%Zm2%Q95qr-LUQg~ex4jih6q zGk;Ba=b<2zWZ^nI`Y-d*jOGFq;J0L@&>RkAKAC(Up&(_MdD)}|Y4Yi)4uc}ah9X)t zid4$eq=hJWSr?Q%&4;eW6YquK(=@VbKbn%{(|OY%D-t;zr**#oDE*(r*Q)rOr(yUJ z^6u4$0ayF@hN0rt8+7fx1s>UkRKOMBV>wX|*@ghw*6zm7Q!VKiNkdM8DI)*BAXBG34p` z+LM021YZl{@;iUIorDfY>xZI|t|xi3!Pgi49ya8m2oEan7k!kMhmKI|ha??TULp7{ zQgjpe)BBhq4_@hdO7GJkt}z8EzhB;&=%BTJvX2HI#dT%LZRx>iunoJYCK`$-AeI z^3q2q^po#kXxNjyF!=hS-;IX6oLM^veKWU-VmT$m3Xnt|xi7 z^-&%NLb`nO9dSL%O9x+H^!t(_Z(1+%ZUoD00JKu~@`ThOI7Vw2Zv++Ac@i3qNj-T1Tyb8V-Er(B!eaQD7eh7BmW(+KKeR2cg z34qCz_gC;WDR~jaNO@_^RW)^umDS5us8c@f37`C)PxwrpG8Jck=sx*`&oLPM!MP`V zGN}5eJmKTrM%c}eQ@4Q6%y3`-UHe-nb4UN#+jWKZ0`e5jH6DC`^To~$3(6B);|zSg z>*w=>#Sehr;f4i0r+9b`?=L{xWYC{;{e1o~@hb4`Zdg$K)rao}zSE$0!q54;8tfUc#lwYlAh;UH>%kryZ|F<(ytSⅈ8S3Bb8`S4{v+%#E7{^KZZ_{zh8HuC)(w~cB1#R$2>P-1<^#gNw!63Tp+vbr+s_P@?cDk+!vUGYvCURC#J zH+_ z;i1ZB4#{NPnB&w?2jtVCikrhf88-?{#*H%RhtGQ~_5lN(FA4)tC$fQ$LfPjr9Cc$M zU>d4PTtN&|B;F1<3gN32exrix7><0qhY(AR_X7?ZvwVE(kU$-u$(gJ8WWK=v zJ@9oH3|jP5#ivO(AulzJVcO45j{4~|-vU0!jPP>&v~1!J zg0G$)pSuCLENc}$0tLkUr@kyJI@XCh@H6?21(70WpRQ|^_Y8h!x$Od<&R>vR_ac0zyg!03f-uTs$4Wa{A?AHR?Cn}YkL&h!UFP~(XM&z~k%ZRv6@$)N@ipK%Zdg$K zkL&02gT?oN7rSAwkm1801wPB5Z-al1fj{N?DKAAnp9o43zfT~bhdli`*K%x>HtQ;N zSKqT`8y}=II=txQ+>XmjZwg*z!s4n#;vQZgVgSa996Aobh>n>ufMb7bBkb!8lI%X$ zA2Y=;Mi`tGqFAIO^v@JeLpsRkcmA1TB?R^5s?Q*@rY|$aqrg{YM5*{WG?|f{*zxtBvBM%Kn++ zy9f*`J{>>#{P7-+=}ceZT?IZJuQ^lP0GTM#CIIPf0p9|R7;qc>=FI7DKr#@3w8_mFZfp9(|n92%vwYXayJ1^L4Z@c5*9VdW1;MS zB>9|@CC*hhwqBMr@oj+GaentpjR4XD=Wh+1b&c~YU4x0gX3%MYvlIA-ZkY2eUZb?I znF7VeQ90?H`Ip9MVRMvAV`z%V1U}gf3yR}iKlM9YOaor*h6P2$^^<;tmp9lhNnu=Rf_`ci!cM?i(x)exY6I z85Nat8mpJ`Ho+eDIdG4KHk`IBwye6o*@HG+EXqsD3(hF61Y=oqBdww}JEdb1j6ySl z%lY|rMnh|JV?qqev}ZYzVhZ|v`^D#r9iK0D{1-2F==Z^=SnSY`ezuDpTIzqg*rDb0 zvek-E{_ToSXSbE&i4@El%mM)}31-9tdZUwy5}?OQl23En!_zS+)%B`m~dXItAv*xs@Qy3KnpV67<(Y>kZk9x#ST3sRsmwe6dlX4-3p z1!irX9XV52?dc^=Gut;)#I zw+C3^qv?-F^0o*ew~0hTk?5JuBrGEuimVo)2!>OUv&#tS-ulUN9}udgq(F{wKO4e4 z`$;seOi7)M#}37s6G!|}{0@3I8z!;x>pa#}c=bgX&vB&4A*DR^bAqz#grRAe;iw@TdGd43Si%YFL?fODtNe_3A|d`vBm{pR zA^7?;ucS_l2aY4*!eJ}A-^o^ZXzyg>XkR;y#uLZGQJOUfIF!bPIDLpRPSgS!Hww5v z3uGYT(vB4`il2>|C*wwC>d&~%jAvy|WIU?6Q~{_KyGZqB7P&ULeNyn0A~z+$=9Do5gT2mk}QA*hkABCB#bN z$iFu7qaXPaahyWCjX3&`or=yC3esO94mo=i57q>d_te0yDL!b3e|npDtOJlKfwD&dir2rI{RA?kFRR&g zP{gd$N?f-y+T6EuKNF`M)R0cEX6rN`iwu=zq3BvweyA`W7vsREWsp_-=PEw^T#hUt zayU-QxBw{qpTyUy_?)M)b^>{mG-ANjKE7)3)f;r}y#*d~b@zGjv7D%f?igA3?)LF< zKh6flC+i^mn>&Ne4bUn#C8hk4pvghwDz|4AZ zt07PCzoWc|@k85a(huJaz6BaF;4k1e<-HHS-3Vj7((Q@zw&SPU0KDRl==1ni@Vh@C zz?8QaOzjAxJiG{`qr9{wv4&W4U3Fzs{9^ef!rc!xz2~nGlP6Egoy3n2efSD-*Oz5H z?tZYJQT0!`A8bi;Ilx`$uJB@%_?v)Lz}c&k9z;3)9{kTL zJO}s~`0+xO^pk;4ho3c%{4;^$zuf6Xd=Zc;18)X?I&l3w@6LJzxYGiiQ+oFT*Yaqo zhiT$loAP){@9XgE^!x?*Wx&}oNPi#rRqzKCKA6=Uj<^LW#{x(46rL)k1841b=&90j z4^S6B4|F*UL70Vhv<$ez>)`Fcwd0qaYd!c7kHoUo+@m_RxY;y8+ylJAkpDdo{S@&y@M{eE&pq_h#7^LaZdg$8 z?knw*M1lA_@HK82?!JTnpK|C=uAunXrLnyfi9w)!*$qQ|c6mvkA;tnE3O9ZL4*Ef*U#tYi93P6;)Vsq zeXgJMGX?M7+U=Zjx^@C8!VdOeIle*M)$KTGTb{;Wa&$U{Fz3nHtuaWe2fxM4vt!}XJ1DJp>HJL`C|JkR>3*BUlMMO_54~Ef z2A;tVT{?WZ_t0bFPT&!PexHZFL_7?9jzQn*q1TD$fnVSbr-EV+@EQYu$HTu=^1o-$ zlc4*D20qYD3)8<$@_%1WQJH|C7zz5141BDIzftnfv85&H(;_K|jkw zZxKs?hxD`r@i%$sD?~eRp73y7P+aGsUnFh^zS5xI?V(>RHUYoUp#QIjeyR8s@IM*! zogVsS;xE9DDPe1&ETgz6TcbwlLmbq@TUy?F5u4^ z_=CW=8~6`_?=lVGsQ)A_sVdL7(oSe^rzMUt`djUnX7-`i%ztJm6~$oNf6w178Mw zoq?|eeusfy0bIKzj7*tdCjDm6w;TM_$HaNsY^OoL3;2r${-8(x?NYu;|1s$Ia4;-g zP*A>!{|xl|4f?YldEb=sO!_OJKW^~<)x&?Mco+CH2AzA~v`fOR0)x@F{LP>r;r2Bw z-@C+dz;igSPu*2^5|pB8)Q-x1BgGYmTO!^AHIeWXEO z4Loe%Jgui)l6XMok4e81^b-vJ`#k&)iHCvb81$_k`uD{1!1E3Iiyrz91pD%cL8tyE z{x;~v2K__evkW|lzH^R&rvooD@Gk(bFz_tkXB+qg;EN1=8t|xr7Xq&_@HxQa2EGt@ zy@5x8HyQYaz*`Nx6?mJ0b9M1c2EGP(yMf;de6@k!0ep>t-v|6g1K$9At%3g-I9IqF z7ZgtdUuWRY0l&k*Uj)A1!1-?C%9nor@4)Xj@b`d!*T4n($_)md2K+|`KHTj~**-SP z`exFzK>xA9Kf%NQLvgAHA0XSm){bl3WghxKQSHHSrL)B@GPgikj{1hL)MYVUAuKGWXzi!YkHT35i!3{qAn+A@BGw~e*C;w(2 zo_IGpYYu<%(RsR4J3c?$?VBC`#JkMFPxH|i`tW5w{Bj?Dix2;n5C4%5|G5wE@Zlf$ z@ZoOX>gYShho9!dD|~pB4`1oSSNZT;efW2M_|rc8H6Q+t421!t`8D_82C-V7b<)g@Z*4&Dg0l+zlbqESGmbQ0-5?N)ERux zlXx!hT(n`RB=H5nyFh0$$ln6|0pMJdBYqR`+V+y738^Djo zdWM#liccIiu)~^jXZ$jfIZ9e~X;G3Zg*ZhcY z27V-%vlYG_cno7Ou8EPp7x+d*ex<@Qkg!{ThZQ~*_*p2A3Wd)DJ_&f1!Y>5QHM%^7 zUjdx=(d+oW0sQwUOkJLvf&UT6*^2*Hz(0aMTw|j?uLFMz@;52`BjBea{m3>+KL(4_ zsVL7;3O@z-0i;*w_qo7%-~8i>ei85@q^CsTw*kKk@sCsZ_ksT!xGukEfG$pLDBPo9|1blmim?he+cQ(@@j$eK6i+e^oxN{HOli= z;JLt|lB9nh_+|rt8h9pft#1eL6Ak)%z<-B_wfuqV6BX;rP}Z87lNMbVYgk&>&@#TI zzG`J`(M65TOIvUia;#<1jJ8{S&R(#QF zSTeV&wK`r=wYWYexKCPNn@qp5BX`C^s8m#sed=Ygh8jFlT7IUpkJ<@UkN85JhZBKi z}L#~NA_0kH-$)Fc9$kQ1?*^0u?;uuK1< z84cK?UmcI}QeFhks%oxbP)}wGrzFf2`u5&y>w@0v+j$GS+(GZ#c&~3=_ien_m#*jf zuCzy7?mm2T|Gtit+wzTY_gZycX>W$>X#JPfyYYI@86+;Z_a=6d8?QID?xpMg%jyxY z^G(xz(3^1gCU)kR@4F-KWcLU8qJ=P-Jv`=MBzKBFwcx+oULSk#-)*n0ANcRK*T*e* zFv67Y#_P?Vd^cXNp80OP-rA7w#;XM~gN=ytwE`?yGu-9(CVZ+^V3N09Ow|fZ^45!~ zT7gMkBb!s*c)baq>c;C$_%t_OZ^EZ}qnqYN2RTM^rs?QdkIZl#-DGbvr|ak@dy_d` zCv&nl-sw7CRyRZbbT?jaGN-%odXt%(<3{XFXKs!gv$p_qbEe=>3f~}A4GoRx{Nzid z6+KrqdM#CZCwp@vH%F^A#hV?uIa)7Pa3dYL?lGMy-VDiQKOkGk6mO2?=ISh&;?0uW zTsLxWp5*4bk^3^mJ!3S*mnm#zPUOB!anBh|@ufUZN1pFXd7h4(P0URBBwZr;zLc}3 z%gEXIJWuG9=TAD>?J%;=*Xw*l)3%I zbYGt4yXyE-=61Z(eJOK$UiK+wtZvtvo1+UM(Y@s6KzW%ViJm1lN2|w9MN@TFCpwMX z99_(b{vwy-3P+yXRpcg)^tru6u4{BT(Lv<87MBx!L#}IXIngcTx)SjcjlYEUSU*%(BvXm1T7ea~o@7w5x0$Nh~XL(owpK}rs^9n@*NdblAXy# zQDZ}G-4ZqVC@C+R(cFxp!iinXq8tvHLdRQHQL3j>YHAW&QrCjnS84NdJ)_X`n6|%oU9lZQa5+;pW`bk>mpB9yOiQ!aW@Goqx_56|*Xf;uyol>ZyPe zP+U}8R32+Z%2g%PHqT@_y+@NL`_3j$7HTa5*@8pGOMGZ$OWh?g&k{gU6+5B2+KUUS zmwE|~TFiWN$-vOo6D(T*`Wm&=;I1clAJ$yDo_m)uoMr?eC3S7F8dV#5jHRTxYFVt} z;wE2OwD^Tp&2^li_aLIU4z0SC{jO@XrhK(zpwi$`-An2@d3qUR#*7)$a`JL91U7{` zh1rvA52a_(4ohjzlF{Q-Vr4~VswdWx`V}qliZ-X|JH3gQ&YbKaD`Z_W)py?+y_T@c zbr4nOG*;F0qRrfS#WUs}G%dP=??GKnI{34)?<;RBXmZwSN*ih$XT|E9V$GiHaPkT7 z6m&Lurj)AfKBb#~N>s4|3#G?k#4HSbT}( z+oO3#TNAn=uY5^By&`N};q7!Kt+WM0yaueddeo96XYgXCQUzncG_k6d*u=)g7wQsm&L#Ebf{*T{sY=Bo>a(>up{k8k@;|jZVan>o_Joxw zI*+k$iNIn+IFeepA0`uKdhJm(KMb0%;zMC$V&vA+kycd1n`R;`JrvK_sO>p4%}n1M zD4{(CD;(%N##%#(=^ww|Q|RK;@n3-*cSg%Y+`*(s0`o*$Q?Rm_+9@gs}Q#8XcM zXKf8+wj;)%0JYPyuB0Ym$!Xo{JZ}}cVOLnU1{1Q{b17@yzHJrr;|MLI%%4Ic{E_xx z9Pt(JYp-eF6A0$;I+d;f_LgTy>*ArJc(i59ReP+!n8>hbW@JHp?4G2g`O%@sJ(f{Y zSaQq1LHRdX{v9d*Lb_NT6{9mto`{~g@yz|BbH;4^S=`FHEi$I)XVLPJBTm@&!o1F| z9LhMDBwp|`GW_xDj-?Kh%ZcMC8Ph2FmvR{AQJJfv(M&5!oIfl4gSP_~eT25;rO(lo zz7+R){mi_55lhHWl+#elrEl47MZklLY@B+Vxh5LNskG62j=E}19ozywZ8LM6Ih`F( z?@Sqzyd&C>v61x1sCZQvc2*)H9L?S0q>$n1(&~uAW6^pE!YtHbrj367X!B(M=9H4b zCBsXOmMzGhaLjg6^mA{^=NN+L(u3>L;v#$a)i9(CQO(8Bog zaLLCgD{44GYLrs)m!t05Y}%^bTnUCY-LChb5q ziH6&UbyyD`FQ174vmOZS4T<5h{xP?#?d>y#N_onL9Mr0ejVyomxTI%0WeqN3%o8h~ z*%`5{s1@F_+eUq5SbKb1y@fv1$^_R|NB0GL0s^!seoanIqlBdFt>n!<2_JJLQ{AF)cbx7709ZEP2Hisf&S~Mq)-6?iX6n2K1Hc0&| zHd7Z31RUc$5mWzkuk)*eFrf(q!xW&h> z<6T0Yt?hgo`NF@9fv}!AA$_n|87+velG->ug!8vX%J1nf^ObV>V@*Xn85iGfx$RlT z=E_HT?2A-c(ag5x8#6D4J9~tQg!iR0bY9br%Q$w6~wG%Pluis7U1zkR%|!w zdDW%iOL0@CtXcO1f9>M+7mG0giN{kyyY9LqdWp4R%kG?r3f;;+%*->HQ&p>~=DpXo z{HKf2)8|^%BJ-y;7W)$PF56&{30u70=qv!vH-9vI;cFKHHd%W_@`~v0;Ju4ec0C$z zk2|$>?Z)(Qs3RU6yeoX+wqWwEXuKV7_eeOpIJsk5n}Gk(_%`q!-kCHcdHb}sZ8Ah4 zWOwqoU69-UBIE6Bif-7ut#Ql_a0K~`sB51|i6dlR$8yezwX4NgkuA;| z9dt`AsUvz}1obkyIGz&R6_z%(9*dX8L*X?uv(ftLx8aWm7)LwexL^9V!Pj-%wYud%ggR&4>P`0eSN!j-H-AkDV7PPRW)v(Er zQ5&g!odxZik^|5_vTV!lw|pN;%yPgyg%L! zoVgj5VcSye?f1vGsjx7@?w2KWe_Yf%e8cx$G35B|fqhp5!ZxYxj(kwF_K848QfODU z)a?P}6mvFfU;E^!9b_o-8=>)Zgx()tRUZ-=TX9x&d$?rF?#YqR%v_J&>roDf^+ITy zEK>kqRQlTC3nRtQ^TI8=^N`})EnRa}&IeXw)Po#E&%p8GDi@P2hy5Zbj-M^FX(s#4 z!6iqi_wyyAa7|uPR18o~_|`x;DI9sPtFgvheM@GW)l`M`Igz=l zsVZI&y(_*7y+!WEq>d}w%14%lu55ZH5 z^36hvY$BDTr8(N_Td4@c4&9da*F*>Vgdrt%_M=&Owifa7IV2Y?ZJNS7N<6bLiV*V8@yJ!#Q2YeLeEOMeE-TrCf3T*CSsnDnM9d zgB8ZDnBz-gE3#jz5-Xg_FMb74{HUvtnTkJ4)(q@V= zqf0_E)?^Xbo>}7b{mGH+l2a9DAZ*V>tG4-d-ssrxpgbAFr{j>*bvF`<;7nD+9M5m~r5-;5mooLI0wt8DBC!S_CjytnBeo4#N8kL_YiMoH(E8rZ5E ziRZ_^u^(0hx9^9Qm@F|iKJuph*sePAPWqkSoA%q{PW(>%0Cu1|j|q`NKlOKsI#oi z^WM9nIW3}byvq>It>q{S{L)IS5;@Pl|Zy=sq1bjI7+d*$a_S_B!+C?AMQzZWWa-mynZX4A;~^rNmd%7@8y4z zm4XMm|7SuSz2#piT&2WO!+iv5gl%Ld|HJRbm1G68lSH=d`JZG3LP<=BqbFj?W)?Yl z%I62U&pRHl`a&EOmy)_7zyle^-!zBh`)kH3nUjn(sMPY(lVC=YKThOQ_dqCu3eY0)w5@Z+Vm*_8+@ORftP05*PNr;` zZ8Gcqe;kVZ>sQ7JH2+HF^%G~KEgcHeoje{8#m|QIwHiX6-=G6zs}?xofKvm~;u4Pn z@O%ij{0kVE14&wF!mfWI&};B035k>`#wep~ID#OJNr7349;-}u;-~^dNFiau{_ z%?>OQKbBA(X%NRttDW+^!$gLkh~uh+I5skwa6B$LAUw=5>q9+HQsG}D1m9_d2#*j# zNC6>~o|W)co{%>B^P+8p9YWEmm&&Ll)+<%Brzv5*jvoJ9zGf#(q-d=cR( z0>&fY5MD)yNEZ{XutY5(@~4gv>8vLN-!j4?=cotm5H%AAeFY)(Xd}GP5|=mpC%-K0;Xie~>U0#{CFU4>k~0k;TTK2O?a#& z-X)x7iT4QS3GqJRa!VW_g#3>QAs>B_)F(g)`6+~upGFA%1`%diVlW{p6)ziP`i2qW zoYrs^emEiYKT?H5WyuebGF}w9mMA5J+&P4Jj+bpv zXc-|I$C-pNOPoyz{__YYTF!+Wlh9s>Lm7xb{jta@?R$Y$h>Ouq2+@9#HS)O@LOj<> z7?n*-$_J~&k#zao<%DR2R}ezEs|b;Z)r93jTuq4lyN(d`>_$SA>&=8H*INk>6XL6c zL)8TyXqVq44m)B0LkMN=B1B=`Lx{rq4k60_K|&PL_XzVW@qNM=F8L+I^FJg+yblu| zZHY$+mk9AFA>=-;=yKRqhxS6e9qok>di{)WDcTER9oh>a>hsft=vw&61ZI^9Gea6E8q}Aw*%nL0Dorml-$Wl4Rm2%(n=$ zEl$~_MZ>*>ILoKnN@G!I+LR8KV30s8th!BNu*?{OrZ9;T@Nrb1P9T8rH5hvj} zmKZ{a{5p&f{k*)i1oZ;%a@c>i#8HGfmKaHR39^(B{aqFz%Jn!xl$wCPX(8bVOB4~dV?0k7MLQt83g%Y`@!S~-pQq^a z39m*IC2T}{AiNeyBW$q5`GnV@>Jy^TELP#wgg2mx5zezjT!q&W-h?71L}P1E;f;hh zqrDK$MLQuxBf5wX!}m7AThK%Z&$7g2gkQn6R)iInxRUUzNQ$CgtME07ext%~B0S#` zw}LihtAo>%l22=V-H2_gS?ivA)Y_+L@@zTvAyxbC) zzF-h&iQ@@>k9J0g&R3e?Lpz&D{ADyz!Y`qn5stFN6hgeL^9fNOP9ppWLjuCf(C!E` zED<3TmM9>cZHXC#Xvc?Y42>>IMDeq67PyA+=tCFx2pxA=#f?Grp-MMiHBP!mtGF}! zH*R$8u4B4kIeoSLWh)A=ouyP5bLdpyG{;ooSf#?){#Ajwt{ob!Fft)qX>eTsYJjPT z>(Jdeb>IXQ_wk1=?tqSaoQnIzLl?K3?g=XH@rN#M3{{*w&rxwtJalopeO;c4JNMAV z?e;gA@XLO7(xHnR!$~L4^Htna`ZsR5R)RR`FoZ@&bLr~9)k)W&zbhDaNfe>>$x4$i zIz}$6B=XvU!InL65QZfwR*IdHlrk`7NJ@Ij(3HbchNTQoIXqKJd`F8PCyLg&iJUyv6HwV95{POUdgx_TRrf{SpY^=%nUsoX!!t!1yDHI4L zhk~J$P$-ldN(&7L4GawqwcDXpcIZkwbd?=iZHKP5L)X}$Ywge)J9M2Ly50`mV25tB zLpRx>FWaG;d54MX_{xYx@yCv+oI9m^opP0(vf56$+D^H~ zPC0nw8Hh`}26)uVqIH;f^0_E*yHM#-(7$>x;o7Z*N8UJM&ln~gEsB*EMg6OVnH#L# zDmPAdbE8D*F{6L=I9z81AX~M}jS`(1vy>7u51kTtYeR`ItxmdH4`ya7B})5O2@H{4 zhwj|Ti6}hw9HqeN{j0!{ZuHI~AbPgd$yW!iNxD|HGFx&5n%Stn2peZ^6xl$h6D ziT>)V*f%4oby!RP6w?S*)O|NIxfe9jXZ1)Gg#D_d@P|Egy$3yhQMC6)zhl?t)`RlzJB zcXk$6aW6S^al1YDg(~j4Ll?JOE9+I!AJlrAj?~LhDcUuzu>ghoyRIZe+veC@QsE&!ZsPmn)?%>tCg^ zT$S+Y-&E?H9&}ozbZYOeQ-2LexGv`mNLH)Juj(H8XE{tY8yO>y;%8r@;>H?Nf7TE) z?om4KH7f3F`!{ZLc#esoxADkKxLzr8UH>X#4tqvOMH0iF8MPN{_K6s@y%gKs~mXBjQ@sG;P(Diz?_(4&g&mzNLBtvsd8uks$zCR8BSifpJczI zRJgByRbaH*odA!!Oo3rd6uAAM(&K?cr^oP~^!TpQ&~qPYvq1;g5+2(vdST{iZwF6O|2vjmSWQjs4k zMIP&4MKTe&cF)3t<-FCYSBI`ixi+{a`MSXMNjK=#_iaic>_O_!4%O^LoR*Uq$^2ZY z@ML!t`hO_>l#2Y9-6Q`jhtg*HS!30gu_(OuGfIW0`&R{a6x#7!Zfq(+6_IcBU-hpB z<|xXYPdumM{`H}YI~}Qy;%9GHaX)|P;&w+ezfp1TICOEd)MdJVr{ezYp^MvHI($jR z{rmrexL;9mzkKN8cFX$@D(+VgUEFS-f2`vEsDI-&N6l)as8$6n?C@uU;||VK;HipL zEv^&RBzTMRCgkLcK$N0IEOGI!`%G^{tEjY*;Y8_^0SVvl4u#U1uTBEIT))9CD zHkgDpgyQS~c9Eo6gRObMtYrK_1db!re%G^eI4S_~U(a|X4O0a6DQAT_{1#8c%EC^f()ZkZ4FDGi>K`?*E_dgp$m{JWh+ zOG1`V+5nux0?hw5_G<&y2Aw9z@Fs?T(|H#NgtwEPg3bScJi&AgK>iPfJXBVTn!A?x zX538(NE{0QBL89BHAwh~bLflV2om{^V>3M=h&VSP^6!=B!9@O}^8AlT3t8emhW`Z5 z0TSn77e4nC;S;!1n&HTVG#ft*8qyUUq2NdbM=N+NAmclOIGQLAS)>g@yb4AYtW}VQ zBWgkC;fS;oEO7}T;%Qg#8U=aSf#E#dK*+-lX*g8#4Z!>toI?v~Cpw1~($FFCkirxk zR{0V6##!P~;;1=4QTP+YQKOzx__M@uNaZ&Q=OKeM9C~<(5GTI=KseSCJUozg1P-Su z_#R=QB@Y3NDz?yT08bU-Fv3$TxoN)^FMDpqc0l?U zEwPXg{O3w&i6~(hhZqU*Tmxa;61?}G_2UxaDEG@1eJvrLUne0BNvZJr2yw{fLBf$Z z34b38z^io$y#oj3yk7^bz8) z!309Ymq!S>Cn-3K5ca;Z;ADUxt6$}a02QBVE$`DJfZMs6`l9V!w`Tt32&~nsg~gV?P)bQJVaQH zLvn-@k^h8~(LM=laj27UCJx&Wrdi@{!b!+i!2Ca<9TLZLk1P6A@?P~QK(NHr2iFn0~7uY`2m=Ak|q90 z9Qm-1ILc{1al{iy0ggj)X@pZy4+&4T#0bLacw-RaFx_av2>NZpeAGw4Q3c2+!fcc` zVE*ek&jOfs9Lk;eZk)p+J{0*w{0+1N;)mhzoPvj8P&o?t7Xb73zz@j&ay0Qb1?+tQ z{vGGS2>$_jg#W~OOu~C`{tz$?hvj}m9OeBYaU7z1g%I_4HzDfBK0@Tzhk$JFJV-}8 zPKb8X0GR(4+6`P`%6g9?715aqpz5Wh$9WBEQo9QEb5gs3mPuQ|UH^$z~D z0jOt$ICOU^;Rv)>LcCOXk8%E9+&xPie7sYh@$>HZ{I~I5#5<1VHk=UsTn=Cw4%zX3 zVB(7j-$DPS!mlKbcC%LDw-MimyUA7fPD0508|mnuJBhywJ@HP+e-G~`!uN45kZ?cB z127GF#=GDL;5pulTRRYk4HZr(fb%YQ(r1xA2<1=wUnn;~*0&1ckasDiffbjV^zI|rnk3P8IQ?TT;~`e{O}Mm-G3ew_EGvOeNeYTsP|&g2f*3{gRj7no*o z2r~F!e;^Dh(2@dPd(tQanw+$xfUK4l6i~F%_yUR=MgW{~AdM@a`QR`t(m;43(oQ%Y z`9?TVRu5_X0NIH{)Y8rX1|ZHBX&N_R(rL^9T_aYgutG#wgnTBPfy04>GoAZSd59lX zPafLOAe^g=K+Kb>JBQa9Ug3;iX+hy=;%6hT2{AZ5hH#M(VL}X2GYO;U#|Rh8B+9{l z7V(%&syrlpEb%&NKSCaY&L+N0CLM=so%=Dxa%D`S#ThU2a51t%9x9$dc!|ssdDu6H zc)QFRoP2ebk$G4bStJkXPA0rgW|cgQn@{{EoO36<*%^29Q0;W$Ur|OWzAEiS$iuBC zGyHa$wKzfU%%pgj^)!aBM}JLtx6E=OzK!=Lar9@%dO6Q5CcIA;fjrz=Li{0F6!P%u zEaE?qb`|8|)7iv-sEk`|R>mzJmPLe)UpZ?EJUn_1@#kgH%EO}P5r07$$=IcgWc=2dkMNLaCFw7# zdC03+6(IgcS@bwT3wr{@|KzM)(1HW1fDnH{TPFOgtP1FqX`Bo0b!B8@H~JysZ^){F zm$@>!@usXIc$q4r8~>111t)Nw`4BBYpvs{0!TXGGuRN!YP7m`0;_oQq9Q$zYm-xG~ zDhXPMXe0hU4pkHGmsLxMf8jhUarB>GB0M0g8ag$Mmx+Ib^Ra}&l7G!Vvc8!C%1_QD zBb?sCoboh{xb~k1KlyZ-l!MQ7T1Gtr`@(mn z;?puHuf!}!MYz?+w{Dhd3;IC?zXh0Tgat~Se4)O&SeS1ce0;;f_Y__>ncxP24;yp|;_ayIZ@byLBlZL$Ey~x|yM|qJ23H?U&BCia5E&jv;_ow$~ zhCDP+>3T}<3w@MVvM`|^h7Sjow-9{Iif#hGeoqah^m`F}eJPJ(yfE0_SYPBA z0I(-{72xZOylsZOFl5p7ByW2k<(+(XLch_DxE|%r0bgJAd(@DZ)r-8R`Y3PmISKua z?L}TO`1+#X218zUFY>naQQkO=>2&#?(2Km2!FP$Go4{ZH9ya8SGvqx9zwR>`{0s1D zx?+>S&-XU?t}_{we;1(H|6Pg>oArqGRE`w^d#YDgfo~aTe&RiQwx?eZIqxSJaEV?}D!{{ZK|#LO(q;>Zv|wgRd{?z0;6~>8f-+$@?Do z`cfXpE>7r&Ax8uBo-l&+`rJ_Wv;72O2>{5va_&~Jfa z>`C4d@bzU}_mUwGLl5bClD7wZeM#@a+Jt`R^dheoe0`Dk8$%vmO$XKQPkoek#*&17 z=+X}=?*j1krT)EO$U_%*P%iBS z_IBLTggkf;DsL)?S1Y;+{Q5m^$kY8%Px?IzzSX86<@d`gLniC=HY%Q;!!Z916spcY{eJC9UJdyAqTlZfd6)H)-q*p`m-3k3 zl+f>rUgTASuP^eRH{`AAMcyC#DDQMs;&jNd@w=)QdFO$zFZ%t`kf+;wPv!AD@Zow1y*XYlo%cB{cl+M4e^dj#{@O`P9wC?M0 z9~<(%+Karwm`v;b#}w<=?^^I_{l4Cdysv{#x5wV(WuOz)@^0@%UN-np#NC`0{xz_J{y~sNpe0|Yxl_Bp3y~w+zkMce;!o&SdbH!M8xsP4FZT%Lw>0_~sk9_U?iwRU?4;mkSXF2Wf+7t2~??v8O;44pvaeaPy4}eeW_Y=iM{XW3Y%;(>O?`#Ax9YOr)$QMANndO#y zz1+4S>E<774fDv`2)<5K49fedVx+t@eVK1dZ25%7iQ#bW@V0-_B=2qN_9jg};nj34XTB~GW<;vPvWjt0@6KfWgmBn*P3oFZJ zlvm6upHWcUEugZlp-#zaX|1YWx}v2Dt2Yx0%I8j~YHe+~4sgIPEbL7!Z5A&eH@5_jZ}BHwk5j4%To%T9y}oAFP9d&h;G%O@cvBFMox{OMGZ$OWh?{FDWf34;P#;J9)F65vwK%r2 zt~xexeqDVXZfBoUwYX(`X+vwQxuL3lqDLeLA*`m(ABT;I46>+}N_3=9P)- z+Px}i;<9Cp4ZS?w+Kf7;=thDLcF8?ke`CYJvdDX}y~C@nP4C+y-EUq0w9kFoXcwaj zC9<>+Ibx`sxY7QTB=j*C50?0*=El~>>c;wsi5NeTbupVpW4Ol@shU3#6-^d=thRa5 z|6}i6z@w_JzVUs|43i-Qm_W3##W;b8@d8Xj!o}<4LP(TL2vJedBqV`ELo%5pI4IR< zQSnlX)~`)l+oGTCi`KS4wQo=TdAeb;&f073wbs6#ea_i??ZR0YH)dg|ZEomlp4GAHO6TBvc^4X45LjI7XuC6- znq%mw&Fzh?&0XiL9XWmKhBSp|w0%^vI%c+Ybz_8EE(gm+ER6ViQH~2?_RYhu9KWrm z**C#w_O;-81Ac@VhS~Q;{GPz?HT(|a*9|_L#_{Y6Sm+e!`(+vyoF%WHxmU)n7#rxD zH!je3|2Xjs7P;o?Jb}JvLAf_wj|=TI9}D!g1#IrSCix0C?ezV!Cf>RJhLHKn`|

  • >Xc6L)YecidS6zk$Xo>fQcqM)zAG!OX|Skr@*R(_ zx;FaCgwAE_#bYtZGaxVRN-?lS1fzkz!~}nsf5nz$J_3DBLEmdRaoa8fy6*}FUkP-I z{)R-j-`oo8cZmUN_fHPLI$ctOopJhW-!IdQBdnbW;~~!13cj}oN!szZ+!f&(8LI8;z_QD zX4(4p1v+I)Rqws82I6MlFa2qaX^qCK>7AQ*Hm*1Oemf?uQS3C?A_pFZ+zAQuEgXxq z?{o3szPmd^`~2~liL?g9{U~z*{=QI>>Ff9JJ3F3MaMz^Z{$Qv1i%5J@%7^UG&O+|a2&Bg=Y<9_59B@-{*>1#bQ?Tu*#S!1p;kncd1 zc|qD$X;+B>o-8^q^hDT1`H4Lz9{#0~9WwiJ#u%>_Va%8sFkj8?e1B?QC^J7ZKhU># zf_ReWnhu78lf(c|BlV+QvAn-N!FVOu8Ga%pYxcKe#N%QQWoI3?Y*N~)v{eJSnP&_Z zPUwtoT9y^)dwWbtnYgDU6SONCyA0zEW7FCYzlSH9W`&Hi`g5}~3qpgDj81=pF$rfi z?LX340DX)RPK>cHBc9#go$&XwRP2$Z_to-Fakp>PFJvv>?Y}S6*jLyoo}7n~E^m@Q zoF8Jn`}ZB+>3=Lcg1p!NBW#?;xWTE}>-?_;ATy30@=}KAUx@Y{*;Ku05H(`HHJEoK z2EHG`!pE0Y55D5>EGSQ_7gvQ|{d1>3cW~-&;}aL*9Hq}<6nU~9Imye+%o;3`lJnkO zm)4LuFRekAS7uO_YoHICD_#r6eU|-OHa!-<=7vfB{qM&Gu4}FlTc*dvKnRk=)AcC( z@+|by@(_Ad21ZHIA38e_H~KLuqr|y{Ry_R(`fpZdc>bh#$+cobe;&sn9E6!Aw%{%h z07k1OMbTCoKsWoE0%D*o7L59KW`}T|XUG5)Tef4g_rnG;kPn(aGqefMEZHIon&g%- z16ei=I>I8iBs+A@_Ryxo7z4}0@x&|PuEZPoE!`oW9vtlLEje@PL%8#ZXf)9GLO|+* zJ~7~zQqmewdm_qRf1Saq;Jyj*f)L+OTrW!I88xJV2%5jj@6g2cHqFGUeT>JA1*J4~uzKY}v8WU}v9?5me%h+hQafxiBX z<=c867gt5*rFV|~1xKa>87zBRfYVp&Cq~4U(5CH~X|28c($Q0UAu*VV9BpA-bRT75 z)7PFD__HP%Xusl#yjbNEVt{SNABv)P8vTL3oUsS@XT;HRI!%d*rzmN#-w2C638u}= zECFXp_T*rm*wZazh#95%lQB0y8^x%p`3l=L2d@Tnfxswmh zE~qhT@-vx}aAX2X$R7$-AC|3(ds~e8XkF0>(e%W)gnv?IX+CNr(1+bG14o$e%$X0O zZ9rFUVroJR^dauV?b#vp%CSb~U?i<|uwdDD#MAHKDAtm*GA|LQ26}=Qn6YKw2=r}B zw01MR&!>rj zjfyjWo7i&@Iy2{qJ$xgO8O`4+26}NN_LRd~)XM-jvrI>biYI$vRbB|a3KkX2%Zy@V zw#pE8i-9|w+&zHtVFT(w)>|)Lhs@9K+>RN`)Xw&6JFZ1Lk@dr|LWJ0lvrt~fW4zjq zd1RJR;fRL6}j`XLvJCqcoN8;h)qd6 z@ObRnCD$&!R%{9Ows=rJmXVc|~wtdLV@H9(P({_=RyM=EZsWS-}g$ z(<=}^ZNnKc|Eq`NTbO{wj`&oK0pfV~@eijVV>{C^^nJC#@;1$vB%OTD=K#Eu0&O z`DIJ^m5k0{e{&+ce;slW>~F(-|I)-IiOUjV&vVep`eMyG6w;m_NSxo}qJl>YUJYZKSNdJEQXIGk59ne&$C)8gnUiy&o8MoS|4mKfL! z{T!1}YXdDD4cYfauL#Za$3fp>R4>Qq5t_h!nI5%k?)OgtTejFQP2(`q(EuYG@- zQ9TPILeV6#XYjm%1DR*$PlnS1$iZoVS%Jd*$zw8%>R?u|e=XW#Fflga&t$*Eh_zD; z+>3ff4-2QuI?TL;GXu`aICD*__v5dx-o#&{-oRf`&-;i!(}y`vTEk%Y{dgv3SiFxg z){G!+1Li0pSc0(-BOE9=o6#p^D47qSJiyGtsxMURP^hS1CSQ-kH|>e6Kj^WQ6iQ zj4$TV>y>8z{0c7gk1LzO$9kf@m^{e9k0G&^ z_3|4?SOw=>NP+zo#QiO#pfEDm`WW)z-$I@{S*mfqg`7>x|JUC_tS=#}y71kiyE$Qf z-S{XziZnH^>RD5Vj~;9Bg@oTghD7j_%t)V6n8-0{rt|sa|KWp*`!m|1!4?!8Yl}ZP zIuX5q3^x9G3zaParv`Hutrh|vJk2`KTygM&%EKDB5BujI*Kh$kKhsf{6@ubf`x4Lx z3P15Ja^iy4x#J4=VI%chxL&Ez4?EXPpCx=~2+X4uf&$(QoZu73^N3>YlXZ|sl{>+Q z2dM(!F()R-Bb}Y#!ya<%cDK%Cm$5+}&Flmp91Ar7w?Az%zwmD31RpkOtq14nBO?G9;~KI*|&dGPff{5B8%br1fZ9{gz!{*nj(qX!@K z;FGmmoGd>NUh2VDc<>GnzQKck)`Qcv&;@7@yhBdH-vQtpvnmz74|or7no0UQz;D&? ztN@m@X!s1^H);4{;2dM@^sT^g?6ZU40Q?3G{|fL-=sH{J+YbD4T=Py&{XYV}7}p%L ziT?)pr?vD)fbRm06C={cV3x!sG@QW^p9H)W*S0;gfg`yiuN*j+#M$)az+VNPj~~;o z0scdczZ-Zb@KQzpr$5N^Q|LOYXU@=)#DK zc8f18RMGR@+(jz70Le7rg|^Ou0(ZQvv;gun{@J!xWWyD2t1W;co!`;x&g*PPuRF7| z9lgk{%(avK0^~@>I5{tb%~p)9y%1JeF>W)8Y_kj9W)wLI-DVWoW*52(y~sAZ&|T_9 zw%LX5VlTG!vfQ*{DYo^_b{Bgw^l~vsa)HkLA?rC%gWg3ua)}3Oux#;#b!BZGjaMzl zN8!fq<;~qPYH3$vYg=0b7N}TFRV-YvWI;_;SzUGIC3RMF?uj>-G&OO}Mn!8I7CyAL zuNj`Jf|J|Y^|59bx!ma_s(0ubRKHR3J?UhZ8d0@n^KhwMl;Q2J>av)cMpRML+|}GY zA_t1nwxGIZX>HZw1vPaGo4adUG1GSP20XNH#!7LnfAYH*_~cJ_iA* z4sl6!M5ylHtHu7kT1>5SoOQItXxh>%wf^vEtDxKq(}t$|_i8b&BAqqMSy=YZuNIT< z>4smKrPYR<8-JvW!zl5eT@)s5Kl)-YgHIY0On3tyJApnhWzg{6M+g6gPh(X^7%%_B z=C07A{tCu~TS{7bTO54eSW*8muB;u);VL z5{Td3`>4nzopOouNBLuNGs7}|Di#XKD@Z=yXz6(8r@2PG`R3D8jh4(Zd={9RSz*z4 zy%CD~tyHi>v<$rSTsXGSvVGSZW|WdGEV!N8OqG-HCh7_I)=OC5yG6n+y$2*b&?~|r z;#SCsTgSVQ& z+sxqYX7CO(_-QkEry2Z=$>(o7@HsnqI2PWsHzC4AQOf|xCM~W~ujZGk{S5e)g6Cq% z%+D&^q$0mmTx31m3s|4U_)CO8S#M{+N;w8!l#KRuSeZABkXIL;Q60GPzE@G=_4%te_Jkm>`A331MUxVMOh>gwO=>Dz(3{ zQ2A$qlIs|MzVcOwZ)3g08`VDg3)KGnIYRo37xk9UcxL`~^34eF zJCgksmdO5!{xg~e=$ZG!fO`DQNlG`YJLbAExX65?VT`8kY~<4p=(2XZTZuIpKduLE z;!~uw1LMwU+M$;}rxj8+jFY-Crj4d1Z0E_W<_3WDl64 z48TY|ng-}2P`+irMw|drk4rO0nSh(ZXqtc`b^>ooY7oSUfen+dt4D+xR)*kiGn$6z ztuY9_QukD)8+Wv0rP~>a&QQ8>_dMphXDQvdLmzY91xhz&0moeTY^57BjbpC6Sn0-W z=9ufAt8`<=bj)?nSGwo@3v{2QbYtc>DhGg>7)a8WT8|gwrdf{<=@(j$2k9tjj4vV` zj}fN9tn`n(u7-E!}leu?Gso#~?FyU3cZk2}RGsGM?ZkfNLx&~wVH>2*%EHEm8u zq8pj6#F_?=%eUN!jXPC(b(itqVmk2c03`i;Ov2y+bVBgBZtwFo(t)*6HyO!K+cAP3WWt|`dDG`^P* z({`>A$iXz7YXNdFE$27?98AMKM<1v&3Y_x|z<`gO!bgZ1Glx(^1+8DBozX;+zdk8_aH((!Eu7XhZ=~IPjb9h^9fGgzfoJ5GfJ=j z@^+f99uiT?a*~14zxO>SkF9 zc8mq{0Cc{>tdZ9Y+PW8lFRY2OMPt;Gb!qdh0iQ14zUIRfuVp&`B;RJ62;7#32JA}z zH&mca1If8YN05AW8NMegnjBWJMK=QF^@s7TSA14#_~eJY&)bLwZ}srqjfT~!(e2C6 z;X<};72!j}V|~&N*`@*62mS*;oo_PuxKfCGvJWUeuii2=+%C|(!K?SX;Is7-GElEq z-m~CqlT`N~ue?HZ6kDF`b4QU^3cggz>D zMspBDS6;+CB?78NCNU9-`UWY~>-AepRWpUbn z4h^zV`PI)rZGRHikqoO|xibH5#mYJ-{XW2XpyNOAfOTFnt~tjyfjD>pXc3u7LAH?P2zdLU%`ZX1#s${37moQu>(rrJVqHT zJWVVD&NgY&F9U8}Tl_7GpNZ(osl$a&5Z7rqt+)ZWe14Hy0&*3syp-uPMIY#Sb_Dph zXz6`;0{Av?yDwATf4b<$iD!Y^eTnoRyXYSizW{!=Cja*?`UxI;(>!=k{002wTKW%M z=|3UHqheXMR^U0>_BG4rL~%0k)t9ent*_9Ni`rO|mz%lOc-y&V`OFgk0RCeqjz@jlsYx#o#{vJXM(5$ZcJSdSx*5QWoVb9P<6JX+ zu~-1S+=&Z_CC)YJbH(Mr>z%lOJk&QSf4=Ae?Fo&}Lw)VwL(lv)a320?g@E{+i++yy z8gL%4YtwniuN{0i>TZ{Y^KLN!+;2Z9qCNjWqx(dOcm?>48vWNUdYN=+#{*og5DCp7vgF8UQ>4)B{b`gtyTy*%XjHjRFG&I5j}5D;H-rQaaF0sI<`{)mfyop>5}pGN1- z3_JKlFC13jfLM+Gdl&si@mJtmH2R>6zEMm>+kaZ4XFGj?_TMZIU4B`kbKk5Td^qNz z1o(c9e!h!-o9z1sGVlD7TH2OLh{eC%i3~2PvxabdvuL6HTqi=Q5 zzb^asD;j-|i@sI72>gIX-|wP7B;Ex6hDLwKMSocMP`BCgMK((75cF`XZYk=2l^q7nOUC|4?MWgfntK+wV-loy- z1`fX&Dxkju@7C}KfG0Hko4_|{_;-Q#YWQy88#Vkn;F~o3Mc{X6IQt?G;I=|Q{02A= z;2r^#Ogd_8bBWAa}Ce3^!~0l!5{-wT{` z%1Xt5C-7X1nKKpsHQ*gEmU*YVoxm>yjwBNQG4Kn3+xhu#;A=Gc-+^Bb{4~X%iI3*{ zH2SH)9|X=}j`Gh1{-}o60{^wf-v)e-M!y00k2L)A!2bX|qU3D@elhZcC@KFr;0?fS z`+o!c7eG!^^drE3iu&RAPTG@>i)(Q|<@jh*T*ZF`_&Xq$ zDm;J}&3n-IZ2l1NOF+w3{qaQLow&C1e=2Z#I;*SCUIogjc?>gY$2ftl@p9cOJ;L{cV=gANJHibU~{3nnHAoYKgo(A;qHb?U~ zaNc=stK@#mj-GCD-g($#*SxlDb$N4Rq@tk_o4C6WiJjWb%}q58?M)qP#d&oRQF`I> zx|-%SrLEl;$6LGIyR$7f`-`wIyrl7}(w^0;aqfe@LEEBV*v_5fNsg)|wRQH+TVCs1 zX=^H$FIcjC0XGk~t-_8|(WoxEM6>jU&}37(1b3{JwUo8AuPG}P@r1SYbiq2DP|+p0 zc{six5ySRzoN~ZVM(%z1@FtLluSjxBzlUP`2XJrDcbo*c_vbsF0^Hm49d`j&|bnqt~6^Vn?q# zzjGYD?)=VyuMO3%>O3A8=Gdw|9vJ4>s%N{iJjYf&+nwdPw(8mLEYG#G%sSPIVy>eX zS@wK{oD1FFD0fEZIsPQv1vAg_C*k3TQL!l+NJ>JplE|vL?UUx$%h&YPf87_!8n%y}rh&Za`~cu_xz_mlJjdUAg1orPz~m zb~;PBC+CinmpPuC(~F5r!49PBaNNAi@#LJn!b;)EIh(&l@Z{X_^uiwJ(%~rgCdJ4y5%Un;+9hWWa*{&3J&gXh^&Ki|P z!anaxVds3VC+DmmD}^WLtOkqV$@v^dxhLmyY~>s>bmc5NDQcc4=PV+N;K?~l!XhB& z)`cgh-kdXE7NaNUa~{=oo|=Vd{|=f z*tX4wCM(94Jl~d_9CivKw(R7HQxLJGCkLB?h%G-k&J;v!4ap&nq=CMlbysw5L1P(_P(hb#t7J2~;gc^4Ok| z%F3kvq)#2kWs;&;mJN-CVNT?t(%Q1sYg}>>Rn=9}*xkBL^TLEkk2o3Q5p`i#^P+~X zZsiEaQ8JPXrwhAkJKS`5$FaOQtwljJ*Cz1vRRh;K-st7)*RJYl(%8TH+&f=|2I1hs?bvx41WyMr2DqB@o(uM~|WP5S*+76t?M2|s;Ep5hG zfbvNGB%84Ptg2+#1Ke_+x9G%a z>18DSZ=r`McTiU2B(voWimnCOe}=f@vTAx*lJeALJ%r1l)P5p|C0)!*MeTy+wWx%+ z?A;2jX^wToyJchpp1z&fuIAw)@v5O&X2t3xJ(iO&JJoWWfj9z{V_MnO7y^|NnQIJk zI=Z|&-rTTO=jn(6bGsUoCw)~`tXL`?+p#oi7c8#U2dKI_=>om3r>&`V9p0A6GOts8 zQ5GM|x~#FGtZQw9MFg^Fl~rR_C6ukwU1C)?ly$3dPS#V+YFVsST7@Vz_K?q9P))M0 zJDO#~DQjqN#4((bXGlw`lQHfD$#FcHMs_;swXFolO`=I#QhCR=T8|xVxu|r-*{^b3 zk@hohn!njQM{Bxjbu%QW0N^ zW@262?jMOkSdy(aA)As+#BmP}ydVy4Ix$@H9qHOQh9pwqsSzzv-SCKMH#odN)IeYxKpT2+l>BC(S&n#X4_S2Wz*|`!&ozZo6ncv#I}pU(Z!9_p$~{%8I7>9R&R)b&-`i9{Dy~e(Q`~ zGyZUJ;ihe3I=$H4SYb$ScDs)FtC#+DFm_XEV(-`fm_Fv4JH}w;4>@kA_{4$0q4eOx zpAh$mhe|3crLVxW3apCWDNYgh%&QPzxOE3PZ$9C>JJNQFuvuYqeXI1>ubK~5%M=-5 zSn!a@wbBQKxmWaMmcsQv7;79fj2rMX5B|d}eY3`Q;alC-bbl}wveAb21E2zxH~NW(zaV$jQqe}Ge7;s=f(to z249FV-+@hIe7F)Za>f=8uq1X%4~Dz_b~>!m!uRKc6DfE1x$uT~z%1V#C3SF%SxMi3 zgY~{senuGn4)x#{scaeB5}j(kYa9X=p0w!`Emb*By>r84-|6CzsJ?Z_r;mupgcrrM zd$WUQXGFy}FFzq~<-@VdrUXy_%d1vR&)sF7{{D-f%^4T1$@#>}ZyqrtI9_UH*_$Ga zYw_0W^vfu19IQ7d|LhcL4{d-xT72;O=(a=R`YA6Osx^^z+<^n8|7Y~gm@jj8z@I7Y zw$g+SZ<#pu#nT)~(ubqu3+?KC6g(j#9PFf=U2hmsK*pZvP-OL}e z*Y}b!HN=*PT4Iilyl&Yn4#w)Y9qPS4d$-K(-ff4X^18R;C5NXKo!RXTQFZ!i^ zOXonx7|0Dt9nlWsMdpZQ5<^Y-PG)-8TyG#x5!t6AEd##5%lB;xx4>cHRMO$*!l4q+ zuZXd~FZGL0ZA02>aqvHT@A{V{_cWG~X9j{_ve2`7WDsY1t3oSx`p!>^nD33miNtaKd}O#!Jf}DROC8)FVGN@;)!~ZMIArH_2z#*S&k&J7!DSn?^2uer`$RCRQc3 zRctwAjJ>^Laz*yer3b~>=PG_!aoK`-yDzKwG^C%f^WvP{C4&>i0db1u(GxniEd8tB zSoj@Z1;)Dr(O}J#-W`Ma@4oiZj`Oz<=BMrd(vJHN85z^w&3MOm(C}qv?>~|e`O=Qt zOM|;FgLUSi(|fCOo+Zqu z!BqmISlzp~zVl_Yv(kzcvKB7hZcNR}wMMx}OZae9L=X3hNd1&HKhzakeSM99cROqlgyOuIe$+0u7^ z+PjJID}&~HBD(FpcMg6Nt>DW?aJSntZOgSBrJJrbHaFzlTJnR5;;#IP0x4}B zJKorA%qo*up+#jYa1tHr1B}d52;9D1Ecc{1mYF6!t0e zsUT&aAM=e(mzvAQng{=+sJ=hO2mQX=W9GqMnW4kcuI$~$G)S409t+BR;ZC^A zJoq=2;wh8fYf;Chb#In=Q9f&B9`b#A8(OR~v~09FVvmj&kbSawDnHZa22<7E9d zjE7;dEf!HaBb`=`PnD%;dG_6imK8&;Dbejacd+t?gmLg!#tkvX%lc4WbqA})t`C+a zz4#*S?p~Jm?hhWtxZpqVg80UPr_Akx=S!cscN=$Et>**F?{C%li6~0*S0-C^>6_6| zrBy1sWsU8ghk6=c@kW|;_j|*a{4)a}c zFuNdJ#=By$>;v4v1}`wCPH71iFox8;j9^*xO@A~Sqkm|ZD?gPY_l7lNa*cX;Gj7Q} z9BaUpED!5Wl$2(l>yuuLb%&$nllLOV=U3R$gNA{eS@M(DC5L-) z*rSSfuHnr&NLw(=NSC!pz4#?$4tN!K*_ay0wY*PboH!uz7)xlS>-E|9*rDmh44aO8 z;R^J9^uVCylbK$nVFy;aiA~X9v_%A?_4pC@1CQV^%R2!5@Zp?+pTPCX>R>d+YlNcu zV6=B*j>wJ$ql*xaeUMS?HP7V%%cT1OE5XBS9#R|xZFAJZ8TU~KpWmO{sY&4&(ES+M z?cjKThQDa(G+O^-IfzdF^*J7-ea5(`i9>8h`mZ~n7D*w-QLat+qn0kI1CAE!Lh?Jl zti4q5IF>t?9#_}?kSU!1Fg;?@MbZfWAyJy*vuu*rChU;P{2?3&s)p3Km?ovRKuIIQSnsn(|B~7_9ho_`4k{t~6)->BKRxok57h z*dl~~7VsH>fCDAx5Kc3sw+%dQ&?`4wu^5)O2&9+0vfj2}yDhCB&YgbmAeIgI7XY|&-Na-^M&#B&WwLi3aupBcQNuC4{5IPZRzDyAcVe7?#WOV&$?tVOTE9k)JP+ z{uXv25{@y%R|&@&;(o%3hIQ5`?EE_Mxt13=9&Yyy;_nOW2}PJ{h;I|l$L>SIm4CQLKLZwSlarGgOdP~IR!Ilxqz z4oyg=J4E;~gH2F2Ca6aK4DmNY@V`rl#Qz{9vwrutn+G4N?z;C`GJ;jK_vIwP|e8w+A z(<6kNm>GnB!Ojmt=qVsv0w1A-F~d4z6>`oYj(!*=JcyzstVTZ~yuuI_gy5?pMCQ*Y ztg+5h6qg%fDRC5DH6c3FGD5^(NQi;%B0~H@)yQ%~Rl+5OY$E7P=vTz28@$Av2K|a~ zCHfWN*@kE(MB!dZcm?_u;R5t4Lew*c09jucGNkcn+R`3$J-9~1&LcwP|9ZlDVVyf# zW?1Ko{vEr27>{v6dUaW4?S^0>@VrIlYcnC*`CWtk{=}=6XLss=NgvRn9~foJ43{+9a!Ql^fS_tk3EFlLOe-`!z!O8M5FmWAqJu6 z2vKP-5PpDNM1%==dm(Hw#7l(NU^fuq8bj{d;2`yiqQ6E6{1=M;Yr^Y<_-{f~^6v@J zC|@V+Mb{xj<-SFjX^1}&&O(19L}Pu25QE)e!nKAtLKrf{dxWPO;(fx6=zoM4r!R`ErI;6GEv zpG9~Nnm!>KeUuR8QbrgtL^E+2=B)WA;N{YZxLn~;%>qR;4O>r0z-VB5dHs)gyYcP z2!jwsI97=NOL)8?9w5Zc>uZFI(a#9CqMs2iF~qkB9}?o*gw=-l4&lStHBX4ate@~( z*o8=l{Ols!2H(eo$j_66JA`NCE#xm=Y5M1dfq04o~yn9)Z=GPQMxhDKUVdPrfccWQM&PrFq*nEq0bIkxJaI+F;y9m zJGur;x3vRiqyLpoPHYU`ly-CAmNA?BxB70w$r>e-W9BWB6ZPOQ^ORN7M%OC&Sf?yQ z>$i%f(mv?~HaF22JQs~--C+9TgaEGU@iX(4?o*DPZdQ@heVWpJ>ao-9XOE_Cy|dj0-8jZ(qwgmBNSz{O1Rm-~(+IRH zC*V1QJ)WofT*335%B<^U+I2lx%sI-m;?XrtFCWeaz6P}P0m8&<7y(xHe+AV=i zV{Y}|=DQsRl}_%i2bWo)Y+5k7HepiigzIpnY6k=826YZtl`^DqbPdt#h|Q5hxL!vW zC^OC{v9qcId@{UNWS~E>&irM;)uq%SoKxd6y{@FqV&| z3HtNJm6i#28uhp^mn#Em@cs?BeBc(Qe}Z9VB#*dF%SfA;7D~%Zo0K*=Ei3J~wBv6g zuYos- z1Mq5KG+Tr|3-%-9Qui9Ad-cCScdOFf@-NVRmC}t{%dskR=Z(Z#rMqo(b?bAyFzUMm zFUZE+i#-AEP=>URt|7xVyiTP%cI&r&prF6%Soo=V{dz9|((bcVwyQj&@ z-=Mu3xmp>qZgh>%@56ld)$haWl?jPsXM!5~oimrORVG|Bx+d^zh#lArtan27xH3Pf zEZ8u*7U&(&X^7V=-FW;P%@I&I2>ss6!jMMPMks`@co$zWHCE`&OlU)9C8fC&GEM=-qFDZdYd9 zHo9i$Er9PJ^|A2N%7i;c*95%ra*mzC~&kDYEO-(OX_zjEw!JNdp(>E1HBy7e(g4Z-T2%>Pve z+&{Vo=>31_r2K2jhzCa32))(wTDH9ZP`bbVFVOv<(!KRxp!*w2_e1{z-QQHYA3k=v zogVjXrTbg|0^Qq{?ro#1Tc2=6(9ZP<*LRc&JBFGtT5sW5^ikQ@zN?f!GF16T`4(Q! z|4dK*|5KUp=;)fDKlw8M+LP~2WkLVwTA&Yh&aLiorTejCr`zdxyOi!H&>+u3ku)?n ztZEfT0WQl5XTs0(7|WymjKxJ2A}~H}@mMoGFy6>CCYjmB3C72bPZ(2-sRkcv;7(N- z6LDdhetbAeHzpV*z>G2YBMkmQAhfTYiCjEMAc2DfU6^l65uC(JUqB|)T5w)PRFW8ERh%*i#xZ3^BAIOi#AzXRjBpCKpDkSE9x=Y9pkXUX@pkoypFPBg>;;OU6x zK7#a<4DKct>3_gFXYxIREf|E)Vo9_K_9*?b5#Q%yThKLgeE$Le$fL6G9G8CQbKa{W@U~^@fg>j{R8ID0nj=_B-?uf`5mC zFB2Zdx_O1a4Vd#6ls|Fs2VldTm(ZR8)3M%tx`JmA9z=g59qpl%_$2HnBt*Iz!oOjw z66sH&Jcu7a`%&--Le$@W(tj$%FNx##CgF6n1HvLSQVgx>7}<^|EJ1k@qCTerQf`De z$0gglZZpI`1HH<%kEjcQlr`qPci+UlP zUi1RVEsj5mZB z+;%V?`(d6{`1137(6OUkjlES$cBc~AijR0BC zA;57@qkR#_AbAFH$mPk5)LTmUCdN_5qaD@&uKo@Bxx(e?sK9y3Dd}yb{}%h+0NEba zF@7J$RpR(`pNGX9r<)OSGP zzgPI1fYkRk;UBQygb;d<5JImB9pm<6D{RBejKOS)P@3BgWbc{b!8ILs62_feU zLdb~_Le80hlyf$5$f+QNoG_q(9G*VP{H(+;=XH!zfa9Kp4nW$?(?ZREV0}|LnwW*WLc9m#4&gf7UkKxd_$^@<#&5!Ij6;OjT=+iW)#$&FVRmAFCn0Wf zQwXuYE=;(=5cz}&)H~rP!Ecx!eejPQaH~NBw6^$g@C3E@`xA0Ik=&b& z;>X4|xs3>Wu2H_kPe!>Co+7g>_c-HrCHFLQZo>%-Cv)7h93sR-CX;ZsRE@y|^Jn67 z)gJQsY7aSPk;gOs9BZb=y}jAQOQdOXukOc*FOb{L0XLm}tAiyREq#_f{4XPspN>dnk*DZ;(YI_ejnm-Ybhn?s=R?e52e> zE%!2>Nqm#s9xeAOo=yA?S!8k#BIkhIdx)Zwdkv$6_sAlYdj(60_sOD^d;Q9Z-z$q$ z?(M4}z6IOu2=A9gEce<~5&yb1m*k$g3y41?i(KxJTTJ|0vgqZWxTVB*$nC>&Z`(5B zkIJf$d(f5>e@s>hIv}>2632w|BEkV|<0RZ;J=KUOt&_{RLHtt2KaIVMgwM#T!^8pG zjER3=Rv|hvwnr2HfvifoalC=}4`r3&m|C@W|3}sn3^$ZFll~J~#d1UW8saa?ZM(R! z;R%H}?%k+zOia|C{-4RJ$HWTTIT??!yq)kBY$qqgSd6BC8^7A?KVCKo+3C6%AK)K% zknO=8B{2hkeOf&EFohiw*e^{jwi-MK(7&1X4HX{(WdGCUMbP&Lj#msCz)*l0NirNn zpZ>Z(iQ89sxX}4N2Lq3@i5kREAo=X9e*=8w8A%3PG=>IFha4OK6jfuDVjYQ36K9QY zNW*?Y`|LbZ9_8D?mdE~~=i_hD;q}%iKD(^n1D_sj8I6eK^@s7TSA4b%${S}JYexd! zik~f;(SdT+28n3lbGRO>;c@V>-f71K70>+t2Yx!=jo^!>TYPA)GLX-!_sJ!x>79vz zz}7480gyGEymP_VW~p=i_2%OtO&;4Y!*KE*OHtnR>ZE;kdmT>R9Pp)L-~F0AbUPV_ zleZ&9c{vz3Ly*FHLl>1{IC(R{*Qw|_@Rr|KHF@mY48zI$Hu!F~$gaO$dBx}mwtXim z&f(-O0AG(wl7)EXJ*LS!X#{!CgD;i(n6o@-U+xIC7D;PoE#o+5o!M^7;d9z25w;z0| z)JMgNq&jl%;&D(&Su@Y&^8HG;f5 z!I#SYcTkgefhO;9TcHE%IsbvEDh4SghiQYX>iY zZ>^TjzVx=!`FOyx%cXh*c~#&`rCc7<_MuB1RbCzV zQYpW^nmjbIqslt~zEtiri|}A&*GK&b@>YT`6?xBT@?e4t!`1IADatEvO4^6ZqsprV zF%|m;Gkhd3nsoWQ;@WR6`zm^f?T>`#T?0ZI&C*P4k=5XcrvlQi(Ad|Lzw*KMd zEd!rTSJ{xjJ6`S5Uo#u4OQ0lrkq??p}C%_GSBHTdv)ElXu$)@_q?EyFcnidhM&hAZ6Qk#|ZLPfiIQ*@pDbyog>J5Jw!rG9^|$@|I(@?HmDD*0WG zLBqCh%Lwus!Iz4>pJ?*#A3@%)Qj~WAI=OA%10%@041B5B_kB&?*GG`|^AzQkq0(&o zwvHfgIrvhsZ?`7zp%LW$1bisMA;H`JO4lXrdw2wSHQ>XLIwW}I?bhUdYXo^e0bfe? z;U;L8-?kCt)qoF8dPwlv_p~N&#|ZLX245=m5yhm+w(pS<N6*!UjW~7Mc0A%y~Rm*NLipWsOuL1$7=C7JX(Z-bDZ3%;yF%wI-ZYCZKqdt8y@#JZKQ(V0{(g?-fi8LLz_%F%MZMp{kAd=L zMZ&I7P&Bu=uz1eA!r9@lMY8_RDJqhD1qG4FJb6{0e*J<)64@os7vZQA5%!cmnc6MR@J;MSKWR~}4vI0BXjdWHM&-5-nOtd$%xELgi>l~YT7`hP(Uty0>7m`e3$Z-D=%Sw_ zzUjilmS=QF{#5Z3&>yqKBmFBb{ygcq{7H?@6~}h)iRoexc(Tm6RNSVrKJ&%LfdAHs z3W%_aewvsC{7sEM&qY5&EChZ;qgT7=Go>eQEJRcxAX-4z@vDGy!KoDja^>?p4X3B> zvo-u?;86|#4DfOd?*k48;f}offG^T;df4Vl6e|RzXYE=Ie*$zn_|Pj@b~>H*v%gs( zAb#lL56b-6RQ9^pT=cP)M{LF5v(~U#r&b`2{g2^y@~?$UPuB`(zc~pbw;hO|}B9{eQ_{s#~Kt_MGn1BD8ifMQpRgEs1&RltAbNf}T?Oijv+8Wk1ue`b=epOej zp|QDZ<$^?WV^4QSd`4s?&%0gO)w4<+#4PbToHoCbC-<&wULBuZXvMWQH#g6V6c!X0 z)x}rWwKTNNY{cCSH;uZk^uzGIXv%#fv zAipx-1+YesN6xHxcY(}C9;|qGi4?(DE8blsMNntOyUV1=(d#ahB1i9hk=LZs7TUs{ zk}R~v7TSeaXbUW~%dgNDRcM!7p+^@`HnQX-Yu=Da)%+nba+-y@S-4=yf|{zby6VbH z>dG407k4zZu3lf#c$JG#-rCiGGw-VwELdPQOc!-Q`v}CUE{oiBl*DM_Rp>X1I@;Hi zG&RMWF=feZNX%4n@o) z$kC~*8oHW?NyKO=&oU@kLM4rj&9Ux^c*9yuNxei>8AIZ&avl=xRKO4li-(%ZxgZ0zUUe?hON9qQQ z#lx9lHH_hs#yi%wb~W~N^mL(3+rz3$xvTAns*;*;$&%$&;j&p}r=K1!>sT9WZEKE) zFPb}Zc4TJ3%(-)m=FGZyc3~L9aTrexVn+FbikjJlD;5^4sJL*^qVS9vO|1=U>biPj z7^u6t&Z%yQ6h{!t+&8qJ)7IME-PRnQf&ViaV?F02_c?}VlrJe?Pyhswqz@A!?`0AJ%FlM19n&Yj^bPB45 zru%E-T)uZrt)_ z;bFZQW9Y1oRaefEq@+fB3U(Bkdb`2=u5M^T)a{I><`{Z!b9-ZJbJsa*N5Q(L@Qk)m z5Zf`ct*aZi{N-}qxrpT!UoXmWfp4Y8AEP00Xk*mm!L~dW`B5Q{p|+3kWgHF%UNk=c z5JHf};f-hs$Gkc_i)uE0+mc%>3^CgP8WCKN!<+INN4p zD|0qs*WjSqF9mt_Ln*d-3wg+>Jed>^m3ZW5octS-k%$Rm*CC=!M94UG>Z-+?JVn(? zWyw3r$)!mV5VQh@9E$^q__$b)pP8<<{@ZU%0cAnpNg7XP^0`euR4-E-#>&)&F$mxz z9S;@cqaJsv^Rbf~xUvWlc^qMlTI^nq&BMgO^a(<|kUfd83ayV2%(;ZMY6BPI^NB;= zX@uZEo$zC7G2Mk~Lso^_fVB{>K}bJAZNR!jZL|XYOvXd$S%jCV4OQTe5~2 zg(HdNgKBBi1%wylTrff~AjQubrGTx))AJdkM?ubqRi!T&zaoab*$PBh7POkj8|<34Pi8O z%XY-PBe1PWFKr8KFKH8%5onO3X@qR-(gf>WN!m8wOJMb$1DBU0F zqX^%aO5IbHZruNlm2STImb%f6WRsnC>~yoxrS9oU_sPdjH}0aAZgdZsZ``JjRhc_e zF3e}7Zrt)mQ@4KGoP&J3y;+{2jKDl&G>y;)OSCl_p}ZT;QwCrnQ*sU{%IDN6n}Hsc2j= zt^w0gXxYTk`aZ63_)d}W{Df&DbNqB^E<*kZG12CyN)sbvlyI^2Y0^x?G#EG?6V(%r z!9pCs^hzil;&{VxnqlHfR`6K4u0=ktK!U6rNRV?$SSTM!pg}%@K(nk{B$1C2>4d1x zafGOTIezEjXm8@vtZJqY4NOAil%Hc8r}DDdqib=Tr4J3v%%mfUEJ9SX?3<`AIio?f z${8N2Gn;f2D_W9#j=_vVerkgW(vbw4n?SX~6gdrLv$CGkc##YcF>FAoF}V}S2RAZ9 z0`n`&PEq)ke*lHXv?VHzd1bzIdGzH1=V?O%?bp?ufC79;R)(83&%^ge6r?_m+1w~P zDbG=bg5IPlutj5VkzXcl8#lpVn?_mo_1Q`u;~0*{hn6b!+GTTxtXP>u{;^HCJVm}P z#b-;PyieMQ20!KD8;ge2rqS)o&A5O`cta!^wLR zd{=vo1ManNK02;#pWR-ElUD`4&J^T5rpbc|G7Km0dGM`EL0%LCifx}9TaacrdDS4M zV&5K3o*bKwBJaf%<&|Qfv+a{(o09h^pxvi%DQduX1}{9p%Xc04ZuRgGeHK5x-KW8L zmIK>8o;ze1u3RR9Z>^&1z}pTsfX~jyRK+-)ygR^`N;^HG$>Z3_Fr2&~ZVai&>js}~ z-*ijdu<|yhDDR*qFMkAiykVtcUmN&r`%W7{-i8$Ay`jmo+s$z0cLaQ?j6-X2!?o?3 zIf8wk1Yaus=xt42M3eU_u5r(bsVMOQ_%5^&4SL)Cax`L28NI>V?(YL1^|9U0R?IAy zKjNqNj~Bt$qV5a!y_S4`!B6j(^K+B^2P7xJ<)cg93h=!FD)r7$T$DGfa86hcAGUUO zcF}BW>1_DJ*Up}6-O!x1vlD3f|9b6gyrZe1yTQArW5@!IArVJeIO|>D%7rxl%(B+o zRAE}+(BKvg=d#lWHJmS#9|msCj!6iJ@8WMhYefbu8v`uT@aHXp{OiNZc(=SX!3Jvw zABL3wu@OKYngD!!O8FVUGof!PaLUK{A@L}12HHgW#lU&ZL67)Hx-4w<%H+4-mC0|6 zE3L2MT1=f4(-Y@Hhq{iQ?xU_9n`yO=IdWZ*bzO(mL+T34htw6;54l$b%^lKWhOQHm zZD{^5OI1d5^~=APUi^FMg<4!`eZ?PUWk<3b{d?&J7My=Bl09GQsq00TbpKHvmEKc*B$>^R)_ z47q_Mn^O#gDGJ(~dCpLHM8P5j&sH!BxCO6JDivO<;0gt|5Ju_6(-4D;;O>`r3B7g# zUkrs|L->(C1jvvL7~F_Q2E1-N54Zd?03S;KixC0Ls|txCKysc9_zk?WivluiiNXc< zDPrPbz%b^!MJ0yl#XM~u;O}pN34m+iyR;l|;P=Zjv+Cgz8R@bC!+)Rbp8}XRP$R;C z&mle!kRjiKzB3da0clmHadE|e=Y?7H{b?&V2G`{0TW^4$j+%p<4R|Ak~HS6WIq0= zm*99Ie3X~q`mqbvp$kWS0WJ)_3dI~sK1!gJ2Zh!&r4^9gkld1BnuH{+0RamXD1um> z(I4}Boe`AhL&Y}*Ey8F`=OLpaLctkzWPGpVfHLEZ(<0+AqmuXkuf6xV`|RAb7wL`D z`DG{P?!DGtXYG%(&;D3zuYHoP3s-6|YRqQk2x~`k!?9OtABGeXE?lXVGUvbdN=@t> zX&&HDxkt^oMov^gdW+VpS~g3CD9+R~p6$Tf5l%YrhY>D! zU}`JoIq=63#s>~UezbF}bl}e-Ol6sN3H3-AX8tF8&u6mQABitk2P5zl`NE3jMlBWX z9IYdKn(fdKCcMCdFZAF`Jvi;byBv5r_H+PUy1OU2HpyIp@en(&45`2Y@?(sVQCrGn5Cf_k#vUMV9a`7>L0Hv9tkJBEQ`9mE##mz+q*j+h`WS#>?~C~_MG#vl6}o$cthiqjG0adtr=OFOc9?- zmB0i?o966)HK>=+@W`qJO@&}ivti!U;aDUNS57zEt(2vE==!pjpj{ z%}q2>XdbzA`lC#vGc|G<{q($3UMgBJYdEnWajNA_z8PVS7o(4&4@XmO@+WpHlb0cMmp%U zWoH_6$5=a^ng(_+d_M8S=8stF?>i|NmY1dBfMlg}!2 zMK@f2L~TA$BT|Vdd_FTVl?649>xdLC+ImRZ*w!>&X>&~@X`?12Z9K&BN}KB?NgJ(A z(njmcXWA5fT1Q#NvKcq-oODOQo$$M$ zZ)TD{kmbbV<*B5P`_F@43ci$mOo6boi9X(7$_uC94Zex-cnCWQgU>Gby#GGJ;Kw>5 z{1{;*_Beg)+V~6lNwbl6juQC{^YHlB)xbL_0@ltccZYg}qJOX5nvJP&%rHmt} z*0PEKJp*MF0eS|?CW0z0lL+w8C~FERm(?3`DSEa}R_?_VQ^4VsMeRtxBvM>7WxiVM z)R3C=I|=%z(#iBuWZWwCIfXu|NM1`+5m-qlhu%Qy8E>TQLg6D(Nz-4>(T_$a%7~0Z zmzdR|Bs#AqmUM4qp=5p>sf1L`4iu8*FS+~ zSbj~04xYHRctAFe2peuin77;ft(ON$3hgZGG{9WwK4j?3?TY+ZHs9R?gyqe+dqFqg z69K*-m$X3>Hv&37Pv%$J9(>l*=W)4oC!--A0FHFFzDeh&`#k8j0q;9M-6kYz)1^V(B+c9Cmeq4PU*7o`!?u4 zrlTXjet9>dkT!p_3?=z-!ihHDXK%h1bQ>(-_}@d=eZF4@9Ywb+FZs~X{~<27UA>GK zpYOi!UID`8_wOLu1swUITN6iq#T84(*cG=pyRM~XNhP!}bjQ}Uyez$GM%VJ+a#!5V zrZ%;AWaN(=n7iWkI57LQPXnIH#~@DcnyYl+F9W~Ef!TsO9r#;-`RQ@(3i;K^&~evX zG`%AA(=e7TF`-_Mz>^ie{H&NhTLpK)T?ClvTbN1-rq5o6@wAGeV;KnF2AKKbTS<5i zV8)dj__zwWBfIK&B#PZn$CYtDHqx0bb&v>~5CqXtN$^|PT$jlt#Hs&P<*XBu&Z7w+9# z#GFs;-IGdjpCP|N&>~p-b7Z6wLAFU=+>5szKA)F`cOq;Zm#rVQfcQ9b+kv^vjK&wK zPetMr>Q5u^G%*Itpc3lO0a!r^bMnSkcynIDhZoDYEzP0wRoHN+)k0I(qU>d|=YPK&_(^PLKgL-Kwu;1`|vhDiKu^Q4Y?PE|;#&qU(OrLT1N3i5fm@LzyF z8QzmnPa*8?9eg&7V|r)G^K;{0Lj0PLCZS#q!=#_5eieZyd+i0rdbXoOzIetyzj0t) z9BN5^)4)2&!qjpP-sr*pUO>zPLdW~>^58ul{ACY*#)JPB@ZW+D6$RY8cLeZV2(K}4 zF*@7tBh2xW@n-<0ps(7%b%5#kzD>vbvjXrtQAd{keSrC04d#{ie*iGY7}68|Am9rT zo@wAa0kewv4l(`{fZ4xW`p*D94RF%LKMwd(++g$bEMV?uooC{I3iuxoE;I0Jfa$E* z=k1GeWLt?oFCXK>So;&(BfAjWv6l_sm@ymXA_kDydTowHk8T3|!*4xwc5H`7xcg_} z+wG3tS@<>KhDGm`dw1KS!@nlnyoi8{54SL8-PGt(hB=8=BhSN+3cB9fmPgr**w}`3 zGz?q2dV6G-o!)b|yuTmcHE<7PU)9l_UXD%lI^H40#yxKvWO#u4V3*y{nAzgkGSu4N z)-%w>1nu$ZV1X@`qtSzHgK6xRl)aWX^?EaRPU^O|ez2`SgCCs*Y`o+R;E4m{Bh6Jd zX&Th>p{{{JWP;l?oA?PMeHeKJwCQIEWTzr&TDGuK^zAw<6=b5gWl`@4-Gba^3L;0_ zyEQ|4@boIiV7+=F_VRT904k3elbPIh?Dw6J2u?@@CnSO=utYFilVv|}T%Vn<4X`;f zAOC%j;QDrjd0`pGKH&Vq=Rf{zEFJ`$0+nFj;RBuOaIAzo4wKFMUoENUenjGlNjw@P zOZJy6h`khppNYpl#$?I9sX{Ybb}g!Tzj>i#Kku#FH?q2=b4Dj<4y~H~oyS@`A8eTN z;?(k)zlpv6$`ubclnuW;t7F&BhQr@i$;$mPTyNko^|nrR_UvICTt0vL!Bw3%JgVkS zJ!8^u;=lgt6;I%f$7gNdb!Wo`!&lC}r{P!Mzo#LFdtclCU?(V&w_>N`1G2~QfzH?V zkE~kBy_hR^bgEqk9>byNWx@6FvWDw}vfHjd?a^S)$m)W*u|t@@&5if}<@IvJJN9kH z<`)dBvX7(^DLEK@rRwZk!D$`qst$EAtvSF>%wS>cg;=thr5p+7O*(jXGi#()YOH#H z-#$<+ENDKpnN)p36`L1(AwZavyes)+CGO~xJNl@y0_(ya`EASQb~oO(&f)4KwPZSW!?EPZT63B?=Qoi9}*@qBt?7 zXlml5q8&letwGUkLDB6&(axagj-cqypy;k3u`5X29V9*yB<=|k_XdfN28sKE#K!{8 zsjXw!?5$jdjbYEF0CQty2Yo9Lfsd)QQuStol8ncFbLeBS!1=mbW;O!>e->dZ5;(8t#;*nR zPc<7Z>y$#4WYNHN02dgzMK(SyrH`NU=|lG`YwP7wB-!|cBxC^slw_irK8RM+KSQZY z=r@@I%ood(*)~J)b#HLf&VoDQccMSoAiKXMTLzN?QGh$7 zvQUD&Z2jh&P>g8>)4>s3#uN01m&5U&na(m&2ceCcVq} z&oCZEd(pr@GX87y@kl6ICOt*S^eGw+F!nEjPrl9YOEHXJW#Df5$jlJ&RDws&M21>1 z2!N!9C{7<8OaXliYLn<=WMRAGghdpKC}x82sb+#S3)~6g{fAyjiZ6W>-V2P)GT{I# zneAY_l+9&eDH9KwNU>pgjy0Ffp#VCMCX#e-WFcfeq)aA`o6`AVRF)49N*wdRfmO<^ zQECqg{96}c@aW?7B+*{UgUiT-eSW`l_-TD}_UADT zFJ&&}y#aJKf9%!ivgPmY9Qpm5!w=n~xNQ6;p>lJ{-}Rug`AZ&!->o_F`xl2_*-`lY zE=PV{m=oLll^=!Q4WQd;;$3gl^L6-Px*;xG{Y^t-y4z)B!al!GfzIY{o}nQ>3PI54 z_8FA=9OyP!!12F_u-m`<26TIYWB)=vbo76S%l4VXeG&6@`+gI)?iB=Fe)~bU132&kS%j>d8fvI+k=%_RANq&gQgPQY#ua~L&r%|i873>skB;1twnS7k2WUpB=wV8x0ZM^hOpX|d>6Ht z2Ogs?QtR%hd7~z?+M&d!i+4dQ2ijUgd*CrOZ`LsH(z-uKGZ%-7&T8r6(5m4d6Gdv~ zVw*5Fj)y{qW3*95tPT}25F&H{A6TIUe2(Yb?FR9ROnhZ-jJ2A~buomC{0MVhh%H3B zCUPOHAwePn6fB!$;)`X6OblfH1R{ukg?yco>*;zc69fL+!}w&f-qTjeBwNUS^7pJ_;1!_dH(q?=TV1jgnNN069r2 z(M04e^Y~Q(W-@5R;w}c=jV4SF*$}rBzixJ(1fA5KiML^HU?82nZ$Ic5;)eMZENKB3@-P%y%WL-8;_{a{RknK-+Mrp1djY< z)PPTZT5>X&MRJ0p6e=MfvA;N%TA-ziYnDnN2g%8kI;Bu@at^b8qDfA$5OsGW>w~OE zA@g@|bqk(S#{GWs72Dget=yeqhL)-2EA|a#`~#7AEnle*aoOc7S2*#{g<-b*nPS{> zb%-leuY_U7pDM;JH-)%D&$wllI@xLNahL(nn8ms{Bq5Z)+-VWWKaE+ei(^Ja{l+ef zK>T|n@u#a4;N4C zAAmodeMW@8=g_lf`I!g5>A}%eW)Y@~_|T0BNsZ;vv#LDk^HLHg+eQam=)1Nm1>dI_=@ z)Sj&eQbPtdZ{L#M+)0UA|67;jWf$6s#Eo_i*-nVgBD~9p{W2yNS??8zUgO5r^uVCD za?r9p%K6q0^0?+vF}-~rs&%Ld-@aSZ+ty*yYPE7g%J|$^4a*7Fq5Xt=4z`XrLPiJJ z*frR>w$GS`SUfZ5k!n2#H33U_#tDA#R)yH=gL?Mo#39EpFtfcKpSS z;CfsPBUpy9#f=pG&1f#hAa5gon;(c$^c)y)(i#`f-i^{^2j zW`vS42qGzT(dTg*B8x%5t#W*a4iQHwIEVAY#iJBd!D; zNM!T>8T664GwDNOgd~MIZk5gdNK*J#)1PO)%v+*28uGyAI^x0PT>8MDM;{WLi|7N7 zJ%}Pxt)~wrP4tn;<@Ax>D*9&|y8z%XAq={;2EUH}EOQpcBD1hZW-lim^V5y=7aIG3 zx#K5m@#PZVSz@Lsw z1=mIZ%MHl_nqEG$0AXwB3Un6C9(@R7Bm-#M`OJV@2V73Mb%1wMvH)Qk-W(N^*E}dV zDHcr47$6l*EjqcVq-c84DMd4iW){7p=+rw%8>^40X~F3#Hu9zlS}K!4OBJqaTs63A zaV^HR1lLkrb-2z=##^c?`BTN8YW~#l2gFU4K~q)GR2?+c1WmO;)8e3MNzk-3XsQdE z&W$%!RpP3`RgJ3#S1qo^vV07%zV+)bp%Umo6QgXW60n_0>Pg>1q3i;amkI zg5!DStZp8LgchcX%auyf$C!Kp{89|OO$KI;i<8br?QQ>j0uKNmld&G>*-T>fRYA(=yil$t{3Sx8P0WCDUhu&r{S z#~33e;7iK^9UZ<5)bdVoH1J%l2V0PJkK{u~y6HrEj{M!nvm7+*OukWf;*hOTTB}c@ zK=v>dLnfZDwfY_kn2XkGGYXiC)@l%R_d5yNy!%=!36&*;()Ia00=k_@%XfY`D#6V1qff_j`26Y-IUupoAD`cs z9ex-~#bx976zHyxvJ%MWSBs8@`C>iKH1yf{HGwXd{C(Bohu2sf`R&E!wu5hhZh?-D z{Q7ji0^Qva3Jv@vJhvU(gvww#EC+@gaoNg2JBF<$-u3)?IRZLcFMPM@vhj;yZjnp7 z+6p?$PZm#O@VgmweUe)A$IsutIQ&jGq}lTKyBzb^g@RyCNtLcl>|3H||!Vhauez|%6&m-_u^$iDRQ)7cgn>Vgdea8mj$02`-(ih1o ze&r!ep*j?XNk3ivE8z1&T%mkr*n)9PUkcGAwpawx=U0ZUi=(9P0nEWjyFxjY%|da^ zL2D7e(;{&H1s;4cV7^G&70O`DIo&KN&8AwarIWR7o4^fN|WQtJKXXfurTg zD1oB|s=@8iK7X`@#^{6h^oND@Q&`iBQ|NjI)vA`pWotI;v-9v2U`c`Ja9KJHiwvVt zbxz}J+18`go4|#)@CH69d@wgutO8|ppQ6%rSTuIylf|Ps>nAVw`*%3!`Z;{0ZRmsl zJgmvbgqC$e%Q~TDJ<+wS?asiGgSyov&x798Wq({0ur9-+Xkz;xA6XgeoPH#B^6cSN zvtub9$A*vWcFuaVzBG|iFI@9@-wLa39a-6w!clW68hud9st>LkS-Gq;=$unORm~cX zl}~Ss$pLW+pV1AExZ9thZRm`3metSsr=Xx9_2$nxadka+IFh3NmI+LB$8LQpzc#;&8n&*l3`0Qr&Fk!W*bQqJ9`;)1G z{WMES37<*L$?*8SdCf3N5v>)|p#;_*@s>Fv&Qt9Qg{#!nVN9w*6*0cC3ze`oTH(Sk zUs|!L%(QV_H>7a6)({efm8MK1QC%WvonjWX0A$7qNfuD@eOt(_WbwkeC5a&)kj0Ly zNtPJl3HXT61M#yN58{Z%7x87p<0e_$*P4^xAn>0@JfxDGFLIHzkbbE-w4_GKfj3MS zLBZozq38URc+vbOJl~m<$Y&1R2M{1#Nqde-JDK0KU3FC*(xyF|In4|EEF>rBHRU;=L(69^P>^LE za}`?Fr2qtHm`s!-;zA(W(rwptsaOqyjn#`Pm#9gNz5UqLyztW6W>q+?=+d|NL21_e z6!b+LTIh3VC@#?5!jxHBB(Viu{zV4gKsw-C2?L*kU%E)C>j>k%9{7yE3I3LIwAhO9 zPQU^BnqBmZ^oOHKf4_n6h0m|KQ;bBu6c=s5kg*p&KXiS7c);JLkJ2BckD=se^f6?- zMju0nRdnL3&p2=_(BF_i^9BoKOp64my+sl-r1Hh*(1|QbC4f}qDwF9W-!e4gO~kD- z6iS;-8hJBX23X0?DjBjR5h5~9hRzHahBy^)$w_xOjLig?E}xNg<+yPNZsfhFPI2g} zN9jNxLf!tod!wP{ltHE;2EGFY&*kgR=cC|mOEtI4VX@>V^$33*E67Oz*${_EC$f86 z=5^CFY@$U}%kTxboZA)YEDy%p@ESvBi`WV}*I6F#&yjAx&{-bj$2RV}+kvpW8TT;g zx_u(RyKzYyGI2A}Q23mfUse$v+uDP;T)J}5RU!e>Nt-ite!8t_aJi&=0CYB8X`^HC zJBY|3#QDxI$4W4>{3r^gV>$f%Z2}SN)OS9=?>hWu7~*XFUdoZ*WylmrrT%Pt&BpI) z(B)Ep&p7l50OGUp`+uOz zrM#EmA=v!Ma$*dASAy%a*@aK)21ryPnVQikX@G%`t@Jw+|Qk zmOgv$b)ef|0mpwDVYmK1zHhb1hqdhWUS9va=T&(iuL1}eBv$2gx^|2=h#QBm_K zZQ>}z37}rwD79mMj*M)zLHJY$4o2W9(wAjWg|fM-Iz$wz`@%5qKS@4hhE=(7h3bFW zAbg&s^%eNHg}6fX^)Sr%Q`C0>?+$T=@{uSD($@2*0RGq_kl%j_!@U1g^&fyakJ7FX zJ4tPr@v~G3;5{L#Fml!wKU8)W;vaD0IsRA|hj4-F!-p&a>2oiSb#cfIHUfUwA`qX7 z#3xlR;76Qzo)BwY9P)y@0PnR3+)s6&b#ZK4|8xW{l9LN;JZElSj>IR_(-C;G`a1_k zH>h6o;6lEv#xZ`j2iJJ;3J<=@gZn(#|FGDnz4)(sFl{-lV}5?>!T;&OC!^!Dj`aMn zn016N@?d^Q>`TCNE=BcWFJR8k))@FUz^tNb1Ahu|4Z@cG5x}R}KLz+tocJFD z{23s!QqrQ`4~-d|)m&?}qd{7owaatWfW}%Csv)JBYQwfITkvtL2n(Ec zH?Xd4+d!ytHS{e*g7t}8(gWMJ;u~LXimhX?fQ2g=`^4E;Y#2zl4rR;U#x{Hzt>@b2 z-hQbi>gr7fow{?ers^D2SaS}}sU!#M){%pDt0;mt#f#u<=^Uh6KN0lk`&);y+#jhN zhe5P%CUnjdI_C+U^NFr=ZnF!rW1II{(md#zE$ic=XSU3aqGK-Er^==`tMY_sX|bKI zT+LBQYHAY*7am$5T3o`ssPBb8JR6!@RW@fR5X$6}bB1E}p5&?fQ@g(OMuFll78Cfz zkvF@F>%Q~`=BlCt)&~`mp8|F4hGl0zAqNh|lF)C1`>`&}_n^$3q?N$oFEzzf@=nr9 z-tafnAX`IUOK3hQCO2gdZ$d)(QWQhT5jxJUU9}G;wH-i>vJ75qgw*<5pGWuAVG|)$6Gkq{$ zL4T$`qKlt0=7NO!;Y;a5IdK_%Fm0i~$mok_89^;H6nu1)NWYIhbSYQR$I9hu`jEzK zraxP$6n!YGS>IgcxV+IZ#1J#ENi zC2e#o&?UGTV<8%hgF8{K?f6z1r&#BvwUR4jQh zjEVx9V<$hm#W9nXyBJnfDF)Jd!XR2rzg#N^iZSMHCybkJq(4t9#%U?M8*u3YW4Vhl z^nSt^GxyNP82JEwr1KDcjDZxq@^fI1(8n0Jmp&7ZSo{V7Fc1dwU#18J^wIZEqK`6R zBpTc17w;`dWN1d$Ekm*N>u6i(PGzWN->&zeF_3XGMaY0*i1J0ri@}iY7h!BB!1N^V z26Z}bMCN%fYE@hbemT^+{7y%~wo4&3js2yLj4Z7CB*wwdWuYqvflGHj3W%;`ltax6 zozx$~>p=Gvhsx%i@>Q2#0mcG1SsUgQh;;V81n696dGNi;g|5fYSsvt^V5A6bT(aS zd$@t=`uzS5bh(scE!w!{N1rYmzs;b_C4b*__#r4R8^4!w~FYS4NjDf8WoM-^Iw3%^$i2aoPB-1zj%r`?J99e$-p;rCRI{3`GeZ2po*;de3Ua>?Hp9e!m;;rF#1`JIKijLjeWMmj#M8Iu|KeVC;2^t%l2^ys#-KAbRDDIkAQLcHG-}aIP#lk zsL2nuz13Q=p49GGdiUDe+8RxHY`yz{jD8ut`)SPjTh_aaRqub>4_V0?+&mDaj*Qrr z!U2!Ay*t7td>ACSQBEC7K@jq-eL;YhI$NLkKUIvv=|Cs?0KUqz6T6Y{nAvg3{$AQ9Cz7uZr z;xG5$Yd!dbfQe!qor3zg8vrLgcs~UG6TlGN80Bq|*w%8=!RJBx(XUF0?AKV8ANZNfypwY$Guvg zDUr_6vIe$C&jQqG(wcHYBQ>Fsn$Sp{=o%@f%gn(D(xJ|SUdrKqTvSsIzoTlWj2)xs zo~SWOcESQO#j|7y$+eQd`(KUK!ym@b1*c;z&f;MV=xB=ybQse_1YjFz15^cV0*~=f z{BUG;6+e(vbO6PpVa37c08VXI_Dtb70@34?epeZ-g3$1?g1`XD-+K2|RItP-#f9kReGxi1D&xaU#;c#f%53JN)1 znV=X!GSOr+G1X)OHJ8s!Aeqpy5u|VhSoBB*AXj;jV=|#))VnN_&=gquVk`#Pgr;C+ z#iqjeBz+*u4gO5Rpj!mL6z!}QK6RGo5fAzX;z7?jGe3w$IV4SS5VCSR&N7)i7jV+T zQNOYVWF9<6_SqcY5TqJ9(j5+=OaQE9O=vNkZXd+Odyz|VCHRGyBf{@>WcX`L#B+R; zT=bu#Adg95qJ*q2m#z(Ebz8ipu0nv1z?Nk@=v;O-yu|R6dP10VtKnN`=`H}mP4~bU z{MHycc`gWl6LhY#Jl+o^!^ff9 zCXk=M4}#9-k8PNa`P+vJZK{tj-CdyDpo5X$rvbV3{CA-11djEG*Hj$&J&((_2_l;? z^w@a9*8Kzlm)|9zn+F{E$*2UM{2-U9G2aUJH?IG&UU0ju`T;^jk&Sm5>XEW<> zSuUeRGX1?B`09wiS{!8tF$!@4*hO56=a6wnMs79$pH&P`_g46uP;(kCRCfTr3NYIn zMK^cD=XbXGJPCgkezyZtbi;lLO-lIffo~n{EUV&D9O4SqB$UNE9>X>h@S7Ha{LPNU zzf+w9I0$itswNDR|7ofLFpqlEu28KG!;F8odLQ885Lc+K3B!zkkGdXkS%@oCH-=%x zpDv=F^Fmyq`a~FJ{2cj)R!fL0R9^_gjGrs@&F5|N_hcAme8PJk3H3}QK5Az{(bnru zJVja4*pQ4Pe3l2-doYhhvySv1@Zb-7@FzU@Gamf72Y=s#f8oL5RxG5=^k<_(wT^JD z2Vd^NH+k?L5B{15|HOlT?ZKznK^|!{{c}Bd72uDXIND`=0Py*E2AGwBzEJG~{8@xK zS0emrzzH;rVdUQ{FhS3Z&mhmx@Zd3_H??a@G?A| z&O5Zu3PU~151V9_XZc~%tnw^BY@*(Ic07kp3`@N8>}rtg+Z3fP>*(lD4-7PSbq{7F zrn2+ijfff+xG~l)W7I9!-ESqS%Zv%gF$@+O^<%eUTP^4nGn4SZI|ye5VeL*tlDlg8 z^5we4Eo*O2_YF4pw{1;ZQE(?XVz+D>E)SuzQfBfN)vj21 zqmeXcC@7ci$KCC11B0gGvt$%hQUr6_Up6jldV8)l46;S9YwKz3?d``|fo+4m)(R$) z4N$DIW;4-<{@$%!1MS;-w+&p{+hHwQA|&fOaqNXnee-5H7Gv|)^w##i8)~)aJVU-& z*Mw6wqbQ;ejZfXVy(!(*(`5wm4mxuxqKnL!19@CfqfT{?j*M3K==ex=kB;`MJ1YgN zJ4=LL-J?k&)jgqTm{2rKC>l<5MT0XZ8bi@wr&ARf(uz^jspJ2}yG&}w=gW5vzoTd! z`u6SGtMv}4A?g;A^80}N9vb>6Y+JNd%OTjdBvkV5FTGK$Vq)1cN$D@!P14phN!q-W zl<{0dTrnjUF>#@shOh7z>{bs?+O6S2xudWlF&sOCX&&n2@4V*3-ahC$$bqocXsCU+ z?dHv#6=Z*K_#pACwCD)sX3+nMtu(ByvFMA zdwYlWupowXz*$#eIiMZp{Sa{LKVqg}$3p!jYgB#v z`#wfE9-CSjsAK-?PyQi=c&sqA{s{xt>L)%5B>@L7Kpwqp$?2Q5+vLjxMf7v&RsB1^9~wn6iZup1It5yG9L_lNKV zsrQh+MyVwI#YQEx)Yt-DWX_Bs%sfkbX>-SNTu&d$jeh#5tO5F~ zl=>ij#NS9CQuhzhKV2Vurs|d2LAXi_o=LZp@Ej#VG=2*4Zo;UfP4M!ibwss#tQByoN!z?V`D%q()1GD0#v3~B<$jk*8@)h2(?$_P z$FR})XHI*CmO`FAdYwOLJ}?MLKG3`ULGzI``9Lq4&wONUk7Xup^w4=xw-=%T@Z3r! zUX0;|-ElF75jKqCdi{ad;sxfM&BZd}sbUPD9QGC$XcO1P80%A{$FST-AH(`~`WUWv z(8ut8C;cXT*AD*TA|=~dix=s0HA^vEe~$4OhWFAxTidEIohJxmnEpENLuQ{LT&dJ^ z^sBYrq!h#0&j@39{Uv=2r@y9;;qy)SrN9R<_`p-oQ3^aiWmAm%N(o~aJ=4HT2xHj1 z$iSBo#&AjfL}{JYBXQ~&HDki5o(1Mi&&kwDz+v=4^~e-Nrb6h=k$ssup!lM6CmT)$ zaElE6#q{ygO`(rQFAV~X4ykorZ07%QR;`NfX_=M7=-aqR6SiZ@D3y}ER`0e zEBELwMk4O$WvTI)grC$i!mXgYiG?%HvPQEMI$M^5s6eSpkM3eaXVB^p=qwN7Y5w2LQvY6LH#r6SYGDWb~1ew@~#HmkdBW0`p@J4IQ-BZip$3D#T@yqMj>tf(5;Ti z?+Vc6lD`)neshk(@28;4<#}9&382m2T!-Hi2%|skGbnX6=r&lu@xP6*`~H3zbam$a zwS6M%??qg0|MCkwEWE;_+#z6Gej}jU4IKM}vvARopFTqr-_zpxp>&}w(-?bZY8NlY z7Yyl+ZOinsjDDFtGZVH<(T7(6+oku(qp&|mMtV(<51AWaZn9DEY0Gqb1fD9BvJ9$7 z4n;(tWL%LPf@mRbXn6!crA2_>SHdv)PghR?t_yKRa*(JCbMl5cmT^VS<`>>SL-OOs zzhX(@bHm4X9hgn<*A7furi9bFx#1(}z!=lyyM*=@!mGUat38;TiL4|2P7iiBv@rg2 zh-U|l_YV{5BK0_6-oiR1{7nE=2=k>R{6oN)o62GK$HmskO31ImOR0An@a-Jy=*X^t zhVHaIEl_mnQN4anc24f$jn233!fgm1ODOr@rg9#7%XNcY>&(^)qv>r}vwU5Dx@{|p zi}(z3{S7_s8=>@#AUAe)4W@f=te}JKPFt<2D7H~C&bQw{*VxiX#O1IE6OAPj+-&cl zdXjKP0V_~c^GX!>Z0j=`ebN4|YlB*T01a_jOLEy|>sKWkD;m!^C)wD$wXdr?-JiUC z>7ts-MOBNIF0EZsv9YE)xuv&1xvb?+9pr zg$viURW7asmfyx}>$$MIYjChTom`0jh3$RYF3fzRA-S;WvZmz?8&)J2uI;=rxp39M zwrfV~(s+i~wdtN?L{|)?uLsGZiVBBG!M-N@!#dV|747ncj<} zjLz#=9D28I?H#kBWr{Xd4#G;xq2GzOP2SD?ud=fOgXc{nbnQBs&i-2;QzNWA`rfx-0FHLL;bJZnP0*fx!< ziX{_$@#Owj1F?I;_u1AYhw2{H+P-98sHxjOvQiE8t-w$R*SBx?e?D+{YV$jqOPf_O zY4urrhlZ3SAdhM6h? zn~+w%WXN_|$MSG=7fr@WtI2@OqXWoM7F4s1dJL0p&Y!9Fk$E;`IaUTFvL3|Cx^|Y9 z%aKUdrC1DcdO^Vuq9B+u7F5WMtZR^yGU7pW27Sy!@>vOXEoG952$UO~&o`m0QXME} zKC?5G`7n+%tQ0O+Q<=}S@gzcb5kijM^r{)^n@|7Mb17g0JYA^?Jixq2b-6+-Myq1+ zr$BVWNhyt=*jflPn>31=Z}6PV6JH0PyNg#d9<62_eYB>l=%aOQhfm`wk$%E@3L#3t zaEAyY5tNpUb}temS#;|48!@4)4MWiY=g7j#ph?itOvH1(AaWWCuty3LB`gQ%-u`*KkZuoPsX4dji*3{X2I$=TY28E?oy`K*LiQfU)uETLafEGn4Z@_8=K}u%=}izY&hmIa;9Tf1BaNg>erH-{j(@vH zcMa&aIq^2Q8vztCbUy?gpA++I-&)q&gScF}pM!1(aHQk2rz4%8?zM>gu*61x{B(Z? zI-9O5i1hjW8g$)JRs#9_u0iH4KUWax^XmuQEjjQz?C_HgANR1l`*6h_K@bOk4O#d- x4V+tl8$g!=j`fGmR~-30kIS|RBKLvL#uK*gCkVLwz7D#1z>%K}MDWS){{wIIR4xDj diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG1/librail_efr32xg1_gcc_release.a new file mode 100644 index 0000000000000000000000000000000000000000..bc0ab389b7e484c90b771e200f829421bcfdf5f0 GIT binary patch literal 216622 zcmeFa3wT`Bc`m&6%t#uKWb0;wEE{{Ik&W;zvMdr4+%TGv#*#+1gd~FlB%0A^Bn_4{ z!_1h-T*ak{lWs;{a)S0&Q#upA&j;jTNw)?a9W@D zTWhbq*WMZ#=Oj6&KhM7&ZSB3j?_KY@?scEFt2RZ`v7wK7KIFBU^$i=ZSYOvr-|!Ky zw~njS|6cFg3mMdyS}1s#^OhQH`l$dGPe7X|2Nl@*D?10 z`uf`tW9PemQpVW%uGjvCvHxP1w(uhMJGs_`n3n6h@*vaXwfP^J_Pe+~`AMd!*T4^$ zM%Rw<-|h98Z!^t)eeorxeGspI*~2ut-uvVKYnP)kpZ)*Wf6+A9`#t9Pb+2!Jk~!4t zfA%v+uIqb4%#rK*Tlo2#UjOtB=E!xu3Hke7GaqG+IWDKGjQ!fz!aJB#y_R0Xoc|}+ zn!jVtU*~G9XU@5=#%+uM5^caC+(v)RPxV5W0;xILLn^+jVlSPpH}uI$bxQxX_V zj@}$kXTjE)6T{KI;kbZ79N3kOXKdo0vBuaA;T&NQ zP({`i&*YHiBI+75S^9Pk#Ja}1v*~zr1c|DLQwJa*R)OM2>uAEJv_lbBiiK6&luo8{ zh&z#*@vJSvGMwj&15Z+TBYkO)j}B&sMEr8Q69{s*H9lsGLMSmB9ZuX5ZyfEXxKrYE z#z*_R#zN`nNW3|nPNuoAM@g~PP;X;Xuoros=u1ZtlGd(ZV|%YrC|EkynufM1nvLo@ zWZ&lDWM6a`;+|b8=>%Tp5>sXiPM+rCu{(Nm9Ay^el9E`L#j_OB_)RrUk`sXW!6(x3d)sBWb!5T4?xDS`KMr*zgCPY)#1BM9Tb&e2#lk(6$9 z1?y^TYVGK4-`dz4iw2&TMLDwln#uc$&xuJEJ0-NXMle0|R)AD8(VE zuj}s{5dd8>OCS{H$hDm)(^RB7 zyE=MWw={R@4x~*q28NQiD~7E#gD8$tRceStt!Y@Bhoh-Xyq_X$VtP8Z^^hcOWmCk| z02v&HoF|zKSTLA_!Vp>ru1!Z%TXqg-6DhPh2Ca^5&4^6ypQQ;#Q(0;jO&7y>XM4tE zp^zczjt#|;jPb59ql8FRkX&@la)F3gQv?DL9MiM*K+m>Jygi!9>Um}a0~%YdK++lA znNfnuG3Wx=9A!nZlfe^ASy6lxVQZ!l^~}u*UuQZV8_jm0A2BeT{8UeJTgIf`mgz}a z^`=gy&G}MoR(je~2f+*u4DvEA1KAWGj_#sBw0yjGTTg3yH?=|3%V~*^^&}fJu|z`E z4aH+SI-}^K>{6tGL^c!8wu*|#;1N=uagD>nv*38G;~AuYhnN~ezOo1$5rlc{ILZcn;Zyg;-&VsAT98PzRp-PB~iceM;2n0Hc zB%jSD*LH#z24rW(lu(zvwi(S;+e6=cS+#FP`#;c$Z@lLK{C%+WymX4-o zn=jPTqS{0El)oS%dR=4a9VB?KNA$S#=LK9cO`HE_ph*I0&kH=5!5E=%IiiL&NwQw+Tct3#4lK|NzF z$>DzVBrHHfY6V{tOQO>mN6uQ%rq~Kc6ORr|yk{&B-PzB3n|fgqa`c#U%F$olHPV+H z?xOyw#RZrWSw)Omx2wCmRR>W?9*hNJQB)Msk&G@yAqoZ?dxp~S%n)K~<_lsGqfQ?> zVTokF$r0=dQt74vR#&K}xx1$~5KlLcq_Vq^`7yjJq9LZvY=-rr4cw6sgM{|@0D9r^ zbWbuH9p>G6i-hMkcOd|%yrc)bH9${S_m5gt#YUayXn!IpiqB3YBsKRs7KH^}nDYQQ zckoj^3Om|XF@~}URckV3+7N%<(Cc1`a6o8=kr!DGqeL-+mP)3xb}0{!a7-f>OZ$)Look<&7$?oBJJZ0)TlbP(b(H-$^DF%E`OK;Zzk)mYk z_TUhWn$g8FMXfdnAJr@BOns_hGXfz9@pg4ZM+f7r85GGxzw{=aMF*@MUFEE-S9Jfm zA~?K5uWf|XY8i@-j*4!*&^9FoyOMZQySQ8Z-OiE83l_h-h zD5V%x7RXaxxGf>bp_c?V$C8_)iP28f6aBINmn4;g)yrq){*}N!8iyZo)%ig+mGm7&~ z=uo1R2#^qNMZc_@vN_$8i0z>Iis^7d35}HWj9nW|k5H$yD;@)qMg{TNN**4;Zn~hb z>%?dXlRaZ|(3nbvMxSmtuQT38N`>KF#f$skFI3Fy@LThW1>kxac}x!kEgOE-VQn z2LI%>1#5~GG=&`#RlNPSyD+ndx~E3|XM;m1%DkhQky0><_++veWumvNqahcWB;{S9 zuEwoRy@aQhg1QXJ)GpL)T-+Ux_jjg~St?1WO8S!{QUeFM72HWCzO$d|9-9MIyt#R6 zb5|?+cj$gorw;Y7tkIdOGdf~9wR%S{r%vtlHqnGu46Yh+}r!f^NcuON=H;PJ-HUdsvA-XUQYMrb##oG|cT|YpdY%_! zOsbq0#iM&(1aHn%&yDz<*O?_2=Lx(;g*Ux59*=iMM_c=IDY}Qy9o43|FH2%z7Zz|Bra4f6Vt9SgP7L;DXkykXL$9Z`9kZau07VG&w?}^q zIA+$1D5UYeorBb|;=M4Mph_pu;paN>CW)6oFo~W7twL}BRqnBMabKA@0UUJx}MEsDS{Tas9`MlTjYwkTu|nn%W>G0J9+Q1JIXha9P)bL3E3 z-{sjJTB{>LKpCiZWKuiO;b}^a#+z@>GFYh7If4PTc$Tx8Y=GByozYB2C>s0l#-rq? z(pWG=eJf`CAsC>#6Sg|zX+1#6>_{48i1aS~nHLh2FP4tRc=k}C#$r$=IgtHSG)=jM znF0On0tPK#7nS3T9!449H1CtryO|NioCde3nA1B`S(e5WgkHu7&oB#|=1Wx=+3^5S z_$m5){(#4y2eiE}OO~!siyT^rN909kHbK3*WGqQj7+jCGx*6+-I)sWEl32HP>_9I( zjm0tesEb-q(lP0uYJz_L4Kx`W*^(MNd! z7%i)r3!i2H=aS3!tUDEtB?c0);82j3DuMy&l)C*q$@Y-BbeOAtfN2o*x zUFU4vnN6Z?wv;SgW>o7u4|JhYqpM;|66#QTy~Px_)vvBGu{aSSD*G3arw6mt1c0!mnf$kfj z&_%WY`9es~SST@&)G7HEf!u-|uRbrkzSO4drbbVjw5 zOKF6`ww*_$9kjwf+lCaOppxV7cNCIh;@fcQR^&Sg0q~t(}K|~IPWe|}=uMQ$|s8L^xBr>s`7}zRRf*Az_ z5MBq9$#g$<_h4p!R^S?Av3M%WJAFAr&NZ|Th=zUk5YYQguR{XkBr$5~jqyQgZ+%03 z-IkVHdNBu?Q@j51xwU=KOneT9q|!qX7>?I(=}Ym|S`jWt*3XhCtp)T=@r0PSr|Kcl z-i%oR-jnOzH5$7XiG=i$^zF^p4q>@~b~BI^-8~sM9zJY)35@ViDw_I+%Qwn+NF%n4eL!=Bf*j)o6&h$+AulC+_Jx#Unh8kGe zl@lsz)I?v7?0Q4dJcdPBln#h!)PY76O_FFs7|veIuR) zBHDbhz9t;;{)dscXiw!1FrJ@VdyL(C$Q4<4!ey&fLsbCx)+Xm0BXTJOm62!Ys_C_e zDpGyB!MF z((6#V&xxO-qe4`3^;0a~*t;pZGIuY9l)RHdJs*;a)ee{ZhO*gY8rB_u|tnngCwGa8QR5L|7*}_r~48jCu};qkar;FaKLpI2Rl=G zL&h__Q|t<1AF}^g(fZTHS+@E*@!LhOH{#K!K6~Q>=?(Q`gX?=Sp|dXeArEh*lulK8 zpm!)bOd3UKIEv}(0Mx(h#k7#YK-~k=DcRoNP0So<8$A7q=-?x0d&vUD$ zZ>wxO$^6gHG%(;xs;1AaubLjesqy6Zs~S%hR0HolF|!>UcQS8qdHeHtZu9vfmxM2g zjN{%h&78i-l5k0NWu!9f=Ko20ON!Vl!s7^i$Mksmy2#?8g>Ccl&c0MWbiM1Xm)vk$ z8ZN0?9P#_QBaXMnyC|)E#5Uz}263k}JN(AfXV}DZh&!bj(jbKA&<%C&5T%EUjWbr~ z_QT$U_%|*KT^z~_?dI{?fA*cJg0pNowsg_4jiL3SRiPl4JJvdmQ^-7%PW>rwlI$H* z=g7CaydnCpIh-t?72sF83y`+Otdf$LEn(PI^-*u_=B?YjJ;~&7#ygNqdmFp9c$-K1 z;{BLA^kSrgJ>r>UI&+z~Vciw$HhAmn)?Z$CdHogM+BCK}V_a6wSmTG`Z8RQ5MWL<1V_uM^cE{FkX<+&D3%1O2c=F3! z3$;bs#m)+Cu~w-q(U!TYHMTCZYa|=(!#$f8_aXTN=UKL{AEQ;at`Aej>qxLJ$B%QA zpYF_wF@Jerf$(O39pY<|qWwpgcJ>c?asl<9_RLa=p4hr{k|MA!*nMqJuw~u)I<_u` z{rA`z&ekDq*G03~wBLuVJsHZj3o=W9qW3vpM~nB^bn4I_t8gcrc-1#3lJA@l1Tu-M_(dG3?Tij?7!Q=(&z8FnMrrlX&F+Nk`XNTqpx6F2ui^f%}NG z;4b+n9I~vC`pJdeE<<`=fji|9y@O>)uWNLB4Y%jBKHV<#1?(=}PL9eDpD)5L4W;X2xQLJ5 znKFd_0PfQ8beEl>7^}&$nto>1rRQ%8a%jy~Kv(kmUw@vf);HC9U2py-LjLZ+V52c& z_b%+PA883~@8CNXX^=?qa9kwnV9zCtr-5fVV?~gAszkl#S;iREu^u$x)R=mZ@SEtq zl<}Vl8l6G(@{IoA6}kI^A3>u`y}=9V5B7*6Wb_9&phhW1Z>Z$Z(V6ioT;BQN`E3;u zh8|#PsP<_$bfl?_lpL-Mb-;b;sB#KXXhKP*rhy++R?yUC9oy zw>9sN-1)2XPyF-^=Tzmz3riOix|z1VaO|Gwukrt*|9t!tGp@6#&3Aw6*YPEoC`@VV zFZjRVOPz0fkm5k0XEz=>Q^bzE%~InBQ=4aNQk!QEdD=DKb2HzrTM#PXJ;*E2$E*)I zz0_;0VZd*erEc6%Rvd%U}(dhfvDH{5<=7kz%>O&zLkuMYd#oGVwxVln?a z=Q6Q4Td^|I7m4*P3$GZ64J->kH*;^~xtaSrpPPBG4*m7+=VqR&s|{Vo!+u#v<1uk~ zwJP$tE+p=y;j-2#^yZzXS!Q2#U8pib+66`_)qIckQL2zsq(Vx>p9+#<{0x0}GAO$r z36~stac0u{;>?@=h5n;6Z}?*cr9a*fUNUx~VE&Km!<9o6y7~ikZRL@=@RFe=Lwh!B zlOKXDnpg1S%YeJC!1?1<&^!c9%vk~1;-M1X`UADV)FNG3S7l`WnuRHeBTk1l&8t3K8 zS^MAwN*j#;;V(vmBYJ6@AUn#`@DY@0p_6Wey#)L`-=4;(XT!dfFBMCb9CmoCLau6( z`*t5a<97PS$-m5@{E+rINe|Ds{2eG?4+j<;o3~}v?!=JhEp2+Fl63juHRGaG?-<$; z@rE4xQ5yKTlqS*xXt^m8g#lc_0;+=l4RM2atnbs;K3*c`a4Czt*JXb8@zSql$;j?eYp-?;P^QI z)p@^-n0|1Afw?06O^516-#MQuQJ4mCGycnQ6uN-C4=hJ7b{zGO$z14Iy$)D%qx#!U z1iEqQcj|AdBZybg=cK;sdR&B|i^k04R^=OqeHfQClCK2Cmi~6z_}alo@svjLb=df76uxqRCEuuxZ#(#MrSpw8 zzBS;J>AXnc`@D^BH~5~Efzxqh{fv#T349UADV=FtEW`KTZF~)QL6<@%jg0R@HonKe zR|^pFEygAJp0@FILZPM~g3HYz8{Z2``k{y!d@tMhZUA4da{qTWzLyj}3`Y&VU)uP_ zz-P{t2pk2l5&;F&s9){}E?4>6WW(*V#TQm?DBo4SC+Fb1*M@rrxK%m_-Js@X91m)F zeiiYh@KJvFaFM_CUOi^xdjpCl$fY41nSD0CH^C>%-wNm@-}itcURjT?!E})yc4;V% zWPX|hC;cM5eEww)oDoUjB%cQ!UWmWm95~5A{>tZ%=D^7?5l%jLULbA&IO3M?Hl@o= zM5G(i(Uk-ae<>;dDsUGvSNRffcfz4GG9GkC5*ntxl(G9U#a0i=4Y(*CR4%BjD9+id z$lU)>97;aGEJl_8Hs&fR4^1QHF8zi;rn(T&+@lpQ<{~={ylnj?-fhFX`CQ>j18-%c zxksx+%th81c=ZjV^z+#87%wV@<|eIt_PNO-o4$yLZ;ipB)|BMm0vn!MNYglxvsV8~ zIG@QvId2*#W=5^}QjRzK2Piy>abo4viZADQQ${VFX`F144Zn!vYYhmsWTtVVB{I24 zelf@2XFx9IeF7?j)FwH2OJgXJK8tPc7jyTM283EB(>T#vwfaXbjcJ_h5}Te{4%0Z< za+`iR_s>i}On55B$-Fkam*dU+@hWJ_?zuJcP+3-G_euYiH zg7a-MP%DfldT^q*jwxMk{P?fIZY}ZDn>URUJqD}3me*5+pf{h^@m1qwm$7CkKwYK5 zZgqc|)bhI%EoHYZ@#C(+ZpEuDDTRNvO}|=qEpATCR$JY#Vf{Kngm;Y%zt)Cd%XV7u zLci8|D4Kj8Q$it&=Z8P zW%xg$+tJ;Cy_DSnJEbk*OW9lJ{y^6kaeXA zr$&?b3wXH_ebh4456g7Bi2o(*a@|gSp)$PxUAkR_-^)fV?yH#WzX^Rc`x9MHC9e!U zvuAXB6SuEmCtxQ-!7N42|10bie{xUZ6AL49VTey9C=)KZrWSI{DsY%Fp`hEa3tOMm znl)K4Yo35R!90>VbHF7zX4AM_ok!yWWd@DgXV0BUv27ZLi>yiqOnBQkk}oH=`6c6mv3^)h`gc+mjCnPKE=sFe7_n}>O3bni6w*hlP4Xo|qUDdOpdRm+bxG9a`2W<~|%l zqCTNJy>5iB#hvWcxGw{q+Bgp?N%D{G?fSh(zu!pr5yr;p4hz+@o=>2!jk{x%u?Oki z!gzh_2r%|A*~4P(*MVm0bA*Sx*GP_VPthImD#DBJ*vi<;urG^?a4zfBUI(!cFl=4D{khCFTn1`>mg@2Y^;jFJ%4n2vttle$l{h)P}p+#zRZO zOWIrB>U2~_I;ODJ6EDHaTg&=>zJkT@+_S!8%DX7Praav5y@an=6=S`mrRt0MH%t__ zEsAKHI!)@R3i8P%!JiFf7fK9-;_5pw7in<0~ZC$`VV144zsJH6aTIQ_v zVuu8qa+F`Zq`a;C7HzfTc;~J+o=$Cc;OYKdNAToaz2Nw6U7~a0C6Zd)HJ-ht4 z7lcpjs>7Z3`f5JMq{GK1ojymK<}FV_sv9j_LAD99mK<`nd&g*9);oqZTrLYPbsuxJ z9-rA%RbDiHa0#~9es^ZmdbmLS=03z~TaP)%N>_(|vLYN9t4!TJc3tY(vArqBu9tDj zU*%1A?_%{86I%6kH$AIA?Y+ryi;%s1Q{a}$v}5ezRV6>U`?kAo*OBRGZ`+%8-2QSp zaC_h+*3s|M?s)e0;>o*jx$9N~aSIT)0&%O3xb0c~^zvPS+bXln>pskQ&92cC%*t@; z(8~4~XG*H7BQMU(cx$%wMQ%(y68XlBKaYH4xH@_gtE=Bgdbd6jtsnV$^kAa8Z&_Q{ zP+#ARGZj^j;Q!L9pX0x`syg=KOifiE{&!YA5<58h^VmZ>eEm-(V*QzsNBb$=Ci#En z^Tspr1=xjweGqTo*b`Skemg%dTEH5FdI3h#ZIe5C!yC5OEs#&=;bFVD9+x8Fni7RpKv zRYvB8uNx|xN+p+u-sL-(^Z9P;*wE24&X{BMd&f%-S42d6g|LL&hl<1J5L)7%AHJTW zoU65o!nOy7d{a}-;MAnkJ@G)qjo4k+M<^Fi<=}tsI8u889DL7pe=)s+ZvVVCPxuQr z7W#uzX0@}xdmN>r+A;d1Gz)Zy^lqbahoK`ZvFy#)Fpxx|kdtlf%eP_3C z>MHE&j&uj7KITjvdZ7Qs;p?_s*M9xhCG(f$1*b29e3SFV{s)rIsXM{{3b6Ob9vFP! zM&Hx~!uqGq2l}qo{bRn>@h1{n+kDfL8SHM#JQ3|ij0%9tb9P5sDZLQymu4!~Z*KEV z`GXYV=V0rY_6Nmo`-R?e=)G0`aJfG?y*oxOpPTWne`%&>y>IFxVDiFVBka?geefw3 zoObzw)B9p1-vB>m(qeDS#w%&hJ5pl92Aek0{ap3*)cSsqb7 zDL*J*C_nMsv=mqUnXArq;=YmkIxrjcvg%mlI9?w9$yolRbB*H|mClWai^Gd|EeLx< zm1EcQ+9kL&FLe4Cl^wAINUJ-^ZRD1uPPqLUe_~$hPZ9rBwGU4mIqhe(H)ZWFW`ZSC z#a zRQ5FAs}o}@FAp_@KKx$6nM;oQx&A9N^Xh^JzA{r-_s4<47b!H_<*ugu$zpn&`zv>R zG5=RT{`c1jRsOVx_VL8D5C7xqZ0*8{+K}db@a)vo_(5$F`(0A(;NdrB?or=w{MMl3 z_xFz@oE!H$zVL<6-cVi*yL9tA=XO4K+OK{8pyQz*&anOE2i&2?5S#Re+CtqtOsfw% z4!TZzw7r4vAADxwQtTu9%w^7FS6x;V`uR^@d;PZMe|5S!|Fwhf9AqoNb=$3%JRHdT zhpX1EJn@&O{dxa-uzJ#$|I3$NIza42N3L3P-$WID*O1$%e*nU9u=u_E&g>05GqECc zZ%AvF|TG>xMrU-8&qJpBP>|LVnRT&sHa+bdf- zH{UfU^gJ~ih>P5eFNvNi(3lUupGlLQUHXTCj(7g^X7|LW18XMo{cL4ysq2_vY&x0W z#DA^w8P@6c7l^#5bssBe{oE~||Lpfa%f8^?oHD;?kEM7AKj32++qXT;T{FhlF|42P zumdnrWCQTMJ%(##_mYs=b|~q=qPj3$QoS48XzaSo{Edm_0ZvtrqU6GZtpM%2Jq zw~dK3hD?5Q#7?cBG^>7nWDbbf)--7O*voG`?ENpbN2#Azj^ZDNh1}T3y)&5Xq45>X z?h}SC8uzy0qVbp*1JUB< zD>hs^aJkCMAKCnMW3kf<28xHeM@gSB7HiD1RgTl95;d|4@S5zS8r6r|IXW9d(mX}WO)#`jz3ZI4u0czAk`@u)? zkVf(?vf+*Z=a(SdC9V`W)!#ArE6aV2jw3tm?Nj|F(4HK8YixYu;A;Vn(q$zs@|XC! zZG3wmq`Fud8NLo1-}6d3*8(j027x19IrsM*EEHa8JhDzKhJIafDEUaI8dd(g zn!lv<6~@Ipcre>PF~50(R2!vB2xxwj@TSSSirb}{0dxNZa z569E{D2!E0dxfl$LXLk-!l73U{jSl9pU?5smI^~Hm}%&DjaGay$8R(s)Iynt_6Aw; zr5ta*57YvghV}+o@#P%vHz3r)n1=QSS@DZFzSe-)_Xb^L!(YVl<3=H)mc%qp)O=R{ z3XV6+gP9ZL%88k1E1p*TO+$NytokLK?@0qPd+(4HPc^z}Xz!3!Pc^h@Xz!0zU&Z~q z&wx}JPxRo#UIHuL$MNR-;IrXtZ1@_E7i)S1t+C-(+VCqm{y_spHK}Q6Z;v%RwH$Be zulYo-Xs?cZmnchVua30@uQJIwezncMhVMNhxBa+ieS+$Ds;207+O&7#qqviv(xeRU z|JAyk`nY9yzlU`DQf~LKv~GW#+Y8z4y8YYSKA(L7cWEf>Uy~Nx$^Mkh{w(a||0Y~z zcpv}XrhnaL{|}qp1IOf^-dWlkQ$ZHpkbkRneJ7sF@IKOB8)--%w%I?S;|1R$Hm2LD z4_Ahs*%xj2$8>!JTxEE_)V?0^AJ+9EeJj}s-7eB=347hf_qMM89_PD+EkI@wB*5*< z*%IAObzm9ZhgGmkL;ihO*V8lYrSa=_KeyMgt8Mr`UB8FxSF&4e`Y-GHHC&JKsV_#! z^(^Z+R19;CEidf?92P&s zMjG8CF$EI5kPSIT&}Pq&*j47d$m|6~1B>|)%Wu+!BIh)TP#KdWVp|U8EBImTlJM91 z;Hu#>4%QO{G$mp@$%&BOUVdIo@6O@=#LXl4#Fs$im=BR(f#}8YlJ>78S{$LM@_pTo zR>mTDb_7MAlkU`m@wAA#i0sri@U-iDP=FsGdx!X4lcy7V{$Y2ZQlxr|_*|s#*7wr% zFy+rj2(tiSSyv%f`J%Dtt*Y7lLB>N5e{Yl)(zguu$ z208b4s~Bt0o)+4>?%6KtJx`YyGkC5MeN@l&j6uXaXxQ<`d8j@kemLRx8|mJMv8k?a zAbXUtKi2QmbD%vy)%v|ozf<)<{_=E0Vo`fQ@xGbvi1&TCQ+jb6(y@%>JH(j6gT`cy zj^qA)lCcok(KsOqnFo7&kW?Jc!|^eE+ZbnJT0$`t zI@8d3IjWK4NEt`!cQSfWd8Z*qDf6VPFR}R+ug|^1<%+tE7revewIUui<1PL@_ECnN z4P&<+7^|KC51zIy?`WCw$OBP2*REswTCBN05Or7Qg|*2%zGH!}#DT(vRp$q>>Wr&N z3xDff2h{~IT6oX6#FVy`V{Lyt=$pD2tMb@+FtyNG9+}@(;1etPuBuX;pLa)~2i@=(_RK&A8av;2 znV%I}I4PW7@X`*6e+!6x0v*$z!;@Am7$`h72u~i;&9PdeHS!5fztc0NLp^r8EFE*M z`NT18P2H9S#|vtmCs?g}Li4i80`ID!HMD!-B#W(%V0H8Gs-erm)l=_wVZFR8FnwoN zV9M=SgSHsGXu(=UaE!i zu&z59*EYg-^^t?iSL{Fg_S=7Xs=54V<&u2o>G90J9;^&%mutQ!{MwbT91NViX9HqQ zJ0F~v9jJMFep_gI{O0nAHc8Uw`F@AG5cb7*aq;+2oUdX>CYgVMpH^y7qZGK2AGn&_ zhrH7)czvmM<&iT-)>9bS)N)qQ#A==YaIW_8iF1gv<~?$d) z-g2DQ*t4esWsjb6I2TS}w?!kX3ZC?rxP!E3=)k+IZcpHG#C6~4=bg3H;M9M`VYP94<{c0XKYwg9+CEC0h=?>#D10S`F^{W7_KSBqQUb^KNp;1#d|> za^S@ohP@znmeSoZeMed2$u7rHJQq&V?k=IJP&9a^9lhz7qdYt)Z!cIA;f9AXKO7i(c>r%gY-j_{*wOd?IEHxb5^?*d4lQV( z9R2y|&qlvK`lq9RGJ53Tvu6rwe3gH7###1&|GQ@j0%c3Scg9)uIe%BF<5a9XZ>rdF zzu$Q(QZjXzb``7&f8w~nZnF7j`B`(PS0f6Q~|397HY0GvT0KV+T!5-k*iVr@-oYJCukds!|vLP z_+H4oMGF>`l$4j_*L`heW7?{YsU}C>F;?}J$h=8(k|#Id1RfWE`X!zo!6~AYKg31; z(vG_A-=a_zRWEN5dnbHj%i0{P^NwGF9Ur^bmrt|h3nw+$7wdL^anWS#>5IdQTCczH z_{{E7Cr-(_2bVTIt`!FJk2!tiDU^(0_c-mo^9_|pVnf}L$=xz_@J=v#E(kl(F3^+4 zcj?J6QN2dHM7Hz#jP&lX8~Ir_Mmf4SkasLUTrnivAuhD1aY9W;?HpszvtRw^^1Ci6 zyz%habNk2d%xkMZcP=}Ak@F;a>Q|2+(k?xS9aQ73+P!~?_F?=un>vbq^mvvvJVpKK zFgtmOMhw3~VGy~q{I2b#?Sc2seQo>)dD@rHo%_W2jgI!m7;7BAR{PTz&?_9DWZ(G# ze(gPeAN#>G48L{jVuzmA!=XK2czfO1b5F3PdCu$4oy*|2yRTwo(#?LXedn792V1PY z_B`z}ev;k)S2PkCW(UA=DGRa?^j}iLp^X%O?e6!^-NC-=+_jvsZR|B|`T)YgKBE2A z_le^O`vEvsvr+a-_`eeKPoI07v3t%>IZ^zCoz9?=Sh;PwxDL!PL!43~PScmTnfg600p>IU+S>$tw#RQ4nkr6f!a*yZ( z2ny*eeS7?7@r7ke7;)HtA{EczBjVk|2^^2h1EjjO1H{KkgY@ZNBSPH&5Dxb~A6O;j z4tRj*;{_x14Zrh-N_eL-DCs^c$XlXg=TkR!2E_sJRzD$@9}BRAr86GgAwJWVOt&Nk zhv+j=X3Q03d-79Urv@_+%^Gf0c^AH(OW(<&X(EG+gh~#|;v%uL6G3V$r6@>W{+pF1 z0UXKHjYE!O>H$w;c!C0C+a(2w_@ulDjX08c9bN*FZvDDokiJ2M^Mg?G=;O{f92qGp zPXA5GPu?2>`eX!si9|p2{5KwK|Cidu;}=yr|1Zaj=tJ`nu2j8%*3k{imAD8)7unJE zv5elcuovNyM)CzApb@h)FDZO9;~@EBc&5>)oP`+2b1uGK$W^{q6+Q}=8$SJ zc@uV(Z#OI?lScBr0fEZrsur^o#8-@qaFjmS3u@uZVpao_l7@km8z*oo-$L+_d*Um_ zCHZP?d^Aha$r;2y8NM1D-%^E-)>tK9yNz$DQ_T2CN*TV}ZMYuba^>4Do4+;imu77! z9yEh0{r#$q?{V-^nUO}ugLd7h>Cyl`DhI?@flKmD*!UWtSSZPK99jRDjc-^9AFbs| zzE^B~Epzbwy^ZfSg^$Xia50n~VZvvcsx z2To1D#}q!V!graC?>_LgLobaC-wGSwGvJfu6pu#uLN>k=Ab`j)@_E39dlk4f21@Xe zl~(1{csy5a`nv*p3Lk~z4jZ2v6LCe5OC#e!yJ=Lu7Zkor0hWBUBSuZ~9&oFi;Wm&d@jFNeQQ;M923fKR@^bqe2d8(&j_b;et!%Mu&k z4dC;Fhtj29;k#Vt!;PCU@KHWWBcDSy+^#ury*dub!_95Ll}HjuWcX4x+WL=W910vv+q{ z@rw*3Jviaos=tWyndwEjZyMUoWyM!;{FnhTQ-Vaao6Cx?*+bkoquPgZ`f4evFPI6S>4xh_xBkP^UWra z6D^t*U(fNi2A*0x(>Sq4yjZtV9jV#YjGgRq6O1P()^@FL(1(q_1GQ}$U;8zkIMMQ0 z@gG473PWw2rt6m&PDFZ{`D;%P>Is;}iEn899;_7hB3!ilt^;>!cBo9z?!1rVZtC4^ zhi<2_2%S82yTx9}{y?{rPi0{J6WvZ>DnotwjBbCE+l$!`b^A5kUdm5iA^$qLy_`9C zx`;7S8Fr`A=@6tB{$Iqd((RO|wEOK^-A-eXGSoK-i+w3Sxr*FV%~Xc^LY~wr>|Q2+ zb(-~zKWIWc1o8r zyie6ctQ)EqFSpsluv4FbF3O)9boW%Vl%aGC>2{HR>-bl8pyG!3eqYz`!*dzl4|NAR z=^uq&8nVlNb_1Tv@P7P-uBSMZQu)ThIbT$_Ovd8tD9XH)G3}JHO*dgiOPLa+S+_xa z#9n+)RZgIqGqsS|rduJg&dx%Rb6!@GS!ZLV)R==M=Q(CxbBLAsR>|@{Gp!P4onOsG zO_R8gD=9z3B7oALe47~)Ekl<~&lVK&$l&m_|Ee(4$cWK5glS(z*qv1m^= zC2po5S!YazE!ZB`=aWa`BN-8H%k*iEc~X?=I$VzJqW*IXn0Kllq|BoUQ~gJJs)xwGx#XPhQ#vp1RPU2JKklA8Futezt&H7G_uE7` zNWPEkcZyT39pn1$L~Nb=Hss`<^WG!oG{~M$_}>@d@O)a2CmIh#mG8Er_gYZW_vs{-D&lFm1<%-hSD$;|&c=-!#ep>!u>0;|F`O{=?OchG zG)`dXSl9lctzP}BFKfda@bwN_qr_VBr}m%y<=Y+8??t|TmT85K;K`Dh!?6;pt>YCR zZ(PyFe1vm__Psrx={VWx#;PfHJ$yd&t-j{dOoRKhKomM0+$~nw=T%^Wp!Jkfs}5by zeOVY@99bBy&aa4!haNdw;2Uz+c*;(p=$&+P{mx1?=KWd$^9QVB4kRnSn9?yd-gT6JTggGEozRY;pRq}DmuKjp z_d3JkTbtn3^^Wj~AvUEkz7GI+oUT?~8NDvLHwp>tu5jg!y8>T3#hjZawEBlCDndf; z47;E9VilXdekt8DM}D~K>CWmsvFip(s-2Vjs<-!FH{cftaFLtsJJ@8!@R2jcUcr+W zc4*~I*fT-F=`3)w_7}hG_#)1cDB>wJ9untpTpIq1(^~P~gyXnY zzp%+M`4^`h#aA6$w&SV5?uo~ifN9t63D@a!4gbSE@4dWt*`=$rCE=gW4DElov*gP1 zrc#9Hm6-~!_Qg_t=g0nlwzuHKD>FCLEk5ZiE}GDMw1a^8w2zQK1*aS?*YW%hIgYW_ zKRNE6yz+nug`bCsd7U@`L#%o``MDDm?r~gohuDg*2HX?(2ecQ*D`#HE-U5d7)hf1& z6h|EW+H^!?nj_pe<i2ToVn zKcEWy>>G688Pl0&chkS;dS>)A*oXQ8^2f+Q^K4OMp zdt5#{!>{06p8Vp46PlOKfFkZf>sB|oJ&Lb_(IXXvse#U z;XIpP$`&UY<^C&r7u@(>k~>^?Xvq-X#wNDnpU$%8Rd~mKc9!`{LW@Jj{tjSg4qarF zEXuzEy>w~owBvso&`$hp3CciK-sySHytXBdAa+ue57y$#Sa>u2!1J_B9a@C4na}fw zICwc&s~yL_q!U$@9uj*}Dh_a$HQ2GkxkL$bhWA8^goe(SLAq=_ zbn%uoLp9SWSJQNfYfZ%S^vQve&{tRcb_9Sz1048+o}SZnU; zK!2&Z3tdzCs-M0tZ3^+@2AixkgB9=5#OR=1p?;;v@Tz$@n##ocY2Dk7@9EgqL-Mrv zJgqf2iZVyI46U-3F2fuQDx~K6`z&=1+H2F%)RvvY*+go1R%mrv^Aqg0WYP7(Xex_O zOWETZ#HWVSJ!7-?Ajn{K$A;oqQIB_x$u72?pBTCf25V{|8FHmC#3ESs;Is#Nwq@e& z(M(pZ_RmfzVC2_*<%fffT!pSPx-(ez3SeH=S=_utp57S~HEY zY~tpee&zV3jIxhI@^8!ZB&|qw7l=g39JsJtI!{i@yvUiP!GS>@&Dl!%l}-NbrWF4P zP#0~mz}dmrc0=EUQiQGaX=Re_%-BG>fCD~IUv_$p8cf~LxP%P#*J*7-n(b9$>~jSK zgrSSZ98I`rPJzY=Waw9vG-o7@Hf;p+j8#z4|Y+@~Rc%J8>; z4%|aFTo$+rNrt=R`yV#keZbLJOd5%M5dziUeXw{X2zQA)ZNnXzgKs|M_%q`15-eWW zrICDVY`AIIY3@lHiKBfFYQ8;QCB|HoZ!}^c9OYY!jc-2&e&+nF7zYBzC|&Vqgpbx` zbLGdqHrz|V9@JcDg6ppjqe+XFXbo2 zm*$gYd~dSx-9HE4h>dSb;k!iP`)@Wr+J}-We4n-P%_w}!6~4!8d`G~SE1f57xEJQY zy==ps04`Vg!`5a?{=NxZu5$G@aB4bZ35k~%N@vPHna=k0_!=mv?v#dbWbEtlB?{k4 z=p|n>!lRZy`odQeXAu7+Un6j8_%H@%UO*^(wYVf-!p8R?6n^NXk$iC*pI_ly1+e7% zZ#KS{prAP&X(ZogZF~{%QMf34ls=M=%8?phSDu(-vhzJ=#l$N9iZ? zfWnt+f5eA?Ll9Fk+$+!!U&#K58-TkCZlxi=$k5%vpTxhHuw*@n0{Kx`cj6)^ls{BP zW!mA9J%vgo*M1AqsYd!kvfsx32(@k@MrsR>5IHwW1YxKB5LSFX$D8#D5=Aj|nzt2S z!0~4NSfHSZ-)+OYIo{-;5@H(ql9s6>`8*q5tqF+VW5auF;TIF6(g!*%$I4&G@sxkU z%-(Nd#TRkB+3&MzX}^V4GT+8OUwXvv^kpt9egVgu>AAp$FSg-}IsPdFWt}Uf{TWt% z`~D1C0aXp1FQT?jYEOyMyWEB^x5dxCpJSm7zmVh2TsKP^g@R7^v4&?6$2S;3q@Ipx z=*wSL{KYo@i%l?|Xg`P*Utzl~xH%L#G2-`Im6K znJU!NF%5lL%!*KmBDfvPc{=)uWW+VCqm-bAgm;cIR9T8{S{s9NKR9_X|o zYxq}j{3ZiMJqXj#m%ps|H5|XjfS6AtqWvUR{5p=07mNt8eWZ@$SSqx~mV{>%A(4-=2| zd&SWH6xGoFlNLol<>=$Ms7-wh7yYV!5O--vf19-6PWCV2B0SaUw7=wQy4}m|1?-!; zov?J;)3X-4`K2>@$7#RGzvy~;hv`da|DoHx++M^M!87tt=;s@!FA4nu=GXPlaC|Yl zhQPX^FwlMxX~=%7j;ETMPIvl(ZWrM#V^8RI;a@qE<4r0zWeA1*GVVrhU&P+FxJUhp z&JRSqoYDT3ODy)q#%YQ*+`ojh>wr`oo*N5uVHWL_BHUM4E4bRbjrxTCT_3A&(HCo8w$_w>3Tn&%kX|* zYtz$d66C&)>({W`b^9>4uVXacH2Hxt7JTLTPs*GdpNLcJG{vS)zbP|svkv_+W={Fk zJKsYP+_J4VIGl{_(5DiuLOP3@CbtcTVlGy(Vv5zUnRD`nNX*6?R&^fU5E|3yd~({d1~u~x~dUbr*9+aY3*&?Io2P|M#UB!GkL)wCe^KO)qGYb(XA+b z`dk$n6X%AobN0bfhAzh>xuKJ3W=xIiTWos9u8pQgXyw6DA|%{MO1UFv4!AyHZg_`S z>eJ+gNKTI9y`{RugS{lQchNJ(*vIIO!CXYYQyW3{$MyS5xI0peouE4=ZeOMQjTi^g z9SsbPGCcQC{ek;k_-zW^Zx^S^lKqd#ey`4lJN2hXPIbz%yG7gR`NP?F(i49J-QgeA zu@nyKl~6c1&mKKKUlMH!@os{ic%?r)zI#P`=K+rDO2c35o#ElXMR$+LQ!kZpzwhi=l%Nrk5hMPcLkis zn6Gih^?UEWj&=Cz&jpH(b}=czymzSC4c^*Vh$LZCbxB@st; z#9KN-u5r6U75qy;w2my+x7Tp{;Wsw&_4JL0Q->T)_XkRkxmRHC#gyjy?iqGb)5)N- z)t&WgzxT?)#*?n9w~n(J?aEWHyXowe58~>wSg&jOc<;8J*7ojRtS8`NsGcZoyQX2C^Zr@B-ciTgAJDqkA* zT)3~>aQDKlj{GFw^ETW!V6Vm{jl@ksp!)j)?5iXQcZquw&*}_S1eQ9;cs+?b)ti*Q zZjh;b??6U4X(ZnY9Vc~kB4VyN&vlR^&r;I;mtnt?zL`E?*2Wr*Jw@H9# z&eN(dP+U{Gixa&~A?2`XXin4WUM(TyUYzi4y6~8fcygk*Vs%fgxoK$5Q8hHDNO?nP zOm`Xs%lDPuy)vXnK-bf|Lu20U7JC6NW8|LR85;Bcfv&IS_IWrRM)1=+Kx5wT;4TgM zd0bj>C;Lxr_J6b4&)Mv>RxAyk>TvNHOS7ZF2U+I%uCv{6qp zuq!NWgk5QE9Zaok6O0~djv*Hx+Zh1cfNd6mby38&_2;TBzSt6Yj&ATs7epV>8t+4?c41&u%Gm(YGb5Zt(>74&MIsvNrFn4(#PD zsJ?D6daJ8?HQ${#d27{e^gM4;TkAQ#sBQArMUgxpNGkR)FPL_oD; z+Fnc&?!`f;?i#&LVCY;$Is=XPAekV%&EDj~*;o(OvDME^IK$Wh%?L+l^O1YPGMih) z{sI3IvN?LTom*onoRGXyH%5cnz}BR+B~`675$`TVe`eO<{nX2a2G)>Icu zBXJKwpz_fJHy^!M)rhax_zjUP{X#%}Su0+Ay@t|4 z7}@p-8})6i_<0P;qO3`&Zw`fr&IebG_}Wd8AtKkNq4jzzUVQDw4A1QKdMm!j79P_l z@`d`&R=oH+j)|Jxx3-3GfzkV>l-DdLdl3KZujkPCiHyKoSHGN=H=Nv;V#QRHEvoCN zFJDiNbwlNHv$Wt&_G@kSLD;DbQr$*=oTE z@P+J*MPI}U;n;MK^rMcXTnaH;CbdyA+q$`zHtb6sn>$-OdOH)N)XdRtXp`f-Yau2~ zwwR_wZK_q0-cFiuSDN}9PAx6CLTPEcXUQcIl{e2yeg5@Q@r6cDt^ONC+@FNr;njb` zc!~HT!!pPhkh@ik`E`9K-JwrM`x8l}_x^r;_x1I4dguN9PyAm)o+|UOJ@_7uhTf>= zW2cWqKJRzx&*SLN(@dA~Z7SEsFB7|uKX)ftypTlMfn zZFOb5?VYOvdm|<2@g7ObZ>I`b=U5!^iNrE`BDedpE8oz>zjZy(+F^Y7{U z-Tov0(tY(Um*VBEbNlJ*!{Z|{=h|PKYh2jgG3DA88~W!#&G+2QcwKR5oR2mdLw~{Y z_1{v}aY^BGrqdo(4NiihQEIuanX$y4$gQn7f)6Vzly7%u?>H|J~7Ahji&q+ z1@nsGHXq|9wth)|$sz5>6e?%<@Eaxm>xG_vGs^iNGVlfA>xU4tm~-`sgL%gaRy&V5 zmv0YjZ^Rqmm1C{>;a7&sr@Z)GCG)zxKgn;JaMT?+SXm(MAJ^}Dan~S!MZZ(L-2VKq z^VB%QTN0x;2Pf30=Q(i7JiR#+`=GBoRMhSgh<{0ehb%l^4_Yi&J^MPTvg*q z=LT|%Q^@Nb5&Hcfx%(x5+b#|*3*iGz53CCL=*!@Iq>b-^f60MolJOM4cffH+%JSbo zBG<`peXKb>ZrX9iKb4WxX3{Coe2mJvEbgWhJKT8{cg8c$j4$<42wdSMJC3+fasr*f zhYr$68o#KF&~E`t!X>SHcigbUF;(Dv?o897zrNwwGe6X{v(63Ao@owT&m4Gq?#$iQ zuBqj&yt9s`Qtu5xVjRNB*V9vcybT`8Q*my1e)yq;bE?kaUFDcKdgi(6?xnhK6Xai6 z7{9oks?)rel^j}dylnc&@@LOH=X>^yqv=~`r>83>`dPo*xu$l)RpXfi&-7%*kM*K& zy*+-XcHDtqHflBGcO+P%p9?L%u3izoVaPR=>VN7qyVG^db^7+ka3I_Ww6Cn~kA@z3 z+uzlE=Cg}>49uS$ z!SU63$Ikiw^G^*cB<9r=CI`fO^ptK8JjCo@SXN2P=T2azc7a zU#c70wuZsYf*T@j;k`S)y5nKWH%CFJ)LS~^7^hg!`R0KT|8*<>?fGAx`JqFr7c(@^ zAxGu2E3`Y*F?GHFiq`5-kjLmVf$L8^cDA6o;H-Pwx<_C91@n1BmvN1DDSlzTRIC1+ z|L#EEk4i3c9J`YhhTeX?*te<;F^w*9l;Rih8zQy%y}NMnQT$$(Ler1AA@OTec52+| zJav!ru~YZBUOVXY(Yfo(S1)awe`3eeUr1C<&y+S!kFWni6wgy*H#JVP(l10yCYSrj zep_SX$??ej(fbqLX}p>zoxum94<4?Vr1auxN)IS^ zpWlX)*O89nU)qEI6V2Ob)fLgb{5`}e<9@0qfULrGUgLDR-0lzVlA-8NU5jPFc=xVR zd9bvQiuJo$;^1%^6TY*=9qC!3?aA3PI_{c#WUTneUfcP=%bw^e>GXoL`a za5fmv@;Kx`+>~>s$~-y5{H3Dc%ncXk)!4CJ@xeqU8&9{UZ^Ef4!+p`%4kZMku3&Fx zS8H!;*VQdJ19~`~R+L?h!QQU!Epscoo3GBTY}_2otuW@ib9%@>9hXx>;moPn($Umx z4WTlrhne>=`IAsZ+%<*|za@rgakf1^I+z{O*MCLgV)NDr9hIIwoOe`JPIWU0q z!vWcHp?D6U_=PNo*-8%QB(jXaSQ5DjLmb4fIi1E4;ye>9;c1GGB>VZKf5&LoSO&lC zjSV#;bh~m)70!v3LlAY=u_=aQZ*q~4JePx>v6kd;KMq35;mFYCa)_@7h7zN3l)oG< zO{L+~mU=kk2&d@Bd&X#XGmZUAvyx9obiFU4XRLeINMCXoKZTu>1^y(mIRV(a#J>V) zf5(vJjf1gZ%sAFuDQtKZg2Bd~p>#Ymgw)GbI*=~0u1qF@Fa0I(**`Up01tKr>3zQ@ zik%EJ?b{scYU;YCH-YzgxR2gtai)4YJ{X8*;u(=Px=_bP@w4dUXlN%@p1KBQDn1e% zXo|<`LQp5uaQK`42zUuvDVh_&$b*{({Vs2E{*4+m!pV6yJC1Z@F2&`>^?tZDz}Wqz zc^7GQ0^_3@t}@QE?mmSN8@q|uQbx%dmvE#-41&$+?Q>*2<#qQ z(n!8{bZ9<-%o9P zboPF(^rN%m)%Z>;d|rib#>RJI4nF!#yvp}0g|AxSy9n+9HOljAbMTcxuJXConfY6z z@YUJ)reG(%G?dO{s9dUiMc|Y5%Sz~Feze;77NSDWm43}OzNJd|=sl5q5gVTue7VB+ zDI2Z{xJ?vr-N<iPaQlFx_e~m!`-KfhzuiVu39ae69cu@0W zlae1F)p3-+tv0@gVQ&`{{J-RDw(&J7<%P;M;fQYs9@Kce0ecN+68{KCW)Kf*_we{!BL+zD}J_)(?b}VN!8%8}3Qq zyadpVI6jzzXcx1o26yIr)i2=LhBb{ng z`EO${fSTqMI;va$H+OFWALVtQ3!ispBn=~hMhhSWh7l6B4A>TnvAi@HEew(dj1V}% zOUh`&BO}m?Bim`B#BNJm=PShSt-K_W9p98VZZ0^X7ra#R*1Ac03${rGWKkS{v4ee6 zVZff6^zuE=dEfIcMm-N^B%Yo5(|K~jCIqQ4gvmg4wpztmPx8gcjFFr%APa&S} ze4dxNn`!4-18;bOxb4skzlrBxM{%uz7e7s? z{uui#KFyYE4ZQe}+zZO^u#M^S^q?6291Wi%_lgqFnEE_lF5+is_!;sH+N;n|XR6z@{-hG)KpXG`5tei6~| z5e*-4z~gxybn&y=#YEez5G{d_{n?Sz4%pH zcvflQxk}@|O2fOqj0{huhOgAZL@>2Bwl<};@8@csQttTKXyrY@zoOV)Q{B~zE;E6 zN_?Y@a$;ig$25FQ;+qJv0q#-4)6hr zO*I3uTlwWpAdZP2E$3GpQMS`gX!8Ho-YxR1g^x&isrb1ivnJx*At)3w{QMH+&Gc9)zV4B)6#G5+RpK8#@>Swz9(<)Z>yfV((-AQG7m@y7BNj2BmSPxI zS@vu3oR9kNdP^>o@+U;nk{hKQ#c~mouUpF1;wzS%kaDf~rX{l_mM>!BS;$J!zkjyu z*%!@65AzL6rd>W)#G4BTcdlGB%#8sLJtC|ZsEyCU?rS?^sLExO7cV2$ujT<*%F1aSz(cRR3 zdq*Fp%y?LVf}4}{xWuEi`wn5<(ZRw@yBHb#0G;{xH zX8dWS>!s`|0NN^_hHa{(jP|y_H7Je7zOyNi+4P`A5#tPXTde=Uo8zoV;c1or#wb z!Mw6u17L2wGjUT+wR>`EN|c)Gw#Zsr?YVK6i5Fx~v3q>5O}$`eR^5YkjJ@#5Q|xvr zR_Du@;hH?t?lJewuWL4HR^2pKbLpnUx6wU=ZkncTv1b-~#X6S-I$NHUZ?W{-Eq$-0@3Zu$EuHhJ^q0zqu|s_3gb#rZ zQZKN^yYSKDch83o3ESL0Bzh6`>E^yI-yD1nw{GdjIS=+qdV3u`cDkCE^q7B_RaC56 zwJH)>wQL1$^`ZLsb@XEh7nHpRb}?2pS6j;#KGcGHN_vmu?<2j%t>!x7)B&z&48*Sc9`%bF3X%o;jcW@M7md%Y4<+*t zVNLzOGy6wRXBEu3e$KiNZozpe!nkI|E#=8j;@a9qoP9F0Zb`zQ46g9YRp9yY!EjNZ zaovyK%8eH%bK^HA@2##J!HFoi2W48r!^ym4sNuotRWw<#Cvkrw#Wk-Vp@Ii8u#&o9 zqPy$EBMhN0?!#JAtn-Zqqxi)Nu(mXOz+8cz7tdR(R$Ut-xefPY7wv?Jcn z=g((}f`-?Sdb$4B68R1HbIo$k=%rbQ_n#g8!nDJKcoL-r?Sb)9tYxm581&!YJS`q- z;2Pi0*Hkcn;@Cx<$Z9Z33-I@TtVks<*Q{QLeF3@RJi1iDXjGVc1k5$o8Q4{D{8qa2 zOLu;_Lq5B3TstmTw??`CJ%Z=VhK)%-)_7+u@f|7HadX!DM`b#~p6*z7q6iK196O}X z47SLUGg2#pweN<5wUr0v)XiB}yq5NX2>%u}Y}{UY<_oQidCf$de`9+_>9#~cytIwB z`QYdV$1kx;cY*(x&8@(WZ)|P8A#sard_yF#-isk2Ugo|LWOQFg)`UU#WtFSRd$c04 z-YzY4lK(ZI-IO*2I4lo0M7B3?r}ZRPlMTDN)A1lV z-J06FyL$VlwwLK@QFA?G3j<*@@wmIoTaZ09)?#JkjD^DX`wn!S+Sl1z-ucz0qUnk6zQsK*ir*3}(7;|D=l~TAM zK<;#DbNS15uZqVd8Xw2dauk_`qsXyOx4)IZm8HRL(r~u`7fFL_1kN44PFMKY9#`Sp zuJL^ie7n-{b!dG3;G@4x8}?Te-@O`N02Z5IuM}}qf2Q$00KQ6?laJ*~@qJt4+YAea zUn#}MwT$lg{>T;IVt^IjKWTiOuqabx7LMY}8sF>SQ{^6A8k_GIzy%>A*`(SHKIXqt z^q1(v8)#CI&m9lN zr^cvNJh-MvanPZ9Zn5|(Ogiy>SfpEHvJE(Jbz3m82$kMdN`S8X&BL?ulh$0jbe9UO z3+Ijlamg9@gUb3+Xw~>Je2f>%ikmNqLY0mWFppBFlHe$=3Gw3dC7$n( zsq{4=1sc9UDFqzY?JM{x~_7e7zpBR0fISsHN-3H^5zN9-KM`xCtOo~{_&muU7Sj$=G= z4T;zNLJ_eLETe|!v`OMi?Gx@9M?;?eVL5>2$Ctp%SLRqs`$d|3u^c1h`#Ovt&;E1r z#;j+YchQtF>}V^7VK07stNF_l@0~xS$v@QOyWcnY$FCXvs`_Ppl|1?~njEseE1O`)IoAc2%r_?=<@riWHvO9?)v( z_DVLRCnY>~P3_HXw72HR)Nnp~bEP9{U^sI%>iSpz3>T zJ|fxNU*9q|e^*Zx>bYH!Bo{evX+3yI&&Guku zop}~m=z4430OowBeOEg=Uxg5w1VQR+E&bEhJj`bE{x#Ys=?=@Q_?@A@mDJ%cf+BpM z5F$z);f0l8ctIr?o<`~jH{VUld?!OU;79#Na~LuyqgH)i{S$WiR^~ll8r3|%>{`K7>h4V-m~)0=$!QvSw__GP8_cl{^i!EW z=?_jWJ$<-vA}4p=kvo!?#~-XNI<^aOj}^}-{`&r$$n;ZL5|`Y6S8@pEFBZ=&{$BMb zN4}QIs`yGOv!Zq)Cy)^qyF)kc$%A4a8z7e5TB3n>}zmVYC-)BjHd@Ct_a-JQXXqa%u7rk z_g(B84_qw9gBLTrEEg+qDg~e4c*~FTUIgPD8)m1M>CAGW6w*9(VE9zf?_Uy#T|2fw zrY2p^kLO}c|Gx`AQat0-;Oe>Y;KGcvTNmN9nu}}R_pMmcmib}egIV!NVAk3NiRi>4 z5oxEp!iGqxQJH8jNW7HVTd{R(9!~NROU@nkm2TbMx;26`I7-`L6Uk|qomkRltfCt+ zE-tQ+Q5&YIfg@{h@`HnQ%*F7rt)(w?u-q(U(j-4wncY)xC&_qB5MfH{Jzm}*+A zkyvG5<9Ki>$9mhhuZ(pz&W7=TinF-{PHz#b1V{Lw#remwCQfXwf#Qi>0sHxJ(c z_{w2MK88i{-HK<%NrjK&h!Mz2DZW-1xWhLLK8A;U)D_<#p51(0ugdSLQi_l5cQ@Z& zSA0XTQ+yBN+08cqL2-~%<=bE3+0FNgD||VyQ+$7iXEz_uPc4L*Qi}U27`XWkyZG>E z^Zg5+-F&+taLiUI#m9b=n{NyxQJ69P*xpd#`xTzue2*Z4Pr^(o#rFmb+j=}dOtu@;~c@y z2YZHx<;+wpS&rf!EU){J#IxOPD!$o{;vOt7o^Pt7xaZ1iKSS~{|4hX<(NXEf*BIUj z8{)X6QM&Op;_tKZPRg11Lg~M4jhdsz5|}fFrzRo)ObtKNaf&C7r_n!0&9Ya$n|!9d zGYVzqcf@v}=ihAGh7TNn`;^OsvG362yENH}yZN3BYxdvM>&Se(iRw&`C#8M9m`gG!y3gZH_o|a+u2NR5kd8h%5`h5^)p~F> zf|QZf^ig6>i%>0!3mPt%w8U`Z9XLR1`&z7FT`#ZUlc9Y!W8Cq)feIr(%7sG^?BR%I|X0747!s;tmSZnW=p?-#a z2q4xCzEZOeWnY@_I{C_|!+kk*nAZ^(!5^sk%Pl+#7~k*^bbg0IsJJ8^FEPtU2>KXx z@V!YLd@MXZgfBon!ZHDKxNo3dA;jmYgQvH@wY3kYt*Oqoy*6*EzIMfxSfNMt@qO)1 zt*>2xa*1_Nb;Zg2GlN@#BXg7C13{b@=`UT6JG+7-k3`u=;R%!IUq=Gb!D;z8JG1(I zBma22T(^{%5xwl!AFMZ5>GZ`jV>okk_iL%5VG+T4xyr2AHO7wk*EVNN_%n>l3XkNh zXpB9$nViXZ)~TTH#P*C2eeV@l2aXJ`E*}}hNwdE3a-4^Vi-fMqxMKXsv@_8a-#aTl zc}qh9pEu$J$}LB33yysCHsh3GOds)`9qh$WbLnH}jM8}{*)u{u|M*vL6Qwl&d1~{c z$5X+uv1fgKeKHU0@r=VFvU~jJsj~eiQaOz?Co(hMKZ0zV__M+On!wpJC6Ap8-kKK) zp7Vd!IJ>*2dhLGn^cmK`sm$Q;x!{-iyd>s})yJZ8RZ_OE=480l=X<6)IPz5W;a6$D zDik}JwRQc;+2zCMGH(^^3?jNR-jR<{3S-r912dUZ$xQQHxo{bf2#*76GMc2QY3Xc9bb<1GU znZYjvkDOV3=E(H@*@>^b2>-@5 zA4VXu6MK?Pon^)M7C%;f{!HKhnBHLE0NTC;hJhn~p5XhJqA?il$B%0Zc|Il;=dq+h zStyI(UK6Oxex0gWw{FP*wz*6^Ft~R8+W5bw2BYiGyy+{(>6l#mh%+*izU4Qy{c&eq zJP)fp#crmQdBX6u$$~SxKIw~99sZ|xGR59=cuVAol~3O`(zX7iacTX@a0ha8Ak$ZY zbg#C?V)8@PC;ct6Yb#(S+wx4tBu!;ijm^Q^|{SI==$MpzFK3&Q|C^{%I zG~Rp!CmR>lW^XfA;4IYl{O7RmxH)5dVg0UTymM}`Z;5|wUc+nKj~Qo=;wF;5ja%o% zeI;{R=AjqA@z!}*d-kR=2P@^4bpKVyoQ63@)8Av^sFi7=N@nbL`uET9L8jmpBJHb+^AhwDp6x_++i0L>dPhgE6FME#EPj zzW4*PTBiRX^WYD=-@mD*2D?9S^dcVQ_eQP2w-$OSd%fqa%yD<;#?JQkZg&^ow(IKa z|8(=V_8VZ!u6Ao{O@D7^H3pVcO7 z{<4-Kj{e?*pN9`zZ8Wfy;v0nQ=GzCpD9p%5bH(>{Jd@Xt9~I9kQXG`k^FBOZ2yP?| z&J{cvcJdy{t2@eCg>?d9dx!lI6+%gT= zPxQLalz7KXm0pF<((qXl@9a0VzIT>?T$kZ+(Qul?JNswdC6MWvE$uDm(6Z(GMwuZu zv|bpB`;1}q27_>qgxyjP7V7#82kAEJIoHo_V+Z-&pp1M>+59G-%C^jjEU@RrcuOcq(V7UiMVUlecLpM)`S| z)R&<@^6O%MCG72c?u)-2nDfDqebx|O5|$eF1R+H*4=J@RW|ESIfp zvFM)ao$na_=_i)MCM0c$8?NqoC&T~bh!Mg0?C71~XP!HL)$A{mPyEU8C#k7D1Z@ky ze{SNmI9E{HQuEZgi3xGYxHb#trvIinFLBenn}bb3<67gIxkk-NU#Sl}8_?q!sleVE z{9+Xc<~RK5zHo9wGXGBFJN_5v))#jNlXDy9*5AKvT2h?zhYPk9oEcnDgtlVfiQvf1 z)kU?l;%H@_E~pKByC9W)U17smbl%ynp_N{8aYZFm_Ia8)hcNI~#mYojdiO zaShtEE2cNpoV*8nD>BdquVC+spBGah?bKuR@1u*NbGH;wejH)MPu^KEJ!baAGGpeB z3FGp@k@AL18!lZR1}9UkJU$qkm*}slMp}*snzLz^YN^~ddb&Wo7Z9avfzxb3yeP3C z{&wJ^1o|pSriPle@8vWb=L*XLXaA`%aQ22a&Y)(*=e47kQ3XEi2ZuA_L#=c6`_B$;9K_xllS`H-q?IB29_kJU z_Cw?|?q~?8=U66UDbAjWh_k!91I(`pf92>?77zSqzsH4#+pz66AfIug!$9_ae?x)n z597XwS{ZDaSKNUD1%uIlx$O^p?#|r3-L%zix!aR%rcF(9V|Q~awrF!G$(e~WE$ba; za%YEWy0)vf<8}#m8P@kL?_Rlv^Jba{*yr2SyyMpP`aYZ+-Qk|?vw|i!m9ND%@&3t2 zlDi=_o!iVcD3iRH$~f7)V@G=@ma9HH zv;#n>Ck4RXN}rB<>W%oiCuxv2p}FzI>RIjV?KN|9XZwy;TwpG{TQIcq-Z3%@iiMNA zRN7kGTFsbE`Q_T zOIKb#qv7720`~Ey3G@qE4dWrtMOy{vHURY;gzk{q6I$NB@1h9B+U#E*MXer3r^rCcaJuw*m*vqV0?#GCSLId102MPjvO&y>nXdAx;| zmZE<>mc8kIuK2P?o+s2^)(EiNS@r|VJ+(Z%iAOCtAmvi=YmZzaKJds9xd#+b`CZ7v z1hh2}CkHq&jA?Zz?Ov@Z+ub0!n&QUmH`Q%%I=&{v?(&+V-Pu)xnw@POx8qni%LBd3 zYk51lqiZhRsEfImZb<*_4wu!nRsQVsdSuzEXxQCd(;#g}H=UL0HClFd_tZMCOENLxMKSxW96FJ*VnR@T|R zKQilX-?f&G0ezOU5I$ghA4BNO@x7of&DWXV9$%#pgD|JNUDUyIA9c7NqW(!C@4TMB z*5oB0-v#b7VU5InCab8gx7L_I-)hNxU&;3)>fk#}9saydy-J9`gFgRy{4AX{F#Y3~ zXa1+mJ{58DSj8=^+jm-H&>uJcyu9M-3tp>YwbShJ=RC|^jACVqu_S!Jhx?VYuy?>X zGA$k$S9?IR;xC*IEaUx{h5P-u>DL(NZOFwK$;I0GDA&^m4~R1Z1z1IL#e&1r#-7>F zwI$2tDNV%~l@2bOKMs>CX5*&Q$Q5((cl3%{Iw z%-e}yJRK~}ls3G5w{Y2urvs&OwE^yVRTzc?@hHe#VjSj3qmSIi=;2K@3QJ4^h4f- zpHhksRgQ;`7lWhvl6-Wl_`2}SPpRVjEuP)2JH@vR=I-!C5EvCc>WXhSp51&!5EwV5 z6yJR?aPyVB_}Dv9e1D5)@>SqRRSO|q|C9A2`hndNgg*y>yO93pyTJW}as-`zQBikw zBjp(jqc9A^oRd5ZADw9mBHE<==lZQ+BZm`^Mi#ItPYqvZZMbfswjAbzxGS!MftA9ST?@A|N+Hl??+ zvMNKn_OoO!NL7id`DZWXwVf%1*PUHe+Bn-J4Uko)7f2IxUF>``aM)%D;m=A-k6QX# zOW$hgw?Ll{+#q#yS((f8=a_Ao`RFoYL2`F%bEiGqZMQY9NcJ`$dC)nBQzUX@#?-8*8f8ZZVhXd5o}W zZ);cY_TPO5=fCdT%6FB;M18who}>6FrD{DilRY@T3r^i-*5!0_gN3W00CgXJ>Ap38 z40HFl=06}`$hT%C0=olPrOYC3hRyS>0r><#tR-2GG9Ijh^l!~tSX>Tsr4*l%mF_nG zeSB-Yqk-l*JyU;cCZEg0(LPi|mNFN>D~aDGx8nNdJQy$zQT+HVU>}Gw^N{C^*cFkg znLWi`397*3By&u9_g!$Ub=9&}ID?n!<5%;)g0DZ6-9x$>{XNt&nC7TBkoVIN)}p*T zd-$B+2%j44_Mgkh<8F3zFit)n9xOMG4OUiQ)eL?kBnckKjpx>7EqpO`PlUak^=Izv z*>~>L>FheOaIgp~@{Jp-reRk;?Sfb}asB%ViOY;ftBYF9(`^$Q5TI%3R_5PHN->05 zFf$%L@DsUm9*ljF;>|T=@WqRovA)K_w3detWE`t`@0HS_>hh7Im>6%1_|}epk;w5c zn>Zsr_GMXv!VNiZNy9nBH9H^4nUI_bi?i}T*19J>JWG>+J9BO;q^K`Gpzo&CNW4)=YbbJJXe}Sg$|c zR_2e-ldO>#SgpLrI+!mr+?#8L&)%6ZnTmLpt+ZEZkd{lPg2RPXVRk-+4YlD98Tz-MIdewjyGt1$zA@l(AMP z$@KD{{jl$Q=iWO#TCCgOoYwvivX^asp6l1uU%zIH_x=Q@hizT2aDCsVu8q8sp?6b9 z>o#sbb1jXrF#P75n8|jV20q=~yB#+)U@Z(g=3c+~BAti4{Zg_7nFp$5u&!&t@w1 z^*3+tz9BurEJ`+lOPO}quR#;fIW|`(^_$=K-$%ptzwG3ObS+zV3sF6Dl!q-L)n;NV zjICg$R126*5cg1)kmE zdkJzGeo866KZk)keD{HmtvmA3T=A({E*0OmVV92YyOuj>QauhnwxG$!)~n(>f@gR5 zxHC8hW=g5>{WA>Q;rqTT{ZtE`>Bm;Pn~$Sk>B9G}#`ml%zG}pee6!)+&Bs+f>G%p@ z?hfDUuK2R`tm3;$<4Zs;hrLoNzRNYfH(lXVqhAbPi^jJLa=P&SvBvjXSNO0%$_^h7 z1;T&3JU3qDo;@M!a?lWf-yX#y1K% zU3__4oI8B?x%d{j_#V*s-h`YkdS*vnN4 z)>8dg<9h^rEPqUw#rP?{4>dlnj&pk4CXR&fYkWTfpDL$IU3|rG?=Dw7$t6MpOVMAd zSul6U_a`nsj#Q}dU8nISr{Lqs-)_ElU3`qU;=2hrrXw_|cHu#Vi3aMqD-AAPy71(0 z#+QCjkuTjy(4WE_|GQ0;5dRK=d7%_Js8|QX%2pK!&|kR>6pp&eYl8P7GbT_u@VmYd zKgI(_GEH30#qew)o_9G^e1LkC+x$OcB*^Vqx)Yf>@}tt!YF)5b z)HuqIIT0_uK*RIP>?oc9l;(?i{L2Un(f73F7Zx!U+#eM#9Oqz_zDg0)C_dUTebN#Z@}KI{GOf?{ku}GE@mCcs+1$mpMXx8eJYMLZ-%ZE)1?DH z+S8mTPTvJxDcbMBkM=CH+G4xV?SH;S~AI3^7hyxDJA4bok1g5suSC3K z$!2&_{*iEWZ~DJTuEeHn+Fv3r_t=*Uu70OI+dBCupIa=M`IV3IxYLp&QodY#1+r31 zzi)f&5euvHf4Q0o&_@W=;D9yo;2mbO4ATs*O7x0F!8F_1q#-mr2~k*+i@9LuyWJPG5BYI(4Zu?wAUh)bo0cVNph1*Lm9%Q6L{cM!|o)Q-9O)*b!p zZ^w*lXV+&pbzy+ZapN7vhfpC!EScXYntvqz76-3za+Lsh6;Ba(LVxVYQ{h-QGh7T0b;c)@uuj58IQXtJ zysSeQE(`^TP>We-Q09B>j*ql&bL>@oRJ@hWsv!iN3>V_h*;9sh26e2>3^y z&~2uF^jC&^yOWN(jKlAHvDS6+ydlojPPemv`Bjw{Ja728*_gNI4QC>>E8>^^`t+LD zQm;g(#}>y#iFrCx?Zl7#->f!pZq~+eoLH3{%lh}%m(&hnsxkJ^R@&nPF`i!a=Uhq2)fRG2G7*eoHjB4p#*h;j24{gtg7Y}COoNAm9!1*&^koC3-9?0R2ae3BuC|An3YpS}wb_**w zUM;wKM}Kb@?jLt%r7Xb4_V%{M-Y$G&an3(pl`gCX=?Ug)rvg`379Fx`ig2Pe(s)cH!4EbwQAg!IQq8%KQ~_)gzI3Yl;T?l12^9g z_~@Q|OasN&gJ(Bi0s`B8N-4evVBp4eLSWpKQn=kPaQiz9eB?#Rf=}}agG9hb}RD@@aQTfSQv_V_^Gf_-UZw|5?D$-QdeQ6)w{^l-7qM`vl+lKdd~Hxo8Ur@8na8iLbOF>Mb@6(w#y~Jj;Wr zoF~dtjX_0BF#ftr9P#PLpq#paCDBnFgJM2XF&%lD6vN{veGF=bWK$n!E=x`B^vd^sDb! zve~B$ikB>z;b0&8Czc$QGSX8u+*F@1&Bwz0Oqd@C=VRsh+HG&&-iQ8}x0`3L!mXKn z2M`>z;wx#|40QC@^mg=jV6g>G4VItNjg!BYj@R0E((T0csZ&(?HxcQ8wr#}x7Vvbe zRg@Q+y8}a|LZ(@$%q-VD4U2gl!f+Ifgb%}f<xAA$KL zFu&O{FNb*<%x{Ew2{|nDnPAttmS*xN;cgVVFM%z7@%ExfhmYZ*r=)x7r zx!X(k&)Xk~J@B4n zMx+3qTkxEP=ebCM(u|CwTw%rCST}DgT7%VPXm`uRY$(`vWLtLh{#K@rpFBI@=Ni#% z+M8`?gi@}T_AfC;f(`fMF82xCXg=-_j@+MMd-|ppdzDwzx$VCD08@Es{P^}qb`(Z$ z*@{rad`JBeniifJ&h;JnRba)@Mf=O(Yb5sY_NC*doq2mYQT)wE%4No~~Lh@ zW*VGx6*m?Ycbj(viSn~YGOSa4S05^btIe4KGi5rA2-3!9rOo!CHIErq+Uyuw(`u(p zcl2h){W(v+0P(SsUTT;9dSZPv{-^sy$wf(HPcT+J&-c!kau$7?AtMv|nZcSDGTzw1C$aJFlRl$lB5Z`BixZD+t!l`QhR+OkeRC`Bt{)Ml>w(C~ zkjTE5&=-T-)-MLGuD^QSk<@(=Y2FHkz(TlwKD8^dvZ0jj*WAKSB51YZ8TaYM;2S?VQ z8QmC=NKx>-aS>T2MBkT;du5yk?GQC=osICs5tmsFv)8_cQ``m5% zU@d;J#kdP8eBi~@Aod~-M#AXbn@>^uDPljZpBQXX_9!te>bW>Rx1lH@N(&NsvD6`) z6J8YirY3Zh7 z?T=h-`5QT8rm+vVsF_c^OU*zDd5HUH;7{d&4D11>%SFhKU+~Pn^FG{MW`?x#xi1`8 zjMM0U+L;r}lVdIQ>cRl$f}^nN=ez76hJn_^DTmnnqT{no>DS7dHPobJ|hg zwGTfPc%ry=c`9e#8_DXEM)ezs#aThy{1-{sEDhDXkw|7$jrguLIci5}y6}tN&dNG! zSPc0vd3D-jJtu+lpE|!H@I?NHcb_gu~lsNon(33OhC5Ki@Z0?LQ()TN9;&h2zU&#uLOC zf4enNmI`L){&Vh2OOmDdlA;Z=J$wJq8ZmC3MxV(Lj4}d;AWvB2_>`6JW*LYXTx|`;$^#+nVBS@MJ=%D~=HawON;mtnj%LOK zi!Ms|3`P>SI%F_pL z5u<*K8-AV|9xh1M$hx3BejfPs6M<>#<@x-n$#AZdc`{G> zbr5fD$>HMo@f{Cs#p#qa#kU=A_Ma6SU&A-$MSMlRc{aN7c-KR>ep8yg3$wQ)evF_V z-}X=|&89cpv~{|C7c0?1o3M6#Gi|uDjO9Pas+;g!i|1PAL8F*p(;8)jp}JvRrVQ7n zhNU|;CQEBJCYoeEn7RJWj(O2vWj?ue+R^KgdJm(uNH?$S50`G+I%__&Vm&mt$G0+8P#1{%j zaEfUIZZ1eHiZj>z;}_vX{=wdxwzlHE#22OWXIX*Q=K>v+ZQn&%fupk_VUHd{lL+{a zqP3Ph0e>IGGjHabi}vd*+*{BpbF=QyjCgtX+<}|Wo|^_+L$<8HnVEsI$~G<9Z5^`R zhID2gFfW+awql-G<)3*%b9Hhku|_;%*IfonG2V~hf$Vs8-JB#-qHQ70Z;-nbrXk;1 zMqZRa0U>9{BFEU1~;u<_QJ@htgXiN0TC%}Zn)Ex)VdE(5o5Fg}lEWgOjm$FJ`Q zSaK`s#N?gdzLPRjQ-+=OPCv#(76nBlfwo7&Y?E~3If&8y;>5H#>b0Jmw({=Fo0=bL zKGuTP!m>H7$J@APgzc0M&Y$+Poq{p>ZKE8MuLwqc@#3yyU7_ehx0>bR-8!(XTak<{g;Rz*sXu#^>IylxcoE>o>3a>hB#emfsw_ zxBG*)*v^sV31JPJ?Ht^TT00T;nfHUfgfp7M%qQR+`?9q5*wvM^&UBXe;DNOZ{Z^^Q z9HLBTw&hubO|BJIn-A?iS6foG^Ju!>)oz4&wQ55$U1ZwCaYIVkJnSfvX&Wi2r=Ags zNIfgEK0{zlU?cm1#(VdtHZKU(+@0Edg&8{J8C(z<26Bdl1nLT)Pc1xY z_;f73x>ZK`bljIagqCVich)19jv1F;GWJaMqE~}gl#clqmy89zmnYLXcq)*1Pn<6i z@4Z~HCo0}~S^QJYp!inorFVkMBIUx6h1! z!GQqX!IcpaB@1IdS=+eX)!XjsJ??^V2RD{~W-ayc?)nbQk1>_~XM0+w$L>$XD!}kn zgL9))!QZ!ct^~4X_V)q z%Xi5i3&nhqIrMQvwwu)7_}F&z`gnGXoNF}gFjsj>68nbr^pHj*S9|}afts%E+q-s5k#Gt$h4sePWP97r&UO=q``FWa z<%Qukd2=e)9W&k|PYZjB)@`ZiYn%I<>)JcJ+j~C-Sk>L#z5_G2xB$NEf*f2B2t(sj z_=}6>d$D3?3R^7jv5yc>8$T=^tLpFC-qE_YYsw-lClKn}I&n^RS`OUi=PlrJw%nbH zwl6pA=#>6ULTnmP2c@O=15*^YcXaLSGuIhS5fHp1la5k%2Sct2`$$A>2NpT?uj^`S zSFlMTRqxr904vR9mQ8YPo-gORvoL*ho7yo;W0pPTPuiq6E%8=W@=DVa<52~#Dvgw*#n?cA{gAJH@%HO)Ivn{;fwql(ol7y0yAAFj5hfwf%> zom}}NzZqB>+JWUlpIyBJ{?WME{grlqqG{Q_gD-rW>tn0Y*ERRHIaIedcXZN$hUd|e z?K|9`>_4ni>NuaTRKR-Re6V{(!#*qy;#~3V_z}Y&=ZZgtpMjrRUBR_Qn7y!-;%kD5 zn{Nz!bWc9IReYbvvzxCULIh??DZV>l;N}~5@sU^YJ&tEL-vbahm#viI8-{_K?``mf zVaD)<@KbyotabD8c7WGmrj+7)1_o}v6!^MfMn0}*P<$ux?B?U?>V-70l;ZmpWH(RON@4FgbH~28b zZ!494PiTCH!8Z&PafPQ8GPzJzXS*s-?JKDC-^EY4r(gCr!>BVi|o1@3Da?jGRM<;R1-x#L^8!O4$huJFB}@!bc$DD0I|>G$^4UO+d;8PsrM7B!xGmS6l3g4ALC_c-0|&pg^z1b z72hQq-`?rYdR8}IorW6&4qn@ed{pfk?oHsrrj`7waQA7rGr%oPgWCn1J03%b2l<%J z{63J6@74D;zQ~O9=b-G<`1ZQe`4cX_H#EKh@UcEsivCjlOyk?<;)}wbIEHUJzK`zr zayR(ygSk?QZyIp!_#SlSTQ$InZm{zT&|&hwstsrc^D_=;S7c(nN*)A)9Q zFWvX;>l$Cg#fPnQHs8w{-{=&4&ue_;F1}B@`2J1fOHIM|j>cEv;=`6XJA6fGPr38A z0*z*Od{z1t0_QF-mEc3x$?|uzi|=ZUFA2T~?3GgG?@EoY&c*i`fK~ZRXneb-;JZcR z+w9`o;^MnUHWy7=-?sk+O-;VIH(rG^`y!ruzu+~sA^Iy;3Sa`hmlL>~Antu)qwj!ZGYrU%o)xa2lNQi#+Q2xeLU-mIkN7L_YQWP8yu@ z%k8fpi3g}BzUgptfFpMW9YZl)ddx@pmv;Ou1P*D}t*q_;ZudEw`y7csXhYmJ6~i|}!_Sa?UZyd}e0;E{e?dFZ(b#h-KXTF=-mt_+ZM?e% zrGNPvp7%is@uba3$x*y5&C6dX@lLydBQK8PZE0RSZj*ww^WB=|fbrx<%f^c@l6WWo zot&aWKSn;hc#ecPino_}?dM58CzstVLh@at;W@(LD4r|h6ob=)dhNF0{j2Bol~f0+ZulV4n+;jfT*C%>-H@D&=qLc^=t)^z3<%QXBljc<#~QT6kCsI?9hza=iFYNc>tG!k)0B{35F1qZ04bB2fp7 zCqH)Ld-oxwkhL219>o$r#N=Ny{It{;0;+ulEl8eDb6^$B7^JDtP&Bkl|ZtL)as8lwW*W!+%=Cv&ZEqzqnDu->Bi) zqjHpA+^pf*LvoZ~d`7eXjO2654|_n4@{27Rev5`@564k{(X8Q{CEh7N%?=n(e$k@g zTQvJN&Av^u->TWOXW=NnNNV;;Ej&pFj3+-%z4GQ~hi1P`v)`tr$2JY$DU=DzkRduH z-T`$wk9hKn?e;laCVsny->%_zX!bkAS1d#Ty5YH#gZy0@zDxXf557y|@0Pdo(a;P} zx8}ZE!}ns7%gc%-p4}sz7)$qM?k29T^_+E{_Pm}w_|Aq;}Hh~}aXiuYHsW9}2 zCi9$NrD$IZnMRHHaSygS_ctQtp!mFo-=oRjwA`}}<87udY4*o7`8S%J;e$gze#M z%e|TYSBQV{$Q5$@m*FwvgZ3pJWcXl)lbpmXT3CwVFVo~@n!H+*Io?V>CR0AnDeTnj zIetp}F=>C5_-~s1cQpAKP5z3Ctr+phG4V@FHvOv;)6f|pAHTu*XiqJ%OZA{2!W}KTV;{ahOXqxk{5irO7)q zc^71+&szNQ(H{J+C37wyAML$YEZNMj4dR!UY`$MNh~IkTPm6h&mnENRf1|k8Bi}5V zEIA_iKO?$4@)q$GOE&YbS^TXf=SX~ucnPvn#2mNmSuFEKo0#y(TSZQ`86J}_DHd6> ziSH0mOO8nQXic~eq)_L6Oj-`^Uex9+BTTolJ3Ue^IMi3AnTwd+3(}@qi#BN)nu|)U zKx>}7_-xX;Gk4(hrS&*sva!8+TWxzkR_Av0)^*&P#F9Iq8L#d7tYuo=+^;Zh+R1D2 z-M0D){F=#!p_oSQQ&8LlYGtrzF|=*Cwt7>2UsY>=$L;OHHms?UD+sv+-DTK`n@*Yr z%w?6L`i5A|mZpK~om;oI_g3H0-`-cHQd78nx0kLu3;f*HC>iN3)H-`>F~0N;%OXF* zC*{HwVlx`{qFqnGyi4%0RNaX^Bf3dN)HYTQ>?E*l5H2&t)X9_1VVYcSZR2jhjVj*b zDjhqAU9C9xB$H=b0k#F$oXVXYUXL?#4}se#&CUT&RyMUax5-5I=5Q?zr8AAwk)_#P zV4dib4sC5MuxgBfO}$tG%D3HG`JK)QlhG4Qmx1Yw;l93oK!c%pc{APGmf-fowHd)& z2JbR(YElka5L|m_smQ|I9c7> zi|Pkw`e8Ff%g(K>jaav9oklCIJYLxGuy#GT1Mcj1aGPqo9NbpU-Uc%;AeZad)xCgH zu)Y_t!^umxZt3f|vt4~dEHh64-TNU-RKH*AsDzFM`EF0W~1NdnMeqcD1POkVuPh?~6zeuy;eat<5yB7RlQm zUM&^-xcK@bF?RL&k*M@L9o)f@MZwHZ*JIw|4Yl_g8&ykNPq=wViaR zGHQ#t&fYrhmsZw|Y?g_BvzBH2Q701HSBA0T@ZkAD)C|o{KQ6-yIThLkch0S*p&cvh z<6G0*-H#nK>J+jx2b#GP*Dg;VnMs}!@eu{VV}-yu+dJHTS{9y79ck>{TRAjqE3h8# z%rLq(TDaXz-mKxawM*(0uB}E5cBV~AZL=u3$($C@BvX8RXv^&xlkC*Sj7b*Gb_}sejk(i%@2tjXH-+LNA!>iRQm($uFCI z#Lz!j=UYSP>;+}c8if8)VD#T~cRh7<0B)oHin+EW1fFLhlYf-@ej#8beE(gDA5q_H zo(;+HaQ@Wy9dpdU_kFC}r3~{=0T=owbKNp|U?phJIm-}8RJhq?3H>k29R70FF@*4! zQU9SiAI$KukHUB|-o#6Lm|spA@mWs&u(_TvbVP^*W!QI92Y%3!AEExL5RXxRO^9z% ze_e>DsUJ0OnP)oTzvN|n$unl@Z$f7}Oi)LXB&xE|$J@iX6y_i2TAAl<+AIxRA5g!>|gy%Y#tMWGgSLSWyp|>q}zU+94O7R$ z3z;u74Ku%I8D@UtLcV8dkI8Rjz0`jK-S@7!-qSZKgnaJ+dYk4iS@q%bLf};s^XC|H z43FWv4svL=xqpE1mgN|7#4<0ZKF=`o6@i!e>(V72GV^=>Tw_vx`RM)yr@mr3&tGKX z<|FX5XZevj0(XUZh;Tgz-XRb3mvr&2u`K8$(#2?>KrSJ`X z0>3AGzM;K--_Rf9xf4I?Z{zof;Tw7ZzxVMA0Mm=#1HQ~5?9@rgzc2H?DOa+xVDQAe9`WMda4`C4VR)r)ZC!zQwyt1LVOHDum30O8J=1bmbS&7j z;STY1_Z?ZciP2#ZjAjn)nh}Wj@K=WPIfO45KIH#NphsBY2pr4oF~-W^>*tK~V>!LM z4z3vx2Wtmbb?*rW$1;1w!RCR;LDX6)G0JcR3L+;Nhn`NY!6RUc}Xb`RgVe#^Aq~4~y;YFMB-$ttE-I#Y-=IzG9 zlFN+CezLRZ;7-K9X26j73BF`_tO9Q9P^M7IP+pc5Cd$goYV%g+F!hZ^n)4Vr6R=h zd?Z--;leWHKvu%S_e7ozpUCX>4UGmEuTAi&aOQ^mtd^{n(UQES=aGz0br83&CM`8|>2GkU_u-|aPyhkE|@V5qzF_;@dD zU&%`D$;(}q7cI#f#b0C2?t_uzfu81ps=VN_Ku^m+1n*|+z$ME{e;Vu^g-v3>f3PYq zYgw@O(V4+3AA!&1y^jL>)gB+h^P}VU_GTXRoyh6&ZQqc0{#a9QR(r;}wK6YC@}l*l z$3D?BysTt1y-<6p?!4u(LV`WZH*0#YDg+03u-Z~&g zr|0J2z1u5GLY9oxkCsOo#AwFsU?a`*Dvavs$6IO=mH zRO#EL%L+5L8OJkwGV6WutZiA_#3;)|W%${M?|2w>$oY~-QHN*teC|+IM^V@}R2#5r z_VD0XtmohGRd_c?eAVCb)8j*kt8r{O%5Np!%(DDIX?X!tF>q{FPvGgIieQgO{71xC zOtbR~KfFEglg!?tgM99XRu%Yv&ZmYP0Ta}=IUDy4J|nhOREBzhL4D$z&J-noAnZ@% z;@cG7wLdSbWAIoAU#~&b5WzgeV3=mnW90h#pm-j8m`V!s#k0mwBKW?(5RBsOG!AAC zy%(G~p3{rEvBxK+x@X0UI|S#hPYeM6N| zRa9V9mlvP~aBy+Acqsw5Vl)ZgY6}Blqn2T%Bo47QEkX@Kwd#)%4}sXULk zNW~14l0Z1zc*ZO>QONlv8?u^nmSuJ1HI*X|5aN&+O)>U)mw#J~1`wu_frWT$9)Q_J z`{~2arWtwXE3!JyFWc}v@zUw@=g(JNn|GtQG;?P#?(5$0oyVUMqo0$0p>`iMMC9uE zJ^S(1DC*g9SJz!{q8zP#`g16gg?LIp-yimkg?qa1syNs(kQkW0&lvk{j|$0et&pUE z%^aFBO@*kG-(E=fSfLWb8w$nfL88OP($G$E@Z!ChL&I5ObkIVS?-S2YAgpTsx4Amgqh(}#1_y& z#Q$W}5fJ8Yu+@pk*zbAPW$(3DP73qM?>F-~t36r!UGKY|bzghk_Pd6Vrm6(`6r^W< zZBbpUSmzf~E%t5k^CY#aZfNRu@279~VtgAOi7u|S-3DytDopXO|S0BcC-dI~gyj;A&lPIOTvhY!lcV*kha)yxo2jU-}qi;FSh>GsZ=yCGIpT@q{B zoTz&dqsymOfmeB*c#3_);*!ytHn?@6{hoN;@@(GEUh1Fv^A|R3ty)}sc)^nu-@l5! zN-!p_gRhdr7{&d zvGw)G6qQ$0bQZ^ErMm|=sn&hQw4w{yjxa8Sudc@ndh0K{a4z$`WlO=G!?^I6W5wi) zg&2EghDvvBKx$*VdND7!bm)?y4-SbZ-asfURn`yomk&%mf4kWCx2Q%%wRPJgKP~BR zUn-u+L-`gJCzj`Zr@pN)n_L>%9ephFoyg`x;MnWn-Ma5HqLvx znYVb)P3joN8x7p8Udu}KBo)(`UY6<@+H?#(aRPCupHW!ZdR^VMUdw4{`)^m)6pJSg zzklCI(OK0qSciEYB34qcpn67rq1O^CiS1g4ni?CLJd{^dUeA)kd}H4|C||U{WL%bA z(IqS~jy^eFn$(W>?1pH21b@AD4}V2F-$;2ykrbp5PxZzus^vRL;80Ct<5|h-^Dek3 z+1A(BJCI!4*PpC!JwLf*-I`1n6t^X@b=C>hczyi?vy(OR7R_6jT#%Z7dg}BAi;~q) zMU?3n$jnZD5MEBpXfLPMtX_2L8eFT_*`1`GvVoqy^~nVbY8KSiUM}jnQr3~_SkoiC zxp>TPgleYD(5dIwh=Qq;&Yv8K7Zm4}ct?51L`%J6y_w!|URhp+C*}=oS~u9S2KHdT zvb)U_)h4N%!K9iXC_w7#!nW?bT-$%SdH?^tKa5$(9u-p_X=?BnZOJ$0c`00MITF8O zS8a^!mIY2dD><$|(V&&({I;zdJS_EOr4asHgx>W`L%`N>zaWvxvX4xM|zl_ABf_K-@4g` zccdSu9f(wf)SjkkmQfM#%)a&N%-a5i3x=+kzj`3EffwR-8P1V*xy=neNo~w3U=3CW z)dHdVJ3ocxKdk?qxu{mJ8@}@@;1-n_|CY;hagtDJf{sW%<|3(XRy3M=c!^j73tn zj79OwOHC<{R8Fh7WlV@$pfKka+$VX<*rdcQW0O;p%WoMgOm(N@kk3!vG8V%x4$c(V zQ>8}ve0kSoY^Tx)&X`i~>qI})z@7Q!dFdjh&A6PJVj0WHO_P_FwnyI-1L8MNCB5>} zcEc&cnBC|tPSs6Yj9Xf83v4Ow4|!T^h{Y&KYJ*lWi0#o-bs_Z5n)op1#1@8>9B!9( z`|wt2Zyg?y_Q)``5Z|z~U??&#KRxqB@1Z2_7A>rxA5r;8L+qswcRzR8FWMgHK5*GD zO1*`*We>gbdUxb@Xmdv16w161BO=LL5+b-0W4Z8T{HO_eqTDdtx*Y-fCov(hcl`MTiBR6y0SrNzc;>?{O=kxL3TUV}J=BA>hueY}z!FODd z$;FnN)JNb0^$1*x#lupeD@K`xh;-Y=^+>iuvkKJ`p}6}6+$BB zB;Ju^{4)n`ib6>0px2RbkOA7q5rM)dIF1CUBR>HsD`4olSt@D7n6opptiQ3N_b(ra z$u}wA_U0YS5s_`oNU0o-l*1@S8duJY7)}P4yKL_ymx7ENZiz%zf6N$xBQ_k&_RXQ= z)yRfBhm_%u;WgoB<8cJXpD_mSJUG~RdDuc^T!_a!FnHZ~w()KS-HM+vCSSVXVB^&Q zkMSWMZG*Q3&o z-g*bGU;;d9jkNP`(8A-W+TeZ0!NcJJd8)v~&&2gp4&HUZOG1eCc_w}a?<)=-)6eoU z#^CL89_~s5|81c$@}5{$iZVi+2I3!VF=Ss+$e4g##JpjD40fTMu zPIT~Iw({>p3va1|HwrvE|4iDmjvNCrJO&R^nqEBE>3GA+7pB{!<8}uxZvwo}I(UaH zyg3%$w;jCL1bB})cyC*He7BhR{oKJToB;2q4qhHA6Z?7A(|H!&VFxcU0p6b+yg~~v zW#OHK7ph&aN+!UofSg?(B^KTS3$Mk&E1dwZ*}0%ez>GPWc{dfy1N&q9J3uzZWYolS1fua;1pzQ--k( z3|Cyj@&!_!bzB)UT2vIZ3x(xba)F^Xp)j8#nZQIb5(@L}krB&nn!~r>Amk?;evmST zLTx``e2xSHL+w6czC9A9|Dzo~-_(Jj_MWhRzIg*fZ9QTBOea72W(^Fr_k`tVN% zo}zeThUKdr{v3zTH$z~eI0qZ{&z?RoQS{VdK6~!KL@^@>^HTv6Pf?s-4)fWw1}2I- z!oz&_l!1xj{A-xco-Z&_oG+iMN%jLC=x~dv4TSMT?K!rgb{y6~`ejX~wu9N009yw` zB!4M>)Ml^@wlU;)83HzGyH6!OjGr;2zhDU1r2ig2;igJFYqIub-Ea- z`?IFm6HzqzgXPu@VAHfCE}kPK2Dig;U6u2 z=kPh6qmznXsW{$xIWYb;n!gy&#pn;}9e$fb_h@w!C7r{~6XxjB%=V=yM#p)uDSqGk-XCrS^l5IsBU)dWV)* z=|5R&cL?&gTD<1S7a}16e~vhb3Dbrc%R~IRVy(kB+LP&AjQ-(XhyRZu|0(fHhyPZH zzd+2i-ti2-26Pa=8gY@s&xZJCh>tmZ!A%MC6}Pnlq*f}e6<76nmR^06-0-3+ow(SC z?>RfK472oim1^Zye>FF-AX{_Z(rbhw7dI|$Y|RW}`LMC~O00zmiFQHTYAiHS8*v zu>GZ9m7QFN<3g~ChqL^vaNI><6(m1owN`ZTnV1Z7oHGMOAmc?{M+#a}YKd5(j(4Uo zQY{yU{ckK+Vi&q|kcCI56$70;y}cdyE?%#+%6KDG>B%R!VC;YTMsCO<{IzsjAHK6y z$#(@A8Tur5f)!`|IUftFyQ62lT!s$d?A2%g`@xGl`qvSbX*%-PfH@@f2e@s0!FPf( z?xBTY-JEiKE$vsfkUSU1$D`P5-s8DC|LvL_T1E~&4IS^-EP>me!z;^2@*OOW+x~sm zcabu+aBlm~{h{gjn4`?h+PCf9avtv|lr5oe`@)>@KErtu^6IdpUsUwa@_TE#wf=&| zY^Wh;zB=Q0v9X_z)TuE5?oC!-mtkPV*+zW1{<;MV)hW`=YW z`~2Md>-S9IHw^#4QzI%I}lCO)^ZK;bbR=1qW```D* zBuCw;JuIJ~5 zaYFL__dRiNbJ1Npj%kX{KCT;QEfRTeingf-MDmL}VvD@RMRl3W^6vK*d#PBpHx|F_ z;DKo)k=fG^+`Z$AWjM+IzK+Wt9xF)9sQcw*^}mUh^I4T-{&1jFw8i!LOmMO)J=lCtAQ)yP&lbcZcMPhVV6z-4yet6|e-K~=fUU+`& zUVL2ZiDCSZUpxhYI3`ACP3I|$*nY;Rdix}_t(onKipH@mbMtW8 z+YZB`AK7{icSI6DJ~>I>rHJ2MYf4cz(a{?kA9+*UaO{Djnj*kEYUCG@ydPIfsbq5c z$S?Dz%d(l?^s{v{4sD$tJ1|G`n8Lf(C|sO98J7b{JMy-W=OgQI(|Zf@8HVXLXK*^Z z?`$~jfQn6N^Klg~b+uPq+EqEkJIpJyUxQs2{Tl1c;U_08-TSqn#L~rk8%JYsBQK$O zNm)+urIZs@lbe$1S?zr0FPX-z*f^8II;z5F9E?fqOyS0NZ*P9{*Sf{%^ho9C^k@`! zP{-0=Yp1U+#64PF^y0s~Dn_S73MPw+qO_NsG$Jaz^0!{`Dg>U2(g}G>Gi&uRO&>&V zW;-8wbENOY{fQSJd9&_@^8NX+hi^E3Kl3bGTW|Nr#LY=!aT@Ni|XGW znAUVzH)>i|@k&PPRumn0U%~Vj@??DX^~Lu`WPBNZqAx1LM=x<=bs9I@BMjbLPqb-G zmv(>eV06ua6C$(o)A-tFPV@l#@1I2{zYuFG?`EA4$**pqtf&$r(W+|cFPW~DIII(= zzIO1ui!WH!w4-NcdtUnD^F{Ub`}b|R8WchQ?p-hX(`345o#d3a%IJz7=t&eGDoAKh_Q(-+sR_(Puf5B9(k0F0}hc~j~&`0V7`n*w$dun$c)g&rrW=opx>M3c; zPsh^gp7p%+uH8jV#pt2bn{P%off5lY5fxs`?x{^L4KpU7MLW)d)qNeB8@6?A7ku5vjg&@ARg`@;mpg97`r{@7c0flvj?n zubk3&d&d-=EAizs`YJ~YqK%_@(HU37npTVsUwCYLUgh`3Zc52_5fj^v)88@=Vs&?* ze~&j6;N1~#63HjWZW5E}r*&p~^!IPC%v-4Pdc|lvT$n#u!S|B%x7cf9zt8+b{7`!4 zIkEG&Wlcl-4%S819DFjm@8B@(ycy{8U@w^w2S=229egqZiIT*jx*NI<<`qM#s_WpA z;u7Qyj-(#^cyT-%Z-$?WH3#dXP1(w!c3@Rz3z`sfnfL15!BdM&k};Ffk3V@Z+8I4% z%Kil2z$JSNmKQ8vfu3XLUXh&9J_D(cJu~ujv52Md!#iz8(~Rc35U=5)hS9o6$H9Lp zzAO6@=zT>U7-=O&kDLBdcIFV`RxZjr4%SCzW-Ab%`bb5#V0ofljW%+}2XUBQvNyUs zx;#=jqg|H3UK6f9sfjbAxlVBAqh9wR431{}k*}nsDk`!@S8MB}+@8eFf@ZI>VoT}#=v&^KiB!Dt#=04emB`V=9*$GM zU+z`L=C^H$z9mLKjgGqUH+hZBam5!hJhn679Y%RCMSZ;@zv9yNVziv>nwjlIO*gia zm%vz&{mD!{ik!N9<+{p4H*|7@(Ky-_U70}(IW!C(eyO1TGrddo_>j+hSH6*mrB!%5 zm&}o=!OV9NWS&4CeS2QITb7f!tD@bz>q|IWyQV#I*H_ys2TY%=a*lD$$2%rJJ!?Ck zz4EQ+Rr5_PvCyB%_R6TJIGETTi9&CP@TaDaR_~|knR2u`t*LbTrQOA&*}nfca7lO3 zXtpD9AdcQ@%JyXX&hyH)-`CwETV(Z6a^^lc<3T;&gI314pq()e37PMV@8Z#9MD^`Y z9jr^p@trI`lb))ae4KgiMmNHG^&O;ZRbI+6x^;V@Oz9MkEmL<#KeRXAREOT2y?7+jCVSJF?PA2V zdOK~mB8^PnJK-h&i+E@q1F_u^%(NnyX=Tr2UNW5Q&XRN)YS(O8UlZG_hnRO97i>MR zc6%P%L_gj#vL{QXvvLj;LAq|{c$v9@@~GX3F>$g`rv0Xd==175iPP=L*%(_8k13>- zXGzJ`0L-_&kW^yl$1#hgA5YHC6U)ox>^nU7E|+ufc&cJk-krhh`%CybpmRgT2KpA2 z$@X7vD8Pt`Z7)_AvwDne7zf?4x3sYlGw7B~%es9Br>Js8|A4iQ50my%NE_(ba!RlK za5dIZM3#MySIb^!ct^BxDbgQNN*)))3U5#76Jda=x-y)qB>#+K*dJrrAx z(cqfMo5O3W79gw()!g^#1uQLzu~@|ixSccFCs8^>={8IHPASbki?X#lKRWc}&|MAr z>6!y|LkT(V_2e9;wE2Od%AuLN*Blghf9H)f;$2)RXNIp06)!J7zjElp-5m!%3b*#k zQ`)CD)s-LH&UfV$Najh`8M0qi^*RC>^QNuE{Lu7we2??J%6f)hnsc4v(Mb_+fBu{q z2U5E)?XCdTFq$8^6lsh#O{&=T`{C6XMRLumCEC)fNmvASrcMY}{EuY!`zQJ|<*f;FAzh+Rb@?(j{&JIg_PzIDE!Pv2s z`#;>Zyu$u~VW4mA;ME=d{462UZ&dpQ*{Wh*-@C4FU@*P07suxP99Ll}){=GEK|6v7 z4vA^y_a+15N@;xI^$#(4Y8wpT@zohWR)Lz#^(d_MWaAj=L-C@?{QN8>iy}K$4Hdws_;d)=~MURYF5IhZVNm znAIGpiMBY>6I7zIk1QHGcfFnl*;`X`8$th``{ z>%3|XP<5W0gG>YiUI#ahuRRE^v9*y&`~bgtav}q-jT`&>Tl%if^fza&3KzZ#_T5OB z{%~bB)7i7Or?auUu{(n^G7aMbq>Au1ycDRPItLR?xAEd5^H&b?g*>qg;)|Eu`W#8A z-#FM;-+85Je@<3tu5QSo0@o~mTYp@{wZH_0s=4g4)olV3`EMO+>A*{DVm6KjYz%*Y zD9cC(&~{|+Z9~SpRb91LbW8&>Y_y{B+%}7wJJ&86$h7IJ5+;hh>Rgcjxk9+Oqh}Cb zPD-v5LYwK)$H$Ala9(5rj~Dm%;B!kkA{rMbzHu;K#Hj2DtZ-Lu1&=nRJX;^YT5L2b z6|BW}5+%D325*Uk5snmqc^gd(;J=O>5hogcOjl+*Ix~UZ{T$tdijQ+Ug_e4akH(c3w>2)EH$PRQkTdJ4OTNqU&F~1QO2p+b z&hjK3<_LbjLN7f7Oo|@%$QbBrS?H_>MmlQ!nSo5Es})xt^sSp$yQt>$T!~z^UZ#=I z{Z3NoHW(V*(}gn#cGBywU>{AF-Ze($H$y>!JNwqHLvDz9(6}C-vvL zAvKA931puBF+5E4LwGHq6ZjcJSsHE{*?4yVkN%0rJfIxu%ki`0*ACj`5gz4PBifhX zXXD*t;StB+@%WI9w-z+{#+dZ-9J-BnuZ0%}&)|Iu&o*8bbQONaP>$x~_}O?5S$I5~ zZt%W>XB+Ph(7Dq4B?s?O3y){F4c_Ap-dz*m?Q-xQxA0hg25-NEw-t1*_&o!6JH1a? zcs!?O@P377JH6kS0B;2DHr_K9UI};x&z$c!ae8P1ytf>@7c4w}bz|_#5IH-3J0`%J z2_ZXvFI#w}7G8~mw`&5tl!Nyx3vZ@{cfN!7-3joPIe2eacx>+`y=xu3r@+hAe%Cm7 zhb+7@3-1O8?*;Hm@iT_u(p>A{y$w9du|G)SXX5u|2k#B=?D(1XdzXV(vPsDiufoFH z?clvV0p3mrugb!!vhaTF;PLxsQx_rT_g4oTyc*z{{_i9U@82CfC`%XB_!(pJ?==VS zY~W=f#Pn9o8pa%_@mLoae!FvICOX1G+@+&KY*W}=3@j}d%Uh^G{$(MT|R|_0t zOgb`7xU;Sa(lH;xCfv`6#OA4L}P2{v3$^8yq-gQC#E!T30ia6-tojn2G zZymfs3y<~7q_+eQcKntCZx#5)nEXpX&Q5O$@J#)~5q}@=GzV`hJk2yY{@E!+V5C^0Pl4NZ?1)RrG;0B3T4;R zt_kpBkhAM)jfIC#gZ%WK85trNs=k%QN4#gA(S zraUfk@a_N}>ywzbfEyd}WM@UmoOayqken3n8{&Jo$j)V6U@F-`DN$(;D?^jlOH$&LqUFzWd3V0@s#58yxaPZ!+@NTs5h8(Hncr_E?RXBKOTX>(f z@RmDxi-ETad}B=hr5(Ix;8jD2_4zjZC+V8sFg4GSa@Zqe0Dv>Z3H>-WL{7Z39K07SysZ}AKVv$-#RXc)9Aq7aX}4Cy?9i z$l>-3Ie$Ws(wO?P(}~|9#LtxPHy~;13+F?2c~JjXi^ig5@LqKA3h{C=c=uU&e{}G+ z0FQFU7`)>!n76~-3b|bKk7FPQNZ(Xh;XVjglaA9Iycd9n|GqKdwmEXYg3w96RPf$v zal$>@3iq3kH{o(#XQv}xlpC+t!E3YdwpncKZ#sBe zfLEOZ?}v`uHpu15zfnhS-voGXIPtp)@k19O`>StR@tcl$j-7w6P7v-qM{aBaxfVwb zci!Yo$JLHpDdcjE{{|pu*T0*sbbQB3$KN`5WfS1t?cm*E;q9^To^V@y5x znIqRSf!u#Ma@RrbRs#mx;NfU{D82U}ekt(z{(VBru^gvi@MD)-;f&mRSZ70y@>rgd zrUh~)EIOFydW~nsjg;$EUgTdRcMjz2@^}XEyAu+O-#_3-Ifl2=3HR{{!rh?5HSwcd zu6n=D3Abxlh$O;cxKHC}!u^QVkBkH5cz9P%z}Sh%0;UFq}O0=aL)uQ4Vav`wCq zw{>E( z1yTnMs-`w}kInSN9C_BHz)*i@7!NNg%TRx3m|rNv3&y)a$n-{io?&?m-Yr9Yo?*V- zv(SIB!$+rV8S3*4`!5kkfzL8v$|Ip2E8-pP$R7<2b+$ZD9t4K^KEwF-NR4eU${CQHo&6k?zKPmZ?BcF2OlXB$eJM#0Td>}R7 zkzeS@FO>2_zSKhhi4RfiD2L;Jx|ARErMTl9m?(PAu>6@)KIw~`=|Ay-`bop`wNgIl zH55N+^|g-wvmF0tN&oG>)LH%$AEIa-;qcxk<%3>>P*X&vx+74utU(73Vtg z=Sq3J0<<~TJV-k#>KyqxDc|MS*E&bO!I5up_=_EW5Hba$(3%-ePulUn)Zs6c@mb|d zE%l%H5Jl?_<1Lr+LHV)u2PTT0_ON`jBi|ed<0&dGaO5v=_$>~<#o@O){8kxW&?~k& z@@BY%Y>e}$AU^`$U~vrJU0}g*c;sxb3;NWd^&Rd0@UM6H*Gs&hm18r)GEwa4gzNte zQa)%em<(GcDmFXvn=LNmcca6<(cyp0;d6&2Fj4UdhyMvDKRyu%<0&dW>BxUl$_M@R zCms1uJMy1)__sLxTO9sp9sXw>{%sEbHW{CwKe^43zul3)-AV85j{N5w`Oi7>+%X7D z6xzqb<@*IGAB;b~5D4Qbij|MB{GC!hXfJm<@^?A%cS-r+{c@Khe~%-7kCYGkn|mDj zFFW#IcI3b8$ZvJzw>t7$9r>?1@?Ul2zv{@}>&V|L<%9gZ*OC9aBmZ?r{_BqXHyrtI zNclQn>KpzOAEM$uNB%xX{ys^TyV4`B1!`~J#@e~z19R3a&UeMp|aO59#+&*_Z^1B`R#~k^`9Qnr_`R_RL-*NbR z96nc=0~3|1Y62QJ#5n2SYcr9aeGc9}M}D6p|AZs|gp|L|mwLi~;zLwC>Bv7R<Bs|_lwC4 z2quD`C+~`ur2G>V2ORkWVpd50Kp>2#sCdqie@@KP@+yCxbL5|QT6=qDZeXAb?A zL-QQCF^tcd4!y#m&3Ws&kS)gg=9SG)G_%%!XbH%htc+iIF<9SB%`3+04s1tJ?euG1Q z$e}kl^rs#A8xGC$dd4vPXF)UkZv2WxgLp~PtY*cyX>`<)pUjR-8~Q&MH2tr|uNdo{ zr#bvOhrUS5tNOiE^g8^_4*eM|UnudHi?4;~X7QM&S4sW_;s=iZS2cg8u(WM45m-f*N9^^t-`-n%w@&VhWO^3NEXk zG{Z|t|2K&34u79R|ErcyO8L#=ki(Bpwae#5Q3l!=#&f@c_SxvV|{$1kNppBuQw=`e1 zKde__!p-z3`pe?P5WQ8L6{5c?S~RV~zgKjJ=&y@mO}7BESbRf#F+|@dwrN_$_W{B4 zoeW>~Uk{3(fHsChje#PROqBKNr6SFC(4IdY2zABF$;scsi?f+5H zr)kO-i=Be!FNv@C-x6O5@pp;GLiBF&lMwxwIH+mW9={`siWHur_lVOpJy(XeSJa2- zePX4iZRQrHy8sBAT2!XmY8au{F=+&^a?++e|o~O3{p?VEFlV{86osew;5eqB9% zN+TN8F-jS~*evazl3{dyj??sMba|$Pd73YnKBJLS2M5JkL2z0?DspS=?7&S;AoiY2@q@ITdl*StM2JQGJ@c9*wzRYxQZkDBZ~0wHyUaCOBEUt%_>I9lcL}f~Ypi zuEt@7o)lY_A4DeI@M)?QgdEU zFV#XRe@4E(x3{koS^>|`tm}g+RE^S*xuR#iRP&|X?flXKNNt%*GrieNzwx$Yeb+mA zvQ>X+&-!{i!}@Ws7Zrvyq>k2s0&RCFI%!? zNo{Ju{L^bzGi$V7)kY|2f?6oyDnkvS$r~wgp<|=p@#MIcv30G~G-{$2=%A9yRdcCT zMM<{}`N~vPo6ss${ksku8|^B)c-e~8Ep5wI*KZu6!mAY<2eU}IFWlVFrs}p-XeTu? zuG};*m|3?py=p}x3ja!Ed?=%&45RGSM5T($m8Kd*KMQ2l9PgrZfH|3^I+V3aSC>-A z37@tOSmnqZWLIP7zU&rM)@l`wTCt__64C*yoI;vk8&|Y0S-oUE)ZaEjm0b_s9YKES z%nei$D&e7?!SS-l+hqgwor7p-`W8(~hpfyC*&G@+u3f7e$!hdmQkAT#EJ$$u6`gQv z>43)Lfglza4Yc*4>+W1X=y$Gmi8iji0$u}gLz*uwbC~`vs8O+8)CKYTOaZy zJJZ0$uUJ&{${N7vQpK%bJfH)`dMXX|=QTDq*88rE*Xq?BnT|C*t9!e8u3873a>~1_ z_tsAksuU}95RWCj9oYfs>7}C%di?FAtoNvSotEx88D*oWR(S-rr4Lu5SuUaK7wE;c z^KYegHvOK;8RObE6snoV*<`v7(L_r3-Ks`N1%6@QOeR#6s<^8L7gC+87`_rhOX+Ud zi`~s?G~ZJWo~=Gt0ihTJ#ktA}$|`*wyE?S~{=R-)<7D1j>Tz4@S2yy$R@Mi}lYN%k zdl*OB?6Cbh5w85f^{vu_R;L@lG7!7Sq?D@MfsoOtJ5JCr0?|Oh?l|FqCB?%UcU6l( zLqit~4VeK`Wr3xE*OAm5C1%v|8ujIVha70+H7u#O*IaF!S+ntq#xB}-IwyRN=otM1sEdVS|WKW}TgZOO{E z)v^g_9lN+u*L3Fn)VnL&fs|Sab&s;kH!l)-sWZeC*KahEgion89c`?$etp+PS-cf9 z9I*!YM&GXnkl}Oq=f??G59bb$HzlJE>li~TuyJq-*byruRdO#u*rH$iLjr&a5G(!8hr?nXVZo#oD3O=nJ6Td?wN>j+jZeA8-ewdySh+Kh~3GYAB7yrGcG%CkSv z&;^Vt;_3ue;lW3427Kg(GVj~4YF~xszdds?{W!R@KGVEac$xNLX&e@7Y{(o)W{ zCH{I9PCSeI-hdNX>B;@(vJEP{c)usVhbtS<^q{6UYP_qp|4k}h@oPMMU4r;S(PJ&` z>pc10d;EG&e3CM2yLK*qfXakSB5aS>9L=tx7Tu-i{ zMOr-h6$#UgrF#+on9jG4d*UOcKcUhQ|D;M+{8OIPhZX;{C)WhyH>-F>-sj2hdL!p~ zQlCnJ8&9-qnx~uN zpYfy~zsPAiAMZf==>9oR>M@Le-jm4`P8zv#)mtT+^24uNL8 zucJLz2j2#BXRnfP80pJm`s&Xg>shv>*1wS+o&O18wBXQrhs>O8cA0SJ+H{FKs9^MO6}! z!Z3}0f*^|gXS7%e5Wo)lq=Vy<2!V{1kHLJ|F-7u^04~{ z8u`h!T9#)!?b*7VQQle7$WOKh)&prnj%)jj|4G_zq5XK^el+N^?`nFV&fh1HZn#Hk zb-5wjZu&#{nQ#WlM>)xIL_L=E1#(kFv z`9!$jPr0A#{si$!kVd$~D;v@E@fW&Wf2r&1uQdNv9qw;*KZ5!{5B``hG9OUS+d)U( z@T5LT<`3gt_PX}>e|0%Pp6MmOg8bj=_WGud_d#v{UiClIDx!`~e(;eTc`@u*=m2)(r%GKbaT%;WGU*cM{Y?mk}(>`TBOpb^; z;#%^o?`3}h9U~t4%~}W7b(j5YK}5ZuiX*B%LE)>ELt~cjE!eXEM?WIn`?Wi4=?+D* zvfsQ`x0_)PyZH!zv*MQ>7g6;DILwbS_>=kbq^`%`)BRLM1YecFUu8tBr;YNK{UOSm zCh{SbZxQsnj7MZhg%??)@FHEhey-K^`$k=VGpc`yT%p2=pwnV|iS(#`F|y8+XC@+7 z>GpDyu9u(H?~f1b`iV}ii~jm_KeI*0>om289H~@iuOjHo*v~|c72>o7HA&mduc=)G zHTw%{<|mUW$xwgir&4E}aYizE`hxijlze;qh9%8u&r@LlPO$a|ln_aEo+Y1Y;V#t4 z=uM|qXLsiBpVB;~X)u>@|W^{zdZG~DR24AcEOt_9W!Gm?o+@2xGfKl<)svgcRz0=q~By6 z?(OBxfH0GG;+|y`Gj3WI-u>!M!sxck$MXI(F~>`*d;842>jg+#$@Ydr!wbBT3j9?! zX$szgEANVQbOZus9yzf@FsYna##+l*kgYjy z=`}})5~AMFj|*-(vAA2`)zzOF7{FZ-6Js-}9qX5cE^U$%jUW*aS=o){3JrH;u;#w? zSG+4htSzkT8R*=I&BmN}5QV}=6dU{c`n!78cVMmM2r;Pd?95~b4UZo0UE&Tqa7jztlzJ~oK-%&KGzf{ls%Xbn@IewIjl7MmL zOy7Glczpl7lUxciZn%6e8iT%18jgK&)XF!#Gt?QH6X8M`{uo{xel{M*ng#=pemYw4 zY~$SnJo+ad^T6Qoi#{8V?^?c>jWPMM0S-3ay}+X!@rY~i_yv`XceCcflE&cO4$8)R z)QTU+BL&V~0&xZ8Md0Iw8o z#N+te;2i@n8*cBA*Q3u)>%F$r>9>Qw|9`l*?g;OVk zccz24A9x%;8w0j93mv>R3y<;!?;?$7{9&5p_W=ZA+-WX{0OMo&t5Gma+{ri3eHxE# zhlX-&`^FHDzahv0D{I_4K%Z#{EkhE=k^C@8^B#mP_!&bi8rqh#pdRdfh}21N$Ix2F zkM)Ob$fN;}VhrcK1}z7JN1knL_xD1tj@>31yWRYFd%VC5PMCkR6Cd^o3FOcSir{@PDcK#41Kl@+XI1W;HO%oDDj_iwi7^_=bE;vn8MJ zj$+hTEC>09{J#(JrwP40C1uEGKW7Z-Y3MxY#BwS|icb#F#o|0ovn3Uy{;dUV4E=vh z^HqF~7WX;)?>O`iL-M8Kx0+^~VeKzOpTzjoNqUx;YxPkKZ;9r!W)!2o@LmvO$j4E- zp5E0xnM_8Xh3a3sy1S!yo;<=i@ieNc3rF&-akJbHx2872LhO{srB<)$7|5(%*Rwtc zYeCI|)cH%VnUFjGbi-9K3Z@f!(q`{dDW^b0@2mt4W*+Bnr%b#vYU65e0nRw!VESkK z^IebN)5Y&SG&(v{Wsm&FVLOgl{IMm#j4MXFPWI;+md{AQ6j!f-NO`b!no>m zweFbI#$T7j>SL~T$@z;GEmWfKye>JW`ZIrBaw>A+&~#7s+GDi$MaA2&r@_ucPw5RG zg|~_)b?TSOo|E|`#WBB7_FQeJv|Xd^v$b6Zdn@vFsixbsy-M3#Y1avHFYLq30@@-# z*9-9w>GP2}Nvtiye*!j5DeTxy7&oUp@&1P}pM+ht4ByDYrbHcVnyq!7xaMRr{SfRV z3aO^v6T^7X)WZJtCm;uV9d-#9!`}Dnl|?1(YOT5ycJhxi@@B!Fw69epVLuJLD%dpD z%8t&}bP9G?C&5Ki&1y06?~t?S2qsDH z{JILBo;RLg8#y}-l8q^63XX*!rsK!>@%`e?uT$s`zX*3@44$ElZM(l0^J|X717mVe zxkN>NXw6B0whiakVgK&@dXmFOA}vEbx3-BQS5DCmEc+th<25P`^RGxuqIzFxswAB+ zKB{Tfy&~qW)p9dy`xh=4x?=unH3Hw*&-M1zIBLt$eU~k%hv;?#ws3rI&~V3dk1)I^ z3j>`+|Fu!T!ZU02cIG>e0-ix_gz-lKGsQ7tY-d6G*zMf&s%$E4r`=UO{pY_s;kg}0 z&nbG*tGvCgZ28Q({@pVUi4$fu9pB6y%-G1R=2=a%=J7c)a!j)rnb|y3?`Tfmf7FWF zG;tocb~H&JH?MH-=POnm`h5Sb4bhh;HCJ}u-jMh6M0(GwV|C!~y|W>@zf}56wvX*$ zM5l!2&2+I$GJ9TZ=OnrBSAQSpK8~X zKB7pwE3afk((Jcl)p2=I*Yj6iR9!hbJzBW8any@8jz*%-cV^GS&Srb8F4pwonqxcX zZ1*Ze^3qN(JtLhr;^C<%9Zg4=vb~TKu{z!-K73P|7{2F}&oV`_wc;Crvy#>4U2svd zt*@_lAc?KGB(6VCE?KuG)76#fN@A?viLI@^{(;%ant6-nEle&*%|AVL`hrEt>i$e` z2GwVF@`LblT1I<0wPy9AQ`hu&tnchj@*}r_p1$?T1*pEYwU>)}41tCG2tj!4rt=%I z-<26U_52!9Fm=-TlOyqh;=B^?DDRkPsdub5(>u;9%d5aKk%3L?20PZk9_&|kw|Rnh z+}X}gY~-HNxGkoJ<|UjeS=)^CF;7h>8hSGe&R>%qfW&x@y_xw(;K{?UVDplTyL$#R>#@R}AiPXNU@v(|| zcLPeFv&HtCy5QcL^2=!TtI~Y*jCn_}YVj>* z%zk{4&DSVrUzFjG{W}NzHr^YW2TK~faHZ+NUt4YzG{Z2)gqwkb9c~?_b9@UiT)tmS zxF5r_jmI4nrp*|Gw;2vLUN`XS;6^;U8@w;!*~V)IVXwEEbnq>1 z5j@*??I4nHGseX4B{clFA^>FNe6wt=_;fkb<_b6z?qo{eVfjj>Dc$A|*V~iX}OLjW;S?R#$pv0p;9DtN~ zrc56Pooj^06;XSHcPbL}Zbo=rki+37-H!!y}ybd%bRI1d5lMK zGYY@n@@VkLvyJWkUX1XVXMxF+rx_W>F8sKIaw_aQeF0Mn%7G)iuz%Al82%)OKS|;x zeLS|vz;J{Y#+xkVt9%i=UyT%#Rt4{0x62#WvwN zsf)^c7J?ADBO8ZM*YIURY@l$Jyqa9rlhMStu(jc zQ5uG?b`0>wUp;=SVB9ze(~REm;360*41~830)`$#sL>O?uW&wl8n@RF{$h%w8pck~ zTI9TBL8_}^om{=JI16e{ujRf%PNqMd$>D*U7$N8RXRO8{%Ub+dumFGXMLGV^?TnO# zK7KUlyZB>3ri~wP@iW5A`T=~smhS6coayb@WQQmxRK909NYo$FL)AkczBkQu^mlgi zLr7+Z62#NQ`y4V$^;j>I`wjkBQwNuOl<6}=V@vhbn_NO)oEhjG(8#Dl>_y{vS+KXE z{Q=sjaP8V&tKDy?Iz}s84V}CX z>kJrFoQX^_E2OrYTup{Y@^Y=5Pl12Aa=w`-p;c#Lubi_lc`sMay`|xmb8lIA<(xP4 za^;*0v|KqC?JtE^&L5cb|83=b=>#k1NZw6cIX_{ar&i9BM_xI9IxoC(j=JP=<@|4u zi(EPX$#*~b8GGgYX6O>*$~g^J&JRTAj=>gJ&fCTQ z%|}`}&)iL~_i#2aH zZ=dn+m>fc~JI~>6Jo9~%ll|`AJ2|}iZ@0gE0sg;jo{sKXu+^9;1-e_=zr&J7b%#QJ zeP+v{d&#-7J^*)Ht_yUo75z^;a_xvfA>52H;XVKd8?P5~!MI$#E9mFn966p^t0F@i zgXaN^cz7L2^AO~6&G$HOMOTp3V&ZrZ?`FQ&2DzCGKpXQ&8$tQzX}r8|g(Kf_oJ%l% z3H&DG2MFJ+LjUpq_>_vfMf#5>96G!g^SyE(Ss~gaSMvp9BlmBTsbFdM_>cQtml@ch2ZaT9TQl&OF1yuQh#pYcm4g-8>$)lI}CHM)-hveUV6A2M^_VEX;up#=Kx8S$0c*)T{f9`P(N| zKDi;UDcUY7qy5?Qp4i~Ed$7gchhOh0%R_iLr!Xh7H@aMu7qtWRJOc^5Zi5%8u0<*e z(^K|GW>4NPbGEu*KV!A$)moXOUb1#iWOf$2KZWU|(o?03S3PBaO2@o*cQs_QS~j~U zg7~X^W<0!nPc`Yk?p+IN+JJ&Gxru-+7QK-`SI!d$d(2eP-muVqppq-MD;0HFdlgEY z%2%W+4~L^Cn@fgz2B4fJ%;W?ZDr7pZ49`f%3n8vrBnJW)4)Dd-`b@9cCt-{}km=`U z5txpbK=BCY%;B&CUJic{$E+KBQ3FsX*0XL|cg-K)ziIqzye`m`GsfUGz`@2F10F{<#A93x9{t;R*J(a1X$)RFC>t+^ z;S%FRJlY2D8a&&09|g^~y)g#wDmd793E-Ldaok|=ZpX8Y_j%2OC5^%37Ojn!wBpCn zg~59m&o&Jl=%^08(Arx*q!Zr2a7=W5^Kj`4y13FhaE_U#;Ryw$=WALta@VFy(l1T(?Q?CXb zydf)o>{ATh7aY82L8o%y-R|IR0iJ2+$6I*ccJTfT+T<-^P5d5l@U~j%#bTfzzXOnC zJ2kVK2ms*Z8}s~cj$9t(>~PKV806^3#Dj9V%7fo{+2JN8z=Ns-iD&YRa=B)NRd7cd zvL@o2LBE?B;V#J4;Af0Uubl?+uA72#!$fK}o{7u!vOcnHn7qTIcnFUC-pm+-XJ}*F z?(fBn5Ye-YDGlYs8DE&so<1;~(S`XenZR(y7UsJ%xI%|-mpJohn!}$aXV!e@DZ`#K zFx-&~hnJA@L9Cebf#D8YSiV@wxBDXO`2xdlro!?i4!-?nV*HPGsN^R%K*`f46{n%z(FvlEGZ!nsfo+iWdNE0w;j~ZU(};#)U)WmBv3Z(EV~%Z*^aZ(vkfJ|!NQe$Lxr=1@lH+h=2GQ`;dt0?}wtu$8rTFn3WJbSeda`eTC5^#b49dp48J_8%qe%KScZcd(gyHd>#T zo}NBBeY_matlF+dHFX%(EJ`m(pMsIiXgwt(_@-!db7E&9z7P`S6>wL(oQa(r1?8n< zyJ;uWi9JfcAvHRBvlBZD4k&(7^1TrcyP{z!qVxB^V5G#`T5^q)v{Lqqdj`8#WOHsc z8MW=sc!`HXaTy1%N^nL+xb#c0a09|PPfAh$1l|lYmq+;(5hqRKApI*1{;Kw-*oKWU z@7TF;u*U;$VDQ25fLTwcAJR+lW4~&~UA1^l;b)A&TMP#q?-20NeMmfe-1T9&*?8Tc zIR-Jt;H`y&jaP_8F%v)9CVrdoY~x)6Iv3vc4qgfH*rzeQh^miw51wtjn>8PnG$wv` zg0kaRWyOzusfpjW@NDCK9<=>#HF!H5Jl?-*;>W($;63l)(I4Y)jKTX69PId=ZN-nc z2G8A_dR+5dyw@GP#TFj(+u%(`V(s+q(>z$xnE2&G$c|sLg~z$L!8<|YnL76rc)7-- z)sVBtqo;$m$1EVFamS<7i&txykT8$5OJ(1Z>j14$Xdu{@FG--u*;~j$2=JDgWQpe70q-DSsEXF~mQBAMx0CaE?|n6>4PCjV`0`zB zzyFnF_{zJ9M!aTlAV;_k5sVM?fSO~4M(e5{6}~@KFjDr7K_-g)2w4ppj1;icaG?!% zj!ON&ejJoA?_W~h{h@>QoBQJ*{h_j4c9r9EF6H9ri}c-`xe7;qXv)x;@Ldr{p|a28 zxcVfzV?53J$?-P(AiA?$#JbjIN)2JR3OW!3x(dk(+osL^K#oim50Pp}@j=u9pD z&g1bC)$#e`@nbQ&Gb@gHO|#nbnnVRh*iyf^`~qLa%g9V>iY-5`dsZE^j5jL%;l~gM(MOwRb^B6#DL1flD&`4!>BR08qlXuY zk!ZJf`%!XKpP#Olvj^|K+0s6Gd*OEP?#lMawk%dm^QBu}y4pHVS-S^-fAuS)Id9r@ zhR%)*HC-QBq7hmXLaMddE9BbiVH9{vetJ2QR%sC@~Cv}>T$IxVBhKt@#l1I~w zn~M8iyz=@#Y2CHTG!WQ)AJELj&mMnq{GWu|G5Ar2KaR88@Z);|!yjo@;crSm(=vE1 zc((C4US~H%Jo+_wSK-;l+X7m5S9l8W`tfYz)c`LEH{vl~2Jee_w(+)sW}j+|iQnho zVB@vv@h0)uw;H^Cc((C49_Bp87=uT58}BmUQI2>F-{Acm&o(%$Lr64fh&xBV;*Unw3GQZD&0OfFmIChF-=T2 z^Vp;nkK%DSoN7QoTaRS>#&&-%#_N3F2PRLJ3&(cK*d@UD7Rd2|;j%@s9D{aaTBnlW znV>L!Ov)#H0G4=Qct$8JAD8lh6kAAOs8=~GUnu1RH@gKg{?igBDAGvFmi` zji4!?!jJQXTO9tEHJ@e1`M|d|&79);_6wS3edYL{dnCkTJUHHGyElg68|@!TJ|T{= zDk%AC{N5Q{vFabjFfTfDmVyIY{YsUi+?=mr(fF?Pn~r~r%hxG`#PTyjxge8)Mx|Wg zs1X4rb4EaprLCw!J&^5W59kq$xmT9g#+vl1<05i6Zb?X2WEblN$JcCw5oBtTHeTXK z!!D}`_@v{YS&o#OtL2ig%TQSi4$Fmdbf+Ba5%JijNTX|#;jv{=jy2GP$1lz?1rTwJ z>rbLRTjQRhT1Gsni??IrU>`n1;9&#*TcQcZ^)>U~{W$}zN8TUTS27jJ#7d`p{=SFDA}NK$zx-9FquWw@qMPbY@m>VI7hnIJNBf8s*x%XX)GgChUx=<#_I>RC*vDOf zpNF3rnXJJxdBzyL<#4d^wgHd+iATQ%Z#|xEytSYihA{^3!*Ho^8BG zK~KZa7=y=kI~#AriXZ!KgZB`gZM^Sk9xQ1L-hH5KyjLwejs*$pm-UANaFDAhIhJ#ma;c@I^;`e=xmx3G3ukp(@k9!_+_B`%l z&}T{?>JLb1+svm*dCyArT(RiqFz!-yP zXk**%@5MZhaS04#7Z}dl!hF+Olnm!-VLn?%U^p)e^V#DBhV!s6pFK!mIPVJc?H-Qh zhJAuS98Y12^RBQ9TWnxBZwm9-0t3TuFT#AbsKD^PnlPU&Brv?6Cd_Az4-D_43G;&) zG^Kd|jBWVs1ZRG%1M~3XybeQc-w^8@pHjKuo^$GP_%}H89iWNNn!tJB0}lTQ&A&kM zV{+bSL>T_7hJa1_ZHG4dIxI=f8&9?>H08~=1S z5WiULbND|F@k_*SLiEw{+X0gV#_w3PQ9`KjO2vGu&62-7#GfhJ9sboJ{w#5u!&md( z4m~jnHm~$})(n;9q!33yoRjRFU`}vGUIVla=`p9;0Mf2)IbB16X~|$T9s;nO83!%w z9H+-5cQ6C3X}m--pO-7O`e1t{n57r5V%|7 zW~3jI^&LZkIRdkW`VK(O!0ds4NIt}{0uAN?A#uyu5)MxaLLR~__V%3nvsaB*YVB=R z!Q3A#5kCokV7RBp-kU)n>Qzo@2G?KZyi9^xCSKk?TZig7kooxKaRf1CY3b*eAY zRM9=NJ)!ppm26b%77u(tTipMSvv>`eex4K^f65IE)hpyU=cYa7IBo|HJDH6Ga%YWO zWor!1dA)sWI-siJFWwpZpEbwjd(@bSen1ln%`uuMsdq8oPke9j$F{o+KUQBes$=`J zMkC|)kuoHY>Wwn_6j`H2i z9XJR42jdAg!=j;W(nR`kL}))8IrlJgL#ByoHEF=3xEX~Y4+oHdF?fm!{@U*E#oQsh z3t@6kg~z!=m|q~*qJ#QiYMqgfIr1?nAB@OZa)II8B8<K!Jbv&4P$~r#1qt{OAwX7zRK9O!&hD9W_d14vsB)6)*_m_Z+u7OO z*)wO(%#eQwKk``z97A~qp%D2m;zvHqN8Omup%D3AHyj=vd~|$bdjIH9HY8#jIj0?l zR+7Fy-p3xTtV{DF3Rs=U%@yT`AIW)R8>F!{x}^FH0gtV&0OD97;xKP~y$G7&EH#W7 zEcWjtee`*q^xb!Q0V;*{Qii>T?*P+z$16zWGr)A#0ey~0t*B(@tItg%!feHC3}Jn- zZxGf(oAX@7E&c_|zUwQ|gD!-)JN2$9?4|MG!M@Q)CTymG>frFeH8{~+7z6G4Nd$gyWU4wnGBH+D zEZ4u9RRYhqFI-&=Ncck5m5_Nmvz{oM!85B=R-B!agG1HsC$aVDAXf3SHJ6pC=g|J@ zbX_s@Q?Nm!tNH6!n%+s{0{TlO-&?CQoeOs3K;gNB1n-MT z(B-?N@c5;b@=;IG*UN9H{&EZ64-DQPfXDWq_k-VK!TUXqHQoT??pukFBzW{=(&hV` z!lS(4%>$Um+ZT8U90}grh-tj}0O5UL`Pd&8Ji9g(bprB)1n+$~sm5zkc>Mkeo*fr> zEbuIz9T!-n@btI<=MU)X9j}8&yPGcGQiaFwwv_KVgEv(NkM?tow?g6Z6EApY4c?P= z@Xi>#H42aVnBZMDcu#?+^+dTJmki!I;Nic!zqHB<-roaW8`4O}@hj>paIGw;6q8N} ze@ckYrLRCgckYQTgs3BiDmiIpWuj0k5J;QF@-i9c&8Qh_?*C()A=a*0dpWVM5c8#V z^)ei1i1~cea$;W~=Ia)P*WYCLR`*|E__|lk{LO~Xn$3yh4DtEd0_4PThM3PcIwy`Z z#C-ik^877^&o?e7jx)shgOVIXIL;9B`9|c#afX<0#~spK7)M;Ai8a7ykav>f5Gg_- z^4jss`3*_8FcFf^b~@)b*7Zm8_?6`ICjSdj{-)%#;r}x5`6ST)?2m@;P9D-&p4(9v zmWRh2HEL%h5Yx7q_)w7dfyBE+26wvy+mxxj* zqV#w#p%Y?(NS(LBF_Re!G<=__E+bQ*b8S5zX^Bd6=P4*WUl z@ObHU`U^f^Jti||){NHQYAMRC!Aym?#m$VW#W z@0<6N5$ER!n*>$`NG_LCu9Hq+S}C}W(&VY+D7iQF?RDX*jXyoT*UdRvweiB~&L4I< zUr4cOWFr|^p+IIjmEkY>@1{c$!nu#W#xw7A{*|fwd&2#F^Wd?WM(0ymX?qi%l}&Bs zmzO{D%FF`iS$PxYKKT;!Z}YaF&n)`YLV9ARn8V>8X^{Fh57kHIVR*i5Od;klci zr(A=phvZbl+0shJFZ*lkYsBm*Y7uBc|Ta)WHZ+U89aCmegjL#YaijtN6Qsbr0l|Vi|Tpt9ja`*5sY%$Z-nnk`9 z6vTE6j&H58*2E$^N3bbvfV1|GSh9a&{LwiH;;b7dulfuOdO??Es!!FZE%; z`x%Zk-pRm2;7IT;BBt?1RQa@R=g*MSc&{SPa|sC^b#aX+>tXYH+4GX}Ee4pzqmEyM z_ihMjJg$c=^~Z0u;N55Nz6T!bMM%nbufaPEJmRo?cyuzn#|+*tz$?Og#NZuQc-pq} zC4+aR4j%g!`g%_&JnH*$y+1N|tjy!!3rSsm-{8FlyuA?O_40ZI?+t@@9C5*bSZ0s- zt-))?MauoqwjJr?NWIf{i_fQ!q~C%AurmA;i0B@?l;I8|N8c}=S4iaO!=>x5MU_w6 zcJ2yzZ2{oBz$>!tdJPf(b_zCeENeoqTGKNaIfWogp`fB`m9ef^n z4LEN`Yi>=F*HwbxWdh+qr~fa;f%y!we4eD%eXQQN@H!FCT1%0y9T(0-aWI#0U_8!> z^pnHD9g#gW!Ft}ehjX#!N{DNs?I^};g_o))zI&w_AJ#N*eL!2%Dkta1 zd1*`9rX*O~pEU8OgM24Kj6aR~eyB9E|@%$}#VffDQN#?kHhkAj? z?+<)_i#cvTYWPP?{OczEy@ z{x>52ZEl`1#2qpJ8-afu#|we-SCju;s*R!iQWIZi;`f{Qw2429ILqs=e@XHk!}qqS z(Q38oyC#|6gV$;^P1c!elyYC&gK-iYqm6#Nc_GiGIy^qV_kPF)uvyV4_jPhu18OBh z8ZtshqHlC;e|0MMpY>fE&vEt*j}UxYBUxzkwZ5`>2_o4%c~9QSvKOT|ETzg5b-HY} ztgBVPh&osWeBG_GHzvoeElrGD%fB|R?xYnI%yi?5%4RxmMIcth6g2A9+59onIz~V~skV_F65U z?>K#Z*>03q23y=3ukTb~tE2u`flZG6fJz(NAB3>kEo0ab<`b_C>!hbh1hv8!nBSTT zlrG{{@L}LrkL$3LT7xo{`3NK3l>_-G-wK;v6z?+eo?!di+o7^GNschS9=>}B%PIbVTDSWUb}ZlI!FNLzV$W=g z*sr>19rm>y|G96|60A1h{gCHxFD+X#IS;FhHg?e>=G_XherW&lgB$$5i7B@8lT}Ca zeGs$#2pi8dU_ZmPPPXN2hJ$rTJ(lNttn_RtKNBTD*PDOl%zOK8-M;i7S4lc|>iAnH zt|k@Q`xaj<-MZ-f$I_FjUmfZFXE&vNSG!83W#!A94PJKk!L)Bi)@{1+ZGAocy?ctx zN=z>{=(!xzz9p!!zmds?edJL4{re`TAA;l7)V@(`CNom?*&TBNaZ+_a4orqGz5Ar^ z7@Qh>0@f}%g^y16j8(JCxS{M{TAOE^Mndx%^>-Vae7nWAi!%JN{Y3NR^sokmq#gLB zJP0Isn-JIi=TzY_ui)*&G4(pZo5V3hGZMT{Aw}bLLWt#I`4|eG=>3BC8Sqm4gaps} zHg&1;@%tip-@>sj-&YV%@e>lfmyn>#w_D-ydIawxjy2vn#8do)1n&Y8G~T4b)Ap}F zK~CdcLOjJ!Nbs&8LE{}&c>KOe`Rv-J{{)ZsTuAWj+NLLfmqLj5gWqGpYeV69e?(p1 zggE|ZB*$DcpU3zdI-*>W9c4SxfyKwf5q)~*Vn^W|9PY&@B!>*kl8A6O<^{Cj1nke^ z6YH*n^~1W8YrtW06c5SM0)n_YBs(LW{@<{p@L9@fzFXy%krXyhB6Jnx^U{D^VdRbu>#!RMQl6MbxA`6eSDb7^;pQx+I`z6m+e4in2a8+qQz zoM@Mct$YwPjXJQ(?|;MYYB16=Va|RaAa3RI}Yt0%*%T~JH`hUpQYPi;twEB z`4m6eG4>!7qWlDYAwn z21H@htwF$LV zawabwaLFNY=8095EK7l6;(IEtpADynFsA|MciIc&eHY5=D+V#rQamCcTxtP?*H$z{ zp^g$thBa3QHnKJz!o0PB-QT-|OS)f$NXBRy0(w= zEZK&XVYcJ*O}`1g>719z=alJuvL&5y$NxaicllP=rn`Iv=}sOGzr}I#NN32t9g5=m NcK0&u@b4zi|1Z2zJ)!^r literal 0 HcmV?d00001 diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG12/librail_efr32xg12_iar_release.a b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/TOOLCHAIN_IAR/TARGET_EFR32MG12/librail_efr32xg12_iar_release.a new file mode 100644 index 0000000000000000000000000000000000000000..d5526f106dc90d9965f0b3082f751f213994ff1d GIT binary patch literal 545938 zcmeFa4`5W)l|O#pn~)g-Lii&hB1`}^D3Ct{1Z#CBe})7D#7R)PS~HW$gc+G+hM5T_ z6g40!P;0Tjw_B}ty8%&A`*nVwbN{@# z@680_wqd{f+dOzV_uO;tx##|U_uV<~o{Fo(=}7FFvMR6rs;OJEwx+tSc5RK=F;zb%9)Gq zKmY0Y-X{()m*XxuKf(Tgd;jE3RzmmN51q4nQbRMFxc}d*gVO81z~1qF$J?w_zaOk; zrN!=VeUp`*>3+G5mHwW$`=V*A=>4wynEPyZxQDq%yYIP_x!>u1=p=LN_xFFw-2avP zcV*1|4sOpC-RumvfAf~M*49pc|3G^*n~nEv&9sGElgU(9II@iuAtn+|YD2QGC%&~m z9aZdz*bz-!ifaso)PiuqS^Yv zY&7HF5soLqU5Tg_-JS|ZqK@d6zIawJ1f${Z`u?7tXj!KeBCfF&a4-we-D|OSC<_BZ@AKevEFZ z;-d5_VnbTveTb|D+g6n|)sDy+p<=ornkp%}y+7I)8O-xSr**NN+Q_t|NQyQrEmD6< z37`=d9I&ut%0fDzVt4X3Rnm@hxG$4HxiDx^;FiAb=m1McTGFV(#&9;wg8s&qO`WY9 z{hg6;Vq;r48)I$$&g$;2UNL^Dgovmui1D{IG{!T0{DKawsZSyG;lA$nXd)WnN$bPe z=J?iFu)mK4HFWg%MWxUU;ek#4*;IeFEqPlsEhDuU>Iz7r#YmpEXn0#=G>Z(9X-&2s z-I}~j=E#Ky(#c+Q&3Fp)4wOs8BhgGlvbQ(chl+?$E}X43x+9v{l*-0?F(24tRo0~H zhGcitRy{oNrk9Dw7xJDzz+#x0S(3Rl;~@D{R8e zsc!TPp{48ys0coswl?&q)6u>xO4^U^Lqlh4V>A;_N4u4#Y-?Lsrfmyu>S)=}6zpth zpdzAkrLy$=aK^V}L?`JkponLPlfONSheW@$@DBYoLTc!>8TlDBmv^=c8*zEzg? zNGysbj|K;<(XF(|lblVUD21&6jqR1`D6YK(9h)|H@D5}vy%p<7tHtZxWOJq?X)kcT zrEW}zQycmd*?0=ej!d#Ads{di!-ChP8lX`_gTEt|j%H%X1Rio(S*(WE>uhD9S)LxaSc1fp-HIvMi-#SC zR(-g?n=gTcR6K|%zGL+Gcs58YCI@@_U~gA4VWZH>U9vSs@I<#)HIK6C*%<9jcJnD< zQ(tf(gRUKkHT7lFgN}rwvDt*71^7}>G?-L_uMp97v*~04PmoAjtRY*p$}3FsD4{x%|01qZN1iu1LQ zSWwIO_ULv^AXM>hjWk5U7?k1OjK!11Vj_@CZ;fX8@;D#g5Nx32^p+$v=on~5hrtrT zUa?lRts-xTB=J&0O9eZ3K3=kCqT4sbGZ6-8J&X~?M2VL@1ZY;vWU=zdNQ|Cah`%A8 z&i02Bs1_CsbTqYhbk;}HO}(k?AX+DaLW!jT|ctl<|j$(a;mlFq% zj`D@H(g2GO(7MoT(C5&YQCjv9-o7m^-y?OTHQJNqR9dI(c%HT=qR|use@Am?LyTV4(U<5st)jwxebEGs zSs5Wlsz4eW8XJPqEP7)@Vq2akAFcYilU??686Dpm#4{T2Y9z^##746vYw4j1%&Xdx zsZG_bLwyLT*X`&dI!(f;7v2f&qKh!t8$LaUxp z2}!+FniN4IWs2mRCpuD$TC0>o5N#=x`dW2%45-MW87m@*2?m1xjg8cc+R{nhEig{H zlf6126YcM&;bV{HPZ?U(BvXTmyFD81E-r^tbV2KyHZ}!Yu(-t9S}sY|T+MV^L%0u5 zh=lV#Uy7&Yd)QbaYwv>1(L@Rptxb+(qc_Mike%IH?2rcsMoof6Rbe(A17bVQPD)32 z#FPCQF_+j#cttBxbb4_ct<-!LXu+GLT~0KEwf&h!8ehMPLKVqTJjAtCm|irsFQTf% zmb0Dcs1!`={%o>09%;pM+MY~NHuupp+(A=CaYn0tV4o#0^|VBz(bi<&)?$N6lH0<4 zE!|Fml&(F7<$lqGa(~)Z7h*ZBN73^p-87J*T}7LGPC&mRNSiVRiSnCp1th-EFHFH- zU2M$O1{YG`C56L47qfS;$4tG zb2+Kg)~)IX^D`|av{PlKg#ItF{ z*s8+sB=mkxzqa7HOJ&BYgx(VL(l$oB`nS@elP_Rtk1`#{YZhlOc*5{lbPRu9y5K~d z{V7km$sS~J&`%En5d%^@(}XgP#%W6?5(SxPZ>vH~aDeg^TM)<(b$~4bYj;TSAX0QN zEdB8e=OsWKb?rQ2DaLzmLB@EAq+K3lCXyhRhD3Ac7h0!SFOZc# zxp4Mi4}bj=X(d7%RHVP$`=vKxj$8XnR?d86Vxbd>(#8hT@CY@A^D*`W`Qe)9KpkK$ z){J)se}6WKC6ka!YbSfO-0{&_twEtjs_w4GX+2qwZcSQ0CEM}}4z%Fca_rEfLUjJ% zfY`TpL}D!TQ!DDM9ixcoC?=v~pqL13;$tgN{L*ccePcMD#SBwWMHG*|WhdoFh#Y@h zOFReoudkTr__9UF*J9~MGZ9ITebte8T3PG%b%SCSTgiCgiuWY75nxXk4Bw`H8WMSk zHY+Mok%|dav_g6GOSDaCbVS>5;tC6@fn zQ;M@qpjNDSZYc4iv=x%;uRBr~@xGXhBopnaXe8bfk2J*i4=fG!d3kNwIK2%LS3a_M z(;}DP0R2Xs>{FeGN99)#T6FPd20xax){4X8rz$M$t-NMYefioXzJ?n+u(iv#BxOM< zR_<^XP~^iy)F)PAc5&F~w5RA8pwUm$q^u20YmOEt(~f+L^X+fhM|$`RYg;&zVLjL_ zkK&j5YAaO3Qrl2}{w^#XG0k$MG1(Vw+L0AVAl-{iQ4vPC$X+2c(?|c48B$~?drHASRd7}Lx zmyfrNyL`0sQJ1GsGv=Qe`FL$PBR53l9Amw7qo3BNkvf9kl;!FU1~NsscoE1Vh%a$? zFU#ixDf$~mk>q&8Xhv^A?;ypJ!mtCsfb`=nQ5y@k%x$kJalE&P9fi(F zG8QEp2L$LxrOvJ}ewsfEy%UQ#JI^Rdt!SP?C|=*%gnd-rTiXZwA~&MMs2f>a5O0j( zM+P!2&|(wOnhjkk{^PL}l8Dw8#56|Z`3FONLi|L4LD5;e!B)D$D6Sqw>y_ZZEuJ0F zFWnWdDHK|i;!IaW8JW&b5mkoOCB0nHgIUe~G78n>jKWC63bOF+LPj+W;O9T|Tw1a6 zHL~a{HWV2-7^wM3yM8c@gGQh$RT=ZOIqKA zLxOm3h^8}m@=zZ1yJaVqd0gv;uFl{9AJL=(Eo;E-jLd6|-4^PhqQKU}n=4}(fCwVg z&>nZhL0dKX#8}vpNt9J+i6favZ#^eOQa%;l7|+J6C#Z_2k-@3?bRr7I9pbeCyUMT~ z6HgtHN<>J8mW>^jbs@dSlc5Gr=^&^H6e5aJR8bs6n%;yWcx;HpGbsT?PJAjIMQK_V zzTQwW6|2>xjI!o^jZK@}wOIW%MvK2vtVN;KUHHO8t38RUJ^&O%^lz)O_16>)aXis`&?ZDQW+D@#L zS0t;-_+v_2R;7D7W8nl*w8(rau?`_?kYu_O3vNpUElTof2^&MANPfS=64V_JZ|#GT zLp)+d0$MJATXrnBKLga&&Blz0RdzF4HP74dL-MLOGypW6~_MV3tdDXMcvPqZ^e z+XiXY+1c3IQs3Fu6zpgYHu)P1B070jEn1(aZKLLD;6<5ms!U|LRY3xzprB()|?C)*#a`tWD^ECQ#8+|4l27akVf6+#t z&0Yt7wMNf5a1%72MlVCSQNw2<+^pdjA>69rOAv0;@Z|`1X!vS`w`lma2;Z#XBs-+x z*CX7m;eUj1Ov57xCp0`Cruv-2>pve?%HC)365Y+H{Q1kx?z7Q7?9XiYWcHYb&qTs+ zIq>IzQ=Lo&Z6@0Lb%foxXG{Eild<<8`~`_$3cMHepv0Si1Lb{$(g%TGhKMD=IX;}&5xx1gWO`dBg)fsbH#ZGLBiO7?FR#8i(~qA^Z%)DBqz50I+?*y; zHT=bj92=}RM`H2R&3t;gIo)$J4dG-T0Jb~^ZdQ{^1jCaCaApveiM^R6OE9!ycrC{E zYTKx+sbNbn+-Zb$uC!C?WHg{QjBAjdbFZ>TuaVJq@wL@5`bxH>TLu;9T8Y;v9_S)O z*VL*2RN|S{C}nDpt%y;2)Lf}zl;9dj)-J_ysYHHTjU0HSG z%33eFl^4@2Ti)0d2(GN%vaY6fOJH+rt9SWwdVqDJ1E$h24|#W6xO!DJVs8tlY40G@ z36u6t>`W!o8N||_Ot|meiFh`fhW^`KH)T z@A8%vRaIehay-v%NEIIE6tSWT{~I>6x3pKa^hFZ=-4H2b8}Vy>BwE!T$LBT4zSeM8 zW;x#^!{>EXybv2uh_-@c(OwLhs(4?-5)|$2PVcA^D}jPY8cRjEv)BQMs`x5ORTWO9 zPz5qjMS~L$t88HmF?L4cMF`QISj-fON9ACf@m83>Xv8R@y8E#+SS+q8Ish|VY643i zi(k>I&MdYn4&!D1VNFpX7WHgm_|g;$h2>YSTw7F<&M;F z3tPKtbtf6vV*5YZeP*#X*0W`h9^lsV^a5H`szxsmr42AS*sAysb9jEJRjrUI7z>D1 zupQhQ;Uh+k*3o#Xu%e4%YjZ5}6mM0s>((>#W3E0cgOWC8#!<5^Rs=a8Rdw~p6QWt^ zsmt@CKoze?2U?ZxDU88HLvzZg1kmZhJvtp9HN;a{G1cU=MqW~~nmViO#O|bMKYMJt zhkn3F;)kdr8Rm&qU3@;rWHMTE&H)W*tM2TgB%`P`yuQ8j6k?tni#Ap!E60?}D3$N1 zi%}}MfGgYIb>>{0hf&MA`Tnkm#H&A+l3qh!3nq{glX)W8=t^nFut@kN?R)Fud` zl8ViKMOXxL7(cUSGIC>a)Ex7IMF@EnpFBs+2S4cNA4FoXa8a2mOYh>38iz!|B(y-s z<}W#CQ9C~r#>^<>iy!Op-cUSU;qy}Hif3C!9xpOlLLt9PE{C;&X-S|!XQE52p+{v% ziPhDp^vqyiHdb5-RG#>)zBrlZKdOR)il=OMw)YI_X+y3z(|Kkwk_lS|XOLv0Vi6!` zS#5EWf0kqIASN6NRKe6DDkmTfM+?#CoIFSDxGE?*W*(zgoP=opRH7dncbp`G{H19* zUzw)G%xPPkD5MIzu_BdRx>Py(BfWcd_lt&>;i^cF$W+6v2MiZhj3DZy7)3l<6eTq% zLwL2b3CpC#qKjIW6DUxX!8UQ9=w}?K>5RT5>XcIQoOw!*DiBZ6pN%I(i)52YJyf-o zjPrVu-sMT}XiNRtDlDhfYMB%F-Rl_A3$3k`WILz_-vb3Rm# z+&%bpBiBqZJ5wZS$UA`WP--BwCdMZH?uTn)zLHZv^dL>Smo)W(ULEs}lrSG;REMDL zy}4#1<{$BGH$t06hIn~W>+)qoxH;Eigp3M5(Zl{|2|}rLPx?HKPy0N9qky=5tlH!I zer|W}=4u`nC}Bek;l|m1PvBYi5Hl-h9&_O?!ChLp@R+Bv{McmNQ*oE$o{4)d?is^| zH?_{h?ZWNGU50xa?&-Ma;l2nrqZ`*GgO$uRne`vI=`|VtBZPm2e`)_chs(vxUDIZs zhh1Q|;WphaPl;!er_|&2cs!FmWu7VSsh(->A=ACvbnh|UcbV?Jru%NweUItB*YxZ& zJ^M}10n_t-({rEc`GD!U-}HRYyogki7v)nwYvaKa<6NjdA|`tlv#o;ZGtZR zp$m|@q&(zB+u!xG2KIXHcHdKa@1%Vt`&|cA z^|)pApf1K!9onH+7wyi6aGR)i-ZZGfbCoyg!SkLX^G0)>tGucE@Vw8Hc|)0Vl{fw3 z!SkLk^F}xHzYCG!Xt*oRj2Z+Ru;W~f(;BVaU{-pbd&6Y2tn@r%hB4EeYg}l|b6sT2 zcP%n#2;ecr3>q7zSz>t1GIN?S+n@?ATP*r|8OBT<;TRj&08W{PpSK8NV6CTkjENB8 z5Yj~uzwuCqm@g#m{*pXEp}; z6lh65-%-9^g2L*D|0RT@lTIRt4ui46$2G@=$ z;*$mXGh>hq7WzGkp^q_!vQVASZ&GM?#!v<%;gboUXHW({&p>yoOPXAelus^5Dkm2T z8PWxY6*FJApT0p2f(lIq7D^}B2;)C!jxR8 zejI%Ir9^K*^tQCezWH5N#}XK|}Oiy-^d#o{M#3hUQTf#~wS48DViBY8CS(M9s; z_Yljx1x7BGh0B%2EnI5Wtf^khjbYAi;qvQu^K2{&m-VFif6>CF3m*|UeittI5x5}Y ze}I`w995KW&l5QstI7<)M9b5-x)%3~xC#FRAWd#Q00S-jML?g19|g`E84XSJ?*XNG zmc}%t{}({YkNP~}Cjl4ZMt9>lnNZL(i{?)QGYdUKsh=qP3aPBZ^Cm9T&r4Z@q$3IN z=`5(>)RQ*@SL2QF_iA((o_=IPvWOD%tCVGJ^x5n#8}4TNH5>*Y1!g67x`%y8<9DHc z>~tqy#y$pqTEB>^ls#liKZku0xNZjYxQ#xSo2}&QsFWSE(dV&$1^z25u9UrKg{l7L zbF-F3G-&ySnZODYeF2*eyxWQ^rMENdaxpJ2-(D*YW-gF_pN3zC@Y5PzZG}nxBA))2 zR-8!x8x6k};U(5Wp_DaSG)ljO-3a_DjUKYmFJ(#K>oxj-jb6#_1)kRE2W|Ar*`EW? zYV^<9=*!qwfDdT&qc-{q_I=>HH2P0%^lJ73@PitC#73`WIp81B=pHLf<*#EG0Ds(y zD`j3QO!U>P3iwGYu9U5@!bD%g)&YOhiYsMpR+#8lu}=pVDueeAQq>ohuz7ae~D^fem&3E)?2_*1}Xep34VBk)EI{~_>Z4gVM5 zts4F-;B6ZIpTIjb{50?_8g3wbvxb);9MbSv2zP7ve1u~fehI<}4PSw9O2e;2IIH1Q zwgC-qL3o#j2N539@S70ctKp=}J`L|h_&yEaf$%{MzZ2mPYdEF-n1(-q@PiuurwBi! z;eUbfr#1X<5dNHoKW2rgf8oPOw6{)w8gxpd+Vi_snD`snKLh`%6$dj-q}TC(w`jya z#WDX*VXxchQ&|~*@e;YY#9I{WN1M|{&#y%qoz{h`9QZm1eyaoD3w$xga6QtJ8Q_D! z-v#;Q68}5kmjI_V9nqf!{%(}%^Ai6d@NXb}NaDW)&M(Bx!1LuK@XJspDi)=mhAI3l z$fGqF;g{r~{lFgp4#4R_1kOidDjV@9fnNcfp2>vY4g3}GEBry=9|gWh(!U7& zcHs2PCH|wp|4P&6-+=!u@XICrH1HQtzN;l(h8NvIqz4O6zZ7@|IEu&dYk^+}yi(%r zz@u7ybOWcf5Q+LIV}royB7JAzdA(oaRNpfwcHGS_`HFWmn@jD$dT{_d4vK8XuX)z7 zqrm}jScLp6pYv;{q>Dt>SNrvw+wob)Rywu;mf39M4LCiDe~u)-6vA;au+*o6w|T7i zEQKP&>P&q6G%C-`rxV^_|DBJB@^iMk^AX(C(r(cS15C?c6qc8oon?)(zXa5x$pjQ@ zZD9b40I2w@j6VxaHHCF266rE5^G}$F>hYElC~Q3Sc%@2>-KKS=Wol|SYF%j=oZ78g zS6cbnD`BOTue}OZTKU@Rpw7zIUfw#DFIAGJf1S#=)?VH^l`q+}>ijC-T6=j{seEhg z9j;Q6srK~BQI)^i-WgUam8e$j2F|dgc7Cw|n`&nif0@MyY1kBO z!Ut^l0Jj0>LdPRGSyn_1#Ish6m{j;zQVnN3a<|xlxY{I$!`t)o3y+5dwc`W~747); zjYsp3oOp;PKz-6w-Y=A&3qdO;T5(Qz?I`e-qCI)={U&VNc~xt%_=Zfx{oYG1)ZP(g}-oWu8wq@=gow;zpOFGTLp%?AB7n zMO!J(V#Z81rcSeXVP$rd@J4XKCuu6P~5P zZ3)lb>>B%78{aZTKXaKaHfwsZSI>mSIt)CEn72<@ti$+v!eSl9&(cO8PZ+Y~9o>>! zF-%yjV?6Pyny^^6KbVyDIZWFv!v7YFb-urzJfpcfXZgKt)wz^+Xs9lf8{JCXs9+-t z%?Es)r%SxP$@Qnb<*9Z1neno(oSoR~W3kk_^2bWJeY)W-8ChuTBhK=!$^O%eSovYH zMF*b3J#@PFi9W!GaJS(O885Mtkb74T?8)CV{YTXUN8M9@bY4XzmsNS_+0*RcBQX{m zT4xMDgK%ilB=Gp$=8qnU4IwtojZ=(^a54k>mVS~S``tX{^n3o;&y_W0GwO$ce6mV4- zUdokXuLz*rsYP>L70ilrEr#`cXwh6&Ve&X|w82IRvHN(eOK_?bQko&TjS4}}wTz%9 z9^w}Fh-sl5Jv=2W=|Le&e2P2#Vy*9sC-GBM?Clq*4HXYr@OwgRQLcG!s3P!G==wv~ zpI%hG_|Vs5#*z>F7B_r76r5jj`KccqezDx=@xJ}SjK^}#?Bh?xa;-Cb>;d+11K$LE z@-!>|wwwMoAIUYhxN|M*W6ei=DBYfym}{PIQK&35*C%wDaoBtUz35B1>)6Y_64%Qm zP*d1dYyr;RK2gvavtrUioQ-;b9+348uA%CCKUF8eGlQom>YVGS}?bsRm>PNkb7CE zEK**9Z#?i#h3NzBNb0dYkCX&rJg38_S=*-9a;dxPrya{}tlqahcKJM`QS`-J%c>zM zJLU~l26h}S3m5?dxtDVZCBsIAkkY;2p+{Ne>&Isu9(qjl&yva^|Ivn{)6K)gk6sWv zigGhH^lxmKJsmV10l$~^(xjktaIMUy3%rx9MdeSiU0R)!GbCCvvK?f~&sBJOeA zLy+?uq@P?iZSr}zUql>m&a(yK7$h_Tnp|Ts6IDJzrS%Rm??b8b!zGI<0zzN!zN4>r zn0KiBFy$aF=QkQ2{_%#(3sWKMOOC1ZB}Zww$?zY)^NK*ZX&CgKhlv!3BsrYVDB<6I zh`-u5ATIqg5%qD1{8GdY^52c*Wt$>3*H&;t3&MoHP(%Obgd>y~|H+PbygoT0yEt{x z@981jCJec|2`ZymKm#~_`p2*BxM0}Lf8xeZ+dMrCtGO+B8U21P__(b%4Dh&J9A+r8 z#iO6X`F9-mGR&X27RYZ)@LT((gnRjCB=~V(ep>>0RTK|;Ey10zg&>IZYX}a&u7Thn z>=y_kA8yySNZ1#Wp62@8xLf%G#$b1vQ55f+I;N{Yu6^6%uMEDBE zZX&o#)DNr1cLs#NkFg$tP;M*1`=wni)pi2!4R8%wQ@-Dsa8I zJu}h|5svuX1i^O?LBylTywLjy-p5Hie~`GL1+s+E4eV$L!qDMQ2;RlmpAtl+a2rbq zd5Cc6^%n%8*QW{k82b#tJ;DZr46gr{@B`wgDKaGaBH>WxO9VlGj36ra%LJk9KM(}{ zNrC~!`1st**i(d~p1w{HmH#xsA;ym)qxfeDU(eV-61^Q;wjQyA(_yEwZTc_Dl1@Mfg z3g|u7^&&z=KD{!Nv)I$$_~y5s`S!El^N;dn*2Pj=lwv%!CBtBK%|XCF>-N2_yH%B8 z`r)m%V0@LJmQvT}5%AC2C6qARsG`0XLY!G4b@7g`E_0EWx~@h*_Mn@fh|puP)ML^3 z>Y?{!OenlzRI^+nRai2}qiI5*(*iO2;QDpO#k>2hbw`{{CFxc4;iZqbqytU?Jc?6bq~fJ24M&>reA8} z8(&TIq31!qJnsgXH=a!6Sqn7Rs*7qwK8#TrAz)^c)S_{GwZNLyy0DHF9U_E)xlSs8 z75sQsgWd!s$d~7hS2Era@s@C|^0u1)I+^$SbCih3a~|>ieV$ zc){{xQc_>h<5~EQzM@}dT!0k(JNoGe>+ z+r-=W>g&aU#;b#j-9UWp;w`!iLLLH6@GmL8L%fZy-i)u22nX{&5xkMH=ZNoKe1$|f zI+NGHn|eQ9>;b2|2l)~FBXQVtnG1ynPH;fN`z8Dc!2!k(awhnf690mPj{;7)iLt*Y zcr#;13BDI^y+j{m>=}Y(jD3gVZ-IUUJMmUa@zC!VfUA;>{SvTeCu6^%c+}4b;FJ)) zk|K!md$C05ft)3PgkMfDj12{XU8qNb5tNG{2GK19qj-@fi1I!w;iV`e;a5wzks$QB z0kCWbzMLiaLF^|JyiIBHd@{pFGs1o-rDUv_UhMU_c)7(kwre zUN6sKz>tK>eB9ynobQ4`b&LzSQHP=EB^*Psf*`uyB7zutiwR=rEg^`ZcL_lZy-Nvh zksEpFYL$dzs4XRU6E8BpX2S$m6t$4G$VqWahQ zzKRCoeZj#;^+$ZXe**pheDqWE=M0jv39lv;)?8B1rOnka}XW|=DM95UZV)+)6 zhc0g`FX^XbkcujduFd&WoBSR4^h?zly5N}jGLlcpAbHO#M1yxZ_&$sQkkIHVcn|?T zC#VPv5GpU}%f~(-wZp@>b-r@&eGW{-Hw`yk#OKWSaSX7r?DgCgV;8!vI_Ki{ADNP=R=&15aR*p@-6!?^W z=(3~A8ycg$-)Qox&mix2W0V)e16}EdqK~TI0Qkl-KK?_Khv2C4{x66-C0z#xf$07D zwpDrk_}T{aV(oh`_{P#-UeV<7wb3Z@T*yqVTh654Aox`M@wL?`^7eyoyDmtEo#lN~ zlSj{bx{8&z3=4*_ly?XClz!I;aYg0bGe&tQHF>@>$TLy7W6`eKjC zfwTTjX!060d5Arkl0U{1 zqFw)jur99xjY_Y@w0>!pd?c?d-qQ(Zy!msRtW%rT6hF0Tb@ggc=sNqUO?Bt`aR`iKdvKz22I>6$i7Dj{bIQ3K!@=^FhO>< z(T+?gcIp6kQ$;SM>>c3u^5oPK==3+@_yp<553jQmK9nYWC<*6II5HbYkaM3)6F!t= zJxqL&I^jd9=!duyK9umOPvK{zXa2fQ`v!E(jMk?g?>xm>K2y}Ru`)T!2Z}Pu**{Gb z-^e`oP2m6`Y=HUE9jnHyRA;8T3pY_;22ntJqvXK8R-!m~HK#y;^ys?C`iec@K* zyU__BN|}ta&x@+EoE-6~M0_AP;X^5dXHN0@!n0_?hZ6556F!uZi3uM{RexX~N@}<4 zjNhcHU5?+^gOZf<4!=uPDvthTD)~=3zje;0=96ucE`fI-w&m&5ZA0bwZgbO!cTTtX zR?>SqbZL(WuZ>M@-e0=qNNLXw&zE0in@%2oBWAohR5SVFH$tppZRjXcPa>a0yV;Rb z@GaEr_xJ$$HYj~*g)gwSV2f$IzNMm{?A1kES?|Ps&s6!#Jj@7wKMSl2kukTxnt?#x z0&BM61zra6%OnJ_UFydQTO<(Lm{Z08L?ga`q=4gsXqy2<4)`(Ll$L08(MIEtr z&SR1N{)i7#*yAsV_=9cwV<_t< zak3TI>7X5Gd!#?OVMREbO~`CSmTQRnlBSiID3Xk^F0UDn3 z;fq@OWYW6mr-VPTFbb5ik7+plRPg6Ee5&oI0_yLFK&KulE;oBZ1p&$T0?Gfp6(@db z_=1K%gYYjj{FoJ{^fTDM0{@j2=VmWhVWQ7suK}l9TyFNZ3Ie(?ubhVpnqyUxo1Jfk ziGBeivoEp+6_=YWv%*Bbki84|_pCTKYqY{dzlgO1U#6xC)W^*>`o(M;@b77KyDy1_ z+?PbDHN850M^vy+Abp)i|Flj1V)l2y^S%e%>`5E_5=OJNx?C{!`!^e2$xZ+t(&Uo` ztGZmUcbp8}zo5})T4kZ~FT=SBD4&{QQGT*?RhJ9Kfop;PSfi8WtGZk;7Q7z#FE#of z+32+_4t&WZmBP)^HhLY~4g7C3`T-k#HTyX5$2Iz=Z1gqk5b$qm^uM>!uVUW@zC}%g zDBnNX=vTAnf&W;ezht9d!`=Y?3yp610Ys5p%*SS+Zt1*pak=?;(eZhp|4ySXrnayi zGw83tOEi2HaF2#x1AMB6lP`yI4Q~TJTf^T2e6EI*h4Fk1-v->P;neq*XgHnoUa8?^ zalA~!$=5@*hLZ(yorXUQe2s>G9{AN7{&&EA8vZ2kMh*W4@MaDF9`IHT{|WFm4Ic*H zq2a#UD;JY-u z0r-%Hw*ud*;hTZ))9_n>->2bQfvbyrE6`l5)5+I^y6C51`}4uW?zPb;vyacF4Xa9TnCRKtn?We5JY124D6zA)8x z`f|9&L2q^7oen(Vz;`+D`yBYEG@MplE6XpLp@SkA((+Z66?*ji<;I!f+ z{1?DqK$y}J{wi>q!s(ezI3DTjb%ebVC*KbjfZ@{;zYO@dkmf@YUk!XY=B!Uid_8dT zm*JE6jleGf|2~PQfd2#J(HevD+XAE}nn-qq6R;rY7)(XEV}sRIF0=VY{`$7EV4}eD_l_tAZWeFFZws@5%4v@FSt4vV}J>EL5-|1&TWm{t} zs&#ZfmD#b5rbGOlQTD=EXZhFItHe6dpQ=nNrFE`9d8W|g)q(m{mwLQ9P~YK=!8+;R z;f=vM@898#!8-Nd>5W0<>-5H8*ULYVGBO4&NZ!_w1WmYffcu4DdwUCOf6vB_=FWx~IbDeNZAG+-O7``{w@Rd?CyumH1*9#M_7s#!{S#6z!IoyPy+k~Op z=*Ex}t{1Rw7bn4|quF?Gw78uUe!`4*rNgwy7t9l`7baXU2s>EbAIL&Zbd0WOx_B2- z3=^&wCR{Hhy8E+Lx`zecW&St2UQlKtXEt;bwj{r|`vsZVJ2iBZmMo(ix(z+XDw~cO z12dP_{{YSj%IgQpQhNs0r=A)(kTM6KP1O&UZQnC!9x@iK-~JSb2ez9#34eBb{m!zq zIWYI~=|A7Ii*ux(+I1jp-u`U5;r2bZH@svnIZ>NLpy|Q@ zeI+~oHs^VE|NHl|4;|QPR#3bN*Ak~UAw{Y*a3HWI_CVlc0mdmMfz*QY0-Hv1?{XdU zEifuee|Etzr6}b`;m;hd=CJ&PG2L_ImO$yTvQN|pS^{l6R`9UlTOd(LV;B9Ef77X* zX||YTu*Dy*$IizEE|ZQ? z3Cm(f@nbw4;J-$?%P^NA-fJE|K45xX!>(luj?Wl$dD{nO4p2^$0_P*`Z0@8&xWph? zQ#o!fa~P(1#8D88*C z{8!t;;dtM};X{4ThihULUEnOA91C|Dw?5qEzxDa9-M3amzIJOkGSvG}gygZ`4AV~6zlPNLf#lov>BPs%*r>8 z>)bieh_50xd73dY-Eb{+AEz{Bu|*>zX8p*pSr#%X5aXR;$t*ui(#j$2&EqL@V8Y#r z7_k{X|HzQve`>DZ2*GIr#X=M4L+RP>uz~hHty;iq+=^HqZfb=T?$G`z`(6H1q3iu4 z*BAzBdh&UbC;3m!2L7bs?=pIgkvsh}8jNUey%F0#dB5Qw`K%#wBBvebkPj5H6J>Jhz`KqbjyfN>oJKKCCKIWy8@;HhI-Agdn zG8r{ITZ9R3Chb2o@U>Uw82*>cFl0lw*h zflmYifjxmqmkIY8lxF6UrEqT{M${wqPaY`^fHPHg*-rtyGpj**VVY~ zJ6(IX-534Zwp=UbngspzC$10ePW-IL=slVso%r2ipr`n_W15=7n-E;HQy$;kkjGcT;2s2U4dQ)p88Q_H+tt;a7AQd+ z1CF~fwvbgU0dFPJ<&5&9NFRW#z|h`aHWzZs{hmPX+M~nx3Ex=x%C$M*jk$fVWf5C6~z5 z5Se(4EohGMGKMGP8Fi8I2tRZa+$#?&gx&Wg62F`v^21qQ+{;Ea z!F%Q5f)B{U1cw;I87TY^(yIyXklsaZXWVLp!M@o~@sJZBc!BgbazA6Ogx@2*i@+c| zNH|PpHxoQ4&U+;*v0a|A>@B2;b0yjxKMfaiunGqLRl+~S*w+Z&ExnD@NN*#Ee}>{$N^c|J{~qD1#Njo>|3ku& z-%kkMCcTSX$=J^bMAp$( zOAff+uiPHMo{iTCYHd6f(mNxW(1mcDb7bDp%0EVT#dY2q4`n;JYUAME9fe$aHz0As(?qPVs(ZS-+&#lR(>=>Q+kL)!4jw9aS@Id|JaZv4 za&I#;SnV}~HMnbWuf$!4dll~0xUa;$2KQR8D_B!ae`@GYE&W+Zf56;WZ8p}JjkRXu zO0%)fY+PkFt~ML5G#l5LjcZ+vHPyIlaM$8qiMtN>Dl$!F=HkNo^DqzAo*tK{#52iL z>T!EKp2?mv&lJy8&os}F>Dg_1_L!c#OwV4^bGPZa$MoE5diI%~{if%D>3P5DxzF@` z!1Ua2dOk=qxOLIU_J#1rTq0`@lh1fIo<5aO|KWLGD)YvgWIXd;g#6UyHE0xTZe+|4 z2xnN|3xUN%=ivhyt0JdHVWM~NCcuJnJQYE|x2}B%6@A$H zXJtd6nblG!EM~`3Cw-7mnCD$9^TtBinfG{g$$YPW}wP`#RpjQBO(X)|!AcX);WX|)CpjDuQ@_mBAF*e^P z#zn?_*P_uppKOE}V-o%_JSO;Ms<4V+6r-*mPA_FsO_yP?^QW2Q>5)gc5Mf*^BKU(H z&sG{z<|5(f!Tg|b z{@+K5KVggK>fw1~Q|~^p1w$_O+Q+WWG_KCCZQ@BC5x?8i)#TaYNi$lu;W1`=u@b*@ z+SI~Vr5{@4!D3{t1SU3{5_l9WM&>4FdK!SM-z}W9mhBhrYzU`q27)h2_*+17Q*xT% zZu~(b_1p>>fW%i0NbXGL5q>RvY7mZXsd|D#_+XJBwkg^O-jB2dv5k@-_yD$r2!j6} zg16&?SAx*zDBxluE%1HKD-5=1%PCOC-gLl@}RK~I9M_;4Gr4C8@5f~ERdK=B)J z6Wj>jAOyizPxK77>j>Y3`GH^?w%aH^%UB;l$Qh#e>#?&)FbF>$1ku6C?G3pndPLH{ zL~t`c3@3O4wyg->i0vwZnDo9$@I7!>1W0a)=p#^a^HW9;^)-(m>T4Ono6xQVZ^m{W zU|9k?mlA%6U@!EL_@4oiJEFfNykEG(A^I069`#Ocai*X?>7&O5p#PJE!xFv;Scd*v ziV2M1YzZ3);;Gt9un!-+61*EbWD2>KF0+NOI6a0>d@ZwTIk_9BS<-v%W8 zN-%)P9now+!j}=e4enzIqTk&@FopgDIHex#LJ<8dMz9Gxa|9c(Q%JB8n(GPzGNaOBBqIZc8tIa<~zj9*?Y)6?4_ya0_ z75WY;5<}yNe^H5c=Z9vXzWF{k>Vta$LB8Dc5Ax%i-X4PI%kwoZfRcn?2;~S~BqkWz z=RJ>b%>B~{R!D~;mx!-A*=5q1&{Bpk8gX4A_tTfl{d7!J$bvCE0p}20DV+(elFo#% zN(2m`&6;;)m=gfLJqCwzl+CWHaJjBpHC6a}M1dZFYg$I4w615sM-MmRqqe7u_?-D3TQN2#1Xp8# zsC=h$X~pHWf-fQIIyeYK*Y9yn9=Z;{is|mU@0t zlgH<}QRICGe7kvW_CE)K>gC-~lh+T^GQW!H_g?UgrT)IH$>Vb^Bo>qRGw}7x{B+>d zZzCqUaxhST;d3=$F?qLu?>1eK3_IohNR!9s`cdTlJNU-ZzFSu2^}}O}U&Zu`fp0AG zey+)@ID@>G$0+X>OuVZ87HjezLs%dFec)Rr={j)o{VDkN>kKmdO+dY0EnX$siQ0`n z69J3W%N5}3l`?eTY`2erPnDxmG8U8fIq;38pU%dFt>mexwV1pm;M=1sCc{qs{!){t z>am!-FN1F^J*-6Bb}fKfV?Nb20rkgV?VNl3}O3XEk|zEjNn1=fF3X`U_xTsPyA&!BOPh0KV;G z(C=HCJfGw*R^Fe0FEs{v>rhCgU%e*p=LlnYVTrgAeC)Zy6TSNlDj%Q{E@Q=LG}F!|MaTipl#2@ZBisI&jLHiN^ARf#kJF z#$xhn!55Wu9XREERFij|Chuj0_4)oQ;3J>7l&@O$QogU^*6aD+dj494So`GylP>QW z@SR2+$;0arzerx9FPuMk(d+dpUrVcTz@j)~QT$z9R|l%syJ`)7jpWzaeJ#CrHqXX7 zdvQ8x{*KRHq%$#`$6OSgX;BdI2RnAraiF58Iqk3B7<5cx477aQiQF9;FCB|`w+){H zn^OHMwRv2kV-i27lY#%WhSM=xhi&*|ZpcLWQ$wE{4@%U9Mmv*;pJ-w~F$Tx^(BVV& zb4#wIlZrY!8(UlIJKLIq9nHZee`DccCcIVG%ELlhH~Q(^(2Z^3EGm7%UDAZRqzQLP z(MVRDk&sH^d&9ijs0nvT6Yi2k$LP-{w?_M___xZalL>c86Yi31{$TJ8a=HiZ=Ca8M zd25(BMdA##qj?o_xIJ=y-)*ne(bG-1OTtl5k(hOQ3;9hM#Sagbe(JmhXKnLTRT_i% z?!G&c?CF6onlZA+(~vMm-U)X}nNgZ)!d+7FE;QjTDG}|?_7<-k8o-?s?vf_lC1tXI zXm?3`!|RMkNbvoP-`7zR33-QyM{vzXKRF`Bw=>0eo?EcFb1uFTqfMj`ZWBMLcN4^p zB)PHM)BoIR z`x*rt7yUR+#Zeb+q&|Y1(xMdnq7Cp_xOI7-K?W}hvhD9hz<3qN*bhMXcSwNaS^`|> zdk-==-@!vDe!t~>rIOYMK3!iG#_vfsc`5Lrb*xK;skczRDqWTerd>)W>Plnb>yvy+ z1j$pnsyKqQ->GC1z7u@Kejs^2X!-{AufRvuNBUA*(dEJYAa0%SHH}ZT8}Z4uOd-gx zQfxjK+u$!t**CoNJKi*RB$K;Ah|QE)_pvSUcW9s)~2KXM#2TRg8SszcmlNt!gnt20U9=DXm_j%#6(1DKINEnVqS0M2!TFws z(@!$Tf$y{8+~PxFiIaOGnlnD6(MPN>%`Y=p4)~|6I5O_H5YT6Fp+-;G z=r!zp!0EB7((kp=SF%3_PFB8(PL|N>a^cJMFWT_c>?s?*h8+ifm6rZF8~rNwYv5OF z^piIF)%-KZKho&=x~BHMhFyrVg*5sitE@!#u^QleH9A>TtBc&jv;bc*NyWIig|)(5 zum}x?uZEuwe2IoH0A8u#mjNd$YbC!Lc(sPF1zxA&^}yF?_;tXq*6q0p6_PN#Ly-J^;K;!*>Jk(C`Dmw`lku1HW0r9|RuK@XrA6)^M_Xk7@W< zfG0HkDDaeqe;asK!^uK^K*N6ye3yp*68MmY{|9h&(eJkQ=Z}Z!?t@%-vgz)FTyll_ zeY81U%DvHYDUy4xHw|T@t?x_6juC;ANVsR$zp$G;4m zF5)>i?u)SS9?eW3oQmYVZ~$rQ3wL3Ah^4}9;dHn+!&1rHqUq}H`d*2zpf&P@d!uk~ zbft0jo;=s`^)2F{XhU-*NHhwxgyHcrs~!;@04h3vN67cJ0=>;;27}cz?Mx7iDYCOMZpD9%f@w`!6<%R ziu99b9DgE#_juu(s5jahNe!|#e`j@fSFe~9$;S^OY71igZ4Hg_3{90p2PSm_QXlT? zZjUBl4??8+aJD(VH5TmeBdnpLzb`6d&V7vu!lP%1AASG)59FM)I^p!`m98 zS!9q*YqIs|*5qw6M=m^&PWHCLGjS@K@k6;pJQB?`Bzt?4eGRAy%7wGFMt4LLn^HJv zJ-(BdD<7+}CRH~iyQ8-1;cT1u4}6j@817BkSSX?c2e_;J6fO&?P?@|ySE*$|ysZpQ zsuITCEfqH5<`kY}vLMo~4Hdy1N^NcEPp6}OS(KEz2|172+8E8m)6s6FDcjl>7A2f8 zfSYimw0y#i(u5nO2{%fe(Vq0m+JUV#Rd~w72r>~3XQEZfu3PzU%}&=+69#Y-25>f$ zBfF{AgaMr0Aj@7mqZ_h0?K;MqZo&Z0Uf&Z2a1(BnCfq1ZxKS!HD+r@jX(g8$&8HMM zrL$3C+%0EW{^BZTYVHG>2fLFIVaiE?s&FO~l@_=f4#$GzoS5^+q>(J3XeJd~72Sz- zSYj*3Q;Ghq@jfkBMXrpNa}(b5poo`7=QgAYn;Z6s{4r+kY3 zY&;=aB%4g?p{lL%Y`m{0>0O@mI+wL-4P5J71Xq#$%Ngz8XrKP~HGhMQcWC`aYK?CE z#(%27pB(+1feVgjm~f~AS1jbZrJ7Y3AqrOvm`f)gzc9Anyy!=+3WHp=l>3Ls>5Q?o z1o1OY`KF&de%>%!`k&l&%;ea-m@#4)yK$SRhRhia|L3@8Q3ZF^F}zQ?yZF)@CZjM( zb9sdm8Ur#Z$45X@t}hgB5~Y0KP-@*XUheV;KNgymo+FTP#E_79aeK)XjS-r($WQKQ zMoQpd#m!yN_^CYQ>qAEunW5dt)9$>+2>C~FMxW#*IlDup6*G7mKX(;F4s7gsP!8mR z=C?kQOwMi&_=&?GGEjTc-A(oU0oO9)IJsjnxLc#?$31X#;`W-)!2`w-!#g8}G}RaS zW`z7NvG9!0$-}cLrfr#TcBt{xu8zi$XG&(19^@*=wkZ*C}kyq65a|+LvTJdylG^(XGO@j;OL_ZFFE+utFIcDO*&yrb-y|F z^*a~Li5+pdPu+RJH4Sq@-*~y{{5dh-MZWogmsqGA z{0w(y;|-iV{Iyx$Q_NRCBe>wHm+NP;k%esNv7x!SO4oBnCCcVy!#OYYgrkpAOP8Oz zbJOf2aFXL^6>ys4Te#@pTPIJp&!@Ehml|da&GR&vhY!8MynE^&KT;le=)^N-a^y1C zhu(VSq~~(f*CONPr;N!L8YL6ti6*2swa@`Xp>a0mU> z2fb43j72r4Ypd_7H-8YE@45W+4}uFw0_jXntJ)gYb2&rv473J&_0815w@!?t){z9) z(hHB}T5{Kw#pe0$sw@k6o|{$XI(29JyoQCqN}tQMOd75~wJTUZ@(dg#XW4vUp!f2*1j>L`jhp>b1e(rIF4|e z8Ecte|B?|lLUV@01MJZL`HhRf$F6S(%&n2`c&G*|(9gg8hS}yiR&z1olO*k-eUm-R5JWf{NXr-9}2@2Pl_BZl^<^Lp#92?Q*Y1kG@!(A+9guvTF|=Z zv&z{=E(v{x_(Pr$xw1LBPmN|?6FXckG%Ejh|i!f zT+!4R!#+>Td{+6^@s>x+m%@z@Ty43YV@tOjf%_X1HEbOJHCy~$-0WawiE%K-=O~gm ziHEu?NK*aD^6l{k>R-b{L>u0>msY17KfXU&?$ z;5KN$sJ!qDi@Dqp4%GMvK~0R1Dn9!Br>_^SzrSvHxvll?B4;*k9d zj`-oeajqr^n;!b0fb43>G>7O71n0thjNtp^IV|%SjQDVYe-pv^{Fp~>BZNLrHi+y7 zg0L^*X5b&<$24;Kdnw*4eJnj7k6}b%x+(r%=~D@Xxs`C#Z;~M7r3hXs&*wq8cMuM_ zg9IT5s`B)xN}g_rV5K}a?hYJoOE@Y8Suh5B=KBa@M*09j&>@QFLuO4B|6zjQ`#3@5 z|EC0D|MLlnKSU6f`Y^$}akwi%DD_!_wKz1FAmaa);A&|u3?=@K@HLEK4#Gq#eJCN_ z-xGcnWB)+#e#VXxM5BC-Ae8wgLG%}le|{*_vjovd|40z=#|WZOKOl%g{g~i@^r3`G zdX8`(V?QSdzF~s(O!!m+|E~x~Bfmg!Hzs_70mlA=AS(4FLBzjG@V4U^Ul6lWO zcX`iId7m%y#>925%8jur>KrpKuX8AK&hx%d<~{e^<&C*bl=~u?_q_4V8%4CPUm#TI zFyvyX2%awE*#P>8?|>rfEuRDnr2-4aR{?#*w?cssZnHw>?LBvSuU2_4mU-i`Jf0P= zmm5zqQSM7*-b=psb9Gi% zSbyX1%xIOYIXt?@v+?x7YNCZgxXmkN-k3bcGjA+}tP77LK3}=+{{Pr}7x<{EYkz#t znUD>8<+2>?3jQ8He&+q=T;bfh)*E(yj z{XA#RS$i!VK54E}qNs0`FdM*`wdbj_@!O>@8^F9v%6Wim1uv965AC>*p09+>{ zIIMZ9?6STs+iZZaYyb?x=xFhrRARnT0+c=oVTCHD6hI1*tL(^3qvMgQ?2L&<(nJRJ>-c(E?j++l>Hp9N~mp8-ukWYr~AzWm?Sz?$THUPu&)BrLJPy->}L^KiZ zl7Xvbc%)6_tCTN0L?+%O+(aC5@KQsDlet^r4=DIG!20d>8x!(94t&BL_8XB2*Qhrs zcxHQ={Lt?i!X@?_4Tk^uBk`s725ZtkQ1qcbDIBY6cO^k^Ui-zNz#$ICauE3lEA@JhS^B3uYZ6of1B(hTcP#;)N2|bH}YOh zxD$E<4uM?e5so5+{4s=A;bjvct~;L)a>@YfaV#JX{*{E_znT#GGyu*<=j|pO1m_Ka z3^TQd@OC(9AiNRnNr+D1CRxgP2C%-}-f&I)S>SZWs#9U#LX{fId9V%Vhmt@g%a>u$7}FL4Yam75^& zP@*gh3i*;4jVfOfqf&ATqA*lNy+A zRV<<$_1<~16e-`U%KPgS^&a|c6^m$^ibXU-y_d%7fTHC4O?f*klts$-nWr%STv@by zZ;7`E^8F-KknbJwV_v>*=ds4ShL<42R+uL;#eN z3kfmWE+WKe3lU*1Q`*BEF|WGDs$u;0yM?!{Prh5|f^{c7^nO-k;XN7rRD z_)KwWN-q0@@^lmJ1m8o3ewvT{V3wPYfud;?rOz?JC7*7a*>XUU!%kWThDb_$9g0s~ zE-3GPjTmsdhwmH=U@XQx5*BuQ&MV3nz{hr>zC%@B0Pq1Ea&1s~{|3G;Fp-aa&qO|N zxwm41G)b!akGI?pz^BU{p;!~i%gjq0Tfr;u8t`d(Ba_Ix8GNbe_g6#S=p^zo@>7%7 z4nD2l*d+3gndN1<+nxec~ zEUa2Tc~9s?UOV_UgXT@QA;TQce=_9BdkW}@+VAh+Tjv!9+$(P_7D}yOw&G7D?-Srl zrTyME6y$x* zkXMpK9%B)uQs0yCV5apeOCs+~@TJlpj76m7g_Fp87<{SdcQQIb%PUVJ?=0}8qTjuS zyak55S8504;-oR@sYW#Tya6Ap9!Hh`}P zijYq~Mw9P-9Ok;Q2c56m7bGX8fytEjNALw9jPfcK7v<60J-h<6=|D(M45WfyJVMSa z%A1{H45VRp1s#u&_0;?$dxWGX3o)anz1{1%qKE&-9vS~<971x1j`#Y}?&}pk2GGK9 zuDbz;;^40*ANu_vK=!W2zoX7I{uFQ~jX!6j@-H1kzU;z>i#H6MzwzEQa5{|qvw?HG z9x-q_{BqO1_+UAzSrf}c((QUw~gPqc)gGi0hVdUpPi#v== zmkuK1^oin8(Cdxszwey0{@LPL;M<+Nbm<^6e*GlzI%shxllQG3ay)f+L&#d7*R=8K;Lt z2y{9nv{Sltj;1j>j9dZwB?g@iB6Xs}$X4Jh3_2Y|>O_Z;Hv#{eL8pUAo%{$fz6bcz z2AvKdb)v&azO(*?L4U$UUnryXy=BmU>7rjE-&KEL(CN@oCqM5;q~R@_ozlf%hnMYD zCB^|yH|W_e`Z7U>jbjWt9X9IZhb?S5@beA&5*K}ibmn=rL2q=?uaNJ)4;XZ=XC}TC z{7)Nnz8inW!0DioP5|wcF6f}~c>|||#+MA74jNxEa5`vw)xZw`?=o;YXne!K>7bEL z1$B9J(D)|HNI{EP$`VAl^{ZlS_rssZ^DZb#M4-s?-sS_P2Go6AqWa9mrsayVy`T z<0Y5mKOOjDv+))VUk?6dioTw7ls8=AyMX^E z=&U>SyBGKm4gBALe+V3EO8Qg4eYjrZuK<7B;C~zV*MW~y{C+4h7W`8bJ`wl`=y#IB zX8^wg?J-N?6~HeBUas(3;Qxj8*7|<}I31*F`mMnE45#JY2mCPbG3xqBsivCOBbO@^HM}S`deRC9jD1KTzf%0|xhHKpTD`taN_I^yX&sl1nQ}t4rYzr>!#9T-VsVs-kKM ze*MI1n>(uLU@Y7gtu^tA<_@vGJx)^R%$AP);11C6O$Y~+4D5+tDKeTTPqYs|52N

    A=&Jugm4|G4ki?a{vG3-cxo>p`O|7bhAy+=5GI=SVFw9hp~Ei zv*eo;tRAI{tL9bDYwn1(mA1hFLv6H4Wo>HgaB`%Z(9%WAvE0J%r}E3`&J4H3*3t8% z?NPLHSw(g6`c3p}Y&+X@9EEPWEZVk~ZY#;GyoWAxWoqZ4>znEtH^3o?sH|EH#(7oM zrKP;Etu)%&vAzx7G(Gth?b_3_m$I}Y+6K>`9{!~rEv-f-?<7^5w9`?Cm)XmDWS7O7 zqMMhu$1k7P6m4yf)ltECChBPG?8M=J7U6Cma4m0-EsVBzC?B29^_B9TyLdya zt-h&c~*Ik2UiC+2_Sx&cS0 z30xX_8&i5eH3NB{kYOOww`_s-T*Tc@+*q!F+$pfwEgG%GYs&WGy1F)il&?ZriD#GH zu`X5Ya@r8L;soODm!2sx*)rQ>>*R0u6I>Es5>jTg<<~bh;bj1RfhN9gAkz0hr0)So zr-nn*{&IBcm~|z0cdFU`=T1+xq>t+QR9~0G0je(>4lAwO=(sZ&8eDQbnAJLe`rAhq z(Z!}OJ189h;+!rw#gvGRD@TLJ7a#kebaYl2P6wdUMP^3$ zU*79%eW<25EP`||NvD(2UE!gV&#|xE642M28@?!=v|VA5ogM}!hKD2 zd2vZtOnUmb*h8NB$o-M7$Rpzy92LIKK2JUwgEB=I2G}q1)TD4sU~&t_Fp=euJJ9elTk=@~Y zWbdTy7L)HgK2ESrcx2t@o4({=Xngc&cmBA;B2aPIH<;RE6Kl4e`}4Og-*4WwR`Dv| z?)_r^p}RH;AFM8SBX?3LTp{I(&#}CbWzR%>cUw~iA1nx;7uGaTf=|9Je2OP{Q>8Bb z`+-LTHERKm7taEB z`=(?Z+*dLPvK}k3Uce{WNmkbbr^OCu_yb1=W1M#{EQTZ3?1Y+a5`eODgYP zKu5mmM>$ulXz{Vmd|xCdoPM|1eNH$}UbA5z9GaHX^(JO+F`b778^jq0GRpS*q+?KO zVsoa4Bdh0+ze!yOH=3<^;bJM{^~kVqlFtXXm`Apri+KiY|8d);=_TD2vl>Qhf=gJ) z9sJE%4cCn)?<0*FXxGsAt`B|lg5jy*W6;BQSY#b&kj_vSp3!i|vDQKJj%5uxBQjQ` z?H9qW`p_X?R_Krw3LWxC)9!|&-(XkWA67qDTO&)S)Ei3tFLYOAp-n-n?Jn=CFMh`t z3a+9HRkXx+yBB0(PN1Y(lOt44j+4VV>4P)@J#AN_ zJkL6kF2?Qm1zYDI+1q`|qYZmLwC4Ffw3ffavsF0T`0b;jWEJMR$nF}~SbSt3T*X!l zZKwd2DujoF?11GrTiwub#lmhlPt*!|vcV(QqKc zdg+v|$*0~@EY1>N*jM6z<*}0U_n#Tgl~=JnzFYD)%%n$3-hc65OP&w^GW-^>Jtcp5 zao<}!M4V2UP|_Vx&(5?}tSIQm6zw)?O1`ojB4!8;T=~JV<$fvv|HF5UNvo zt$ynr<-VCB7_~Z=d)0J1Arc^S@J)U0%<>X?F4UUx(Z4TGO)qZ1zg` z;d&Cm2H@qk;J?#!;pwfYeQl4r_{PLrz?xzS{AU@c9s#fwXv%IRxG24L_^4qp?8xwC zSXg+{0)qnSfs8;PFgTDI7?LqGFg&Bv%GhdUY_l@1w=%X{88=uNJFJWwt-wuIV5b$> zWd&}w0-v%1w^)H&t-z=0SI|i`Q;FcPu=>;y(yoLFkR~Ot36!Qbv`>*k=`(86{j;BHyky8pEz8MEbv~jl@A^wEqyydYF&G783r8+*>VoT~`sm zRXOlHQ|_IXjwP>B`4Pg0l>^T^@4qb!Xo9s6N}6bh-0(R zenJR;nh^c>V?y-XvxIwu_&FiUd5#d9WB!8>%7Nz{%7JH@a^Q(Zd53%`_dP|W5-xywB_SGfu*%OQT!>A?g!jQzOXXvIl^gd*5q@56I*4^%ML*UJ1KxO$7$5bs(ds{UzR`ADc!dHi~zTA2at_FuK&tr z@5{1rw~=MzhS8VxM)NwU0B2tJil-|z#`monX7h6>L~vM`q_PQcPwdMkFv~_!cG=mg z>|pQhO(!tvZwW5 z+0Hb`Rb}JRvM;AUr@T&hy1`J~vOWEVK|9iJ^xuTXfa1}cBFMG!l{R^OtBpAVcpsEy z&s1e&f$qzekUw}(CKH}7aWB}ieb5bQJN!55$D!Fuky(AK2<~}KLQ&>T2|7iP(_h{^ z6L!a3)e1#@+X{FBa1y)2GcY5_vd&Yg;O7jMrvFD>(O%fI9s9}^EvHmSw%kRk<<9R} z`2Xh13Uf|j=}0iAij^XvzE#8=$(c|@HbSW?8^1>Ta$&)52q$rgvE+KwDBs`SGPqD4EwgYNfnOwbba6&`I9Jz zyIg#ex+cX+z_R30as=O!%iSudTIF4FzD$hT^E!24E@ zQ{TcppEb5FP(GEvEFG{4>ofLKl!d3MX{6()$Qrlm1!RHyeHXcW~(*8D)d4v2cAPTRt`3tYMw>xL< zkgtbDVYPhiD+(jhuc|1F+CjeP3VH+NWTKaDCj|a&1z#cbWBWK@VGUdc0M=gzR~#z; z9p=|6*DA>WCvp60rK^;}n7zHbzSDM%Qdp1rFn<;FBW$o;o{(Rcp>p7404rU&U{?AkZ>#f z!!jS&e}VXRAs!`!{KpkemnL*MOej!~*A@N&>G+26Pr|RFKhQ?JZU!J-5uZyO{YRH1 z#H$qjQo@_i{)D)$lk{eMP9Y9{=@J@p_Ne>^2wQ|Wpy+f#LjGq6TcH;r+PRDLufW9v z;U4q{A>t3C`Zwg?X`m5mPe32#omg~?|1T{6YJP0=Fd>yH}M-}4DkZx z#CMh~8iU_n3i+LkYYD%P$-DRY>icI%eg7=6*CKj5#;alZT?(qn_XQIP7uahMzc*zQ zzeIf>#Z%5C;#KzA#P3LF5WiG8ie90icSqaui)_uXTK5mQTKz?Fxbpp79n%I(SBvrGw|$gji!xb@>r=4k6YUG=cOqHuUGlFll5>6efCi75|o3?xEQB=?_d_wJ{IyQz>_fa zTzpG02Ep1Ru^%W;j&r~U@Li}8;AuFR*!~>*y3SugN1J-+^F(}d&QJ)FK2OAFRzsJ| z{?xL0JJ+=GDUeaX2)(=aPOo`+z0N-XsH-T5brwnNjHMt%ff-d9h-gCWb|eHE9;l&D>@!H37p9?4se zTfwL65mMZVe@FN(`6Nh0qo@TJmkcNp@@lF0iK_|_}B3B2_k7mDi_P9kp# z_)^jDPD5UK5_w++UnT)fA-8z4E5ai|cnq5_v`7OJ#j|(2%#%koRkx`;AB8z2IA_ z=qB*4lL1WHZ6<>{_pX!J9wpr|TA)`e9?m1LyzhYzufTdFue_=A27ylJv@8$$oOA# znqFMBXhyW7qph)KJ+?fH8F0cO{l?k;?&{m3s~Vf@TkL!&Im5|unnjJnoZoYr; z2d8^;ok;(o2Y<W;k2d(% z0cR1K{}$k%1%9^T|03`waE_mnvb=t9U+OF-z4ffj#IsU z2a6IfPjlm5)OxtqJE4a>uah~qw?EqnT>0hI%a>IwTv}by*a4Sx(r;{WQF}nDp@+W44xDRoWr-xzTp~Ant)<35&MXHpojG)Kmk^l}}zeH#fGWZDv7}?JKagX+2&5 zN|Jq=%Rny!&f-1>XK~KUrrU~uJeykI{v(f3TqcFARRiJZ{!>|kbi$pmrs z@q?}N@hY*aYW%K}%oo6$cgF``diPr&T>ozHoMX@X50}6l9o!5lj)3H_sqa7kl%y^` z(w#?lQ?{F>LBfBKPLp`p?v|#1m*@N5$`1kV&xd=hQC(tEVDh5CmBqut&@z2+`rr|O zzICC&R^5c+L(6?f4vOQx^G1iSm>|x1>tG<~9?QIo-fU$AdLt7c-_p_wR({FBA8Ac{hO(B$XBcVOHpzaIOOsl@fh-&S)9+;u zQDtK+^jFy!E_Rz^Fv@zPL;9<1r@vt)F3ZLk@2|2sCnFqVBURa$KYdyDWR#^7=c}{d zbjfJ(^bemaacw`vLLl1%bGR>cI$0|O$Th<2Xl1NY14}_Mt%ahoXicN=&BSSG!3=y8 z8B{9c*G*qED=gB7Wh@$OWu_1Fjr5JO#`#Y1oeH;h`}s?5Z?owz|YLaUI<|L9?1W4 z#Z4o`BpyVF3B?X)FiW`zW1xW~7fty=5Dg6$wGV+O@iZ%b>N?}%F3VE6@toXDH%3G)r1AfxO z_aOM147xtO87HQR#7GQIHXrq6UomlP+>68H%Ld=`$RnQ|D}dzlmU|R@sg!#ahPy5o z!%?P0^45Yc6?wljOHtk;EDu`0 zlak203Vf;P_Y*^&9r(<@AN6~DzVDIo|A4ts1DYt_pGUj7UU9AF;X}{w0%X$ooi?ierc2Wjokeq-FK7gi z(V@R?;JmwXJnnY#GHh3u3io3};E!?sj6weo=bZ9Jir)f%)yc~ce{{}CA1z%_b~$+& zw#!L{`*DY(>#o-g`j~j-asA2CW#l1)evXTNigX2e+@P1b=%rwnl&&ZRp{nUNuG0v@kJhPVxQ+@vZ)d=5CbF6-;Rg!7<* zbDQ#H1K;bMvpr9j{b$lyA8vux@}9=|Gz0&+bI$80%Ii(~t1fzg-ZqUC5Px>j2a9eO zZr@pdudcA{r!_HM@en_m3yeyAhSn7UMEg|gL965;`aeR z1Lbk;BK~dQe>3RM0Y40!_iWPt2>d5FAEWT&z;DBOk-`UKai;p56Xfp)b1ba5y%}P) zH#gSTmqgdsm2VO9d=XyCiph2M0_e7tLc~lh~5KGBjKgR*=_h-290T&~T?9Bmy7GEaPFC+@T- zJ~QJ^yN$wn+JDVWdpu54^(|IiN09f4Mb4RvQG2us`Aig4kvx(b-8 z>L8>>&{~6P3amCF+9tTl4t3kx1u6t?yp*02dR!`v-UgzB4j6nPuvoOUwH-z-_^4C2 zzBbmD8`~7c=jd22j02Ikx;J~M#&s%Eviv0D72;4&B&MpkVqx{dijwJbX3kA0$z(`b zSW#YKa$#Wj2*T!^NZ6c|h0UE^SY5NezIJJAEM`aV@;04QVHfL(3TWF@7Q>f3T5={- z)}Z$gHDK^HVDN=+wQ}4TpPF4pDoKgCv}ZUmM@kk!(lo-3glB&Z-n1$|Wzo(RCkPpt zsF0Z{mC}X>ofH^PX!9dAXzy5GlUx`UVT8*|-Zh-hWJ2?vSUb&oLIvZ-7|At^^QF|i zJ=mQt`-sIj*PWoNdoS<=9qzjD#0_h(pRjEQ48CC9vj&z{Yg@g&-orA@wsmQXbs)%n zip&g}SKFKY76^?sZPAX#mS$V@fWcRS=(2I6EIWj#-BcLZ1JOaJCu%O-E2YI%`{w2j z+p5X9k=kP#jkiA5j3?~GqgY;^+)|78i~)l$&fYfLR2IKaq}8!(QH|u*sAmx;Bfd0C zM%sk7$yxzE@Z*wWHu8{c*CEO%972Y1m1r?&*7_G5ppTn-zX zs`WE)K`!2@n7bZwR#A=$r%mn8bq+-o3>UsKfFXd z^5M}Vp$UkcxM1;-&SJy@T#(;zc4%a2pfnh1l~DqB26hTx1k{jr7QQjf<~vn>><@&l#c?Mh-~Am%T7YFZLY>GH6}~Rwi;o~K9wd<;23`Ju z1*fb0FRiTG z?sL`0I5_>0AJ_7fwHUtAOKUM?%8$i!m9`&Lo5(##w~3lz$oE(}{x)ky1F#Jm>(AFS02dMM^V~3kh?S_1J9XhX6vQ^%%@Z z7LX47VnWbY0Q8k5-pMROCF<$5V8Q1E+01CRzEoqV)&Y>;0U|goWXiJ9HT_j~nl2k- zM3#+V&|hWavxi;pELAp!Tz{3#btQts!UrB%Zw%-DDx1?$mW_^=WsmN^vYq~h0fa0Y z)3m?p?X>wMRW_D{elHtqn5;LJn?7(2&MFSU62p&@nOK1_vc(XX_wX}fCRS*goeaTp zJAn|(Z8`I?VlPvWs!afXJL$05xRVh4{De-qdjK=B+&)SiW*grlgs^7_!T$?F+)-Xt z^xp#3W0~$!`Gj1y4-pUAQ5uI}nLkb(@;(5ppJ9J~wlG%YXI|iOt2ylu7|`|!oX(HB zNLVm&0mLW+IxHk0$@>UyUGo0H)}hs!yiZ}^v6b+B-8L3ME6GI>wZ*0KX2gj?>tn17 z()yUK$)>|xmDa~>RS{J8HPnI&Dep57t!`R8iKkidQ`eafn5=`!CEpPjhmD|W@*}V& zv2`B7g}fG>D-(4@69yKy4NoXU6^d~9awt8c_?r~7f3e18C67xKu*zGotz zx7;6MCU2Bf_aAS$=VL7Ea^;xrMczX2HMvDe%q#D4L!O)yy~ukeMR~KZ0%-j>hM5x8 zw+wu#==X>rPtM6+zmpJnF;tXp>tI877f{A^j{SXZ1{J0K$uON@} zL$2|FtnYu|&~qNA;<9YzpPh)2euHyU-dgbOK_2Bz!ofs&nQhU!#umdS(6I^swgWk@3G~ zAc(ghGwNbB>sM97)7aWr-0_$zv+ul?twy`XN5RqVPT9`-&tT!khj{Q|9(;rcAL+qI z%V(tnxTOVA1kDt`qKXPhJVScoy9~pePaX8)^%US-;JgbGe+lp!1MdPpA2>%K>3;^C ziUW&*#C@n-zCmXM>L_sBG$fr~%O>Gm%Re7D{__Dv(kp>X2Y;HvBfu9M@|uA^f{R%` z>$4U3;|9J9xK8u}M>9X2{D^!sEb@KOr|1mu(~M6in*F_K z;GFNjFmONSv70_v{LV!m;-L=_Z@cKjJoI7WT^D_Xhdx65!$lwIp^p?9Tt-x)8K_&o z(PAX%Va7E?8Kv2 zwof{BNEcgN*PkVJ0{@XgzuiTjD((mVyg~n}i++yyF7S9CVSEFB#o+&qi+{T0KW5PX z1p501{+^3JSEOOA9yjR2fa~PPPQvlPKQQQLxac!wd6)<)rHfgh+dnCol`bxD@z0k0 zc%A3)F9bc)z?ZxD=SY6;^0ZUBr~`eJfv_%9G&10FKydtLO4#M8hx8T6mK=*8ky;CCAIKe*_n;u!F!4f;P^^m&3&a%g(0 z+hZ&j9+mvqgfqp3my7dU_yVy2_&dh+OI`GZq6YZ;27Qf-eu>xuoRNm?lrFA!(JRI6 zz!`x^(?9Q`SBb9zPj~8+F23cWFB4A!XLKih{ZC!=OJ!7^p$7f;F8T`b4)9S1{X-Z1 z3XwSoPca64G;p2#Vx`CdKF*+@bkQ5cUf@Lr{Rb}kYVjQK3k~{zy68>fP2gdJe#Av@mN&vn z4EkW+7*+D);qw&Wj3{NNbdlqtw}}Ga5rcl7i{2qF2EN6hFLTj1h&te%27RrIzDaxn z_`L>whl{>N+y%VLpnuUtzgBz$_&*Ig@6|f_vFYm>;API3N*4!R^iJ^_aLy4s!HcSk zzD;}poMT+m{rZs`8GdXq8V#Ip8Z>>pi@rll1K#EINxGQrqTeLu0e{P&U*e+g5?2F{ z_bI%1n^H8 z_)mfFHt?5$-)Z2#1Ae!GzYY9e1AiCz9s~ae@Gl#927a18WZ)x#f6c&8Gk&`I@$S+6 zd^tu;chSd+kPGLVU?DzK&qw@y!StrO|7pD2gX?E3P1kP~HGY;_e>8rP2migAf13W9 zfv+(1Vm>A z{|oTH8MqIx6raL+&9 zVTJDi{u*$t{~qAnDps!OUk5$}bgkb3;2FSq3t@RL0RIp~jsFe!Uk!ZXP$Awm@L9k& z1K0Xo2K+O?^OU?zz<&rlN8z6aJ`ckAHk#$#2mFgTFH!hIz$bxU>;GNgKZgEjM#=vo zaQ+4>Qutxuui;$R?{C1bfqadRz-NW|ps!H;X90g3QWX)3d_t$w9#90x%AP@8o|ZyUj?tGQRH9s4O@dN_G< zTT4ram=~@ptGcv0D)YkYn`?DWW81pYrkXYOCZy`(=DMYuLA3Yyls2`&d$f@u9Xl)H z;x>a&Ra{!pUbU$h;y1(;gYA3TV7e^Y*b#1NL%x{_ztS-{lkO-^l#lF1E_bH8zJ28%G?Jj?&yH$!%oGsto zDn(AY?p7&s%5}F&kuGB48bE1l0ZMYbvjwNdMQXYVQkTe=Cla1M9Z z6}s@*?uzF-aS>*FYVPc7o$aZ)6B~h3#4N*!jxgI(b0(XXf~V#jz&62CbBg{nOj9#vNNlSv}9*K6=})NOe)fnojHW)g|- zd7CqUH<%6evFe6cv@X_$@#+n%fm?<*OMYm>2rgM3F0Gauisf0=rjqsb^|3ZPY=*PR zT5pvuU0gM&4#2|H_3V~3MdSzNumwJs{3KX zl4a%9Wu;}MRdTzCEBoRN&D5b3dro4_?ea$I(3dWox2U=lPj*$Y4UO%1Je!aG-^(f% zRa`Q^dTDIkvc|QI&8uV;tE;6;uIjb1wY5!cv(PAUymhmKu5YSq+<-?QQ9K`QQ?;Z# z+FaKZYg26%$HP@FGSSMa3iFCZi_4&!A)>NsF*KW3W#-{Iuexffi;Y=J=Phw_m0^cF zG%77EUe?eSYj0?2s&jU_SC=ll*tJi*G}=^K)!yD%iM?g0iF)=#^C3JFIvE}fu!}}N zRkB%;zpVHC#*V54>`OPVt!Zg;QJUG~c4=j`7$5HK>@v%xr`-1{N894&s!g_ESq!kY z&7KRnJvI@WOBi}!URzsBo84hbjWECe@?p5GrKv0iH{13IuP_>~2MgFyk9g}!24385 zQzvB13dcGL~Hf0gQ`u-`16EYe;3A@S9LTf zX&AYNK&Vo@s zcQ>q)?P|zNYg@v$8*MjtJYTV6Tg;-y_F4g08C7kA^Q9fEAWks(uqgst(%Th=smQZS z8{0b8N1MtP}9) z4N|Gd)4aJYHLH{J<2mev3|d;sjJ*~+5V>X`a?L>Gnt{kQE=M0`1Rp$R$yLVK%k1VI zaAYvx$e<3tB<(H6#xUVF? z!VC+a6sALhjBr7CYS@klQxx9!);ls9%sJL$2{zs06uJaxA z1+l#!N9W!KDS=!#vTy`_(eiixxUM*|_*fw7i)c!5WWoCv!5zWkBL~)zYh*-Z`|5d( zFLGUwFc6ufpl@H+Uh1U}QgMX*!9YZ4o?tLy(ib0#v<4tO)EcSpT9pL}ykgrUISq@C zq*Xnz%9r!{s?4x246KsZfhxLUyK6*&ldMQ z`qaA_C4tgtgLU?sFH)aFZ$h(R$?+iK08vNu(|lQP0W2gM4!kRZfp2y-bk2`7upGf? zL9$0fjY3`#T5ZDv3O@h|l+>vpBo1f9BL9@}`!lAbO^NqBxqNUwu`9iNe_HU_^s@b( z;}1NVnPI~P3hn|7A^#@|NLfw2h)byWk z5_U$c4}3?N%REA>VM)lwJ0m|S?PfG2SkryF6>JufaFj zrVS@8_{6(b$s-@Wb7bVP0~5#X4~epXf7;*|(pv;UFzIr((VfC zgDo6g72|z5yF%Ma{4ZopJ^rFESg@~q!H8g1q`TaQ17rEo&ME%qgIJvkLjQczlJxFu ztRhFc1znYJHJbkR@zTz4_oBte1V)Z;a(DUj$6=V*kP&Z5Yw(c_|Kej?*1fRu{ttzZ zy8Z|)O88^6C}DbdCsv6o;T)wPe6iFsG_PpCFF5bTQ1~k!iW>)iC^m+|bHm*W$Srbw zU8jcYgm2Q4@i&LAFFAkz((zg6y!Rp;svK*L1R`_8S=JP|e+emmj740P7Os=7VCr(L z53@>Mc+@}X_7C5E_t%dG&*@$;`qvXDjcJ&CC($|Y~4joj~W1V@D6V%W#k@e>{tHz5-CD+}*U4{ZaJyB%;2}c8tBRDRiTM-)9rlpJ4 zL4Y(=rLk)nj>$N*;pyw5YoQ2)_TZpXn94{Xv<$~M908OmFi}G#*h|(LD8msRhddl* zIKnHybMtZ-@jm;x^E&UkTLglEkUuRg5P&@vto}mylg+ba3Fc|A+~R&Md&e*#&A14; z<1VBZP1o+vLhrn4H`fz2QQ^FOY!u(t*O>7d5uNelQDkCtP5ukqVF zHqahzcp0q5Qw7Qoj%1hTL*?I~U4GCen`*nt>2Y64Z}={9FVC3p<$W2x(8q z1ju2=afS&(n?*S^MVH$2{+h?p0_bu`9#W1Ju;W;6+Qzu$mPRp6IS3l!6G7sb-cmWZ zhoE8{OJ@;+em3EI%0Uoz`O>6O{6YE(!X6~)Lr7-MX8vHGIF}HGUqJXawwVwXD2G9i zQ%3v^T(^Yqb=!@GcuR=o#9>!TQ(BSX6IT)z!Tg=@zhK%-c%Bfo zgnvP#DMA#wn(!SVS_nhJ-VyySOofS;2(f_>^lKIV2}01XC!D9Ey!=Vn5i($RdNcEn z+TQ)?-RO4We}-8)A(X#|@Q7{p%1Z1Zp6(M55-zoaSuym(!^BakuMzru;+uq**=|6D z68e2&A0hI8K#0okCq(|!gw-&^CB*1>mf*KS{FE>X=M#k8FmonEo86gy+Yv& z6n!z_R&3WG9FDFe#Gtv9a4for@CJ-e!XfAi!W%J82}h!73A->p3134~5$?ox3_{#r z))Ar;+6Zq()d`Pd`vu|eP!+;ku)T=zuTWLxcM^UYsu6x5#12AScO&6#*nUCyH(aXd zw-VlgO9<0^;!eU5LVT963&Ge3UlZcQ@7`-Ip>2s`-|0DZL(qnn+?^)!OR8n4#e z)B4Yo(F9#KPUL!jdf%3f;pZf_FZ|Qp>WkpSnywU>*0&0bc8a(61}F!4QiWWl!i>IE z;Uq%^EbH1wU+L&;r55>03*6@Vas*xP?df0$58fSRW_dF`>Wp0-M>ney`=xjF4FURnJRl}|CNmgEqiUjjZcpA z<$YVWd9UTK*W%Hi*zUgpKe;17EcCWi;SBHl>;Q&?4b zL8~esM*)tRIA-CPjiV6992`YB<_7&$`FZ@4&p!qHGn0S7T$X2*z*k)y1Z)I$^GH$Rkc32s`7jE7n z(@?G~8-L^os{RY4cC2vhgCezt%OU z-kqxK>pq6Ex2dwXehg)AS7l${e`Pzbb#|z-@#xx@{e2qln>w9}6Gn)TkNykzwatFJ za+6X8@96td74y;28TPwW*?9lomt~vpefdK~zHN-)#QKy{;O4$n;AE7gQyEUYkveWw zYTVMdYMAZ7U*GX|*sT=!bl)mqzW)wG0rM^E?Mj8)`c?(AEAUdaM_1gb)VQN>)tHQ; zbt=b+GczM{X2wy_thpXpnj%qcnwR!pU|jaXPK zWpE6Ei^U}7;|=vO_vwW@lxZY^*uZ>01 z^-lX%51OnkM#gZ~PS^H*+iSLk;mTo@*=3ufWMXo0`JM0@488~t+3&jwzi7vg%6!u{ z2PwQ?h$_$vAF$0o3co}HRp4K?eeM@NXq#^oeg&Vqng1_B;7%e69})sfhA8}3+YBS~ zJ$$YPp7|Si0VIT3%hyQ%D!g(NK5R!{DMaSer2o;5!jkz1+l->{>(U}cP`|&E&Se~< zqwwFPg@-8o2J(nQ7|j+k--g8w@o&O|8sVe1IYQyLU@1fT8^~k+V?vy(@DTC6w%Gyc zG&d;xHrheaml6LCW}d>YCjPi>RzUs+;@`E+2#9YW{yp1FU;^;%yzX^)T?Cx)7Q8J2 z&K_)kwx5k@ae#Ex>qmfv-?zO{6aI?$zr(Ub<-ZSD|B~_+4fuh|xA4=A{Pf~XNbk&q z^tw!#Lx}bZ5$?0SBNzSv{X`t_dBDt<;pLhT<}SZdc$dQIt$4z3ZLh>b&|k-a*Z;!y zLR`3Cc_Ri+ufn9mfKJr^Cu9)^U3wD+POreEk0JdP+Y2!1(i<@FprYrH{!817FX_^o zFYrR<{|e?KfC8`{kmGs-AjdO3O;7ke+MD^mgV_b(kOS~OPWS}cTjhThaP~vZLhP0=cgh61DHnUY7JV5v( zjC;Z#!z_dF8JJrD)*rLI&<^hUkHwb?UGao?K;}{_IO~;Cr`D@H`!dKC5 z3escpke^{56F-dm7xABCJQD|hggDA+BYY0}G9P?f6n&e5caskN-T<5cI=$Eq`41uf z1jzoR*HbGK<}2Y4%vZv(s0Seyq2~#Q!HX_o7R;Rpaf5%Aa3uQ9XZ<&m5j82* zQ;bzG2#e&4wD4W8y%BHZzz8TQgYclEW0*>>M)~onV z8&y!k&GyZJHd<3j|Aeq@5U&&B9O7GLlS!Ma>BMi4O($)va*6L$Hi|bRqyzC=1e;RY zM$II=P1!8oA>$KD+a@%vv|*YhxcKTX8sqYnV}H(V{#IIK-oBcN!d7l zS=l%~h((U{ui#OI5H}@siM;ca68x zh?~pB#J`EffDkv8MTFn7Zrk{O>B;%J0c87vlTM zwi1gxx*i5t_TwE54lgIZABzp)0XY5gSNXRfqe~;mOH=tA#{nE#$F*29LW)M9`8bYI zJtvWm*Rc)8Duu{fibKkS<@%j4;a?BFJml%5b@$36pO(i5BPOrBYa#Cw;2UR?<=@`q zkx$E$cA^R7al63{;G2?yJo0IIBYV-0+ZJvCpV@7_=|?^-k0E53y!GW)h|hpe_W^l& zlSe)+@1$PjaZAO0z39jFLd#}3V1KV78O6vd-~ zx7-z>c)6V0Oo`+*gi@3D68LmIPNy)WMDpGUNfT*FH~)C`TV5QOH&HPrk{1JCyD3PW zd*!`i$jeS5?=A3cNI~A!C2{>GC6U(*K0FrmNM8MZZ^%0%iM)5gcU=!@wynN7UfQtG z>Hat?iM(y#<6Q72uYP|q zArDhPChGSz4xf$6zlXs$&A|1km+xdeFznPs1HO#&!3Mqud@RSpfuSQ)qIP)*d}|fm z1m1d#T^Mf{s47z;d1rtxm43U;kcZP=<=vm6ykU#t`r+quukua@Un=_TG~`t#k#|pu z@&-XEy>3(`kvA56spz-Wkhd&}yxUTg_YXtfrAg!s!w=Y0^xF(RUEdW+ZUn=_j%#gPsiM&_Ax6V{doqP3LbXitLQExM|)xxOVH zgWbu|P31tdz0$cL@BA8RbU);cruzlkkA%D^ zLmD~6uOBPU0$uu9Q1sk*WpVw<(#Jxllb0dpJLlB*6zM}j`WaBySG(w^iDuwmcJeaB zM(3Q@pKkj+Pzu3;j;Fl>()Ym+oNF?~UCueLpD2A9yyWC%h<|g=Nzb-@6FBk*d*lz6 zVb;qz31!LkPaRc!Pnr0dF$!Yk;>J_;%nO z27U|hO$JWm5E@iyeZC01)4(4BPD2Y#|0Zx6Txk4zz&~Z+PXXU;;6DR?r-8o={B8sP zE%18{oFP5;7&!at%Le{8;13zNh4Zf&I72i(V&G$N{+NNEj`PP2{7jtxyMgE8{D6TM z;rwX>FUI*Z2EG92uNwGL=bYmu(=&cEMa)GXV)O<1hZ=2X+Z4p>YU6QTZ2VV-yiw?s zKYMV7xYUXCQMf1SM0~ObF97~B<_Mq3M`3+h27Ev8lN4SHyaIi&N#PrS9|b;K;hzHj z1n@kC-w*snoJSP?B=8oT*D1UUIK#G%S2%nrikT?y5{3H*+3UHcj{?3Gbd8?{{664( z2B5x$z)#0{mBMKp^C0M_Dx6`%vv7_qti}OR13ZXx6f5x-;FAr!6F3vEA^%R`<8ZF| z?*dL;H2x6qF$Vq}*Y$X!==-pg>WQScz?48lF(ay@C-j*PQ{}lp zN2)@2EJF?h7Rqp7Ae-6om{{(7CoUGQGx>F)40&bdQ!Ji@bWE;%$Ti6EkdW@MXEFdF zF4H<=Gp_40M+mH8`>8^Y{GNilqjK?P%1>w5XiEbuD2m6xSE(c&22(9Y4(&YYS$@!_00GAN;Bc5274gLaOV z%)o+nj+Q)2OP-~5o~3nmf><)ZpF5lxES0^n%Mks{n)>W3n=uWFHz4X#6w|~_t3nJl(!IHuM|Kt>F~!BE6c5dgzvRS6f>whdSqQ#`*i|tu zRK%CAX>65!=0X<6>N{kHY&5VfLxj~PEQ0OKwGno-=94)xJQx_z>hWF_6~$G-;!BoR z1WR*E&p9W^aA=JP_!hi$&WxhG8L*bmpF3+#?qxFzf(R-c#P1$4y$r#BXBMoOpI@*d zynNxp;PmNrjnP%r2tV9PkNOu>M)PLpA$Mc6tr;<|+N+~&vFaFulfm2m^jI^vn=fc; z?C5BU1*hZx^xD?-7sM^{gVW0{DVtZae135H;)X5KH-4^)Y2!k2Rgi}nxiep?#&bAuZlIdwzaHAjAnxvLzaxBlqfG(MVU%Q%S|pew-FKDT05}XBoyLM zPb9{P^E7AX+=P-$hLnXB~-=Z6=Fw?IMF4& zG`_b2Ck#R)gUhsctglI4H%vD~GELq!T*%0TRy(nFn)ieXHpXJHqP&9q*|U;s80Sl= zdwZ}uUG@=+ajrW-SNC4v2|C<$;fWj8U_W8o4n&|Dh(I+EfvTh0m@|ABuCC`paT|U& zc-I0_+Y{U`bv|xt9Uc6=(c6V~{3!fDO3u(!V?RS1cLApesbT9t1SQ0X_ed?^q^y!yIWb8Ta+{erda!5O*wXMB$z4+Xh+@ukDVGU_X) zx&1NvqsF1qTJ|1^s*_QFxNB^979tHDmr;?rE39B3BI7_+bT912IisdzHw+%`J2JxO zpPGKKyCSn8=g1MOPez|zW7TA?DXBp;mWJzVmNq<9b4P=}_JxL$ z+6Ak()$UsTWbL!7t-9_7qZ&%;cC~D)+tvJJoygf$@5}bJB9aiwxcpn)6(tSN)^BUb zj6B(}AYwJ{sxN6=P}g1YWMgK;TK#No$?DA7>sO8at6u2KKYk8V|cM`5o0HN>#9N7 zxW=LR_Qhi(F%pt2??{Gk&{XT-6Kg9n{`#`Kx+0|dhkA8J*l&nn1et>bVi%=%FFd8| zwMH>DZGXk zi^T5xjtddO_UBswyUQs_+|9qN!{8x<{l!P>&_07;E74uvP$wxWV$T%B*qJD%L>_7m z9_y-nsD4UA*0IoHKSmtlRfPf(5!_QZO14p2u&Xv7Z6tCQM0Z6qS1+i^`X-{JRr_9S zIT8sy6Ma%-Mnq0%LTB-T5ep)j?Ykm@j#fnILd2x<5zlOYYlL8&GCO{f9WP0@Aft65 zGFAE3mh5Al#amZBA>k9NDWm-eMDM{- z#w~D@?Wj3|(Rb2tz6ZzSp+Km+J3|1LtwhwH5pdWKSQZk2FkzNDT;90prKLR^$h2&?2X z3GvnTEW(J|aDe`sP8`B!5Jpwt7<{pvMZ8vRvc?xs8oh7_@ThYIJ2^s(=yTB$gM! zLB|TRY!LgaY?dp_9-+#{Q0%X=`MqD3jfp4gjbY!HW%oY6F(9M@m}h;dfZ6FZUXYc? zLLke=T<)*3Pt|3gtjfl^(U)bL4UeLXg%zuwtUNU8O9fC*Cv`{#uHBw?gMWv100!$3 zsRq`?zEnf5`AU&ZN{zV7bgcMNiD2ID*z zZGUXjdh^I;K~Uk@wq;W$9$K*Gh#}K#PcuXCL=hwoI_fSmmrCb2VhElv!pzULJ*H$X zvptjW`ex>15OGco$+z8v4Jm+iA8}~?J;GVGbu0N^QG950cNJz(Yi>#UD0WoN;<7!32F68 z_*Fvi9Uwg4cGs0z17~u?(GkA@%)~EE73lHv+*QF z3s1_cBE*wd4PglS17=o1f5J=9e#|cxqLZ)$R+r3&-Zv31h1DZr8Jx}#&Vzo0DEF9x zw1mvWLsWq93OrW=4nb#)1FXkG7Ohr?%*R6`VYzKZYQZ{f4{!@lWVAH2*4PiN7N6|A z?wd~JiV1qiM_k*ngbqH3baXK0qMU80irfQ?xhMS=p(?Z$wcW$WM|Ebz z6RMCf`H(C7Mo}dnGd+pzFZ)vE&jQZ@bRMt8IF*TQ&vrKD9m~LEk)3Vx=)Y`FvzYJU z(e_o@d78t9Y%i1Vt_i)n=;0HSF8g8dRT`qw)H%9N%9G;`=j7|s7yWmE*ezG6$n=A$(01Tgb)=gHYX$}oIprI5-_;k8W9z=7uvO5+f|Fb zT6+VxwzXRtYFk@vYf-W5+RMgXR>XE25M8!(&HwwIcji6wzBwnxZNu;L|LhrfGxMG2 znP)EV%)IY;=b2}KH6O;f|>y1kU_bF;A4GRj!7zx_u=!n zOup}ekG2xYhg&Tj`Mmiqz`*EHbkpZq{3c#Icn};`Q%)Y zL|z{F#v<#!}zR1@ZF9xjKownc%w#G_M=ceulhU#T9#}yrI(*|2r;oK79auc)b|m{)iZzj>MmVk4Mf@UI8QEC@-_S zwI|xq6CJsyur$e@!ouPrkl@~WPvL${LU7KW!g(zE+ul=1J#AZwUM!OP3*9Q%BebnY zM4W{^g(%YBd?z7qGar4HNT-oYc~bVx3V#MZ9Ut#L+{mxOpNxyIS>zvpUxACSoy1SW zC$HxJIl|icLI0Ho@cnp@{=vZf)chv{b7$fk24+Wg1azZm$P3}b%O^h)3~1Fr(+Z%0kP7MQ;wHEsmXHgF7>yX!Q48!&%sYJ4-W zc34aF^v4Www~L-B9&q6-`8!vq=TEyQ4Lb2JJorx@%-_S>k^dbA=Ho37_+q5t_lc?K zuU7(}2h1@-yb_pgPO-#|z197BlI`>=zh+${ z_HAK@12?H)D>3GloP?50hA|6E?b-3(knX<9 zDCU+*Y}XypiuP6}}nMdds|R-Yq+@iLh&o%-zx6wyh(!1tuvp-o(4cUJeukd*x~9 zAaPl`Vmp%()K-uLI~MJtA#I$+4mCA5V{?01OKQ(fYR`_`lPbGKkLo7LHWjfuHFBS4 zOYhdiy-{-D4KKR2r!nc?B$KIY)Vy3&Jhjv;YiuY^?b)&0gxl9!w)f^Yx5l4k_I6NB z>DsA6cqx}RPZN5&?cKP%Et0@Meh+5p4tsBy#GKCBVPmLKC5v;$DXl0$Jbrs`Tf4oB zs<*S#4CQZX!`8Oe&d|cnkg|m_rcE?z_2n)0?5J;VfBl{vThQCyv!hCxe9z8a;d?cl zEl%tXix_t_aQBE0dmV;rS8U8|%8X2&vm#O%+i+0imdPDB+_&(lip&W2HDIsBK=vWE z>!j9)y(5;f&zw5(h4PYttuw{^$#Z;z;b8sj{jcux z-(PM$``jbq(l?$d>I&v`9a{Lx(DDh@!?n8(aPJY*i-ofXK6*O1&mTJPxR^Y=CU~SR zR(No8bxk#?jmJgi1i4$u3YA7gX#L=MLlY;@ex@ykeH-O7pIcj1GVt)LzQBX8W(Gca z@SGDqYhsA$Vh7t|x1u~{Gc#sBR-XRsuIl?w`{X{A+M$UV!)v&61v{ep`y#QMv;Wx_ zDs2+;GSDVzdBdyEL3^a5J*GcX5EFqZM}zZ%g9Wj0VB*oVd47cY1A(K~Jmyju%dIGs zwfNELv~XT*xb{bo>kIX5WbHDB@5zAOn=Pg&8tTH&wu0PH(%Cwm3jDNi}qJPbRvkduNe}V zWzP<;8eTKJ61CfBg&vZ7eXtV-eZ-I6lO4*7l)YhP53i~^4P&Jt@#o+h!!_xVHOGVD z@X&mem-&Zh_eHoG`Q+&!Ytu9#*S;Gf@4t`q#l#6;riEC6I}!?!hZ01H5}Dcx4K}gX zLw5?>^#{W_1(U)d_`6>cgS&qt25myW6M;2l1Z20Fsw9Pl1Md>z7H z0&PG1y2zw(FfyqcS7izGw&L*4BURt&#od3jmmT>+9PrzD;Lq~uqu~tCO z7U0JMjs1T;G8(UaDidWj>_1$&h~VPkjriaxEWO$c9}5$5^#|(`a#=D!A3&x@V{oNX zywhG-$8rY$%hm81^uZ?;QJ^i8LyRR4si*5tL zGL;M6NMB4o; zWE0F(d1LI2XWnM#DKk204vpq2po(7PFCUCHzcG(>08rYfpz+^W-K&kp-o& zUdCf?<}k}dqJH|A?(U$EY5N}dSr^L_S4AeK@6QqE$>Wzr)&l!%?o3RRrx#V{>QjC52ap)x%cJ}lmhxbl2r zwR!MKZ7|4^4_~yUeCR@k)JjF2r1mpp%jY5$!}z?DkM#4ADKYw77JW2`9IGg}RJfg^ z6m-!MTMH5A}3Rtm7V(bI`>qcO8dO?3I(#|@QJ5pEDWAorP~2vVtj zCVez0iXwX>My1qxLy_cRz!(t>0&gbrh(*y(FdiHpys<2e6nwl2~MXeN7$?f`83Vst5y`I2@NJV+_aCpka40TMjzzF1l2-@5o7|!# z^2+-m_;mT?SO!-jdH)K&T~dPkk5}IHxp8?j6l)@RZQvVA`34PnaxQ_)MDm8fHm5LsV4Ws=Sc^73Lk>c*`F6rIe7{`@3zKA z5vHR|(qEED|4A3W(?R&uHGb8FC(6@z;!y$dKLGL#MMehrRm5?Aypv1^=BuCW0%DdE zru-@5Qs4vZn$iX2i2xe$loYpa@pQpc8Cdi)^#AiYGR?m~klyB=BDk|1pzq+E40jVWP#YSpMx+o28&0BgJI%}${ zVfb1C(cE0o+YL)s&0Ds2iSB4?eQ$F`N3Wcj*I{OsYPd-bU?`HBxV9C2m(D8>E0ED1 zwOp;m3bkC%oK^^RR!+07u)UK+kZ>(x>>VlSO1D5R} z&#U38yMnE&s!?5MPw#b2TcX#%WWN*F9bMNRjpFqnrLLMXF~2CKuA101f4-w9TUwAZ zF)x?GlPz$k)KydJsworm$`-#;M2&8fLnf*EWy-|-+dD@frLKyzb4;yNX!F{qNqGAi zRh*KT+BVcn6Q;^H7;OEyl)7quN?n!5D6v;H;_L+ZJ0)@FaddOzV|C1ow)~Wd`B7C! zQ|hX1?F*&CeYdSat~Y1HM^{Ev{p=&DB7}(hlk(BU%MqO2Zi0T|& zUsba~2luZuGOs1QU5!TqrN4POBbo-cgm^cvgfHcWS)Ny~I< zpyiwYO!&z_%>c|q96eBe??8I>Ewd)%zw})2RJh>4>*A^@&kSxZp9NHR;Pw8-z%%1zKK6LeZ}E5Ll*qf z!_Oo9-P6It>4OtbSQ8oYT|_!~2alfKaJcdKPd1$UJkqy5e%_~E&9aU+TXTl5ez<97 ztR1Yfk-6XtiOgw)W3D)_iQs-dK1hYqqPp04Ce_Ty=N# z{38c8Z;GL%`|7I8l~VB3%<|*@jsJRHUG?=&+^*_xyqc3gZy*!uqo02@=i;SJ`(r0I zQ&v~gV61QpLkF6MwjTDS9nFiqvL!gvpZ8zStr_a?>S~pWtT3=2j)h=^o#hf#XYLZY z2ih`ypI-lq!1U)|-|9ON^#3aS$H1hcb1I*WiTfWax1RfGdEi;!;77}S&+P;9&G|&Q zsI_+1gayC-#i3)beW0$gb{2Z$N#B{N!d9_{vHy8brllRlQ3;taqAzxbZMEG4XHE@e zA8LmRYUn|HpRR+tY&mo@*20K;C@m~a!Q=Zi*H-3*(yD`X!D{%G@GAxA{TWk5DU8tD zePsWcv?|utLTiPp7f40t46E#Tc9XD5xYT1SqtayhggirQ6=6hKb`(OsJZYglD5K+6 z*VjY9*-%&IvOok^Qgv16PRONBtly)_q&kUQ%Ev;7RBOTNm0UW9evnkXfI5m?S}ss( zD$pB~OT$IVW+V9LP!8yG>0@PK9(~Xk(8s#@CG;U5qNJJ&Sfx%YiXvCbme2=%8GYnS z{VU2F&o;|t9?EfnqkP(q-5IwB?+DzPzGuSTw7dLwYtzM0h-d+$g;pBR0?9^H1>y=! zwW%;^7pF=oOyWMt65&>GEz*akL;2DsLC^ji+|+O$cgep6WW1tF`x5LXedVq7J-7UNoiYbmZ$T+2fK`oaSKDde9b{wd}k zFjp2>m4#MikyTl2RhC$li>=BfR^?Kwvec?v=C3R)z*UH=2v;$#5?qUA|Fh7^yv-RD zL8y5L{lT>0gkX9w5DW%0f|h#ZHk?Q+OBa+*cYopTr@8Fm5s>H zH-Qa+fh8S%9d-goXQjiwFWxQ0?Y>EwaqVEcv&X3)N>0+jXDcc&Rk+f z!ev3l1}svwklH(0Irh|*1+6k_qfl#%Q%x4s?P`?Y06!D+)FZ@T`WF2QV3UgRX+j*Q zkMYJ4nz;yCP^eWVrmAfClrxn+R8zPXPs}xVs#Z!>&5%;f1pPaTewco)5RcPGe&45$ z@*Sm*uJa;&@c##V=Fc@|=9i;<+M~)`Xsce*-vCTi)%Vaxx_0Fsra#ZNtwq(hC|Hyv#*pD<{1`Gmo3pjreU zBT`ug)su_YXnrm)Q#(*Tflz%pYSG;C4x;#&>EvSuB83PkMax_?Gw~dyXgOCYTB3Tg z*Q0t;xeA@z>q@*43Zr%T0CF7pW-!v@SYBCo6~6*JVI*W)w4QV)W8c0rfrQ*|7ybFA$(=u)xBVUi=(=sUUN(~JEHV@wq!Pjokb#Na7 zrlM9c`Wl;=<<;%Oc6-pnR{_3nDn8j)5hkBE-!tI574cr@&G)_N+d5y_w~-)`y!V4| zmsc3DSKcIy5iJk1pmdb?C@$URjGPU=%NX!DFW(CA?e*{wK7q?@zvsZmeAs^aVV9^L zzX0D>@OYiK9yOREbv@+RMS?`~)`O3I!|S~Aer(7?*Oo4kykCHCyH^;nS6*ExUOxHu z3m(e*1uhJmE_l*KLWva*z3u$Z;A^&%xc++Ec}A`fV3qBRE+HNBeHE8^KbC;6#%J@% zITv*Dy^agfj(gu6rF`zh*a1J7OnDy#-$Nkr{)TK8DK8URjJ+|f#t8jHt;x8wAc-bp zNy*}3@P)>p$@nWgci|jO#-%L!+ty@kfq5cZ0Y<9Y7)mK4bW%n{{LNGu$4^OdGg>Hq zM^6m*v&odBfzvxRkbb(j%fS30{9zZKDE1qe&+AVE>!$+o7Y#a<4EaK&XH3!`chRSa zXMp9?S;hy%zq#ns#4+IbQ#c@oT=a9rFmR<4$Cq*kV5Gf6K9yrmR6y>L(a?{L6br#0 ze{u)J5?A{3MHO(76BiJxoiIo81=4`(eNJ3Jv^rtZFO&vUUvT0A;(bn-^jtv$s=svN z0^(y%nDn{gv%tT0;sW9;PMGxhf(BE6=fnlX6Hb`)i^cQ6$DFu;A&c|{;*X%cY0%$r z!lYj+Xb@EnYuRW4dB8@z{T7M~Ku;%+bOFQoE7RwT#h}rMs-|3f##}Qs{;2$H*mu_92qXE{RW;7yxYKwfcF@9DKOhi=N|^v&W}0YJ)Z={S{FS- zG`p~TuNVKW`W%%~>3m8)@!uKzoF~lfLd2go=-I$u1Ev(tNmN4pA@DmOA1_=IzX05Z z@K+T6Junq_`4&O`zW@&dvk1h~@%s9EV7|o?Uy8u54El25e>3PCf%&UM=id#y7?@>a z`dfh~LpXlyNc<__05G4vq(2VKH>5cVKLcD0`JBf|e;N3G;42j7!7hMKe%ZiP!1EOS zB4EzHNCuVebWsA#yfm%^W?16}V3t+m7%(04VEXY_>a|}Pl4 zOLbi{UTYas-PnwG@^zd4Eq3yC*S5sT*InHbCtr7cOLV>-4doJ@FPqOOPl?XgQDHty zhI!?kE!L$iMr+tHx}3#YXWD6*60J1tv`L9pns!>FL~C3-?NFj6J1tNG$x!Du-Z9^f z;&T-gpDQaWD^_;YH+Po90`EG<;%`m0Vexl_>N7Op8)_OWV(Yq^nsLg!G!(3&nmRh7 z?NW{%AuTKkI|1{mmqySk+PB1c;?delwU@oBLmIDE(QTXRJGb{nZAqRaE}AP@ZL8MQ zx5d=<6m^v>uen*3?dlyJq*uV48!QVq(Y%~nbOHvK{FR-RZ9C#E;ncIjYymrVW!u)a z-X1r>Q@U%LJL{V|HbrZDu7xF~7SX)DyW44RiR}7p$C=_gC9aneY~0e^((DwVp{aWl z?kh~hEpKY;sOycUw9pHSQd;OKE%azg3%$22Z1r?k*b zpXtG*t9aRNgeO>))_0MfFZ&UePl`pyGx%|>>{5kxy%`i(FhT-Jln#1yMzx*p= zhhGc&d_w{8WN^w*VDhX1gsr-YCxbZyH5KHB=5K}=@`-+2)CtyF><7;bop^uwoPpt5 zgogH)`<@k{>_a|W&~;xKsJ>h3@upXoO5eBWyn$@!DD#3|^(x!g@utYG>YFNdW}Qx} zSDMm!k&|gLlxdoH_zb?3OOwi^?T>u_^uz<7JCo&mGOg@*UE$$0Y7FN!h5B+Hi)|J| zSHT`L%X&C{+Vi=6&{1CT4U}qag*YQlhEJ|r_wI_7Cnq-h&mjL5**Pq6Y~!J0Csw}s z^6-jjvGXVShbH^eF8%K#nV0_8k>RUzA{ht!Lv@ktN56V9&A0o&tS4hI(md<%aLtO? zk7K)IX=nU%?v9CAM%(bp!`AwN8_Ms^8D4SV%*m6RD}8h8`~D$(;LK}7;?=eOe?D{K zMD6Ud<5rh35%sdY2-;0M}>2!OHM=!t=xDH%>#ix&RngHPY~^q^3Bv#OuJzr76n~r~2pw znj4nt+sXb0rCRrdkhDUKMI}2R(@Bai$M$T#w-AQ(qvyCDj}O{@LcAL)Nc6E11&teNAb1{q z@Xe=>#23+DC$K~fhj^(@*Q5^peUDNaSfgwj*I^Nud{}i`M!#N~NtOnPuOi0kUzk49 zRnc#RJ~e&l0?FaVOf8s%)|%>`ST zH*^GL-WW&YnYSFX$dhg!E>mB9iYfxiG@eC3Pj}o`5Ta$^!0qXGOt>@6)(5v5VA1;r zPyFzyA3q%d-BIPo)G?mrGKT_n4rJcvsy4y&GoE=9NK>h0Wbyrjs!Ht+1^?cDE+Ro-}4I9v6`Bi?TF z1uAdM&Sxuc%&B(XcoCFsj(482cOp{Se-pk!1pfv$;2}lYNM|$CRyv0{eLPO2ZS)fQ zP)M$UpNZGemBa<|O-6ABj0lR zXtoCWn6}?T|4O`O(tno_AEAGhkou{ac&FVD%<_Gc@nPF$d{&td)OF1&w>KiSq7kUu znpL56T!E>pN;)?vwc=fxx~a@x+LW(^0Z-y8+ot^N)wXUb(@Pyy@Ke{6>8Vr7`04bK zeir>|TbI;oMPtNmzgv#;Y)djBl0%i8I;(K#&uR2CWt6_GK8~!QsH{xEqd)Q8gNoC5@<;_l%>Hs451t0{H&KW_ z`bjQ*^p838(Ld(WM?b*KC6x>@lgX_#D4P7ugxN(NErTM;-%J?s7;kFNZn^q7hWmnB zA{Db2(#QQo(dBO{6kYwMVj%7~eiAu!2m78VBKb}vU}U??d#Gshk+2IljrVi4iesCz zedRq?aUaDE?ZtifI=n65w|(4Y;6@&mH!U8=5ZlS*`xP2o-ZM9w+-YUjYDd9uGDoQ@lJuTe40hoR}p_kob=vxukDd>As4PmB0eh}5{#Wyh2-Cca+9rzKF{ zJ`D_iH^N#rqlL2H#lfyCN@MJ`5G< z64m$J;2Vp)Ck%NQ0!iile2ntS@!-(yhc1y+UOo86QoipP^3X&{2p`X0fBXvbZN7mWf3#RI=a(3H0o zd|gT&UZbU>yv**VmbT8u=B?Y+u0?0ZVqxMPi%UzFm2kh}SavMVuxB1;$6^kP{Nq<<%wZF+qC0e#k)0t@5fXB69(pj!~MYTa^lj(XPq$l zC&}MXUvc8n#kZX>>Dl7P!0b=9OBc`SAbdZ5>HP+N&?#WL{Ox7pKY~sJ54KB}yJ@ox z{68Sj(1WI9F-PPWcoM=i0HNvJx1=5SVjkB(`T_ZyPDgR?)#Wb!46)Y0{C&~n!QCFb z+k?%$h)n-^(8i6-eiFD^6u?kyopM-1JOn?&Sb zUKTfnueLUfFpcj-)OAODnz`M<9b@hwkv8?oQeReCyT;*DqTP{tZ-zV8$s|EEb4r=h zPitCPgI@fVPH&QP2J7*9*}@u7FrT*WQ|9#T9?EWs-i=>sO}){^?$#D_gTwaTws!lD^mcZdq5Ms4 zy=@(>ouP%Dp=5iOi}LXS1V0GdqfI^0{LYP=(eBPS*ikn##QFYugZfUEZ*x;aybPn5 z)VHQuLz6AvC22>}E}48}0S0NpNhYS^Uq~W{tWyL<)43K_8_+x;@!au_G6I`NfQaBseuy}JA6kD}jYPefi)zu2|b_BknT4zn8h@UqjxU4j# zQH1ph>EQG8Cv_{*>0_N!E=2%v>43Tx&=Qck8QJvlwSNkI5T$y@Y^A<|^-QV0k*U-- zu-+FUA9Og@!y7LReyj{Tj-PCmVrCokWS=gd_P*UPV7`Lk2xzqN+d?088_zOLL>}7l zvvCC1+0q=>%fQT^pQs&^*XyY{Y&S!eY6je@zecHyE7+Ligpd8fveIC-Jky%wo9?3u zNER9at5G6rlGNZ4SEd8%0Qz3Sqy0p-dvD%yoihzO?Dss|i@({P#c zE(GwI2|=f0KcEQhLa6BPD8S=5eoVf!8KbNE$aX@S^S~D}63X^O{8Ep+WhlI+f#igj zD?VNHD|IEw1gAxFoHG1Yd>uv_1O?^gGT?FV1J<%hdJp*8Jv@YW<1&|4p8_A7kL8ek z06zQ3eYi}%7s1DVO+MLY;FHgrZ#nw$Zp3??H{U0~r}IU(lrE9HpM!5K^(e=9(eiY6 zNF=Wwe1GRH9I&^1KQ-jZ=K**q?*J}z%`SM-{R({7Xkhq<5jNYe2;+7S;@Ez=uTkDp zxXkX@EuZS;Mj4$ibMKW)xT3PM$ z#Y^ME7Nt1C?k77VXGMHEsi_rlwtbp7G0binZ>|%=yGT%uE8=@KfX@~2dkxG^@lU`7 zPF%XQ)~g{`#2*2u)DhtSmIogKt}*C8KzOBrf9iype?X>>N5R@`9DpA5Snth{)_Pe# zmXRyUTpce&n2$x`@n134o%?USUaZfCZ`5`Mv1a_gUgvG7T2)t3wz5$kU9Lf0w7a#l zduwV{HDw--AHcoKn5k7&dv)1a&P^RszNt`t_e%C1Cbg>SEPJF@RolAkFQxpH?Okge zi~X=fYoxOGxmT1Di%zYoCR}hg8VkBI(eAcpr^6;~)%fz~=&c{;8`Gls2zKX|z0GW# zbZ@bMo;<_1SVngxeCx$@gFUg{f^id^<1w|2HfxAru4C0k->m-+BjJMkJA z;zbrdH1oT278U~7ELmJQz!rY2NHH285BXm27yK6a0uQQNGx$#(L3gP=C%Yhps z9ewXI(^V)icb|KmcbTaLf_|w58O-w#Hj{^OEA$RsgU#7du0Q=>1HL+gLADd{QjfgP zf=|=PuEXACrZ0fcbh=FJfeg$00zVm_cbSQNX7AUsy~{n1f{)+5z0SLwl8Z)R^T}?b zn7LfxU1ll-Ur6zdw#>8^d}GP?kdd#s%ya;G;Ffm5lkTVByG{ecKa8-s>@p8aAUTL* zJ@ma~J-o{}SAb8>0-%}h1prfC1^Dt1M|tKlQ)VyDF~Pgl$aS3J#OpXk1*Ky?i}A_| zStMs2=LU9>x4n+Dv8U(%`B9AcNN=7}Bo;w2iC^yBk>ht@BfFp;YA|&nmwXQ4UY5&S z8kF6eZOvipLx=ei0USrG4;|!d66rtb9vl$g&?NX=lKGAcpCimA9j;Fv0ez#x6BO)j z+Huq5%K+ch5#axm6Q=yB^5pCIGEh(&sL?Ebl=@s$_N0zL`U~QfNBSA!GGJ;c*e)my z*J$L&z^MQ&z6moZRyw@Qf2OzrIKHVeC|X?fS>h%azChgN!WW8<17GCC1;wYFFy-fp zgTPCixS;r!6DEDGcoH~Xrl8;^N$q%m<4eFBoVcJkj&S@y$Dnu(IDUX)Q2fQ=rTmLU z7WzhfBWF+=#EHvaAm)O;$4L`34o_tIOT{}uzsI0g0&C|N3&lF%_@RCA zg5pId%=GURuK$RN#3AJ|8&G!1I7FGw?#-0s}7rE-~;`z@-MR0lvb(Yk|WCem8KXft!JA4BQU9 z(!kq+>kRxp;06QV3B2CG`+zqX_~XFZ`SDwMD*R*M#}K|q;ok!{gC9zrlK%|wQY4^a3e#VJcd}K$ zTK-aC&Y65wBYiaj^MN&g6gUI?d>)g&3;1Fq{XYUm*A41-2#a{;edn5mAfqQ^;d3%6A3S6Z4_W<*FZ)79O zb3gFEBdq0r3-~o)UB0uRqM_bflc{Jl)UK*sy}S`y*Xz1F8``!;yDORtuIp~<5*s5W50!$f7J zoZ7KIrew#ofxD5MBQp!#t>he>NwW!t9Ow8<9>QwIdy?zyJg15-b{{gjSRYo(vqcSQ zi=FDYO*<^s_2ucUCcl%NyLL--I~Tc&x5UZUUArYtzV6yB(fJmm^BDOq(fRU*8u3eY zzQyjluvF*E8*TFIe2d-nUFziPFz9|)?2u3edF#jJJX9&!ISY2N9y`2`lC&5Vv;(?o zi}i?cZsKBHX6N=TwnvC@((1AiW;HP28XGHD)|NNcRn<4t)K`^NO1l~ua20Fns~W31 zdNGxBV*^WbQ@e`lYwLAl>dG4HVYz@a4$WrN)vv)!R8`*yGZ@Vsy=!(rKdZg-riRXI zdg8QeFeAC?9&;OU%Nn&S8_U~zF>y)hBMx=F2@_mJJewX7p9bsuSf-v{6b^aE;~Nsi zQ>VAvsQ)_o5aE-$Tv>(q)6JTOkopUDRlAKCslJc^y$ci8EYcNq-?aLY_z1b z36mP3Nofiha`Qb#zA0@&M-4HhO*lgB3h(@F8@u@drNcfvv!%JSwY4Xj#B#+5 z_O@KY?+ceEGp(qm*+dL?7zMlo93I-(WH3XZc`6H9UqZRJ=V z1B>0FP0h{Go}RLn7MN*FqWtC(Y^Oq0VpZ&vHepJeQ0ml59YCchm{e=hWJ+lh;>Qoo zzQDXmesimB7{h=lBLxE#m9)-aq_ZKwN< z`0m7ppqM}X)o?*unSBgwL8J@Eq-s8Liwh11e-o?-4%hl$eS9j9OASVlPiGC z;T2P3cXvGg+O1aotQ#iW-BB};UF{zl_77j`Kk{Tp?F3*Pk;(&9eR-39FxU1Go%e=blD#A10eEBpE>_ys(zE=LVfs3n`%DZxBx&K+_lvZsGey#kWfs*Rs zRqeYN6T9mq%TwdKD;%SYwG|J(esfcBrng)n$sM{&mcB;pwd=P3^_wFjIAsk&vTX#~ zh6mlEJfYplS05$J<7d3D6F>a>AOZq}}w9 zuQUUJ`k_f=JgO}D_t8iEhv_fCA#U`+{Eze@?-TSP@1N*jYOBtQJA`qDe}gSb%X3HA$dh`3nTx`(LT_lR*5 zzfT{Pevis5t)MuFfRk(b(a1$_{$%C2G>6bxG zm;QE)5Bh#|ar&JYAM`8GwdwD`_)zro6n!TBDs)BqNFP!-mp=HV9^!IapM-L$8%dqz zeEP5iu^!%dO&b_?j^j8mk9D1>tYl@4ZxN7<<2Y4Ba9NX7-k4U#v-(qGvdF3|wkk`k%EeaY z6035lRat6PF7sCw7T_wxRfMY;R|&4gQqju76VlsyL8vtct)M@c7Mu`F4+et4U`8-A zm=&BDoD}T0g11`1T~_cmE4bSV-fji&u!475!97-RuNAz@3f^r6-){v!UPC$teL9i-Z3(B-EQ8@1IRqkZv}3(0=ulhZB}5n6}a6B++hWhXFgibou!I! z{`eNb>^udUwbybLS>F$Y~IZOma{Ql6di~64|@VwIZZqr z0kGbs3W1-8<5>uE7E-VC>Ww6<3V`32|8ELVt_o0g_6mR>amGAcsR~drz6D^jYsawj zPFSt-$1m~myaRaWbsXAUl;f=+{q_lWq}}P?qbI}~RTTW_FT=3VyYDeYk8St8&)$8H zH+*~VJ$|Gb_NP|>`6l3x{E$K4(qVp4kd86h9X%&qWLkcoPfVVK5=!U?^hwC6#6nKI znO2T%i`l|g6^=3MeQHxO3V>G)VPO#72j87Liy|{l^anJ1&p!hmcXV>Pm>~-mm}K#3 zA|qtc%!o9U)iNU{Ai{4(q$46tMacT(dg}9jRi9hzua?%|*zB9ldyK#8}2QP zZ{9BpH<=%b@EcR0I}2-$5V)7Z!UO())A|!-C8y}tpD3#+p)4)lV_mI}Z&F zy28S*9NGGK*#*yU^i4winLheGcP*1I6F$@Ncvs@7#7M`le_5Dd=D}}8J@Ocj z^o!_Yyp+;Mx+~x_T{&?K^&-9=caRwT4fJuRI~WhXUSg!{Q}}(vNVkg^jqwrq%J&z;Lm{~coVm>((pA~E=XO?-n8|3Qp=|3Lo^A>Lp-($P`}`LN(2vNqsrCo%YD z(7)B*8#6J3d?0Tl(Da5^sejohSEkf*9^v@{zLy9hU;eyT` z$eHLoPcXg_?L3%O`r zwOcpK9ynZ1;k3zRlyv%-cmnkCo(WcIIwXTWCgx1~n2?ZEE^ADrkBJE)rAx$+?d1~?}U9yWd{eGKr+=wpB{q>m1=h&~2#KK=E!AsT^!hN{U~q=-HS z0IG;RyK4Cf9dI_eVo=n$x~{5V=lA05K$O1u#Y`{1LGIF5XBiNJ}m1H6B-FR1tx zNO(l`3-n9rc<;~!T=Hh3100c^!{*U{c|Vx9cE@qU$6}f03EU8Q?{z}uv%T2&bX|S{ zK8yp$>2M-G*{2kz=3~3Ee6oMTr@V+34y^gEP<-&DdnY=CrZGZ?(RHLe-G*1mjw6%E zKe{b&YsbXbqxiH0$}7-9bR_)SJbaz#s5cpO9o&b29J4CoKfuTP$@0pv3ZL!!ATE>d z4e%X6yO3`pE;{mg^ZgtK0L$!k-h9u)0MYr^_>sCvDEit zhCDf!DtV8>H@n;Cz=tLr;kN zZ%4qV+eOaxNRUY0Ao#{|-_{kx<>ji(6Ul1^-&orDs3C9eDDr*>zOj_=I!tugki+(q z&nozd%C`x8V`;ymhCB>;=@QBN9r(5>y6No$Fz@d*c(Cd6El`Y!fH{iqj*a+t>-wnm_@?q#nmq^|g@QtOuzcl2bizSu!2k`YMy6Jh#*N6wTZa*}+ zbcxE>3BIwEZ_tp3A|#bJ1irD9uNf~Wx_k&GmDdB}Smw2VH{{889Y{=6-#>wGEalsX z2fQvHUK5j+uN!=0Dc`RRd3fDSD(^qRHp_00MSB@fY8~C~v-SqYWnB(oYhCICf zN|&hpUIX7)##;n0n!0>tqsZ$5-*!beJ#YDbZ^)|{Mc(V+8%uv~#ZA@as~Sb#4)Bdd z-phu(<)g^^uQAGtT^=uA?I`m4z}Kbdrsr+HV}`t|N0E0Le1B&OQem&W9&}>eeya?5 zzd#tTdrpyV1K+v?@*YK;`F`+o@U2e3=Y8(a!wYo*`1staQ~d0wUU?1R+pp-R=aqK~ zd=W5EUcF*WC=Y{dEam$Y_;mRiMv?a{_;h}XO?uw)&3ji|-nE9jR}nVHZv*&FqY|tK z%TGuDbzEjUuf$+P7aZYeUdNPoJNUkdILfatp5 z8(%ccn8d9ynkmk%F~!;rHmr)ZIeUq4@$*F_L$Y7x7o&^H-^mm9#;FV5Xy3EVO4A&X-YY^t=OWUQ3 z_aMC9z?%?`8%InRUBD58z7ydV1M?GS%)oae+-~4|5T*>B-~9;lbE(FkLztgUHU6p- zW_!Z;q9#c{C=R>m86M+~nbMe}PBImN|1tQ9Y3NHk;)^_Zu?JTIbC%)k!1K{=1ilzD z=PArjpUi@NhV;9Ee}FJ&N#f4}p96-O3Xi|>E{hw$Il&l}b3&U(l(x9! zHt0k%Q_>8P+ny86O37%QidMX21kHBY0d2qt_Qh0;Helowu235=qLC~+l{UIWGgvZ) zhPPn!%P?tFI$}y4Y2?VZXjCvZi$?Wjm9=XsR$bFr(cam-1$K&hnrTHw+aB5)-P+vV z?Sfr9MSXRB+3HGVevKP)VQh_e&LkK&)QGO_MKH)Fe-9<@ zJdTB(_*fk?qutwD+uC6=76va8r|WJ_77x>4se|w0XWFGq)$l}b9M{*|+1%Nl@9B@q z>Wu75h6Nfgb{;TE3IA72)#z_fqaS>yx&CTXHCoWyG*zRMjdJka!dFhL8LruNAU$T? zyH}e15c8{t+QotLz%#=&B6c|7KWdwr2_6)o<%2Z;;oG<7R6mZuYdoE{KRx#1Y0(dJ zH!If+Me2f)HA5moV>0tXPo2hxY8asjMn2yP{<_Gy{0vZ`w8 zi=mEi+Fzaz#STyS@8>_?`r>JP+}`(vS0{+Hysr(w&ssB-mh~GLMoEJ)9mwn-u1SYP z-@TMkQ+?>zn;+_b)XI&?vRiq+BQ$w(2zjr0Bh9y`JZ&I6>&rllVOe~jvR?g>V!v3>nM9QWrtRQl-f%1~eMG3L23cmFK<6ROKj zX8A%FFdPdP9fH;-Y~@T;rcZJr!SHSo48yO)$5r~(A}p`U^~#h9tOR`L=|AJUDR=u% zD6oY2A5qw=OA7wQ|JqSjwzPb*9!bY*b3VWSYR7NC<GYvR zbRK=A=XYf$I-mZfLWJl~RvMgGs)T5%P72Xd&GIt(NROmaD1uUTshB?au|O~R#AYDmtD8kd3Sgzz_QoT->oOZxV=SD{n4p$-EJedE>^7XWnMRv*W}Y z9^Fh903734fOC|ldg~4Pwk!nt`v2gw=iqA zZA>N;WA!1%W3l%U`bhsR_?Z}hPtnJ~`vc=c_BtZ{Ntg^WF%YN2Czjh3a_#L2S@0K; zo{uun#~78{65w;)jOy-Mz1`Gb$Fh^0XTXL;N)s1ddjc_>2|=gh{7Dho{T2;07LDuyw3XSb zb^1aCC{MOC{G;G|uaN<78{JY|s^}8ep}*)fjL=2BQt?S9{J9o1S!q=<#v<%8)nZ0f|BD8GMJ`6s_dEJK*VQONWi$2Bs#PZ5M2A_TLQ@BjN z`QYQYBA@J&@X6=R_ov|7hIp^@=KC((aGkI0!$^=w-fHl*dxZge<$cSLH%0L$lK0dY z%KJJljJGa32D%C0 zyG8@Ue*$6i{yqr47Z68zy8lz&5nN`!+KD-4I^w+U*N8CXeE@v>5J!1va_J~9Q(4|_ z#J2~jhWH*Zdp)Cl=*Q0^VDsAe7%-pQntqxA z<*3y(?81|c<4ehuE~a1@#79lKIFG|ZIUX6C2YiW+06%_dIgUrh@`UYoIWg&Cxr;tS zTnk)n(BI>t=ZLK?927eY%$9NE3=hr}JHgLBV7qj&%Sg{7XFm+gHq!J@xahNlK2DKz zKVDZ3yXY5+p8=mT(!b!M=ZcqsJDj+5G310PZ>|^yUW94ScG$M-gh`(--T~a=#HAa@ zZIXVm$Or9SgC0LFlk^2*IcPC<2n}EM%(EEX_^)!q7 zz1PK`FUxY+;D69XFO++po-*iN5Dr7`ZF&2VlfDO%AmjEqAwMvfqUhvDl42W zd=4+`vrJ?I_Z#%{T=aK}JmAk5^g^`Z{qH@D5IJ(xrUTx`I&ez=r0)bce&(8rF@glBUg_Z{FGp=g5L5~0r z8Mw_Qf0LAN(szPBUBCXL{VCtXyFkw|=ywCpGVndXAp_qJtes!9$^12`wct+WAQTv zp5%;8j@PZSd?tN1=$FZ#?rasieNB8Z=miG70Jy}!%YaJ_Tn>DNfv*M*8@K_u(!e(Y zYv+euR`y?$z7_O620z=+g+YJ6LBGW%Z<~~7(mw?HeFp!%F8&@lmpyFI54z~v#dm?f zZqT0sZs5-`>C(k>z`X|kl`H*C;*Y@JHqyW0qVE*xnCqS}=#!nfkN5BI#D&1WH0XIQ z`rnIE;49=O7#7IBpC&E?J#5fd09P7#9dM0-Hvntrhuvh}ACuk=dc@%0?&7~y+zxz~ zLI0qOew%mz_yL3dc^Cb5@eSYu2K}&$ey7}P|09F`Z!Y>?@e1%?3_AOdiBFPW|I9~w zopGhVTh`a4XW`jWYVcE@iKl~pg+adnIBejHoM#j7=Le*GlfDG>iAMjq%EkX7u?9F~ z(AT@@9~Lp-MFxGFi~bMdR^Sx|{Vo^%qv8`T{Ey;c;LQgA*Ie|Ei|+$>8FaRXiJx}y z|C6k*IX-?3`umOa$6WmPi_^d#G3b`_tY-UtQcMND*PzdG(H|6-0Y7BWm$>Mk7S+IC zG3a$J`e#K1`0ECJvy1+DaWn9D4Ek;t{R`qA;O`ss2VC?oimw0<8g#awiN6W@?+p6m zz{d>y6W~7>_~*bw1|9@HW#Hq$rwx1x_%8;26WIP#%TbTtD|l9?>CaZcQ-Om9o&`M7 zz!w2$8@K>?x`8hT&M|N$@GJwb1`Zi`J@7mO^Ia^@!0o`78F&Y9fr0yhOALG$aH)as z0lvb(4*-V^{19-Zfgb^`G4Qv6R~q;U;5q{z0d6qxi@@s*{5#+c2L4arh=ET7w;0&M zvpr_uiNNg!o&nrtV7}Y*8u$|6J_DBkzt_O;0`50(4e)LQ*8}e{@CM-b8@LsCpMm-A zbdP~=2G-7x@3rjjahGMh8*zM36rXhQ+Yi30R04iqp?gLBKG*nP)Nde-zw5zm9=u(> zlWTsy1Jh~z4fVX$_(9wglfFfbA5H(FhyNcu^jr@2+^ z501a9*z_Ac^j;6X+k@}(;IDe{ArF4mgMaJ6Z+dW!^KPKZ@4@^QsU7QkqX&0;@GTyE zj|YF!gAaJ{Qy%;q4<7R1Ox0IeMwah<56<)8%RM;$?rf*mV@b>F_wawzgCF+bA9(PK z9{eW{PIKlaJOAk(JkP)kF7x2{v%r3A#^-VyZ}af)0)7nh2Nt8yUg_ciV3rw+D-wSL z_(8mb@-a;M)4*kzk2oa}{~ovsW1>>wEHwJxBg~zZq+bHO9diJ`M-yKS{8`{T6y6M+ z3tXr02Z6tU-ylyb{6*k=qdZRl-;ey*Z7J_K@OIGo{hT<6C8%?N`3;$P4)6!Sk0^<& zfUg12<=F`QWz_EyRo?dje-`<3N@n_x0e9k=a9H8b10RAs-5x&${s83Z_V^=k8`_iK z_nAHm1-Xgx6}|}g-|!Ck9fg+zzmClM7486j9yp}%2Y^3|=Rt$Qp9Q`Zc%H(Cfur~a zS)%as!2Cwb@BPew2zVRnqsvFFf}4OBDS9sO$59#G-d6%I2lIa_`a0krqQ1JlwgaC) z{dE5S0Q_&j`hFY${y6eKqSF5qxD)kRsqk^&#mGNT;WP;5Z*JY5A>bz=tVq$90>6%X zbF;#Az@G#iw_Vn+6SxUjx9=Wc&Y7sTq(21w-)OHZ6#h2wk5L|--_L-*f%}JBB>9g4 zf7QTgSTYRRUJ(m+cmAe=_VI(U9?xFs-zJBQ)rx2t@WZ;HT5>f z8YoVzz7}~`v}5ycU9_VGI@7iFYlYl^YR6W#^^ngKYnLS+SzlIB-&eK~Eg_oh(^Kud zjEtIgphYRFqN%-|n~Zxz^Y-rUXh&~6A}Xuc5|8LYnW8QAeb=>NE9*^F9oT`~9E-MW zZ)appQ+JCeYGr39mPffy*Rz{=aeQO4hoU$5diELX{llJp#(EPmb^{x$oJH74Y_G|d z#`iOG3$n@M>@CKQWY5xR5pwZHxpOEsw=o-1i=EBP2$=EMXKim_cJIS3b~ZM=+PZzF!OE#q0`CtnCO@?GLduCwC}HQ1Kw?26shT&lC< zjW+ppcE#>$F4fg6c2{$$ldrp)rB1%?a+W&zx~p00s7pcVE6w7px*!N6+U8E9sQ!I0e>4yV(m19D*+E z5?vCfr!GNBWIj$GU7~Yl?=&i0Sl~#}O~QU^C)RDSMDr}wIXRtlsi)3`x_O-Ly3~Cy z3LT>hOFboVY%eVJw25Pa!RgY=bb$&By!mU&Qctrv<|5et%?5A`MwGhyD=hb@c5p^U zscu$hOq6;mSESpHqr;VpE?23ia?W(labu=%=JQfdO*o$A{lSQGr_h-%)3=EO$R$&k zVwtXqGnAHjYT``y%RDu4=KE!ynm7|ahntzJGtn>e)WkcsoRL&m;JFvh2$JK^6uwxu zh8%7#if#_5Z@CNP%=B`&nQ5F6R9N7toimc;0Cc5^m%vj$XC%o{=1QY)M4{*1pwJmv zh0ahagfSKSj>iX2VIk@ydqJTyZVKZ@OPnE7ScozyJ||B;aP2r}R21@|s^au)RmcaY zigW5%gmzJJPW$quMa4OJ@L_MqIX%3PPc#+hhQwM7wcM8yhQE)|NNcRn<4t)K`_^@VOCDwuzWxQGQKz1{FPKXC zeMMDwH*OV-5#i^i%^_=O2kRPY8&$dNi2CTJwjONXt?k~Xe+Q~m^?eQeRn8x{c286B z>!RCifwl#t1g4ADUB9}arm-T1m(XZCdsRc#s=A7@m5nkTI!W#75*p|hcn9Y`j$dF%Vu;jZI1v^P2-?{!VxTgk~G=!n*lhE!zJnMATp@?^)z5k+h0 zGbOuiMwMXFX^J*&Y-^+qsji(RV&nGKX8!P3Rh73&s4p96SD1j>n zT1x|QwVb}qdnMlmM!ipx!>&|<9PLRNQ-b|yaJQg-H0dUB<#%q}EN#JfjU=WF z0;UWCzNM+Z=r-ARk{Y<%*xMe>PZiGSTI6=xFV9FpM?cZ`-HFh;6?j)Mt zv$LZ&mY4-&czd*?Ioh3=EX9v*$&b&Bmfo$Sq~D59Ra<)+M;D`*@G)c*NiHgMsg&7O z`31vHCcnSQU`uCnj}ypm>gkF0j=-40_#sxZ#ne!PZ(H5dvH8)PyNiq3ZF`Vi?b|oC zbx4vO%;#6-g>v+E@3iBU$v+p!$G1FpM9Lr_e&+RdcDDEAZ^8!vd@-!D5T#~EL}*2zW?&8I znef5a^;A0j{>WYFM(PMtds5D+0cYBrA0bCex31>z~Vc9YxWiV)1j+Bf!j9mQ4rRTkO3xKB!%7Re1yp%m5-A(0yTG@zP~WzNP~y+Z$SP{mwzvie`m?ROe^N>j^tK99$9;E?ddrMa}Rzm z=9_m@0wF#pUsUvGsP!U96II;L*76(du%uq z%N`0$4$A%=jD=uClX-<_N1FP1N3w%YmIfz72SaLvWglW% zrea;~SZt#_wD6Uo@?8f=vliW24SHAZ5u%)f{Ob!f4ASS7buUx*Z4-IH*z|$$P*{X; z1ta2PbE+?`_RF&6$Xu<^vcb&ztjmg}r0`=%hb>#-G?)X0oV3s-gA?y9-S(?jf^&VB zO?k#zH2KK%>I;+vkvlJERhiCnPEOUUK0j2yL*Lvc?y>J@_%S;#&EpSQvWy~h=-3;( zYFOWa)3PN3vhKPiN>xjolr5oCo23_drPcmtNU=gTmw+#G8%V1@r+S8z%~lAa4ZD_? zV*WZuN}YG`l}GG0wFdKKOkQ=-p*KNi-P2>|h>IcF<|rI|=@HxH==5Bh_h5S3^H*Is z@W_p)1KA6jP5`kCWyh_uS0aT0zeH0iUWsfAq&+_{d*G2P$#?6)z=Y>-0lEO_$&4>- zI|1s>*?S+k;Jb|NUI&(ZDaJJP>g zs5S^3D8P*E`~TQ`_rNHsvw!@|>}GcoLb4$Nqhj1Zz^FhrAqfEmHxNRiTtWavMYFk* zKu9*5fXhXV6c8;cSTC{lf>v9!)&kWwB1llQ)LNxhTP|K`Yb~PRikDhmYR&KSoH;Xl zW^y5YUqk=+Ik0)=bDn3O=Q+3MoY|dohB@|AnfX(+07<3mZ3J@0HN>U(?N=#ojNK`oc}z{_4WAV;X~02|j^%?l)acE!^q#1(YM`LV@&J z7U#jDofE%nMH=^Do8E%-_GEY=Y?HpAQk&2FRHrvDfDLGawOn5T?-O3=Bw79H_D@;- z2yR*NK8y1cffULu%db@eN9(qf8|S@I@X(hT@6+p>O0Y5QaVneLc{~b$TjH&C9U&>& z$X1U{PH%d^TkCgx{$?hX6Xyh{(V3UGO&(8nxAKusp>dCq&s8)s@-w0=RSDz=Zo)XJ zM;+a!vk;r|j0)`MqbQe+oY7VIco4fP)WGoYoNdFGvkTAM9TRYlKoqNp2~0h%M6n|S z0~O(lZAb~Jfxm>=h3D*M!-(gMqQ7d?55p+c5W6r5SE_;36@lf^&irG{`==G!6wYSBV%Z>*FTR-h+O#dCYE|O<;x}75wJ6jK+5Bgp6cT)}0 zIdctsQ}c!cWJjxQjhePw<)x+n)dGI-)Faex0~NJy7j2M?t(dpf7T0Rt_0!T3QRrO7 zd99Os2WwmS8C%pkZR_$9-p=!$-P+^}`&}e`OPvDgEr?88YyEX-pZRPW{@#R@)I8Eg z@i?c{zEGTix}_sKUJE8uy2`UdEyy^khf6%6pt=TX=bUlai)Kvg~K`xVO;Bz1^y+Z?)HU zEJ2PGI%5s3(}Gb>ocSAe9sSJDrhU2#tEPAlp^`m=%Te*HR;mh{Dq@j3gQU)<;nI7kcA^@E%CMQhp-hxS%F_xEx5 zOLc+N?9Dv26*crYYRJP=S@sdt{Z?&QSVRp$GHFY#vP8oyj*W8c_ab6s`?YDAmi%l+ zjc%!Jh5Y6yo->>U_!&dayeNq+wf@Dsj%J}GGIw>(5VhxAgOLrZ!~VpMIQ^O*ZHy5o z!GBX=AB{ytt+lNUY#Pbbp38VVG5C~5M?KRD^ch%ZaZK$S+8aj1@wn0d^f*WHy_RWy z$QH&{XazJr#TA}`c>vXg;&owe58J*KDSJO3;EX)2S;0vb*gW=jB^KJfqQ3bLUE0~GraPxVsu>`FtK>+?iPDLC#?>5hxe>4Uo(J_dWE*>Qz= zcE!+j{H{T(WzjURo-U6d9*U<5%^~yG7pm#)yW2lirq#pXUL9I=9ma5N|u^IgS z)IxFYPcNJ#B%NGR<&t0jO}|<*uU1m^`M7?yIOkU%=XOx%cMdFM*RYK#g>3i*g{g)5 z+|FG%X|i+w`3CamVHSp!fI+SB_%q6I%wvyK4egvUdcl*EJ%>7HM1ABR{2H5gBCTY^ zN!LH!$2(nrWdHU@9q){KYVxuDY|9=d1>MTCCv%> zGpEpUeuQIF;?!M=z{_oKe_qY6u2b2Ln;wE}z!_Xae72hQ;+ z{AcIq4u-y;hih?%<);fgXaft7M(0VS2l34p)cirnpnnwLQ>Z~U0J-`2T!qiI_>erc zpCo*e@kw3dVGE3O=uyC@m8f(?nJ)~`Ulm}yL_p&&5#WDSaG3sT0S`~*e;r8G|3k$Y zCg^gaC=l!V2MW80MpDQtutA)%6tL!1@y3R3{?jF3fVh(Jg^Kk*F?D@HMu9-&3R@z7 zfr7)s-eWL&CxSmH^#Kf(q5 zYEjA-PpJI}Asdm3LuzkEP1%Hb7Hzz4Js_>Bo-1-ZnOot1BdOAvUgRX1#3j>(q5sIa z-i0mI$3-oU>$N9Wm}nhHnvXu(U+?U|h6v_CE7=41s5q%2nutGifKt4mfI+MKX^Fm@ zXpFw2FQsGQKHnMv3*z~v)BIATlTO<50gLguJnjBKnD0Lw&6t-kwt(OP3#Hvyj5yLx7QxWfC7amuR}!fBjyCuf8Y0E}?YjpG*{TQ;1%m?;gQ! zR9G=#@M*UIwn4#upE&MNSSitbMc<#hSmAGeV6zlx*I!2%-*nKf1MEtL?`T0U8*e3ijl#Y|6fY!S zN3={~w-7B?*ao5%3cG`7rNZtcikFbzO|)9k-w8j8v3m*Ms<8WsW-9CfqGPc09MM}8 z_CuoJ|A;8c{c)lw_a}*7s<59D^zNa~xs<3AX7b^NYq?|mSBuM>v7{Y0}F`yJ8mDf&C+;nzXJ;J-~2_TD23 zdw(Vh|NcsJrouiTipKCaqR7|BL?l8MWXqLjx zB|27N!-(Q#7Q>06@um@7i+&*ZqXa*LXbt)S(R^N|Tn?8qYUJaHu17y03Okn&g&t&$ zu`AFIh)(5I$k@#aRTY;<6G!=@{S(bY`zJac?VspEg_tO6EqCZfm>2djLqL8m8 zit?xp1JQ5 zg&o>WoHDtIDB2@Lc>6#I;O*o4L@!gwB-#hB04~<&i^=3 zFrOki7dvzih0&*p7Afo*qL*W5Jfesj&k;o-Jx}y%h3z4V`gwt;Gro&Cy8-Q=FbenA zM6W{oCyGLNohY_ee}m{mh3|6CW~2QRUclHNiGBy|pD2RQJ48{ae@P$Se?B6L z_Vjn6ISTuf=p2Q8MzoT#&xx)<`zDHV{hBD`6&3U%Ob>{nJl#Z5o-stHDr_K8^fTK1 zl7d`3QN*(|h)z=2Swzvu&LQeoSPIcP#?B?WT45uI)+4SH#dQ}7JWB90i8jF%qKJce zL=hCn6Gi1tB6>Yc5Z$P-0;2GDD$zBlYNBXVmkIuKqPHOQ5N$?#7U^?{eh*bjv<2;1 zq%R-}ePu+E{{T@0$#SAii0ee}K)WW2L2nV!M;Kd7bS2_CQC#0d^f3%IM8k;dB0Ws> z$BggRPVzShe4~(CBk)?Hs}y#tz~3dhTwxoDK8~Uw`UAvuqVV%xk={lW17|{;g3=95oqPYHZqPYGG!T$$Q$e$Gae+&NCL|?%Cis(J) z2M$nN?4S-4FdIS?*PTrigV|7`@FP{=VS;}i z(cfe0LKNjPn&?|%$9!BrmN4{Zi}V~JH$kLdMDz(X1)`|8e4=QFlZhU{P(T#*UnFob zQPlfPfoBoLb#n!tM-=sZ715s{lnERl3cck--^G-J=uHY+Nc0H43nYqmuteYn!EYA0 zh3EqcTTb-PC>o-h6?P+03`VU)--k+~2+r$>BL3V=^aBh{L?2YxZA6b^XdnuG-y?bq zA)V+$3f~Ee2D$GO#^C=0q7C}|t-t2Zi7;UtLvVsuhpjQ*+jWMRLLZZTKZGIwqEdZdNBb*p|`kbi8 z;A(x1+i>B;Fn+Vb6l$GJb;c=b>_BvLx8hda4tK0O-tBQGxCglt-AV4j?jdU-r6?Fy z2dd{XrSog1mioMEX(m2d_>9FT8=o9}a`735PaZzwy^hjMAN|RsKUwr=Ed7CSfln>S zR131yg0X5rwpx&*7UZf0uicRr`*rtx>hLsRzY1 zdp3?vVje4SCOXoJM7CFNM&}DZ()-sBiX+C+ffN2ZLiHM>F<&UWz@6;r3M-;VnUQU@ zaADNxa{>2-Muh}$s%8ima39;BrH}$!#zFU|lM`30ajlJ7=e*f*3*vl!VmN?QHB)$l zyJWjJ{nb6FJL=tItT2vSYP<1ovU^}GF^}mu%STZ}t#z(*+-wYZIl>XtmEDp4FNHi| z9BuV<8IM6J=v6R57{|8*cH`e<6;Mbt4l*9VN4;3szNmj~%Ok88cCCZkB;f?U-ssN) zklSD@cOqj)-y=7BFt z;K=oB_jOwq3xz9F``48O(-GVdaaV4*UEvNC2?wTib)f%S#HGS`aaZHt zWQ&jk0}Tv3;|S7x>U~-N+QxjuJm@Rd$%)}L+FJKI*UeGuowqn{#ps|mV-EGw%fH(9 z>sR!d)C}PozU{O3(r>a@DW&!TxkYt{XFG&la}v_2X%`JxAEaSDmNJ zw%I1<3EPMk{b^gSc+3z{@rVX+p zYCyV=SWf|RqX>|%(X3kBU=SmKi_~)ABS3$)8QfBt$MZO|Oz_nOx`*6B>$D$(3?FAI z``5h@rgQoR@{uN8#oM!q0}xaf3a4uN*QqqgsXUyUPF&fIPm6?4bzObxubD_3eDVkI zM_nR}*LOAkO%Azo2gi4QdIt{)+fAp>Hf5aWJ1lHp*T1&q`6o3BKH_i(ZV(P!-@gvX zHwBngSbHyb1m7g`e!8ZA9g)9}rmwQZ*J#{@TZId^^sfu&!mM$u!wL0D=UT@)inM+n z$Mk9FUBaF3^{+c}i4<^mB0my5C|r2p^ts@%x$r~b!Xu~81?ru0yZDiC;j#X8LH?bB z0+sYT#TMbgkGp!%U$L1c#d>UhQW$@{tMUGd&E^E?DPjAk{cBr}k0L6F+09nrz|Z>E z0r|U%07~9A1EVB$yKrS&|GFZ_gJjs1dqTT#;g|jE0+}_A3vgn7bAw4=09bua__5>k z`H|F}AG?GfJ5Qe<6eYTp$8O;VCdTu@@2}sJsSJ#R>IioO{0p@J&ec7_hmQXBVJK`F zM;1=<6IVvQWHo;Acv1NBLjU?A&ua4Qz66k<{z^FVa{oG#3R}kUDo*eX=bGrX+B)~m zuJuv3IB#`)*SK5zt#AlZ{n=9FAfor2$fRPwaN+f?F7(%67P--QLm2;ESL5I0U?%6E zTC5yI-xMzVzJFbyKw%s-o=Ve+KL`)r>R%7!La@)Z|0rB|qN@x2)d(UpnuEglfv(2; zs}WGRlpDd@!Ua6Z)Svy3=8?uh`48Zuz9($I`(LpACt>?Y|Js%(bmEReOz8e19Qbqp zI?!#w|5ez2|Mc0`j7tBTu>HY*!S;v3_R-U4+idI~3ERg`pKS{G0esZ|Cv1O=zCRHO zd~biIjK%4ctTA}WOw<(qa>CIwvJ0_x-aR8)jd2ZB5|lw|vT~+!mU6Z-)G>?Np7FYEvCm&-ZUBWdSW!&7|DjJ7nPnk zzp-(6E-*2qA>Yi!ogx=L#-2gCwalE9f{*i6=UaKf7-$2o;=2K>#pHF%HUQ46oM#T{9EIbLo~d!~Gp^ z^A~<{f8i(n2tX3EVKh>yISQkdwI+`8Fr8WP`Wq zOZdVIo6%Dgg4va(#>I%PG!PDn+DEx_i^VpJSZBhs{R5HhsUq9c_>zwQ*n>Dx4Mt~% zQ*qpb0hYd8Z}S4H8@Lx(^}q|iMtD)Dub#3NKIJ3Q7`i*7TH(QmPHe}UC=@*ijE$on zLXdly$RYJ0-u$CP526HW_^O=XqMm>YcpoDPHxitK^#oqd_)5ys&r!ZShgffr3XfDg zUp|s3o-3yZ0aQFsjuyvMJV$;pQIx-*D8BtJAo^o0p&^P{>2#u)oy`Qbmdq(y2prYx zNAg^+9g)C2$Nh)Ja}*@^98cEsy7{H38{8zV?&87!K4J}!N>j9$Nb&L-ktKL25((UE zOqeZRqkOs7C|_RQC|_RQC||laS054K=P?m}P_8`upjVVJvqk9;GL|8A}L2Q!d6j7Q!p^w`=FFVyuI3 zE7o&>#tc(v2?EPS(Y{UeJ6LZ-^k(D_O`Z6IKyx=>y#&$Q^>t;rckrb-EO#Scs=#tL z@g;05_fEcKfaTtYr6MH%eJlYX`U9*lA$mWSA`son*h$csXc$8?BI*(}R?tC$Vr?+z z4+W)s6c7$6>{6mJSQ;ki<$}^WAxf_hv>vnunAZQq%vIPjqOiA0(A9#j7xZ>P?<9(K zW3-MZW**infad-hqd#a4)^XALoS4fM_5@)>lC1*MI-DFt7+QZr{O1W{J=b1=X`M|D z)=#}A@Eb(29_J54i}iIiF|!oDo+f62zK$m5T7CUYOof773LsamurG;LD(owwRak@U z04>wk!NgpHbzp?C=nt#MSxi3GEed)8Xv&r7|Dd@)*Vm=wVlq%j{7i+FQ2H;hbdKn6 zP$ejff$|}W zb!*QPEkyZ%lD$6@o}sX#L?QPjQC#;G@zKs*==7AHMilG(#t;plpAjulSRqj?mYhkn z0PD(#!p`MHaox3oE&`?g5hM&hml1`XRYZ}$HAKPRKot4gNECYRA_{*u6P=0rCknak zg6;%OnT+*SL{V<9fKs^}B7PR?lV~p1y%HU(FxuuT_wUFTA|GK7QSg(AVtv*aq9YNf z1zk_{3iv^E9o7pIU5j`| z7fTfUB%`~5Ez!>~@u&2= zuLB0tkXW2Px=fxtCHQNJP36tu@M;s0Um2BIf1YJtYg$GTX;$j1i4sMn2zp?@=I z%GFr^N3<06N9q4!tQ|CFHu?wQudwuu@C39g!vDs)RH6vh7hr72?PM&AC}t{oL>0tG z(3pv+4?%;VDZtB!k9fU;sET!6L>*|)M4gCZM5Evb=m3<*E1)r0r+S1a+V982ccFbC zh7LeIXMqww50vs#KzI(;s}Xi9EI<_PrG_Z#?)?N(jTxYl)&BzYm%lgLXyue3Tzitb;v7)Q@$z zM6o`05p?7ZP*?*f$!!KD`|Xq-i*>;QA0Rvs@d;GLZRls9+!=4rgjP;bUpt;G2&xA)S ztc580ZYxp5sQW={#=t%(1Klq8&kO!*paYPfKa2F^L|0&4H0p-Z2N8w-0-~_HjOdw& z>qO5&d;yI?4Bjd58v?&g7;;VzDEvPQl>AEpt;tZZotJ+7#e$9jWk{b6O67PtQIz9V zL{W|vL{Uz)pfx_UH_!nnr)885xfMhqhwXp3+^wJ_w*i#oh%%JtBgCJAatBR8KY5Dy zXJelSqUc9EL8;t3h>vk-FQpGfc_*N~E<$+|t;2Xiv=;4yXg%TFUnrl_Yr zoH$hRhp4I}k;t*Ggn0ZQ0ioBR_#Wp!IxykExA@rMf#?wN-9)mu2RjQR8l?~AfgigT z>oaVcRwKahX*D`LpGKpj@|z1}n(wrMhRJu(Km$Tp!^&ZzxFJUYqKRUM2%@-=A4K#b z?gDlK5Id*f9(pjP=X00vy_WvH5$)gr*Z7VMXA&*uo2u}g70xD%FCgG5zr8w#XbEbK zXen0a6P?SLm+0kKnM`y(&l2C6U^w9g`W*x9I52{6K>YxFw_TIqj2;d*fg z(I9qe3F`M(w6cFR@t5+V;4Awx2qOaeh^`Vlx!?{FMT72%%`k|r=0${^4=}4GyoMJQ zc9h^*<1760D18GjI)oSfPKLHaK@p<4=?ej{<2My0cI?pajA#b{6e(7E>vyKCjTbFe zo+Hvz`uBMeWBIUt$4c9#ps4wd0EI+1^CIV8))f(cj2As$;eRRN$9Wa-74p*w{|q}3 z5Z$KV>C*Novj`)yqDruhg#N`0t%yg}@Rjg$i0jomi`qgtspNad;oVgL=W-JBKQjM zD#Gt#GZ~^sc$M=N+zSc6kCopv&QOu;45iOmoIMMG|v6zikSqOAVMW(UPLjn-$FDNJ2w!;2>xB77@^TL(b=(bohU|TG*P}C%pF8AVxozn zvttJnq8KsJMA6x?vYjX*^Ib$SLflOhBMq7?V;DK^C5jOSO&8lJVdXnfL}L4qZBG!G zBpniuGjzWE7s;rF$T4Uvs+APj zjx=CdE~Y@lK$~2qkaLOjb0OE35D{{U({Z3uGW+E`J$9=||DiBMvXk(^B$PR@QyJ~L zw;OVX4kVjC6&iAsh=b(hY#7&cCui{JI^+B@oXh#O+co5_7INe_9WTPJd>A_Fkx1vK zlB4!+Ttj+D-)6ZYDG>*?OIfZG0f%hZkB5*DEhWAVIVu-7V=$>P6pUkPF##5wz<& zqbB0tkY4ni2f3wv(09M2FS!?ePxet?DgwMwe(3J}pz_;`kK7J2Ava2ATmIVRu7Mnn zkrpXF1X)Lw=P+3xD??~vnTicO!roUg8p#M7a_&2;4eaj)&mv;KGq;Eto`o8L;zD5k_MmspK7kxKE?gm?43EK1f zZ%Nr~aF8DIB`{zJVGxUw_MPDN1`r==!q%WfveH;6z z@86O>8vE$b@Uh3qfp89@T@HJGmqX6TFNR`%bf@nY$n_--eJ$zB=|x{0?h*P@A2&nJ z@Q=oDI=b`kUdX|8m&2Z4CnlbTzVSl3JAFxz>x+N4N%}78Mc)IETiM0CuKgo981awa zv*4QU{7Z*iQy=u*C+WMS7yllITwls>2#k85hvIX7FZxD8t}pHHPD$UCUi3Wzx$g?T zOzibL8iTLl-_&08O@v%u+Vgfv-?U!zy#Tqs|$}-(`^Ni@sk<`mX3j->)Edmz+^?ZqM)4*G2rhvKM`eA$La~^qrLS z(Y*;B-NmaIOs>}IY|CG}e|JF6C_nz4MGyKOg4`O5CLP%I;SDvWzA_=-oquB?*O&OW zS<+YDi@vRp>r4F(T@mrGvKM`$AlDatZIV9RitwYm{BD69LTZ=8UVdj{&@$=+Q*M5A zr|*2oA(0Md`lxRrChbP~8TPx=Hv@7Q;<_C6 z`q(Y$L&)Suclut3oKe2AQoFv3QE7&M2sJ(Gn-00Y^pAE)pV3~s^KT#IjPmWxzwxaR z|IlRl(Vf0x$QgVg#>qqY8!aX5ZH?$d74oAyeQ!d}s4pSLiCy2cn+$Q%dZkn8UEee zi+|0KLrCay*!6uP>AR&DeVvdq+NZ44t}l#1(D2WgA9t7E^^h~_t2ceoC^SRgZN2z+ zCgl3k{x(SZjQK=&{@o9`zQlv*brJtI_2wVs`sAOa?|Z%IyB~6WiGOiuBu4q&-HW~y z$o0j)O_IKQd(rnW7%|whlbCc_$UO#aUbOR67OSfjrjMlxVAfeXF;wn{;iYr{je8(_w-SpiXdQ= z-($V#8w9z&_;-V(@5jC9yS;`5Y9r*>f1R}8ry3BFA1`aY5LZS6&0{OwGC z+lH(R=XQPjAXkEP@^8D4?ases1m%F>%fzlP3^^YJNZ->!useNQAU97|B+l*n{tY=V zc%<(aLZ&-?=WG8ebX@bl|YL8>k!gZA1CpV z+x@+eYm3q4T#_7qI=95rj0gE+6hb0G@RPSi->)Ip;nelLDCvvI@OdpqW_I5AOkZ}^ zxba@E&eH$pW@mG`@p)tQ6K^2q#;MZ_75vC=9Q3$<1mPi(G|q|2W?r16<8ga%$28YA zw}e{CD{!`aiB1KsY+SOWx}k-Q!Sb*%p_V0$Rn_%uOsKJ{yrrBcmMyEPE~~9Buc{8Q zva*8d#gofQrk2hvDxI2N&?TX)uAxroYHlg7T)ecod|@>klV3VxOnFO7sIFpZOLenu zt0q*wu&$w|5yq;et-cr*TTCyNiURBqKzjgIx^>q~s z$|1F|x?w?cb<+aS>QG%}S#?clY*u(-W>y(e$5f&MP;X_;%bQ!Omo%rPq578Aqrmn0 z%VlX*#(CLTdu@*EQhRw_Qh0riXTtiN>ZX!V<3bxOYpz>Sji-e2OTGCs=M;OVWK6m6 zLhqEuCBeG->X7&Habxm)W3XB=bA0x=j4Q@wd68EyS_B(iFtxCBY}Wi~nOXA-=S`pP z9X-0Lu6$t`N+lSoZf>4fQtr#~A@#cQP(xkA!sfE_P<2^#DAX8gMrw5fq#GvI*R{0N zS9?d}|LDr#(ut83k>1e-GYh6po;S@qdRFZU@95$&85yEXEg%C$NeN>z@PEpTImL4_ ziW@5HmsUZgNG+&dR##b_F{iG+uClRVdU-|j=;DT!>QF;@eFo3O3}m9D%VpI|P>&gP z4V9*%>Lpd7Wf{;>Q@5~7;*uqe4c$n$gwSq`^bEQxqdXWy5r~rvYBA_nEnQPcu&lDK z8%FgCG^B3QQPsgvy9kYXJvW5+}@Qz;6G3{?o`Ug^;y~YoZPaCr8Sjv zg4NYky{ol|p2|QdTu_ZrQh+g_Tdfkmiz+>6>6hu}8R!H&s2RblS7t_eXvxA#-eZj3 z+C_no$-u}_UEVAjO%KLwvKfsPi+Z<@fO<-SzFCGQL$F7)-DN?axMW6j3C-4LA}&4be`I{P;FkJ$H~5UV_q`0PgZ&; zd|O%cP{>`RT9#JyZdDB9eG)<$oZ35~@YD|0RaaN%`LZ%|vU@ikk?T|Sb`dwr|35Ti zUU!PB?%CieD%^76sS8#TH-bTr&9Au*qitkT}bx=4V&LyoWku$SLm~#uD^yR#Ub1`bbnpf z@ly8{V;h=i3*B$@bfK=lLQIFdG$CjpRb}-RJ+yQ~AgIr-dQ{N7yrHGGdnZtMORF1< z8F?2C+RgPnRV_=pSI;HryMQIlWxcBrLb#9ZMU#b#Nq~s5(&QvEmSgUq7d)M0 zlsBU?x?t2$d8kq^np)A-K=p>n{osghaq9Kz57sZmw+)=7pYofg(L92M^vG$MoERXZ zLfqJx3AXk~6Wgk#dPR%#jLI6_sD#Y{hP%)mLobu=IAbl>1eXgL+}c?f%^`i#MRms+ zbdu4GDBYm9Gma^o;roW_GNC0R8R66z8RAzgZK)94-D=oRLBj>(emr6n-gsE+L_)Nm*T~%%S*rB#vi}QMXh#tjfucEdc!zTs&QTY4_ zpM9#UZGwi?*!1_M%~-B6cd)B%MYOAJ^#E7f#{<|)k0MRyyV^XluD09(I`TZL?r^o; z<1i#P4RU0yf7bEt^ib3Chdtf{gPJUQo}C|LFFK(sJF)ff&?ffc7LVqCILVW(PA^Ji zJBt!GCAq6Qvx^cpJXf*Oe?V)Ry`1d`E_W|t9h;fvceULg@ARtp%RSu%ta+YwyzOkl z8&$a<&V#NdxM_CXaT&)x_G%!`^mv3zk52kRQ%O@8PqW zh^IAeXrB^p4{C>>4n3Tx9eyh0fc`dx^2=V@0$H+#9TDD64>?D$j@a4c57SbUSVt0k zb9%Jl*$D~hU*WH-?aTQ53+4_^9qnp+H(G7GG;WhendiuvU80Zm*c!ekG zaZCLA_LA`I@TLUkL1(BayrF$^*wE~Plu>__C->ViA*23?<9K$H$9aItlAAZK^{lrxuKmO|ZZD=uYriq9#@+y%6Ex)n)!t;(_y)Agr(#hv(Bky4m&k{? z3G5{wN_p;}qa)@HPPj5*v}>6%EOoRp`pu=u?MqQEQ^E>w571rfIpAwz9Ytu94Bw$^ z{>-F6T6$VRLUsb>_heJSpmdMBBJw#JRNE%Nsy~`_q(R;rW+&F~2(7qjkn_-2A+~w_ zj?xuub8^ttHY(bKmKl3k3$b?3#jcRjjyC-q+e1sE*j_)?eS&xVkWl_gJpHh@9v)NK zD@uA2)f%?%c!64L+93ZSSEw8^YTNA&$~|jW&f4UO_n}?ApyD?Ns(;=GC{Ln=w;pyi zscn;^l*550_CkR4BqSttW~(2weVu71m$}Om^4#UFwpZeDmZT))d+1y_poJXmYFmrL zIZQn~q$$mlke-l^))&wACL^z%UM=b5ur$<&J0RqnygNOIT_Ls28AW-U4@*gdXAg2$ zxGOqR6GnAr#WnfY&rWi+#YN>$VRz*xfVYTJXQS6ss=FTPdlt}j9_6C;)TD$=Pp2=o z$yu%p!t3r2ooLF0JxXC_igJ*8c{uFkzN&2cgl~Px`p#^vN&UDp?L-jy z{Vnu9H@l=0tvj>89bk(+hd*m_rgjc{KNLS5YXiTBogOOPmCE6mrj5^5E~lKhD-m08 zWx`baeKkM9(e6B$5^`s58l)Y9=642#l7ebGmBEg9U!I1(NM#1uSEAaL!-JZ=+=;{T|FGzq%N7A(0Q;l znUqeC$A1+fLpR+&ovWW_d4V9Z_d!C6u1vQzj2QRMF&J&-T2W%$WB% z=b^X|N+mS;Sx4Q8;YWvOCPgh)4!N3K#p-45#qPzdgW5!%XQx*^w&_iPY}`5;@F*zigymRA+O58EVSP|^v<+F&f)2aREo}nLzMnw>O8W2Df>X15Wft){!1WoKEn-U#$1`CwmIKgtqX% z(|0Ugk?fhc&9nXs#L5D1D15-%96pNAtnF-XXJ>0`{)AaiC_9y^{6w^gj(X^FJe%xM z=$}Dx-Ue-m7VS!aO>j0jiz)u*m!ho!X~n49P-dw!z%Ggl;YIRQnUnJ;&w65eaMlwA z?Mm&O@QL<0VZXOD%r;GY9BWxSl3)ct_H3H(rN2Ar?`D6RtBQ4Wb|OApe9l(YtIYSO zyOyRrseFt)zK~pk@<}-7>4e0z1mElvO|E)>n$x4qPe^CAonH3hU8n(lgktTjUS)!- zBK4~L3vlH|_VQlv*m`BFyEfjpU|T{`e72I%QRHfS1mn@|4#zv5P|^?IaJ^dIcYQI^ckSMrk+mC5Oem}|5T3F7xz z1?>S5RzJ(c2x-`M)TWjk_bH|63B>jK;?QoK9#6>^dOPw14@#ZwE|1N0*CmvuqgGsP zmkvP0h1JyXF!Y{{$iq3?P+!j>vc)|59P3!cwIHsyD$F}RrD+>RiR7k+m5nRkN1K_x zV-?z863zmk+dS$4Pg8KEue~B12oKz<9Qdlqu<->nJ2A(o!l;T1JwH!rjxUuhnc7xJB%m*Ce1 ziE>5hu#PpNWY}h3yFWZ|n{x205N1vtEu!we##O1~lRY1!p4bZjpAZ@ve)PHE%9$%? zt;7yJ?G53XTRjJo;Xxd1Puh|MzvB6s+O`92gi;H5D*st|&sOM0iFaIwikrAynLP0c z>fN1RDHA3>LDyb)1aGTG>TE=a>){J7_hWQNi(8F3K$4sKCXK4^yT53k8jisg8_ZnL zHP`6ZI108*+QLk0^t8{!ZOZtGk8ACXX!**CxgPfRpeBWDN^TEg-kgsyRBgK)Gn@^W z15?S(#dzMCRCd$ym|kaes_K`Qez)3s$$?crVN!4qCO+qWwv`1Y>1y{=`h_N3qu zPVRhI^xhYy7YzVl|&=Cp!Aomnpqdu172m4tf) zKdwshoWQ(@;<*jB2!5z>NFbhT-qG;#jb22T#x1J$NwriNxbWqG@=mTu?M>}-n zOh}kObJFBzTbAqb>#F#K*%VbUAI4QxJ6-kp3ucd^S}9rYYHMZeZki)|55!{rT^&wt zZ$cew?e(~yx+;8S_-eGWFZ`N69A1vIk73X0@oy>ILVbZofOq3&Y-1e{p(H>is3Oat``ORBUb7|1nw-eC81wEw`P@5#zYKycHuhxSN%dIf$Nx@suB`LGnur z>h|*!V~3Zn@~>1%G7!s_ucAJP7O84UVR%%sN^4(&9;St(!_I`%e5wW9TXo!zx^Xq zU7fMjhSG{1g^)_H(6ur6(1C!~ zW&4cBVBibRwf;F9kVjvUd>@n}qIWscY;q4I_P%|F;p2A54JC(+Ll~ptm+ihbT$GuR z6V*gJ5OFy}-y4vV4@1XQeUu9dIYWnCpOM~*6O<{5^MmB(7(k*Mac=lP$sk@%lj_!qIS zfuEH4ZUlMba9~rnA;4QD{<#+ZC2S1v(-ME2g`dwiCT^GbR6jDFWs%ox@kC<*3qP7~ zU>xx;hTSUh2Z8Z`4bz6j#zFi8HvCT;PBI2s$dY`94bQRRB{sa#hJRth2Wz%;$QSorf7;3k~Y9Ekj-d)XN{PZM}BGD0!L z(0@MgGm`#E!0&)h-zCuXmjVAC=QI~4JRg{ry&Bgq2c`$l4SYK=)bTNy4wcrsFURlqsWDvKGv|B2|JSfSi@|lHLGJyyVkspHSJn6 zJJz&o&26@6*P7jI)2=nY*@oRLYksp0yHtFV|JjD!EaaD$pIMMu$dR66>V(gFim44= z=_!Vuu~xe|hW}K6lHDA`|FPC`&M|CJ!OHT6#j)0M&N1y;%Q@GyYc1zo)2_9gb4|O* z5$+76Tad16DaLodx&lpX%8YqsQ|cQl7tg`-%#|&3s#|!{tmewPdOWMq7@FEpj^|L= zw5cI+CZY`evt8J`@Nv?NJOL@qqqBMVI0cE_DRv1lfXbCk2m$Nxn&YW9h%lvF_9X%vR^ z2L_i@GY{2ORqGbI1OV=c4NvgUrk*dPMI0kwI@YCge7kV%+l6c2E?nzr z!CwaN=d`3Q&-d-ZHU6+{Pmj8OyKv21S@P||HDi??EtRt`)T)d;>@GdH-=m=Q(eeN2 zic_p+qNOJGwQl;u=BKi9>J>~}_bJyd=~CY=TwB=3N{%c(u-Drus=DV3Pf_8P3r}6` zlK3er-&~Q#!)lLB&J;7li&ga7g=<*n(akEiZx^m%4c4~{*RTePFGp*pp@mZ$yyW#Jls9>yz;J^c5M|LdAGQt}_JK;w?|yxy$!na+RW znb=~*i)Z1y>MqYS&O%D@*5=o?)^Z*YOHbO}S%iNiTcm`~--eeX2WNfJ>eFS}`i||M zT|Qjjc2!=VE)@qDE?ZmGis}ESL-t@m98OMpu2nekRMU030^Kc zjHRmlth2bYNDHuId%c~-T0j}5i1b}YJ$|Py4L@0J$LIUJ!D)Klb{%#4$%>A&ZDd&$ z*2#)@J=yTK1~?70Zsv4z>k&?mwBj9vD3vu^m9XRd^xe#R_8WDDc;Ve}mNs+`ON~A< zxwdq{z!Qph;75vMHO{{uEFP+cH%OBPNg3Wao}xTil!2Y0+Ig{$ICfF z0B_FZ;(aEnu8tJp1?9LLSX_)Vp3I5UZWeErHZS^*tnp2C?T$)?cv}i3x8{m%B;@qvO`zF=BT6KR%b+1v~YgP9;)qS(7tyi^MRP9z( z`>v{OP_^4s?RHhWL#1DIjl+YJ{KOk>R{}Uu@pE$(QR8QGQ2M!*ep3aDzg7;v`10SY z@k=S5Wx>nNh+ZQele$*Cxv*NisjvnwDUEri#KU4X9=Z?;PlyGY|X zw^rgq395#_mJwOz&w?QJEpZ@g)PdHhq6?!U=ExIw40}#1|>r z4i^q!@^HFpzzGKe_^2a>2Ef2gjL6isH^Mnf{`_~0NpM_~UF2zT(7sd5?sHr>h@F5@8#Y_|tAXU)c8l7i>=vwsA9Z+VeeC*e*ceLERf`BFEyi`!$i#s=O-lEX7zC ziRqHQE)w%(X;& zyZtOm$8~;^yGGwrKBrLM`#z>bzpEuZxKU#%v-G>zlnQ+jQ_2E;u~JI8z9=cBQon0W z3FwQAQgCa%neecS?Rq%HVQ}>2s!{s# zQCc%Vp_iVWM-qP~-$fKN6E{&z4ro}wbM5+4MpPw4`4=;|G34KI#1h5C5%+1xqW)Mu z!z7B@1oMjTbWr7d&XLAd@$VY=Fr2Qp4r&T~Vl+y8=Yv*3jf=jhNhXTg;bSIh2c~!v z;Ww|S4VYvMrFafe3>z@bzgxh3j(?ZnC3>;=j%bqjj>ymOEhLV~`mzItt}ucyTABTT z>TVBI0z;*l2gw~bQRIZmNsU03h6`I!sC4agk&a^SvV8YZd)d{abrBLQXFJJ0M5JO#bpV z4@!OGVSHq{halGhA(G>LM9A6gmYv`I+mY;c-+-K9m-ne2^!*ufE5WlLc74~NuNnGy zpTq@}54(R$AlGD925i^&uB4Cm=^pg`9dh-3(0A2^5&w+#+MR!kAlDate~|R?n9_rP zAM{aQ>8OZ*#yq|||0*EY7yn+9^zoS1gMaV#QQxJbBmVK2*n_^SAlDcFUY7LnnA(HB zKlD-GWW;u({iQ+|9o>~*DdfUB+w#}m{$7#vAtdpmJAH>B*O&YjV$3o8GeS~#`Ywmu zQj2Fgu>1ELNgr-6`O%%e!;tGsf1B=$_=hgvqrL@@>q~z3N&3(QdenCSauj3j$3`SX zONp0ZK=A-m{6mxAM|b(X8gk18UnX{aZ%X=5MEvMZ-}{j3OMXkTBL3l$9`ywv*B5=S zO8PJz=~3U?ebiS3B}VySI@6=R`H<_2e|sf;<9gBeW*_zWG0`#n8{dn*63F$%znzl4 zi+a)bY9ICGq0kKfCibGQ2y%V#?`cUN?pFEHUHjYHM}0m_qzwP^C4JA}+#&7s;D_8i z!I#NP0CIo38**VxmZ-n+IXfu%_c}gEHjjaMeA;bdgqx?I&I(f+!w$et#AOBCbHVE?DxO>n;}HG@w(mjcr?Xb?UsevrRe@P`O| zA1F=N>7(FgZ#yU*)Vv7)7WDA}`prFE{}*7Ar6#SQA$~}oE!Fk4*VjVGs%7AHy7yWRtS_?m!T?ag0;PxG@GoGr`^NW~tG#5K+o)bTh(e5H8W*T}ObqsMh@GM6> zaE-)Iw(u`z=K(({@qHHlB;KAWe&~mbU4rw-4kRvCWb()#KkrX6{|fM*G-X^YV4jow zWUhaQndaixKQG}%oc}?>Ve_1>FJLzVkD-9V50~T{@eA2Q;QJ;17R&WT?3cg~O8gEB z|5Elk@KK2`@2=v&7f9CrAH)6z`9a1!0R8>AMc+);3A|C_Yo>1Uw}hPme3!)cTKJ_b z16ZX1F7lga;m>8$fG?N$B^LhWtPD6H@oO#o`RqF2T8ZCk;a|n>0DeQ_w^{fL813$I zOyX~~@ULaNfxYH@$Hn$p_yP7u;0Y4{h=pIlJ^{W<;-9eav5zIXzzY&Tfd(RRI9Ls~ z(r4^diGP8GU&|%{|3TtUvG5nMIl!S9L!*l=u<+|yJ@7pef2oDvz}5oaFY)EwWgOUN z>_PC4N&FvMt`D(a0-u!l9Tt8I+YcOz`GJ18*g*?_8T$};h{XTQ!VfbQZLdP&4=~#z zwa*poY~Y~8PqXk>v25TC5`UtFe*>EVe80rM+`?~VHNcxCexrrIn%xNesKj4y;jdwB zz*{8#!xsKJwhj0xiBG%b7>5J#Z=eWdAvG6ytF~DC+{BaikoopKLFq(kz1M>w7|1RFQ^CW(qg?|sD-FT);{M8nI z8@m&DzQq55h5vo_6X0tl{?iuz{n)G-Ka5EH-&*(&vUh;rl=u`sW&8p72PFO{mg_h3 z@j>Qyg8!u?FMnn4V2`k5^yQNhKh^BpR3DGBOyI92ekAq~|3~an@P`hJl=mFV^;=ja zaGJ!Y{K&W-{B()G6nK<`Z?Nclg6B`>-wuA3B!90({z>*@;0Y3ctA+m*>i{m2_`kOB zx3Yu4mrMLVTlm}AXTVQNe9E7U{{{Y5iSIOH6P4f7JU=o&3H-g1Jn571IpFV;_#=T| zm2ied|1Y?HnSTlRZ%gt;7WsBIANZKWFSqb_uqNOyB>oBue!WgxJ}}hTKN0;*s?|9*IW3nuvQEH4Z91tU6Oy$ z!v8Ig%9DA{cnK3Pm+JzBL6$~G4OtgPxfR?vHMMlZ~j(= zN^@YJG`ioE`5wfcwm-||1OC?*K+;eSQYU1B|dh#HxCE8HqAy(d;o|o@GTsTkPvXC9x&9Mg9y0$A;9oAuAF;@P%8moClK3Yr{Lfho z+J1+`r}~pI#n!zNKgH}TRG$Cf{>c0>;P02@^DOfJWJSR5OZ-v`|9@Bo@K+MQ-opPE zTLnBMAyR(pEc}17dw`QA{$>lmlgF|&iNC|bSCm(PM@sxiY@z%*6p96-B>vwm*GDN| z1N$UCm8Xm~w2f?uKget=q~EPjJd^puz|WQBM_J^fm5YHVN&G?!e}Hm1aDl`RSoi}K z>YJBJ{1p~{ymBjWg~X5a9r8Cpc@+Gx#DB_ieWLO_aI3_p@{sX9@YhKEH!Rl==H(&t z{|x?KNuKn{_+#+*N&GK?UzIR@*|}fBF~Dz1I0^WGgj0aumN4G0z>Y{b3;2BrUkrRy z!iB&eOSlC1xP-3){zAf4z$YZ!0Q{AN!@&H@ZV^9L13T%b)p9W5r@bkb!CA<&VE8#bQ(U`(XL;ExqC+raPG@QtF+82kY?{J72D9X5QuP5v?) z&bQ$+MHv|O&a>fhHoRQIH;Z%1A63IcHv9`4{;dtaW5bcYr0a8;b*tk@Th?);E$Vop zO+L~#bbf`6ztV>9wBcl_=-v*9^5TxY}UZ1{&ZywisF+wg}r z97R7SiG%#}+VD6Vo?*lDZMepUgEqX%hHtmw%{IKlhWFd>Uv2oL4G$P>jv@YOclXv1r5_yHUKxedQ$ z!^dpcVLYRTVy5;p$cE3i;fXdp&xV)S@LC(b&xW_#@XI!Q*oIHou!lddtG5yIf4B|j z*l@lL&$QvIZFrFlZ?NGX*zh(Rrnfa32l@9m8;&xb=>w1WLu`124NtJ)A{(A(!?iXX zw&9I7yhXw^Otu3*hI@SaS!WQ&&waoj;x~v3@Ea!Kw}2Dz9q#g!1Ne4@#g^F228#Zt_H3I zrXiGYGw=h_^)~~b0X$vs?*={x<7b+{PXhk~<2QvNy1oPWx4?$}w}7_+^S%Q9hrk~J z8~LNX0#aeTP+Xr3{A*yEd5}IIa1*ehZz}Lj!1&MkR|CHVKwkrM|AFt5zWy%IPFV?L(&+}~xucY{Ah;Elj9O7cGe9u0ZJpI-rA1pZY*{s{2Dpxh|m&w#Ih zvxYr4o-sX$`4>HQPvvtK@V|f!eObU$q2I_)3GfKXzdGPcB>v67XGr|b!1-w3*9!eV z2mUFPUm)-v!ub7onZU0C({Gf9zwZIxjsDOe`2PUD0+nIZj|+}p4_qMl!+|Sd-{>zn zz?T6V?SC5ZA5lK{3;8R7={tQiJD&fA!1SBPB7wueSE4+O{C^ktpHlfe1iT6U8Rhj1 z@D*skbH(*919wX0`!4WW_%liHKL3k zUjaNG`i=h80Q^_T8~ME%csTe*c{~X0fHA|rXMoGVFE#uHz6k!H3vl~y0~bs9OW;4k zzxje6jnRxz*Etl4Zb54?N7pkfIpJrgBO^d@j;fk{tRGxrle5d zOMt(pMA~~Xa6aT$3;qJ&*^oEtw+Z-J$d3{HZ~W~Q@?(TOy~SekyuvAb|9Er9b)G^S zOq(fu!`vyAc*ul`o`2I16#INS67vmH&it)(OIR1bEeLmGnMv{ zudl%N*{ot|O{D>vITD-VM-nTAY%{A|8VXf6w3IeC*NJ`NSv7xaKvhJ#u9?{SUh~0F zBQ|B9Qroa_%48M_>zi&*T?Q4+fQ5B6jrsLU8k<`Rm)6&dgn12B`WE@X`u^VZ=76H= zdhC+Mn#-3}^DVv$s#}aL)hUfEmQ;u88mm|{w(^dk78FZpYB-2j5LB@is{<{P15=j- zTb4tBTr&3P*IyrDeMduPPUHn5*0(fd=9%vtDYL#0gI;&RUqoSj9ftWiY((j7xveG7-sFS|1jRBfxO6%Y0}#(xSN^QERQwqS~HACWre&o zyV<5)Yksp0yY|HRkrhLLmXF&2ht+?I1Qgi&9zTwxlw<=hNn z)XU^6%qTX_mUC*Y++FH_mMe^$kF(|63}nv*pwbY}Df|R~SW*XUnM>+VX5UHDeprtq3oS(#o^t#0+Nu zSgtVgKHioS$}+zq5{oi@@Li-Cts>J0Z$+A6BhzR2$Agb-&J3uTKAVST_A`Ap7tL&E z`fNU$VKvh>pUE@>Yo>ihV@B3Yn$y@;h-6WC?UH8Z&^CL?isX~#L3%0JW7rs>4cz{_BxW{J8rjV* zWbGi`TwyOKFEd35);E8$txHEy|ZEHGm@qtLp<h4lk;tnn)F>{bocgMOCjx(nI?w)le zOgkzjqDxGk%iPkSR^~MvYgK8)OhigKrs^2*L|x-ri924E#LPWPIa=zg-TpG7xjSl= zltuWUv%bRB)*YEjB6_-mQb|NZcRa!#=8hD1C@P8Q;*LTk?$})7jyokBjg*gaeqHxqyv61nBR!{OY7^au;WjCZFSwU1$EWsRTu(dgX&v5T6@ru%I6>I;Q{s{j67;^o|IIqg&+0u zHTXnR?qKKyFAX;|hGK>%w}4xfu@=BwJmdqSS_HI!Ns(M%L5$QKbyUipRD1K*m#)x8ObPWnGieEiWsp~5bW1qXGP*Y7ubEkf=VqWL4RpArN5u=y&#Sy&> z4_MmUJ3FGIxOndS2m1n z19nO6j)Yd$RnjKTMEAg_x|J*I%iFL`D>PahYVYjAhMg+3BDAWtL-sGx;nf{YaYC^b zW6bq6)z#JWiZSP$Q%~jUxK$$yzP%lfhn+-Zi$t~cgxKe-!b4M?dR?>LJya>f($r6Y zt2*^|jL;l?OXK-YyK$~G9<$2lyl%K|;GxD43@4IOpQ}V~cQv|S%`Xkyd6esf8M4(Q zTsJ}qUy4V~t^iZ842;=ORXzA-OQV#S$f(^`!K3?R$*Ok09ZhG1VP7HE2MosLSlWX|q{+HaxU;JV zmqjtj(JW3NcKHn%+h6vojbt5JOZg<7d$&46t=wkTjpc@~l^3AP)k(`tp;I-)V=I*RC=Kg^a@Nc07fVMfZ8*T_Ci?d#jy(}~8W zq;kTbxBJz>a%vDA=DaY8Vsv(wHDyLdkto(ho$k~rD!i_*rn|PGS6Q*#a#-n5hxa!K zjaH(r54PEh0VYbsvJpfqizi}PToD*Z(3Pv1U6kyz8d`g>q3^IFVmQX|=%``a-O6&o z{L0yMS+`wg(+I_UKxc?ut7Ay=T3zbVvo42OZGMf7j`7;b9k*g5>l!YoYzX&Y=Br~= zoyC>tM8y;6#0{6%)z#S*r8Ept_wH(2T$vLD>Mo_1y%CE5L6vwVC}${(LThN=PPocc z%*;F{Ha5!;w@j8r%*@@rOvT1twg3}#Oj|ltk1G}6sT?~L#hI`YvgG__ofx1yy4&5L zVVeZYYdGAgJm@PU0p|SKjqGM$#bP%@l)g?#Urk3(RC|jI3@l8iBavOI43GsLRWWG) z=6peF%CN@a`*RyZl*<;cu5fvvwJ+4<%vK!cTD-gMZ0u}X8V)tKHn%qNJ#GjcPKC}6 zuB+{7b+{sd@vRx$b$v_1+_&5@9vLL-0u3=LIDR#QAH6>7E}DP%M&z>a7z}%jl%^cN z&RT{^4@YW8VTS5aYgkN=8qZaUV9<>ghmkG%ie-Ir)`xCV3rDvWQ{&6rsQ`79^EPcG z&8=;?Q><<1?iS6MAcpXUyVyM|5#jSue&s7M)?>0D3C_E!*YqeN(A8eu)uqne_t#*9 zN)fhYec~pH+#Wk&4SPyIY%%?wyT6+}PNZTiPeElwF^lk$$S2q z#?JO|lFVJ99!zJGWFFl+dvxz?)jf>vogI!U2zCSYc#s=v@25wW4Gu|@L3*RO+0y9jk5Hau@zCFyWmFJ8>{_eB^`n$1q6oL&(E*XMLxxjKQ?KgM^m$QZvr5#U-2ukDh>UK;|CPP7 zStzcLW^)g1GotZ7-AmgP_5t_QHZScQd2j9FsrCEPe9J3ysw&Q#m|ecxE-7Cbo?l#m z(45*zZ%ZWCT~rk z`mi7E5#zns#oE@K_if%<@u%mkZ!VYDjrEBe&kKlrB_&AUc-e3;H zxB2AXC3{7X6tBY1Ct8*a_OISS>{KDlTR(o``P@T%^5B&5Sv#4(d7F5( z(vD}|pyY4$Riy9q`MFQ|cGktV9PB|(Op|}Tj&?{3A7u@W7mPaX za($hHLnuX&#dP5`H5i^hZ%cYW>OItABh)|P*<+~xkmd6+w>jPxF?fl8;~sIz;ZKpa zQCA-u*kz|ZTPXQ_zVQRQ(sE>e5RW|P?A+H$$n%`eES&o~ry#tz6WpElPS1el3(vRlLy@x8K`uNkx-Bcbh2@kM z@c4*15AtvBCZFu7ju;?+I?GpNw5YI;4f>aif2ug+kZ01Rc1ok|o#{w9M{42kw4Op* zTaoV8u&(ipfX>l4&(SOoZ(;7X%tFu3F~G5fX|!PK=z1a1yIRy}XqV}ZjS zJTvbH(eo#*S{x$NDC(07m7IaHYW zhub#axySNOeaHKzXVCKG=04PZ+vaO4yxTrC#mfJ@|M>ozyaz)|2EE??{0CP(7DyX7 zZv8bCQ?~smbZmeBW`EvL;l102eEU|`zjMu-0zLl1z}b2k&O>n)MW~@ddW-dgF$iE$cQu zaKF_jj!oNEj=v>4r|f7AOnEeC-&nY;9KZAO^;`F4_|C4pI`_VP898>}SNB;tS08>o z{)&9`W;s?qLVRMNW{NfSTK~-z?>ybVp5ZIJ_PfHr@!dBE??Y{UbsxUo-)9LuUP!&u zHp&*wx~i<-Exewmw(iQ%uD;K75U#>P5T+s z(%Qgy?_U%{CU%7jWxpo$H5<``sTR|}Has75 zh01Y(D>fFdwPCLq^}UY<>|-(qisdyYtnCk69mw2d9aDUfUFd=Ri+sBvePE-EExpLz zWEI?hk!O=Nwf7?XreD4ythT(n%l|q)?Pkv{C!t(wWP3~J*nBy9$+c;ltZ71CTYx&v z@gq0e!doT>jtrbg>+$8Z^k-CU^Y+P7nC=sqI|~CF=3~zQ^r{R~c2pb)ZOS&)#Ykj@g<0v`%8+0#|lL0Oz1J@4r*Q!#7lnFQ!ydwBX3mmGSJObS6 zOvp2o!I(7IHLqIOSLw9}-?rHbD|SC-Uk>VZO?f6h2I>V(RZh(ATNw5XzU`^p{kW%U zjA!t552aM@PMfqY%QN_brm7}ohjaG&dpv{NJh|JfX_dRzA;cbh-+l~SOr_FZ7)IOj zAbo#9A5&+_1>qgR{p_1zVPnQwgX1mFvDQ=UTeoM<-)6}YQ-7Iv&RT|Qh8A6e>o2h{ z9|H*!D+c}cHQ~p`{2XEXrPha6{ydyBc!VblA@AGJW-3$9lBqN0_mOfXQua1@r9G&z zS77X9nzl?+{oVg^zwFB~@7%g?%UHpj*~exCJhE>PzBioFHk=;V2aC7GzVJLLQ~2hs zE|wNpApfQX3MH;X@A3vLh!(YVmmFg;KOn_Ae6-IReBXLBymgoDm$n*-%NeuQTWK>r z+MN8U*~R`X7`4*|o;*J=@K~0#n0d;6QL&#Qi9zq+Pop)51Mw_^A9oCRT-bCfS- z`Kj?Xw)sN>yE4_hZI>teSzk-e9&5bHt1noxm2(?%mSEN~v~W_3H7%$3w#{kph{4>F z+{*ngJE2F6Wtg|bzuV(a!#vMhnS;8+tU;y&E}h$eCX+e-k{TpRrw7quuyvMT2@%5!}8R8m?hv7eXsv0c4Q;aNE>iFnC9>p!+DdWal~h)uPT?e4D84aV=Kg}Qwpt}Hmr)aV7Fk}x>Mx)0yoaj+tk`} zue7Ve^}fU9OdNBvH!u$i3a{TS(VVd@Rf9g8`GtN}0zWfu8sf5o%ui6xR&tmQX1)F~ zwDaxjb-nof6|65?&hlCyAEgH`pI*QBD3PBV_EtsBK;$ghbM(*x=MEtLJfz=~_Dud- zpUi`teGIAAQ7HRUrp#Z(pcmTf`UG77It%q|OS_ANSM2TY+W+!UO;!u$V50bwUVkC< zi^Lb`cy9~KA_sa8)nIm?wg2Tb)EmkrplVsoofpVD{`59KX3N&mN;@$ij%EtH2Vff4 z@j4vwuJgrQr^dlTSj*4?8`eEkGp6NgPk4TA&>IkiW48@07+L@eUTr}#$}_M6c2tFO zW*MrxPu^RrQN_u-YN`EOR2zs6Wy{^r_vb!!2T-~-h#jeH*+c2M&*D4!3i}RwPz>%D zh2gXTKl-3TIcF=xRi8xoyP$(Ulo9VY@mKh=!IkEQ%KEACqbyYVkx?Cas!~0N()WrA z&(rEGJ#btgKcLQ87K%$_rGk0TLGmPOPf}yc>I{zqHXBDbEszj%PrErRG-9q0_f((a%6`TlqpiG zC8qgkS3?UGzm-3MF`pb-I01H|Y>jqC+nzX>iP0HwPz;8(@-G=%k`u6h1ijyHgxJRb{LNGrhphHZrX(KN&@ zN7~DPxK8r%I$_Db>d$@!M;Sq}r)iiEJ4d>Ot1b7h$7>7qA3@r=M+)t*^0&` zV+w6C(tk>X;t~DQeYPN2fNJJaJ$^QL<+|IL!V&&2zd+H!uH-f|vHa-_J=;-%Qc$5LCyKZBVJ z>EBx7c;fFY={rmO-V!CG|6p-eRuK{2LM(+JJ7UO|zVn!gPSWStqDO~cK*Z*GeZ(@oo$se?>3foLE@AjQ zA^M3+ZE*z=;a3t*5_0cJvCJ0N>G11`Cu4sPV$c>h6Q8%lEkroH`vS4i7GEKL(-L1L zK4*yy#1|}a2hlIYokaM7{RXiD`!Nw$*y27S^xsH)+!FT_e{P8%5TCZh4~bRqu}S>2 zE#&P7^7ja7RKhmmxwd$mi142f7YOkLvB?&{AU%x5Z52J(egY;<^&zxiB>% zx*z)46B{jY5)pDvAwFiQJwQ=km85@ai2(6umZ%~A0_}nLOG_*vK5L0uVgvlz5iMJs zNre2fh>ge+@nl z5p&}Uh^UtfiT`8Cy+_4smiR1bG^R_4$Jk;W@qGAkBu=r#HN8s8U)8L)ri_hJ7;#KSb?-r@gEthHGc=(KFA0_Uz4O+@b9eIIe2&8kKtv1l?v z`~db(>=ojN#G`HTFcFP=E3v?4RmjGTs(>>{n^h~sMY0Nn@YyUvIMI|@hOe@W9X6Q|?tnWq0v{DdvuAYLxSo5Uq}!bL=9@-HIN zLsiK3fvT3}Zxa#kA%Y*Hos7@c@neZsq5mf$y@|xD;Ww9vi!f_JV@Ll_yjB(^8ilR) zVudgiiL_r7m9+apA_|*+B*l-={}WL!Xj*ujE}JkMrrKgI=?BpN6Q8uyUaU8uDtP;NL#EY!sxCheqD%bh}d-X1|p2`CgLNO z_yX}=OMH=t&izZofGut(eiNz@QCN2pzl|hx{Jom~rjGwE5re_^h$#H;6Jcaqh~Gn# zATF@QL&P*BO++Jmlz6u#9w+X##7~KDSz-rq6WRlD5!wS0{7(@FE%9sO77Q`OLR;;} zy2p}!KRMX^f#LsUix-H$vBUuJN0>4YkF~{1#O;=NnfNe@ka(&s28oYa;!WZ!7zcV*K#{(ReH(1}&Qiea8^dxUzJ3HWB<2b@(LW4)`=B*4W}OBJw|l z_)kk5N&Gpgj0oeLs^g~<-^MsVd=gnFo`M@UA{xnT;z-=@QFCw|-(cj@rEb@u*Jl$^E@O50AwA{JZXVj>2oONr2T z9q}GZTtS?T`vHlzxRwaLK1aO65;qX%;$1j#jxD}Gyw4K15;4iRjfnfH+leP)K19TQ z)Sa5Xi-_ywp35g&;+s1DyF}36)A8RYo{IjTSPgq8;`b2IZ;6MA6}EU(hyPg8mUxUf z6Z0Wrl_h>g#Pz=-!sh-*hwmhU?^zu#_md7-(hoK#4bL-tfhGP(L^>~OzQ5@3zY@Xs ziVojRT!{Mt;xvo{#M5yJ-EDW0woXJCFrM7@k5o`G?I zc$_W96Hy;I#Ir0hfrxrOlz6r!_ljnHPa*v&i~~BpK+{u+h%Y48TjE$ECONpJI4I8s zUu9alwAAWl77U8OD41ik0@G8gz*wVT#^GFM z{#czhO6_1-WQLRW@j7ih#W`4Md!4jr>a=GZytL5(Rhbv*v}YZ>v|(B*?Gl}K@xe5BM zYMpk~N09b>opvC#X`9AKJCL)n1(U?DWZ~CnB^IPsiAhMa_6^B$Y*P=9}rre4nM$KJ(zE z?cNBTt<#1wsm%Askyqz97booZ(ys7a>5K%Q(rVyc(!o*#jck}2pVn&N6;&$L$ajhY zh^H*LD_b-Ct}KX1yIw1VGE1dGcr@f5pT(J;C1SL`c+zKs2(VXbMH*78h}k~)Y(l2p zq|?eM@<7dAb78L})-K_NtrB+XK z7+Z#PqvsGUT8UMuRl=;OEGQuh;5?mn>%mLgy@zenX`i3kw5KAk&VlU0NY+LhNyVg| z&Pi*7h_YcsFkNA{r>0q~RPq*NwM^w|GI&c3A7tnOZ%}KE6!q5#7gkX*E`-Rt@vf z(&4H&^zBBER-ikz3Ybj;eMP=&RiEs1uk5denr}qo~xWDc%4?{+SDpy&dSC)B~j%(T=<+;;`)Q91aGTlbu4t0 zxKS%{Lu!>UZGtT#ViPxM1wNlz1Cw7;C%w9P)CKpI?MOdo(@Sq{UurB;!+hW9m{_E!&H+J`zuzd@({-v=*kxAO1Q zY2Wb?qxccJq_jT95Zm@-ig=Ahx--Iv;H9B?0d9MUr()0=9GwbU`~nd)hc}B z;HfYOh zn0c-}t8nfGeyVkNBDFf0Rxtdo=x17q9Ur9od-_^eTV3F%fHns{3f+3m=gpVrZGYIgVx~psnx*joA~G?h@btu zPW!pkrfv33dWNPSSpG>X@W<3DV7@B|Amg#`gJ0Hayp&osI6-y})D^k3S5m8m zSsT$0OkUFpyn65yaC_+>%ESJLR^accRlppoWIbT0s&s~`L9N5FfXW3&TpRs3-%^aVZlQ|)CV&ymqOc;X-C=l>&D-Md6{|$5OpgVi zOmD1C9AAgUCjMcXo>>BX928vwIa&#Pa+XRZhIOCjt=1&113qhu)ge{2z%fMC!pC&t z_(m=^@ei{W%=X6-G>D&lm`)qt-yN*9-5Y$LPWz~Xm$uvXr|PuvU12KoZCbuNYrzt! zU&+EhS}TE%6H}>#S@CYidyGySA3mls?ZgFetX2YFS*B8nxCL;$P8(|rQ<=6|02iah zMfZI(wG#MT^k6A5dS_ypEno1?iCk$1xI^?H5<&*mA^&-wPtq8uL zja4L7Ljmnm4FxCZ#PM0~!AhLtqDuS}ojAVnjZOT+9EZ$_Xf6`R7go-vE?NP6RGdl$ z%qDrbqX1R{s!q9FD}j5GR4QTiNj8)S;%CEEPZO~swP|xCat`X@RzS5*A75o3^t{j4 zY2yp;gO#>B7}n^t@iqCuO52?Uou<>qm+1#9ZP(u5`bpXwzJfnkX}dG9I-NGYxIb8F zyY;{X>a^i8;9#Yli#8s_&t9(6hF5}vl{TLq%CyhXX~P4;!Aje$?-e?2 zcw0DFX`kxkJE+r!Cx`O?LSRFvVP&hZN^n|PI;*5uq*rot?!K9e=LAH?A(@NE*jX8e zSQD&?cCK}pb+~neHN{h4@nLXlLzl3|@%SkWjLwaRA@~`8NHN$vo|%*ZS76M<{Bdc{ zM^n#CK%mS@J_6+zwK7O%#|@Hszypw|Jitwk%mduj$UMMJ%}k_czXXqdL_DpTOT;sa zI$*TU>|P@}gAfdH4yrItsyfNkYMfNm4U$^nfk2d2&_-$nZ3-cdTFf9qi%$bTkQR9v z@Xf{oyWbj@GyKD0Z8I;ptCk9x1(9_!<`oCzbQAOSl5&_+J6b@CR?kMAo%%w?w=SZeU;vS?^iW-6OBV4Y$bp zGir_qAAgwgi>$jWdeRYPFGvqHG9Kfj$U*_5&lY8WhNn?r-ivTEsxhpw2UxZpJC_lk zh8s{FeiP{zrH4v+-28F*Owz47gVQBkh8E_{BWVny`b4yHP_>q<<)!}|% z^EtK%0IB~Xjdj4X@o?`7%zDU@Zp-rif^uc}i$bhn__yJXlK5*&^b=pTq&u;)L*ZtL ze6!#_iQ#{;#GORkQfwr?1GlHd?;u~mvOG(=`J&tx8U8Zdi~{H4{mp*TTa;TZ*1H#- zGt(VMyxS6o62E2%y2;A=Bk~8d&qhNdB42ceWutJ5iD%hj4sp3H=myI^!xkqKSK49$ zu@3GIiJ!8iTPu4h+zF9hW{V&(Xp1lr?gr_W%5Jo!`zd>cE&55rtt;J6+2_K|8nFrP zXNe7PqXsNnWQlJ9o3BT{fq9!PL3d4MC!l>{bfSG$0JFXUH;lv|!#;>RFd!4}g*z=E z?WlhmOY9{53rjph+z5F@==Ty4cK8|**S$l0%o5&A;LqTGj)=yxUgM3xykEf{ zh_IV`82$v(BjWl;hzQ@Q!=ESq1pNfCY?USUk=_sam?6_%a)@Z`xxg&AMJ*uRihK}Z zhbJ-oHMlJ!!fwuFIP5y8@iK-Z-3=Od5bw9d^O}AMnD>2bY6C1g5AJRm4)<%=q)lQj z@q0)YSav@8E7Er&ec}($ei+_{dLlxfFtHu|C9wnUSBafy=R|Z?_YzlIVlxr#=f}h@ zOFXIZPekPVT(pg{ZpZ^R-(ZO@(y)u`i0JHYBKE3qaXsXN&c<~ch-gQ*0|l;o4ajnN zgNSw{veoq&L|mT*q`i&D4F4hY*WtG_{6W+Y@hMB(P27ogM10W_8-a7L#P|X%TVsiz z1GD}P`(gY)V6VVz$bX46W%a($d{&Pk=_S81q#S11LnPnaf#u`M-}ORq8>F}NBV8_JEV8RT_16lEzSdG!`?0f zGM!r){x7s^;o!fyfQ;kvKr_^;{sdw{&|USKxz`y(Cyh>m|k$M4Yb zPm=x;>{HW!AdURK1f)K%5iu`#gLo_I6*n~0-wSO1GTJ3D`x5kfK$b%u<8j?IBCb1* zi0kGNaorT4z;zX*q5nc)Hp;7(h;j;QdL&$EEdx5FMu zqumk(Xg@Fy`Ui;6ccG52BQ~L5Azp_105*RWcB|u?h?m3tD{-9)r;qMF(nzl#Xk+YM zM;iUmJwW!`_maK>{Q>64vfU6dhE5^A4!w!6F=P?50EM^9lxhOq1r zjx;-MgqRV66?>WnTb-oILtnulh~-~$@lTVhBvf6W_^*v@aO(zC6I?^<`}_iU znhOO?(cbn1e2Cq6QKCy z%{z;aTMwY9^^?IfNHud2ibcv&Yl$}CIQ^hc9k1#hdwR(O#op08FY z(RKW>q&wxV5YiR=@ua)eO)Ooz&m?_;EE?&`y@>QhvWTSX_7c*U2>Dz?TnewOq%W66 zCS9q|C4Ck8YvR@Lx=y@S7NK-;ej@1`)N>HJEa&qfx+q7HN|)rP5Wl3JkI?1#CrIBW zi&(l8FDL!qvZ$rY@JiBm$s(67!K+DsLl(Vs^*x{Tx8?2&(v^1&>F>#^kgm8-BYnTD z66tz-G3f{3C6)LiSvAs?b}i{g;4PK7UG9p20Uh2^Nk68y(s%-1QAzKRRVZCupGEpf zS(UiqgEv&tJ7tx^&$r%c<5^j?(q%QDYS0xms#v<7t|$Ich#>I=S>^EejeBF#FUqQy z`#&_1{;MuZ&tqh2kMbkm!LtjSBuxLWkHS-!`mPJ!SqtaV{VD7e-bT;lai4)=a zmpB=7E8?Np3W1o5v72~=-Wudc^ogYNESek|1;zqmfko4U@ncR#oDNsP#6rDw$Z?k1 zI%EdM42EM44wICwhOZ&cwrHBtb?|k>6D)e+mo9=oM?4v>g^8zPtR(s^nk&bmM(R_LOcVmiHT?7-kNx}-m2tN7>h}N z+M=mTm$(~YEr=&w99T1)7T7w_+m^WBw*0#`?`fjPdsq*Wligh_Px5u}^Q6 zvQ}@Ef-wzE3jK&B9wc6jITi6UmUxJWxxvFk%pJB8`}I~T7~8jz#u&Pth%xg~;yT<* z5iu5`=?QVA#lKO4{|2Ry;)>RL=)@#IYdUo!P}qap9`1o~}AQr=h$NKSsIB#<`+e97py z-jJ70cK;F$s${RA|%}5|`JUWPE^t%XrPJU-4 zkasQkIp9l1zl#ldr3vI+2R=06VMnZfIhY_i`Z;q7FRnuN zqQ(Uu_>$4@IzwKWPCcHy+mn>%y)L5Pyae)c!Iw;ZTyMxbDS^DNf=|x(OQt@KxhbMwZ31~GfbUiv zZ$hko|6|CjOCawB@Fmk9EW0_P-?9Yqn!uM#es>!3&P*V0AW3>l-F*xV^0ULPWn63FKV>zGT|RKMZ;2CXlxue5;etuM-83 z13nwSpyrR4-%G%kO#QxU$Xl5}-n&W4TlJ-geoYDFT>!ph^!tk;uQ`FdHD3(XTIoyk7A2CLwRPA@9Nj^4>{OUguXM`dyqr-X-8mru+sCd7n)n zj}K6jsoys6IrZD0K;Fek%G+hgyDWjceM!n|!UJGOKj(fWo;~+~FPZ!f81isyEsuEe z2Emt%{k3k0=(j$BytUv{XBOk*WdSo&uJeR66Fz3-WA|WrhfMr@-ReO+SNkZNRL*DiT@-~7mnf&H|FQVU% z6UZw8Uo!IUG~_*=K;CBXCDR{FMjGag?eb5Cyr&Y#`$v-U&bdFL-_r@?od>>T`tcVGdCw-0 z_d58JsgD)tY@PD^Z3201;7dloKO6FXpFrLo@b&0;6JqN(v?Ze7a|z`2f-jl;zG%q% zV*+_^fG-()Irj$<{a#2QuLFF^$oqpK@6QS3?M_nOnLmu^_m>3nn!(qr<4yP?2(v$U z&XD)F1oB=5Uo!bU3xla+e=jGHw+ej8==Z!K@0A4dUISk;`YnGjqTj0t2PwL0E}SbGU$;BoYOGl9H*@FmlJ z|8B_pX99WeCn@hdOqLw|-cBIzLhvOs9=&SF`&R;a?}9Ix`Ur20==W{{dHvu^#-3j@ zv$7l>$eS)L#Ol_K1F&3FNhbFB$!QXUH3qK;Et-_txTZGBKV}DroJfgf6;7dlo9frIK3FQ4QNqJR|Mf97LK;AO&C8OVVL*B;> zd4EREJw}t=3BIMOIHLZdTa22wPsPp7XQMb2@g%?;_wN8-Ey8U4uxwl&w1ZfAd%zcO zUKcAb^b;ZcxSsM3PayB>;5!pMu}7@DcfnT-Cd!+VK;H4V8Ec3Y20B*Wb>MU4VL7}! z;^p_@B;_6X(}+BuA&+CMS=X%7-ZU+M^0JCb=laZ}WX`-3ON!@|&YSJ?70U?qw`|TF zNtMhlK0#d(%(|p{Q2_2fC|@42rh+Cx!UP1-!GmTe^F?dKy;ZY;C(j zO*eM7w}(1<#4NZgnbpRUTnwWRKzhQ{-IyBk)8#H^;!%HCD=&0P)cAi6?r!vmPMc?IcVR}Bj+uUkB; zp{J*-b!Bf)s9TA46`zIlR<(9CcdBq+?1sn^GXF%1ldHh@44sF_NZ6jCeuLQq=fhV; z(b?*Y2{$Z5ekqY=(091!>`}&vji4vHVHxTR15JC-_rhS+S64DDLpXQgBt2Lg{U_iw z8OJ{v{8+|4Jdn&;+yXZwgCD=RhX>zxjYZ~`xgi<+h{ZiTNO>ygpc|4Qj*p5zTzbE7 zqCNNy?2}RPM~Wcmu)_fT@G*ybc<@~qKC&=Ypk#bhV;&n=BAk;j%B<)JmPq1PiFi)#1|U;)W@XD5swdr^pPPJf-W{_ zIFN7;kH{3fK5}FVIEZi$5BkP6QMBsQ8Z?KE^5TJq#_}M2y}>^bp&Mf8%`x;ZV(3?5 z=nM?I&Ov$8W9aG_`rH`$voZ7+V(5Ef=${$%1f=&0=q)i2me%l!P;=MpQWe%3 z3WeqsmzK<(Q{UBG-_p=Fs}Vy2dfNK#wcS0T_U>uZFr4(Zq1R`(ToyGFl$3~R7%Lc2 zKRY^Rjt&MIgFp$cm)vusgXihsXz``RI{1Vr?$S~njH?XUrB0G3s&UYag4~#qr!+<; zE|QADJD4eSc8L>?6GP%`WLNP+88aLiQ{mC&F&oLL@aO`W?WP-DB6Hky%fz%M=UP{Y zQ(h&`iX)Ao={h1S8Gpe zV?&z`>TB(BL*`eXUR_sHSzo*0?E1=vj>Vl#t<7u88_ySJL{)2d!^*Z$O?7p(vcss@ z>W&1FHQg$@X@rZHhI(pX-itarR+Tq3b%naSqh#yo+J=srrg#xcTi_+mxv;LhW>I}P zni%w7)Y;Hf(c9dN>68qvV-u_F>}YOXCF%kT$`{o`bZu8>PiJFi+tP5Tv9-Civ9hJI zCDeF+WrZ-BTw`ZTs0%Z<`bK$m{mO>!kQNciQ+Z=!DBKg^)T?_~q%OW;;i_bY1-nHy zEQXn4-KY#iQa3VJ8lE$M!G*&(klBhZT;15v?G#rWMZqPrP#fxKYVB|eDv}Q3&5DXu zgC*L~QQ6tqg{vFT)5TLmRb{+OyE@xjyBm8ud%IzU!;2WwqiS2!l-K#nPhVQ&t1PNK z{&-(yXM4D{E!5>Z^MqORif6%zV9AMdPAEEScBv1YtPhh|F|(>VP&d1D`TUa7<$*I6 zE%MEr+0@#wsvg~On5K71ZA0urKa9au(Eq*4V!XDLtBx|#A0NkcGzX1b_^gz ztsRZ7pip~L*P0?_yTbz8+dDhraQAd!z;eQicvVqDIE*6DCq*2pa4XO=JcNw(jjeGa zLKk8{ixZB*33qj#7iu)6g%H%#+lbnXr0Iqgh58!W!>j^VpJ8!DiNzMRuC8nd_w;tf z7vjbqNQ~@TaI-e^gxM#?RmWsVTG+hevc$r`@BxIKa3EnPBrWX3xn=b$dz%~4V}_a% zi;ZGEPy$_jRUyn_sv3G4;z~8*hlw&8m~L!EXasULB_~mRt4fqi#W*aosG+NURikV% zPHP>BrwDh|A@u*r$a8p$I#-^Tm>(nj0T~==Ni&X^Y`iS!{-|hWZ)=;XR?b0XT0AL| zGTk)kKm;T3WKxbrwZOHg&4{iw^B-MmHiy z_&5nhB8yha{v4gjNS8|vqZ3VvQI(oweaVP+uTcHu2fAeTfwMSr;m4H42!%Y1tEYEm z;#AQIhq_u5R}I@UnUd1Z;dKml#3G7J;1X*X;Y+G|hq1d=_5qV|uRB0hkDTBEDm?1K z5!#$lp$7W_%eK1}qi<`tWo_a-yKEzvlWOX*GB~Xm*8F8)5$<5vulKYL?_h>86fvZ} zsj;)UxjUq07KW{iz~0)0B;qP$rmaMuzXn}hY!@k`x`#7&g?d`s)u?e`EpSI4PF@eF z(cIb*svJr2IMt+bj|i2Mc)ed77RB6v8=dZMea98QsGZR;mpW~Ns#G}sGy3)DBIN2 z9$&oVzzh&iv+5Iz(M))NmOxTeEG7ZEmo+9Q@@8I2z}!I88ta^h$1{_QCI1yOHqtHa$?)m zt14Qb7d1AkL=D;nYM`gH(>yC$h38m!)#RJm=^JUPUs{Cev@=`gBv_Vv zeWVbbXQ-V%!-%O{93JFvW>YAP8-JL7YpDB__HJL~o_^R}LegoYYis)uaxkl{y9ZDI zmddBVi#RrRtrb-`5kqh9-`2lH_<%!OcUgYYDr{&0!|-NgYtEMMy@BW5>o42b8n};d zRU~&>pf#Y*eEvhX_HQ9Ke|FUQ_236z*7f@=Vfn)It$@X=x8-a}3&<;KvRcH9$=fRS z_LmmmxBungF~Tm`E9|Tw`GqeB`b4fR*gH6}Vs}*qual`yTfPaJ*Q5o;C|uM!c<5cjI6KnPwA zZBn)GCSPSZ2Wnpg@w0K#M08%y0A*=ZX(yQ{YA2a^BgI!GqEb7-oTpyZ2)__~ox@1J zMiSN9spU!f^=g)OYB?YN`56BR?X(ig_(e0lL`6eC5DcT9;IPHXTkq|{XzL<#j zLnXx1wG&D3pFkRkLnT4ynFx~fsYLKWW%-^7S(2U|`C5mbB^MHNg*c74SS=LcE*768 zjrTltL`0rNL^$h)+dG_11pm3jGWg#kB0NY0e~5_iW+K8@5i9gU8HCFPgD8v+9o|iZ z{2roDFR+7>7m`NiE+V3EE+z)FV+&-C`lQNMKE|~4!B=wF@BMR@yH8`LHX0a3DwT+9 zuy|D}4HgEM%Cx0X>jI!2vH*fOv9q-Tu&v{shV_g5R`q0)&jbv zQj3v`VZ2rV4fUf@0IEqtfO)d#u+Vd{Kl|Uc!S>|grI)Hr71@maL6#93w=6mInW?Ng zv-zU6%Kp**xK119oyxQ)AwB2dD|_8~f;gqmYnlDrgQo(Lic;YStpZd_WhuxJ8Ad95VW~=Fj%z#Ta+=2&hByazJIj%~PGvfqpXJC+ zrX-2+Uf3`y^!dU@)uJ&Ady$;v2pcmk_QP~BKZD5r21g!dkZk=~el=svo2M4$<(;G! z(_|N@>$5O3WcAEFUd`;XPDXdd>rgDrMHb2gNeG6Ysp)fcJZDaMn9*^Dl!cj8KQJ2w zeIu}Wj&i%i@UQ6bn}GD~`yD`5ne^x_uX|X>?*Q_;CmD|!*fR{rH1#(`DESic7`1@S zE|;FI#oU?5AIfy@Ea`b#WMPID>q=jFzNd?O#0d;oa?C=hrjbS|$(lk-MUY&2go&0c zZ5AM>zL@;TsVy5bmrh|WBB!upiRer)E0Cp$I*{{i4AOE+DeD3SEe#O`BRd9UNH$Mo zXfpYbAvx_URI9SENKRHToxbNX9vO>0P)2bN+Lp|ljwRm&*Wej&FAF#9q^flBbxmo&kw}cq4^vcly{j!82H&3zKhZ4wi)rx>9shK zHl_o1fsf@+Jy=&fXp6VwXY%a>-$p1*K53hpFE-tKeeu5^icR;({7AaemPe2`6MV_! ztKZ=T5&fJ&mgN$g-{ZiyCRP~eSa}-^d9p2nC!V~G;7dlo z{HYQB&`roAp1cz9B_r=nL!Rslw0;|bmJ%=jZU)~BgLY11`ThjHtDQ&#AH}(8SF6xa zskeG z)$ch&9!yal@#MXlq`Y&{w>$cw$VZgd0lqFBZ$hko1BN`PAdh(Z4T3M3{5E3DarDFK zi1NA-nT))b40*>UkoOk&lCk?$g%SOZH{@|5;4v29UjV){bi4^0L7461N${O+GU)SI zyFVPt7bA{#?+m*v=a=v^+s8s?5($tm13w<*8^q5{cj0mRF&r6;V?WMKd5z$E0AZ9@ zqWLHL2)f8mt<_ z5~A2ev%^-%4htCJi<;OkU${Wo{klbdViOgj%PIn9>GOM+yATx#+cWfFgcX*Qp?0ir z!!pEAaQ+=ugFMvtDH{#?_XuB+uA_1NUz}4Qzd!h~LGuyrUW4ZM2N@A%z&}P{6BT(d z%?Xfq3TU3EA(V6jXr}MP_km{mPW*?z{=IocWRb#($V;3R>UFYOC66UGrAA!6v+Ao< zFWK$Int{%)`p({-kr&P@!%+*l)j3zo>ocsv)@N7&jvD{>)?-JshhA~k6dxeIzP+_0 zdR;OXGppsuQJ1>G@`}-AvZKpnN0-Ttw7j^;U7tIzcyyVpd^JDPi}lfEvhF&z(PgsE znqV%>jSSGE%Vgt~NB8J5*;Uc2k<5iRQT7v=$LQ6#?scQfWTTg-bD@-4BV`n(3^Z4t z$__mdgIYH@x=gkRt4iY+mb=_^beSwojs>NRCel_9P;e1Ob>ZkT*@R11X=kI$WYuCu zX<5$7*eGIjnQYOAyi7LIOcOmoiC#6E?BH#zVNN9cKVEK|Tpm8)>f7Xmc8*?~9=B?|UE>CgcWeABuwVT4+Fii2vxRsK*pzm8<{)tWq#Y;i1>Ww< z5c`0l!6)7W{_xBzd}$4qn0M+#;RX8e0$?m~{X;_dfLuR2Ic$l4hHa4xR~%9H3YzxHgZA2F4~<~2UTLr20AG{lr@fY28@%!CmGWq> zJU$G2rJN69uU9RIZ?7Ko3$)jFV(b-fldhn>@`$$Aek;Dc=1Y6cF7^(ySIQ{I0wZVL z6qky}UpJMNafmg+nrP=*hgnBhQ#=LM3=0iH;F-R#Cg8-j)39Pc%N}RJRhPw;I(XY5 z-}0efkSlZes)N0jeCvYFGxqo(i(xj!UJM%jgnaSlME#8?C?}>rRtKU?hb@Nr8+dL} z<*B(8#4d(e3qkG7YRoYWw0ZeUSb-oH0>$w0g&_H4xd7h6B-M5P-mPm2}(I6+a6T^{6H>JSFrh;uU^o5AP2 zWHs2hmsHeC)Ca)lLm11+sW-kvEjm%Z67{LWeTOz<*tppQlX%o%m&m8%9%1pSPrHv+3rnXE%hlf6YP#sfsuf^!qrUuIbsJ=i{7hhVj*)VFE6F7U(T9 zPQ}yJ;Ps#jHUEdd^nstG;$vXvd)1MA{wY^l6^p9jAgi`zEqq;7wls8T*ITi{)$}UJ z^%4S-$=4BTt5jamA_3i^4Q|39ZdqS#=LPVfhG%}#;ZNz}m8}eS0~Uo=H8if3Azh(0 z$_-ibD%TrcwDZ4`*%42K(H`~=mdin7xG8nK9L6{kEOp)Xx!(O8SBB7Ejy?4y&|WzT zbUg{W(vo!lCofON-`|PD##SgC>mXPTw{Y}WTVB7Uw zH+Ji~=38&L6RWR;3yV-kH@?mebaqvR+8Wj>Z+X#{A>WZ3KIXJ-%@6fd_I7p2v=)Wd zz@4!&MWkChqGP>fHH&LbpI^VMZ&_zu-%|Ne{W7@5psuv_(#273_J#+^H7yKQ3xL$} zml)dRS11-G^*i$Q z$w-l-i+e^F_h`Q}#&Utt#XZrBF5;BO=;EH%(ZxNcN3&=f8TEk&XMJkf$EXjyQ6G3% z9vOeJ5L!+5s1H0Wu&N*Rf!EnKy13`VUfd)7+wn1p-asUJ8Bgq!#t+5oosrrHTyQf? z*^!sl&|g9Sx;)W;`|&rxQ`{meKR?{EsUfVq+zl-V21S1LTffVpx3|6rEqIv=8gb=s ztS(W4HMOwTKaglehT-3#8}2zP=OtRNSM1rvlc1*mOtW z^y(?wie>C)gG}2F%R%w5O-zJZIns`8fk$%^x@Lnf$Q>OY^e^ zj-F}noQ|Jo;QRTWfiLG<155UParNgb?%wu5%cT|R&s|pG-AQ>51k(n#?i!r$Wg6RX zb`>7VAMjWa^!ncmdaH(p#$)M?H!wqZ{k(`z{duIr0U-SP;eXUwx(btj!5WDc%8eg9 zt#H|qx(c8eJU*MRlkk5zM5oGO+a#&D`ok9)rlTErP-sFBeTK;cD05n+-)GO(@2}x; z18bgOD%#mYr92hb;7&OTK|J4)(tC(pAAof5s#`kPlONO15yD3rFIuJ&;T1!^md5)S zzAK@FK7OxEA;%G`wQoQ0m6Aq0l9Jv>AWAM+<5~hPbUKMxA>9W`WFd+3_FMyZWOm~u@%T@k`00+H{rp#z z!=re?rIumXCu2AvjdiVDc442Ymgm?R z$b@CfBhBUlKH~tN^p1tHl!F@bB5N0AD90mSONUyS#9XzWhvUl_(ilgwh$slI(Gxyp zD41y}hg${8U^wVWhg;M1xQT+19q@EzNOZ6znUQ=p65(Y-Qe^0FBgve6qfP6On+~g*qy5UI4ps^PD#VA8bR)ll6;p@-1?N zgLdRqX+D5F&clSpiDQ6sz6|H4ejRe+BQKGEoIHk-R^_g=^xAOoA{Z03&;oM$>)?e`C`*u4lhT^r27l-Iq5p)5KrE7 z;9HG!VvpE-Eb>Lb&dAD9(>8v$D)FWerS5~h$n9a_`as&O^D6!JBB=TkMf|rt@xoY z39AtFo9GkIa0ml`iF4Eb>cO|eQuaqVJcz%=55ewn4Ej{eo`xNNLx?HQ555NwMtk<* z$Aj{UN=i!9>Ra{qKx=SMES`OW;ymygTsp18;jY2`f6|Z97m>qAh3pynj?Atc35d7UZG)9Bnk{ClPM?G5QVY$fEKLF#vk3V-b+I8+49A?*;v^9G!83`27TZ z&<|3yKEoH&=0`FE!yV%;Jf+U`dvqG&dCmcV^h(gw--+)6ZTdmF5;XO9;x~Y%{?7G} zfTsRV{O>?he<%LKUrZR~M~R=94)>tM2X?7-our*8VX>S(!)iHwhGlp9Ol=MP@3~lF z7NXZ?#aUJ6F7x{T+Y++T)m)>ixkguWjjrYzUCrf=L$RAV#a+ZUx})jr(m0NXV&Ak! zuT0?_AgL`c4Mx`+Ptu~@D-PhlCtf0I7qSB_M?3J=mQwZsH?>q;qpq4pS96W7<}yoQ zm`|zE)m&VrgHNK=?L%x=sLIRrk|etohGF}|(H%`orSWugu##mm;!d9q!|0BtaJeOm zYIH|acP=5DoZd~8Tc5fS|5tW2J;0Ni=*3-8KAPgqvr4(#&Yf|`bDI61t_M4S{13Q1 z>;Te|bi~A`gVM3hrTm&7&)@Lhbi@P_>s9!dn^`FQPaH8>3!)t{Sv7e42f2yYi@d6gK*jbv;vCT-1 znD}iq9Wnjpk*hyvI=1P<8z(xp;Xy}C&v=fLj+jWBj&0JiCKu2VQ)&6aCI5~iCd&IT z9NT2$1qvP8>Vo`UXCw^ec@@mwE}n(dWm@UdYyPC%e2?0K6HB(X}ggANcMW8 zFTUfjksL9NY_H$CJifigcf^!_sZZLgH;yBwxQ@gAm)PrH<{ik<-Q@}G_1|@Lhx&a& z^{?7qYjywHpV(e=MY?hvHdfgy--ac&*XaIrG8VS1)AnWduU1<2VeDUL_!phc{x$fi zrSq|-Sd<-o#Dv>{{l7l>r*w3;_RKj2cLOJ29Q!Nq25;aOroEP?Rb&hzd}rn_7SPe% z=e525YuOa(=F93gg^~K#ua97_@%z{G|Fiw; zUlQ8ue=r}=_KJE!z3y=AHQD)qwpW;|wAYd5175rfHT&0Xo{{Wz?BTT6qQKGy+H1?o zo@kqboJgM6D@Dsn=RQYRh61s?slnAhg$ zFd`S!nesxohz^`$5A-p@3|@f@o;D$t3mtF_-#4&I4gZH7u?y862Ge$T9fEqF&x^QF z%}n=VUnGw4vYdhFOC_I^=YAgojKh&}4#IeTAil8Xb40|-bHj0h@*}%E$hTCVn{Xot zM+b&K?bC}QNf-wg4@sNQVSn@q;m0}kMf;ZrZ6`~9>eJOctFy=_4|gR_*$Ce7N=wSr z(wzgZ#IXuxI_^pwdG|Kz4Nn$|S&7`3jH?YJVS9$!L9>ErnDk!96^cB_L;4yZE7FPo z63(523xGB_gv3}nQ`}|5)0^G5qUb}!g9c4a9tJ(b4fBe}-E$gl&i~im*TC0RlzGp+ zNt4^OKucRFh~YMb(n4vP^n-v1ZJMSn7Ft8Gd`XffH%%Z-(tMN@735RCM8NfPSp`>7 z@Kp+0SKRGeTxDhPhfwi@eRY4btM3adzAm8avM;}-@BjbI%sF%Bo}1i4Z+zYN44nJS zGxN+d&zYGsb9&~VXVkOcn}f8B`dJWX{*eM0S{I~c1o~{*GT?AixUoxZ0_vL@HU`Qc zrRIWfck;85{JE+Q{M}CeX_5S61sYBCoDLbaF_M3r67PCJT1IUP;|r*~uqzwBO^e_V_zJ{xcr`fX9E!deOdl;5jC_;PMS=8Td~j z-edT+;6IAE&EE>X1AK$Y9|g~6lh;fx}rt>x7T9T>pr1iKYy@rhjB;m&L5I=@RSZ4i50#bk`rAn;v+@i#qpP8u-SG^_J&q2z>8Fn{ioS39x~V{4!V) zJ&p08yyb}#yz@4g^Bx>E|iTk!SLqqVbsGTKhH*D*> z`f_XFjMi}U$fl$4)$rg6H09w>9xM{!o=3G&Dbm)?xjV;VKRK? z8SBMSFQyrCTSvE@JJ4lY z#j>{2wq~0m4(zCFlF5=*((&_M>)TL1(ngd)TBM0gn%6=m)oUQ8z9%;{ zj8>$v^3?ByH_HTOnZPU)m}LU9OkkG5rf&kXECe(3;XU~v%84Zsm}R#;!%LqKnmEl% zoaQZdL59(%Dsh^ZIL*r$)LR0xBwEs6V>HMVPt9=RG%szzG@%j{FxqxMpkuGBIQr{N?|JBFh(H8n4lov~-S#5&YU$VQYX5VqgblrSI)637Q?54dbTy%Ojxc0R@ z2hM$LG*X>XXkKI=}@4z|O5jml3=-WHebe*^UoSxLl<@;34lkMx;RTe4h zR`v|8mG94r?b(R7IjkkUXzsrBsj2;`Yy7s8CDHE;6>+xe=fM6F7_%47}ONc|Eg80mYD-&QR)T^2p@I16{?vopiN$ z?GeZTJdFrnOS+WqBN0%J8xh!v(5~sQ6GER(Oy^mG+y#LtN}VNM0 zb|xu)R*^23s>L-OsurPjq{rz^75b$+k9@UK8%a@UGilbi$ylj;!HA49#Ax9@^wFe-8TAGo3HCir=i20*SDfrcri5pDx;K9RaHK}g-0FiKhXF{sam z9z<5ny6T20H>&EOa zZH|d|vg!^7-aJ!xwzPHE;$CgQ`hbD={u|0}#GuZ_5`UQ`qyxV2XyB$o9b)$$e0@d32CaDw9 zy0HOwq-{01lzS~k(np)pE#hOiIo>C`ivhQnhc^8UZv0$n1Q7{-Fw3%6f^a%+{Cia3 zg<9~goI*i&0kz^7H6kbNkN6zON!u9#YXW*z+Fbev@p+JQtF>}?ofUo3Uq?&g^O#`cn-OPmYv0q5bAwgQch+L$-e=^j4(c1Tj6-kpZ#nwxBM_(WNyrsrAARcD@q%em zLY%%9$Q7gS5l3Hk9DRRVq`t+qp?$a|332wF1-WAEd(hE`XhD77Lgo!7-z9#3oONPo zAKrK*#MyTq}I1oMv1%}e+bIKF-h+9vEv4cM0k!w&)Y zBbE_N6QyEzv28-)ee z+mo`9?MegUD~Dr8)i;>axKYRvZa_^@0B|GE9`}#O&PN671GASDg2)2F8bVVA``g?* zOk{BD*s4JsnBA4@THoJ2V4%4gG#s1NItEOx1r>`T9C|&{F%;m0J9~0nqtqM1d|Ssh z4jSYy5Ui`WwzZDQ+1s>eRD*K;#1LLP=AwCnx&$BVRAun8VND4nHi5(@kk|wgn?Pa{ zNNio#K&Ov4is19c%@ly=#1aW4Hi5+U=5o2lB@OkZ5@5;m)Dn!4Y4FzyxCx>pH_fdYe!{LovHL2fDj~ zH!M=TcL-G!DSO3E0IUX!6i&{OPCSn$kXU%{?i$%1|Hz2H(BvHH1QJ^+NG!hiMj^5I zRCH({v15zh6eJb~6+R=H(AJp(T}?et2xbUwC2Z3IUsI}lf0#34uLgZmo{-oEKw>R? zGYb0r_9KL`KK2N84X)L&Q2;K>0Nup@_}(X|%mBct6ATD5l8ZxwFT}^ZQb952Lbnb4 z$Y=m*=LDcUd`av=dKx=4K%cGi4o27`T6VdTRyHpBUWQ_a)vmMAP>OzaTKCJ4T6p2B=owulskxB*Tj4Wy_P zFbUyH*=};LtOtP~TibD^fozbr!o8QWZfPIX$H4wGeYTE$)->zt8!VIzn>At%n!J?e z)QTbcXMvbA4zy^Ru?gK=N}Js7;V^8+^~b=M;!)RiJNVMKh9|=FrSNfEr2rRI>2!H2 zldei1o|>KF(^!S!z+11vQ^_s$YDn{`uEx`c2T@hwX<9-aiD#0B&^nXO?%)ZS-K2aZ z4Z;U8Y|Ze0dEzfNk8<)5U5?yKo(x$G6xkKAS;wQ`5;P~v z$^-(+-BIpTy81SPIh)Py1@4N-#AVX&zzr0Gy14*NWb1QPTGWl)KQbg$D5qFpPcF5UXZ2MGV_^5k4xqBeD8)>wcea}ESzupaVqwOq$`0?xgCgg0rf*32H z?+M6VW0g46*S8jrlGVpYk0H*!Es(oGXGea0eLr*b+1>UyeJ?@I9amPVuWt(;X=|Sy zuW|aeL9Q5m&pP_hH4>UcnC9)~YxIGg=Qv94&_zx8!v%eSCC3CGeK14N2VB;4 z@X-fH3i{wYn+^R@^ucUFAGA98zYgNG|0wkz;KOGJyYtS#EyJtW4Dg&!b*K=~t>wzF z5Yx5VPMd)Gmqf}Rr_Kg{m6IR3%47Z2YD+}EQuR1IpPDNio@j^f`s)csD2a65Lviz}j@iF|V9`CNxls^~wRLL3=Lh&LGiUhwB5jwwp=zXpCg;vm95j>tPDuKAyU-w58;f9TN@n3oO) zJyBl}Jz>47dFTo2RLw(ASPyC*dcrzT^WYQKlUvl?T7#`J>TRvTR#^{iE(pWcSr3ec zlTQC}QE*Jh$vQqLb5%5`kd%NZE-k~Zf-J2qQr2jLZ)BS?(RV`6RKGtKbu zZl=AYc}2yLExjW>E)oPPwQZ6cmZQ1nj|>djl+6SExrm5PfIx!sNKhUL$|FH}Bq)yr z<&mH~>L=LrH%FySyxp%)j?L}xH{&9pnZ)r~g7UzjpyQ8`1m%%9K1&>*4dFC%LKqUq zXIxnlln0%&59yiHx)GIW)G|E2G@1|s@FbmXv${q#aLvSdY^<9XIYzc%#{Vzp%Zi^d zep!#8JoriLkf1!E=*^%!Xi#C42k{rPTB=&qyw}8C*HJCUYlmi!rr{#YqBk=8-_g?0 zLIg)@_udy@7ROz$!uc7o9p!MyMVf7yvG;>}-gsfgp47tBGby-3%g<$s%BIB)8shu# zEztpbz^zs)O}ATR@XE!bOTeb-g-e4%hzQAuSFVuPzPi9mri&UWwT~{lSI1l6_t17+ zbQIA=YByX#>-0M;Ej3+J_2Nm*Xr*))<8&3?U7*AZ#+sO19ea03y#?BzW2z$e% z_}ILXbg@3(M4h1M1WVGnze>3cq)0!P6v!3XH-HiRo=oF5lj0^WAU(-=<^mYyLa?O* z>)^J7z;E8|xF!p9!hLKT_W6r^G zP_IXfgkf12jl@#mP;C$>_fo)x5$fe5U;`mcFC&3v(KHe`Wck#(`i{Vjyx~*88b%CuXi=3++yl|2y*Oq>cg;xC{x}~G zqisJsWaIR8LT=F1=Mw*ZpLO(c6=sOj_e;nXW8cQ=&_3LfggAX|kSj*t_Z@wR2Ksg* zhIuHs#h)Q_i^+G%V_@9pr~&gm3voQ#xrFvTiOYR1KL@$#Nb|#UNO1Li6>^)9MtwC# znELAKmn|2_miY-zg>AH$E)UtYbQy9OCPsE$iaHSjWY;`ee$dFSt;56GPlbh5h-;0j|xQ`+23%^EZMrSpII!n%@fbF^4Y$T*YV|@pN`$ z1Ixbwel;lj{7C3O8WR9TEME`)67Za3n13F4em*$a@ZI453UMnx3_d4$TK*>R*MM&{ z@`oPY<^1_+5v zvps;9ai-Je0leT%M_ljt054m&2k>gJ+F`bb^vVZy752fidSmOFHXNs#8(KYtBQMdi zN+*r=jsz)eOL)COYo3?O!TpYbe1W$|cdidl-*i%2NBcF9EPBr8>b@NQvSR!LK-Wi$ z=w7r4E-zF1)b_Ww#Odwc{%y7#??8jI5-?T*#!A3g2^cE@V}4qQ9TdtH_^3UxAjKu+gQL%ln zuVWp=Ws*KR(%UyI7_yOp0XJ5+4c|B5H#mFhK-RqW*GYr+_66_24gOK=`q0VF z@I!}(%5rlK4Lr-$_-1fgZuxNlTh{T;f%O~ORZUg<-WO*G94kyer)OGE&C1zo?!Hv* zv8$`v3A#G&;Xp1pv+}_DclA{DoUpRy*Jb6?+uwL0Jik!`yHe}Z&#Qg-7O1B8PzM2C zgL|&qU9KwjJ@hI*V)tZw4#TO9>drZjGJi_T0)dV#Y|&?As>Rj&fE4;-1vHmCrfk^LEb=|vF%k)ep-!}#%+`k-2rEh0sEZf;Y!ffSW2B|X*P!jOJCc~o`= z>0*NmL%AmMkXu6vTvrPzcJa8m9pJ)npZq&vHNUi&4!tMEiu6Zr(+}_V9sS_bd>2G` zVCIFOr5YB}WwZss85Zqe)7aM&6VQXDG{N0I5hp zOKSqFwShaLjlTcq=q z`a4ogR~k1}&U4zzu?;5kbQvk;3{)rc^Au7%L=~j41+%nnUs4uMv!{NMw3^If)+Q0CXp}$zkDEFeY0^RA9D+8(LCJL1GvGL zsK5(oR=tdw^gl!2yQ9pCb7^6l*t#EpoV1YA0>2G>xU5yEk2?8f0C9c}d}EMSp&kt49FjBCqu_4{(kj%qgE;e#6qwH4 zL0W}+E{HRKwt4|PmwFv4)W6y&C_PiX0s846twL3VH;eqaY7Th5BIr<|-X6(6R`E)4d;By$t0pjip2s(O{05Kj@c2=Wzun_M z@9}@*@%ugAg@e<+177}Y`!0e!=AZ2Gt3CcQ@DD+buNL&2H3I&0#QBOr{zKr|L>%+v z{~Y{s#I5|p;BN$ve|ky&6X5^c$^Qj-J|kBCci=za@EK%$(czB=|5=A$3jQx0ejWHP zJA6C%uQ~johjQ6@I&s%!&|g4vxo*6yld$^ev2IJPm$3RMQf(=qXm8c+R~sB-wT_7| zFMKf_=+~#7F%{UUk=*9q?SNEie^*G`9F-JTUaPS9uIjvEbw__^t`8A|7qiI&{oTD# z;EI|P-lB;Xy5|b6AJ(ZBgJyJY80hF~8tv}R0axaV;|RFnO&z1d0cOp}w~k4wFWj0N z9^Iacroz=&tO|G$qhen;PQ?Yoxy@s7=56WVH|cFH14GhEM6KCI3fs<2HBILv1uf^K zIgR9`x^3hnyG;~HHn$f^vv=nty6qE5&M&`tET(*?MG`4lFI( za{aQwXX1Igc;jZ)bqsCa)~U}}E2O~4)D7i;R36suEsB(_8`ygJ`1NCXo=~8;nxV-G z7OXbz7VNQDTSwuULu?@oCx~cNlE=oJ`2)-p4vyMBpgSXq|Kgu8r)>iy-uO)$h$Uy_C1>O%XXM4K zm)5Hq9*`0Kt1oZa3j`Qx+nUqw3C_|N73kYq;50}q%%Wki!+&I>3Wj&}kMzWgU{)B- z;a~3sOc>ulott=1O8|Su?HdQgqyqN%vM#$n5f^GU_0RzIthP4;(z9j91?T~XFi&L( zcLTuc;Z&{VGKg0`pH)-#GtXXx)giv`IQU;vHS@;OQZoDKys?zTP%3-W-u9cn@>;p# zuTuBow*tRajbC{!tu)w9duo$9A)VT_YT-BOm2F=tJGho~q6^=O3A~%4U8@DZNTMS( z=4e=5@EhhBfj31iM75Iv$KrQ-7mtL`<6TI~bJT`!_<}~LF*}yEW@r8+0elGXjoSx2 zBy1KbglCfi${;(p3-w_d+#Z#kSJazjKJ=YHil6zU&c%5K>2=RBbz@qY^tyq_k^44N zSE*K)*l~_EKL04DrjUKYwpaW7Ly zF%#qcLEbPbNijq5Ho16DB|TC^A};u3)M0dCLY2i9Mcy*R^d;)>0u~E_XW3-B<|9~v z_kmWG05kI-rpM#P-X}L{gbd-!5LMXlY24t?sK5*8sfgStMl&XpynvP$IcYz{Z-v}9 z94Tpc@OY1k=vxUxT=Q&vt&y|knrW~TtnGZV7@tV4-^f`N)HiGyhhFW;{Z#?E+aM=n z!jwH3Pa2z#cCfD)ICk#A<;tA_xiJ__ISe-ml=JI-1W$0E$#;ogFI`O9dS&cEI8NVU z$i>~SukSubpB)Zy`W}W{G4{Rv_|QH)J`&>eoeH^P^nJ?FhsCU*z6XlbHzym~$El1V z&b||~#o2ckcb-?Ax_`hAy-WM-QwuOP%NnLQ$^~VQWM&T zAyH7@9LN=8-?fgu>^S=FDpKEnI{FZm5Z8W(VJRxczFm;B{mZ$Lf%!MSe>lQ>lIt#3?^Z{Wij90$+IXs9Ext zIOWOrdHnmqGl^|PUwn6f;XB1#!+!=mKIRyJXr=lJc)otsQ-D$=#l~#Pj^?S|dMq36OvZ>J6v3MSYslfsVh|pD$4qEJ}{t z?35M0NDpRlCG>G#4!WVBH9;i_>McRN6@>E@K$<#8wh$#)0Hfx}25`3VpP4|cfJO~) z^>qjgCpNLJGjugHp@2sDbaf7NcLP#XqCmAXf%yW%k~^tpK0g$piGl% z9e?+}m|6+C4VD;cW~O-Te$|O;ghrG(?P7%M}E4<9)8zz0cH4@-i4&J zZ0sTe%FloN{wLqrv56_)&4Ess&UAdjmOWg2ESG&Wd>a(?kdu8O$jMi3d@q!J6EN7K zlfts^fkb@Dm(9`nq{u&s6d&yukU|){*a3j6R452{Z0Uq)rNK39}z1a^VFm&YI^ZDWLNdY#)UR>yn6GCq+UckFE$YM?$25kFjy1Xu1% z$i?mU-w8Q)x9}mzv6*RyeO}mZ_jz*rAjh(lbI}ccy&ExvM+#4~eSr8$h|_lwhbEFheO2PIsjFk8gYKFT0*_6n z$DcS?U*E7?Z}U#P%RA>psV6vbZV^pC=w06bvL2f*LhFQm`O1L-X)XOjk4-xx{4{Sv zRB!l(b4rCgZ?*_MHhmTh`&fqx@kV1gdTjaz82b!!M*HtJ6Oo3L7PrL7j~*6xtZe9p>rRDtSln@PSX`r1 zK6+SOwHy}5d02-E6+Ij-t9GFNl{Opqe^uBSu)jv#0>0VFzdMp&tL_88&dGl;l0RQP z8sRG=9-H{oJ{8H&s9!|*sp=07&kgEIKD;K7ul4wq9)Fp~U+M9#BT4G}s+Ygd{r8c;92w1<2=n2*)%%GUdR()8VfLf4alp1AdLeKMH=i!|w;b%He+t zp6k5TUx5f-Ed%~2@LUUQegh)w!DA^Cdscy;hd7@J+IJE7If(NaBEJJXy9`A5YZ2ib zZ21xZ0yu9c?wbyo`zCz|VDzNHr8q(`ifuTJsEW3><_+tc+BU6e-Mp@K&8p^nz=Irj zdb)uoG^3{?;05D5sCBHRw|ii7&roi-XQ0n|R?>c!;`4w_&>2m;@GX1Q&W_%`j;$_o zqF}MjQrG!|9i6$DVmjBiq&3&kr4^bR2@_Tg4&p$^T-SOy_75`gG29bJidJnw8dk!u z3Mh?u8#a%z_2@#$sMvzz65-W}EvIoEZtD{HQK)g5SDRaIv+DKu|$G#2^}X1FlTsVbnE!d2JBgGs8>5pE7Uc0MyRmUF9%*>WheAL6k;~U zw=k3|s(bUq1B}r@Ruhz)0M1mn!U;f4k%9@v1#b$@02CliJ`^RvxD4uXX|OtjJ-akU zM;>=JT3bhFXKr|SRaY1O(O19`QA{Z$Y22Uxl<1C#DKXU1AG#QfH!9wVpr_F|3>4cj zX~@58Com#>a*7tzt<>GyH-hP|e_MRHq3%NIiDxI>fZGSUa@&Usd$5vTG(v;p`k0F3 z!rh;lWgWMZ0z;J!fmcX9k{PM%7{1UadlG#5#@saAsohvC}uTGZ_Y_$EEK+P>;Z{VbnRJ0U7ZJu0I>8NvcahH5jwtxof9I0N##AdQ zwm8ox1xjc$DK@0IuSefd7n9{Fi<4eAHlCzzjQ7c^o6mPU`xy_U)Qx9qvg+oZnbeI9 zHmMs4lT~-QtsB4$sT*^_q}Pp&La7_`&7{{2z=zb0Ic?JGKE~8N_m5CF78bd0%*~U2 z-&n+?Zp{CstowM3Z5z0KEA3DX>ch0H_2NLn%57!kGMdjfY@X*Dfd#0AQmaUI0k`! zoMzxASQgDJfo+S)EuyauH~3MxSuJCK`L@NnZTMTPz)w?w7pU8ny9-Yd(GGq}yz=}w{VU{pU@+zI!Xbfje!W{Ta}-nWcOYl$#X??C z-?K&PI~!xy>a)Wk&c2P1E5^RRcJyJvEok5Oi_~`-rZ8(C7SV$G)|v&Gr>Wysn4#UmvlPTyZcu9*8hXtn_n*Jsc!$Sl7 zI^~16@_<`;3G#hgiY*=fJhu zZ*^KG05dP{9_qlyO(2*=8OsJKy0M*KxBtr3D+f6K!?afpTnC=#kFtMK=zWg0a$M7e zuT*z|+CXISCoKb72B|MPJV(!i4o_E7UvqeV@A(G!JA*VIIedg5hd<}!|2T-VzL|m? z{z;JLBZp@Ra`=BZ`BCKX96=7h;p9h=!$%8pI2|-lg{lwYtp6Cb5`1`mY(>O1R2jZU zZ9#rjP^Ln)2XU5vyBYvr6Qos$e@1Ig84g7L5c1A&^6w1dEI&_u7JO@vR-wKW#F>AB z`YZ4k25A-2{x1I*@^~Jt4i)O}5$|&N9|m#i%Xs~lQNN7jPgVaG;j7ePeCSQ!+CAUn zS9<(K9>2rmZ}9j}di<9?{;xg$X^;Pn$Mdg*Y@oew^Z4Z+f3C+5c>Kpaevilh$m9Ru z@kj9CGlBLHNo)i8R`7f#87Fdh1pGVD2YhcJe;4?_M4bO7Apa%s>>@sMFDpz^$n|B|H#lTB?w^8Rat|o9l_)(tAIduHB2~qm}@=2zJmIV zp5P>RgD_R4p5@{fa9cO6`wn`{-lWmptOQPwv&U)11$S<{( z)_cd++FJc%Yi+eWwpPpv?!7+mn7F$D=P{1JYDfHw|>oT06RW2ekDKgUi;gyDHBFnBO#n z(w!Z{Bc^?0426{3!X}`!<SX1%^Q>9H*da3q-McLSY>(ew;XnTjo;)a*0KH={*nVRY z7Z~voIH7<>jwa3w>j0vTZ>$Kqx(E^7q6yHOEvnnXd8h?~oB+MY1z&Sz=^EJ{Kh&fF z6QK7%UmgDNU7E;#N~{ZqnWXb`Vwdp=XySF9-5Oo)@WBG(7NTH~p;w-`BKlpz<_zvK zv5rCQywzq559vSQV&6$EjMNRodBvAS)& zIO)23AbaXS*7wn!>juak4!s-vzjhRWeOuUwiwCkXO`9imXb|8|wQmLo?i3#f4L-Q% z=H1%2Vfz@d+*$d(SAL%#`!G)E)o1fQj}v+`DtpUUUaL~6FHv%eO3SIgQ^Yf(%JSsi zvade$Dn5$KnZAr2@x)Cp9-$6 zQ)D^v)@!2LbNz1enTONa!+EZ-_O=L0$!GpWo$wSceP%Fom6qDqxTjpD_N#2e-t5gx zpVHE<>FRb}-|7ZAr5JgFeV>8TiYb?QG@YHXH`}uJ#Tnws@nF-b58K4pd+aj*IlD91 zRL}vt2NI?MDZTPt8`R3qi$1~xz~QGYNvrYyCuSb5BC!{ZSVeGvaS%bOfytM}q(wpY zp&};+&Ds?uWiNzTrNY=-qy%rByE!~sw*1Djn{d4Bs#zoHHM8E|j#MJCyGXI`A^}ty zaFyBHUv2j4Tl5|;-4F@>>}>7_Az&L_uv*x-=bjSL^?)AV#seJ z4`5FZ=^Ar*G4%G6N23go!k7_K*l{K48TxohqWO1`N4s84iu`Ly0Ybcv6abp*NzvXn zlL7?CJ$K68PKrkUFez^SZqmlmqClmuSq}o5NW0H$vF3d|BvhOFf14}>`?ZNE!N3{cpRIvlIXesT8oeYjQbz_Ep zYe4v;(UL%IsT3Dp_|{Ej(pBlhQ&_oG6_!_4UWMg_({UA+5q3@$mWvgni}W&Ch2^)I zJeJQ*pv$v*d0T#hhTidXGH&ZFB)8MZfk>d-M=j$}K2ugV zlfMADtDSrsWmy*@djcjC-Y@NtF$T)9_<3Be+)~IrfeI)mW75d^^}e2scZTfOJ2)?_ zm$MH8>-F`05OO1u8~yS1{oc_h&p-iv{;6 z$7`IvDJK+X-ww!G`#6m=#Ob@XNPYj?(TBBOLY%(;EK*-@ZD=2#ZH72~yC65Fvm?KL z`@Q1m!y_soPG9Q8;`Hr;oNYf0?SlGlDN(@jek+V5_5BbRl7n#M0`o`iL5hw%58~>Z54k&$ zmd14wE(Yr3x574j(loBP17F;yFDc-Qd&#oK`XZ6_591j^2$1y)X!$`S>;GRkahXtg z2L~DA=Oc-w1K(eUW(<4%l>>H$Wg5Zv*Rq|1P@!%J;v9XI`a^+9Bl!N)PCnmh{sKH+ zVoa!1U$9ZoGJNLwI_Q!hty13TEK6|x_ra{N3DEa!5NG*W>Yu@H3eqaouY)-A=cxYx zA3kN3Diz)=@{d+Cz~2;X}cyu3TA4;lSwwBNU#e7?>9*yCUIcz&p~f%3dR?_ZP!~m)7qIM0*rSQ z%pG97JutV0TYF$`i?#+z+nbn(^Y)Wam4;q>81JakrO4G{9^@NHZ=H?^RJZNy&b9Tx zLvwEEpaI(i?~e3t8X6cG=p5)X_}r!qYc>t#I<})L&fnGFxdqr?$c33(df<4uA7El9 zwJ%qH?$*KKNJ>LqiUs5f1{r;+k+{O4dm-rss%FxzcKTk}LO^horI%v@5f>hqr0m%4pa&mZm0=7-Swh7oa z0ox{E+XQS|pMY(Xlf#pf!~1%-4t0$54)iBrTWNve1Z=x~yB!UQSLHzsg3R+Tj=!WJ z%&~2FSO1819h@hE#v9G`ca9II9X~e#+a@Q6|FKRE=VvbmWeZlrYngs%aJAI*W&pKf z+2X$85&Y@@`MZXJK;FPb4DJ@15iw_dA6TEtW(Lc$dtXc&^yq;N*|A3PldQ7Y!2ngd z_rN+eHn>)w5I#flGY_k5dao@RpOeZGUmBk$NY-(*>av6I+k9aC)Ui1&)h$yWRWRw! z|8wuls*2dx=PNhtyCC~ucAg+%=RcaNS@ZJBRC6}{JkEcdr¦iVRJrvw5~@n8P2 z<*5QWp>!%knf%{SBE+sydQotmZP@US*##F8h0Tv4|sZtL0!xSsX(&Ka zsFXy2R>Yk$iby2@x5x$v(G?Wtw`{swZY0GAcYsm^xO$f1&nATue!ph^8d7YaoMZTR zkwU5LiNIKXD<}URQs}>k6#6eFoon1V;{$s;`5L73(CjS(|6wkTBwGgZ3$@Kk#GVb~q2OjV{U%POZ=9#J`?a%Sa` zm9r{mSI((C>PASVQY%yN1$Dei9e6{fTbE?ht@XGXa4p5P4A*j8D{!5Ls}a}f*|OI9 zCH$%9PXm9J@(04rOVZ8t>E?!X^U`$lvUKzEbn}XI^J(ek#&q-PWzF?VaMj~#z_k?D zGF;1L8!J6KzXdZY1IS&bEK{DDlBvj4W-^(nnX1gR%=FCRnGdEj*QPVqr8C#3GdH9& zH>NW;r86H&XKqesZb@fuO=oUPXKqhtKAg_nk_(@}Sl0X>>ClRF$5kw^!3xZ`d7aEFDd#1#|9Md6|2I(P zKgM({SwA4fQuZrSEM>m|l@lLQX&a)TOsp%?2bklf)6f>YS2kcJDcS-ea^q7;(Iya$ zfHKLtL6&nj!Nl3=GG`f{az`=I3)8@}-EH7$;8_%8Sv0W(n3V^ryc{=D<5pl~eNg4? zxUv0I;DuW7t~u{TC%bEt6~`Ncw27^12y$*Y8|Ro}T-pY}<50&J9+_dy!a-9QHRO^-|w9SD}et@5wy{xzQN8JCP=1#N;($T(X&I zFNT!_j-~r>xpJ+LYlOj+W8X7S&ad}YbmTRX8~yR?or;Iu){BK(LY%&1AlDaFC7iGC zMn@mkUDPsDk>AgAMVa#kBLYjy{-BP~R^hccsa9iErP<+0Z^jCD6W~;lkW9s8ev7Og0|e=(qDe$X#s< zIn;0Gch1xQL}ELiVB}cuOSs(r_%P(2KpN#_EdZt5zu|Jn!38zp^Np+^(9fi+uLE+M NkV}2@jTH4&{a^3Im1F<_ literal 0 HcmV?d00001 diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h index faeefeca14..f8cd45ca4c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/pa.h @@ -39,22 +39,22 @@ extern "C" { #endif /***************************************************************************//** - * @addtogroup RF_Library + * @addtogroup Chip_Specific * @{ ******************************************************************************/ /***************************************************************************//** - * @addtogroup PA + * @addtogroup EFR32xG1x_PA * @{ ******************************************************************************/ /******************************************************************************* **************************** CONFIGURATION ******************************** ******************************************************************************/ +/** Scaling factor applied to all dBm power level inputs and outputs * */ #define PA_SCALING_FACTOR 10 /** - * @struct RADIO_PASel_t * @brief Selection of the rf power amplifier (PA) to use */ typedef enum RADIO_PASel @@ -64,9 +64,15 @@ typedef enum RADIO_PASel /** Low power PA */ PA_SEL_2P4_LP, /** SubGig PA*/ - PA_SEL_SUBGIG + PA_SEL_SUBGIG, + /** Invalid PA Selection */ + PA_SEL_INVALID } RADIO_PASel_t; +/** + * @brief Selection should match the configuration of the voltage on the vPa pin + * of the chip. + */ typedef enum RADIO_PAVoltMode { /** Vpa = Vbat = 3.3V */ @@ -76,7 +82,6 @@ typedef enum RADIO_PAVoltMode } RADIO_PAVoltMode_t; /** - * @struct RADIO_PAInit_t * @brief Configuration structure for the rf power amplifier (PA) */ typedef struct RADIO_PAInit { @@ -84,9 +89,9 @@ typedef struct RADIO_PAInit { RADIO_PASel_t paSel; /** Power Amplifier vPA Voltage mode */ RADIO_PAVoltMode_t voltMode; - /** Desired output power in dBm * 10 */ + /** Desired output power in dBm * \ref PA_SCALING_FACTOR */ int16_t power; - /** Output power offset in dBm * 10 */ + /** Output power offset in dBm * \ref PA_SCALING_FACTOR */ int16_t offset; /** Desired ramp time in us */ uint16_t rampTime; @@ -96,16 +101,169 @@ typedef struct RADIO_PAInit { ****************************** PROTOTYPES ********************************* ******************************************************************************/ -bool RADIO_PA_Init(RADIO_PAInit_t * paInit); -int32_t PA_OutputPowerGet(void); -int32_t PA_OutputPowerSet(int32_t power); -int32_t PA_MaxOutputPowerSet(void); -uint32_t PA_RampTimeGet(void); -uint32_t PA_RampTimeSet(uint32_t ramptime); -void PA_CTuneSet(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue); +/** + * @brief + * Initilize the PA settings based on the settings provided in the paInit + * structure. + * + * @param[in] paInit + * Pointer to a structure containing the desired PA configuration settings. + * + * @return + * True if the settings were accepted. + * False if settings were invalid. + * + * @warning + * The radio should not be transmitting when this function is called! +*/ +bool RADIO_PA_Init(RADIO_PAInit_t * paInit); -/** @} (end addtogroup PA) */ -/** @} (end addtogroup RF_Library) */ +/** + * @brief + * Returns the current power level of transmit power + * + * @return + * Current power level in dBm * \ref PA_SCALING_FACTOR + */ +int32_t PA_OutputPowerGet(void); + +/** + * @brief + * Sets the output power of the PA. + * + * Each PA has distinct maximum power, minimum power, and power step sizes. + * This API will calculate the best pa output power level setting to acheieve + * the desired output power. + * + * @note + * Board and chip variations will affect the accuracy of this API. Use + * of the RADIO_PAInit_t.offset paramter can help account for this variation. + * + * @param[in] power + * Power value in dBm * \ref PA_SCALING_FACTOR + * + * Examples with \ref PA_SCALING_FACTOR of 10: + * - 10 dBm --> 100 + * - 5.5 dBm --> 55 + * + * @return + * Returns the actual power that was set in dBm * \ref PA_SCALING_FACTOR + * + * @warning + * The radio should not be transmitting when this function is called! + */ +int32_t PA_OutputPowerSet(int32_t power); + +/** + * @brief + * Set the maximum possible output power for the selected PA. + * + * @return + * Returns the actual power that was set in dBm * \ref PA_SCALING_FACTOR + * + * @warning + * The radio should not be transmitting when this function is called! + */ +int32_t PA_MaxOutputPowerSet(void); + +/** + * @brief + * Return the current ramp time in microseconds + * + * @return + * Current ramp time in microseconds + */ +uint32_t PA_RampTimeGet(void); + +/** + * @brief + * Sets up the ramp configuration so that it best matches the given ramp time + * + * @details + * Each PA has a distinct ramp level and ramp rate that can be used to + * achieve various ramp times. This API will pick the ramp rate that closest + * approximates the desired ramp time. + * + * @param[in] ramptime + * Desired ramp time in microseconds + * + * @return + * The actual ramp time that was set in microseconds. + * + * @warning + * The radio should not be transmitting when this function is called! + */ +uint32_t PA_RampTimeSet(uint32_t ramptime); + +/***************************************************************************//** + * @addtogroup EFR32xG1x_PA_Advanced + * @{ + ******************************************************************************/ + +/** + * @brief + * Set PACTUNE value for TX and RX mode. + * + * This value can vary depending on band and match and board design. + * + * @param[in] txPaCtuneValue + * Transmit value for pa ctune + * @param[in] rxPaCtuneValue + * Receive value for pa ctune + * + * @note PACTUNE will reset to default values when RADIO_PA_Init() or + * RAIL_RadioConfig() are called. + * + * @warning + * The radio should not be transmitting when this function is called! + */ +void PA_CTuneSet(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue); + +/** + * @brief + * Set the output power level based on power steps available in the chosen PA. + * + * @details + * Each PA has distinct maximum power, minimum power, and power step sizes. + * This API allows direct access to these power steps to tune between the + * maximum and minimum output power the selected PA is capable of. + * + * @param[in] pwrLevel + * Output power level. Note that the maximum power level will change + * depending on PA selection. + * @param[in] boostMode + * Output boost mode. Some PA selections have a mode that will increase the + * output power for each step if this is enabled. + * + * @return + * MSB Configured boost mode. \n + * LSB Configured power level + * + * @warning + * The radio should not be transmitting when this function is called! + */ +uint16_t PA_PowerLevelSet(uint8_t pwrLevel, uint8_t boostMode); + +/** + * @brief + * Optimize the PA settings based on expected output power level. + * + * @details + * This API optimizes the current consumption of the radio based on the + * provided output power. This is only necessary when output power is + * controlled by PA_PowerLevelSet(). + * + * @param[in] power + * Power value in dBm * \ref PA_SCALING_FACTOR + * + * @warning + * The radio should not be transmitting when this function is called! + */ +void PA_PowerLevelOptimize(int32_t power); + +/** @} (end addtogroup EFR32xG1x_PA_Advanced) */ +/** @} (end addtogroup EFR32xG1x_PA) */ +/** @} (end addtogroup Chip_Specific) */ #ifdef __cplusplus } diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h index af1fb40699..b5d858d6ee 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail.h @@ -13,7 +13,7 @@ #include // Get the RAIL specific structures and types -#include "rail/rail_types.h" +#include "rail_types.h" /** * @addtogroup RAIL_API @@ -62,10 +62,9 @@ uint8_t RAIL_RfInit(const RAIL_Init_t *railInit); * @return Returns zero on success and an error code on error. * * The protocol is output via the Packet Trace Interface (PTI) for each packet. - * Before any protocol is set, the default value is \ref RAIL_PTI_PROTOCOL_CUSTOM. - * A custom value may be used if it does not conflict with one of the available - * \ref RAIL_PtiProtocol_t enum values, though values may only go up to \ref - * RAIL_PTI_PROTOCOL_MAX. + * Before any protocol is set, the default value is \ref + * RAIL_PTI_PROTOCOL_CUSTOM. One of the enum values should be used in order for + * Network Analyzer to be able to decode the packet. */ RAIL_Status_t RAIL_SetPtiProtocol(RAIL_PtiProtocol_t protocol); @@ -76,7 +75,7 @@ RAIL_Status_t RAIL_SetPtiProtocol(RAIL_PtiProtocol_t protocol); * @return void * * Callback that notifies the application when the radio is finished - * initializing and is ready for further configuration. This is callback is + * initializing and is ready for further configuration. This callback is * useful for potential transceiver products that require a power up sequence * before further configuration is available. After this callback fires, the * radio is ready for additional configuration before transmit and receive @@ -110,7 +109,8 @@ RAIL_RadioState_t RAIL_RfStateGet(void); * This function fails if unsupported transitions are passed in, or if the * radio is currently in the RX state. Success can transition to TX, RX, or * IDLE, while error can transition to RX or IDLE. The full list of options for - * the ignoreErrors parameter is any define that starts with RAIL_IGNORE_. + * the ignoreErrors parameter is any define that starts with + * \link RAIL_IGNORE_NO_ERRORS RAIL_IGNORE_\endlink. */ RAIL_Status_t RAIL_SetRxTransitions(RAIL_RadioState_t success, RAIL_RadioState_t error, @@ -209,6 +209,20 @@ uint32_t RAIL_RfSense(RAIL_RfSenseBand_t band, uint32_t senseTime, bool enableCb */ bool RAIL_RfSensed(void); +/** + * Modify the currently configured fixed length + * + * @param[in] length Expected fixed length; 0 is infinite + * @return Length configured; 0xFFFF if not in fixed length, 0 if in infinite + * + * Set the fixed length configuration for transmit and receive. Users should + * be careful when using this function in receive and transmit. This function + * returns \ref RAIL_SETFIXEDLENGTH_INVALID if the radio is not in fixed length + * mode. The function returns 0 if in infinite length mode. Otherwise it will + * return the length configured into the hardware. + */ +uint16_t RAIL_SetFixedLength(uint16_t length); + /***************************************************************************//** * Collect entropy from the radio if available. * @@ -288,6 +302,7 @@ uint16_t RAIL_GetRadioEntropy(uint8_t *buffer, uint16_t bytes); * { * int i = 0; * void *ptr = NULL; + * CORE_DECLARE_IRQ_STATE; * * // We can't support sizes greater than the maximum buffer size * if(size > (MAX_PACKET_SIZE + sizeof(RAIL_RxPacketInfo_t))) { @@ -295,23 +310,23 @@ uint16_t RAIL_GetRadioEntropy(uint8_t *buffer, uint16_t bytes); * } * * // Disable interrupts and attempt to grab the buffer - * INT_Disable(); + * CORE_ENTER_CRITICAL(); * if (isAllocated) { * ptr = NULL; * } else { * isAllocated = true; * ptr = buffer; * } - * INT_Enable(); + * CORE_EXIT_CRITICAL(); * * return ptr; * } * * void RAILCb_FreeMemory(void *ptr) * { - * INT_Disable(); - * isAllocated = false; - * INT_Enable(); + * CORE_CRITICAL_SECTION( + * isAllocated = false; + * ); * } * * void *RAILCb_BeginWriteMemory(void *handle, @@ -391,6 +406,380 @@ void *RAILCb_BeginWriteMemory(void *handle, */ void RAILCb_EndWriteMemory(void *handle, uint32_t offset, uint32_t size); +/** + * @} + */ + +/****************************************************************************** + * Data Management + *****************************************************************************/ +/** + * @addtogroup Data_Management + * @brief Data management functions + * + * These functions allow the application to choose how data is presented to the + * application. There are two methods for RAIL to provide data, in a packet + * based method leveraging \ref Memory_Management callbacks or in a FIFO based + * method which gives the application more granularity and responsibility in + * managing transmit and receive data. + * + * The application can configure RAIL data mangement through RAIL_DataConfig(); + * this function allows the application to specify the type of radio data (\ref + * RAIL_TxDataSource_t and \ref RAIL_RxDataSource_t) and the method of + * interacting with this data (\ref RAIL_DataMethod_t). By default, RAIL + * configures Tx and Rx both with packet data source and packet mode. + * + * In packet based data management: + * - Load transmit data with RAIL_TxDataLoad() + * - Received data is returned in RAILCb_RxPacketReceived() + * - Packet lengths are determined from the Radio Configurator configuration + * - \ref Memory_Management callbacks will fire to ask for pointers to store + * data + * + * In FIFO based data management: + * - Load transmit data with RAIL_WriteTxFifo() + * - Received data is retrieved through RAIL_ReadRxFifo() + * - Packet Lengths are determined from the Radio Configurator configuration + * - Set fifo thresholds through RAIL_SetTxFifoThreshold() and + * RAIL_SetRxFifoThreshold() which fires RAILCb_RxFifoAlmostFull() and + * RAILCb_TxFifoAlmostEmpty(). + * - Get fifo count information through RAIL_GetRxFifoBytesAvailable() + * and RAIL_GetTxFifoSpaceAvailable() + * - Reset fifos with RAIL_ResetFifo() + * - CRC Error acceptance is on by default + * + * Both transmit and receive fifos are the same size; when trying to determine + * an appropriate threshold, the application can use + * RAIL_GetTxFifoSpaceAvailable() to query the size of the fifo if it is empty + * and use that as the size of the receive fifo as well. The transmit fifo is edge + * based where it only provides an interrupt once when the threshold is + * crossed. The receive fifo is level based where the interrupt will constantly + * pend if the threshold is exceeded. This normally means that inside + * RAILCb_RxFifoAlmostFull(), the application should empty enough of the fifo + * to go under the threshold. If the application wishes to defer reading the + * fifo to main, it can disable the receive fifo threshold interrupt via + * RAIL_DisableRxFifoThreshold(). The application can reenable the interrupt + * via RAIL_EnableRxFifoThreshold(). + * + * In fifo mode, the fifos can store multiple packets. Depending on traffic, + * RAIL can receive multiple packets into the receive fifo before the + * application gets around to reading out the received data from the fifo. If + * appended info is enabled, make sure to read out the appended info with + * RAIL_ReadRxFifoAppendedInfo() before attempting to read out the next packet. + * If the application aborts during packet reception, appended info will not be + * present in the receive fifo. If a frame error occurs in fifo mode, the + * contents of the receive fifo is unreliable and should be flushed. + * + * When calling RAIL_DataConfig() for fifo mode, RAIL will set \ref + * RAIL_IGNORE_CRC_ERRORS. Otherwise for packet mode, RAIL will set \ref + * RAIL_IGNORE_NO_ERRORS. It is highly suggested that the application maintains + * \ref RAIL_IGNORE_CRC_ERRORS in fifo mode if using hardware crc checking. + * + * While RAIL defaults to packet mode, the application can explicitly + * initialize RAIL for packet mode in the following manner: + * @code{.c} + * static const RAIL_DataConfig_t railDataConfig = { + * .txSource = TX_PACKET_DATA, + * .rxSource = RX_PACKET_DATA, + * .txMethod = PACKET_MODE, + * .rxMethod = PACKET_MODE, + * }; + * + * status = RAIL_DataConfig(&railDataConfig); + * + * // Callbacks that occur in Packet Mode + * void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo); + * void RAILCb_RxPacketReceived(void *rxPacketHandle); + * void *RAILCb_AllocateMemory(uint32_t size); + * void RAILCb_FreeMemory(void *handle); + * void *RAILCb_BeginWriteMemory(void *handle, + * uint32_t offset, + * uint32_t *available); + * void RAILCb_EndWriteMemory(void *handle, uint32_t offset, uint32_t size); + * @endcode + * + * Initializing RAIL for Fifo Mode requires a few more function calls: + * @code{.c} + * static const RAIL_DataConfig_t railDataConfig = { + * .txSource = TX_PACKET_DATA, + * .rxSource = RX_PACKET_DATA, + * .txMethod = FIFO_MODE, + * .rxMethod = FIFO_MODE, + * }; + * + * status = RAIL_DataConfig(&railDataConfig); + * + * // Get the size of the fifos + * // The transmit and receive fifos are the same size + * uint16_t fifoSize = RAIL_GetTxFifoSpaceAvailable(); + * + * // Set the transmit and receive fifo thresholds + * // For this example, set the threshold in the middle of each fifo + * RAIL_SetRxFifoThreshold(fifoSize / 2); + * RAIL_SetTxFifoThreshold(fifoSize / 2); + * + * //Callbacks that occur in Fifo mode + * void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo); + * void RAILCb_RxPacketReceived(void *rxPacketHandle); + * void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable); + * void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable); + * @endcode + * + * On receive, there are multiple data sources that an application can use that + * are only compatible with the fifo method of data delivery. All that differs + * from the fifo mode example above is the RAIL_DataConfig_t::rxSource setting. + * IQ data samples are taken at the hardware's oversample rate and the amount + * of data can easily overwhelm CPU processing time. The sample rate depends on + * the chosen PHY as is determined by the data rate as well as the decimation + * chain. It is not recommended to use the IQ data source with sample + * rates above 300k samples/second as the CPU might not be able to keep up with + * the data. Depending on the application and needed CPU bandwidth, slower + * data rates may be required. + * @code{.c} + * // IQ data is provided into the receive fifo + * static const RAIL_DataConfig_t railDataConfig = { + * .txSource = TX_PACKET_DATA, + * .rxSource = RX_IQDATA_FILTLSB, + * .txMethod = FIFO_MODE, + * .rxMethod = FIFO_MODE, + * }; + * + * // When reading IQ data out of the fifo, it comes in the following format: + * //------------------------------------ + * // I[LSB] | I[MSB] | Q[LSB] | Q[MSB] | + * //------------------------------------ + * @endcode + * + * @note \ref RAIL_DataConfig_t.txMethod and \ref RAIL_DataConfig_t.rxMethod + * must have the same \ref RAIL_DataMethod_t configuration. + * + * @warning Do not call RAIL fifo functions while in \ref + * RAIL_DataMethod_t::PACKET_MODE. + * @{ + */ + +/** + * RAIL data management configuration + * + * @param[in] dataConfig RAIL data configuration structure + * @return RAIL Status of configuration + * + * This function configures how RAIL manages data. The application can + * configure RAIL to receive data in a packet based or FIFO based format. When + * configuring tx or rx for fifo mode, this function will reset the configured + * fifos. + * + * If \ref RAIL_DataConfig_t.rxMethod is set to \ref + * RAIL_DataMethod_t.PACKET_MODE, the radio will filter packets with invalid + * CRCs by default. This is similar to setting the ignoreErrors + * parameter in RAIL_SetRxTransitions() to \ref RAIL_IGNORE_NO_ERRORS. + * + * If \ref RAIL_DataConfig_t.rxMethod is set to \ref + * RAIL_DataMethod_t.FIFO_MODE, the radio will accept packets with CRCs as + * 'valid' packets by default. This is meant to treat 'fully received' packets + * the same way regardless if CRC passes or fails. The application can parse + * CRC errors via appended info obtained from RAIL_ReadRxFifoAppendedInfo(). + * This is similar to setting the ignoreErrors parameter in + * RAIL_SetRxTransitions() to \ref RAIL_IGNORE_CRC_ERRORS. + * + * In either situation, the application can set ignoreErrors as needed; + * in fifo mode, appended info will not be present for frame errors. The + * defaults defined above are the recommended setting. + */ +RAIL_Status_t RAIL_DataConfig(RAIL_DataConfig_t *dataConfig); + +/** + * Write data to the transmit fifo + * + * @param[in] dataPtr Application provided pointer to transmit data + * @param[in] writeLength Number of bytes to write to the transmit fifo + * + * @return The number of bytes written to the transmit fifo + * + * This function reads data from the provided dataPtr and writes it to the TX + * Fifo. If the requested writeLength exceeds the current number of bytes open + * in the transmit fifo, the function will only write until the transmit fifo + * is full. The function returns the number of bytes written to the transmit + * fifo. + * + * @note This function does not create a critical section but depending on the + * application a critical section could be appropriate. + */ +uint16_t RAIL_WriteTxFifo(uint8_t *dataPtr, uint16_t writeLength); + +/** + * Read data from the receive fifo + * + * @param[out] dataPtr Application provided pointer to store data + * @param[in] readLength Number of bytes to read from the fifo + * + * @return The number of bytes read from the receive fifo + * + * This function reads data from the receive fifo and writes it to the provided + * dataPtr. If the requested readLength exceeds the current number of bytes in + * the receive fifo, the function will only read the current amount of bytes + * available. + * + * This function does not have a critical section, so either use it only in one + * context or make sure function calls are protected to prevent buffer + * corruption. + */ +uint16_t RAIL_ReadRxFifo(uint8_t *dataPtr, uint16_t readLength); + +/** + * Read appended info from the receive fifo + * + * @param[out] appendedInfo Application provided pointer to store RAIL_AppendedInfo_t + * @return void + * + * This function reads appended info from the receive fifo and writes it to the + * provided pointer; appended info is added to the receive fifo once a packet is + * received. Using this function while not at the end of a packet can corrupt + * your buffer by processing receive data as appended info. + * + * @note The following fields in appended info are not implemented in fifo mode and + * do not contain valid info: + * - RAIL_AppendedInfo_t.isAck + * - RAIL_AppendedInfo_t.lqi + * - RAIL_AppendedInfo_t.frameCodingStatus (will reflect the last received packet) + */ +void RAIL_ReadRxFifoAppendedInfo(RAIL_AppendedInfo_t *appendedInfo); + +/** + * Configure the RAIL transmit fifo almost empty threshold + * + * @param[in] txThreshold Threshold once fallen under + * will fire RAILCb_TxFifoAlmostEmpty() + * @return Configured transmit fifo threshold value + * + * This function configures the threshold for the transmit fifo. When the count + * of the transmit fifo is less than the configured threshold, + * RAILCb_TxFifoAlmostEmpty() will fire. A value of 0 is invalid and will not + * change the current configuration. + */ +uint16_t RAIL_SetTxFifoThreshold(uint16_t txThreshold); + +/** + * Configure the RAIL receive fifo almost full threshold + * + * @param[in] rxThreshold Threshold once exceeded will fire + * RAILCb_RxFifoAlmostFull() + * @return Configured receive fifo threshold value + * + * This function configures the threshold for the transmit fifo. When the count + * of the receive fifo is greater than the configured threshold, + * RAILCb_RxFifoAlmostFull() will fire. A value of 0xFFFF is invalid and will + * not change the current configuration. Depending on the hardware the maximum + * value can vary. If the rxThreshold value exceeds the capability of the + * hardware, the rx threshold will be configured so that it fires only when the + * FIFO is one byte away from being full. + * + */ +uint16_t RAIL_SetRxFifoThreshold(uint16_t rxThreshold); + +/** + * Get the RAIL transmit fifo almost empty threshold value + * + * @return Configured Tx Threshold value + * + * Retrieve the configured tx threshold value + */ +uint16_t RAIL_GetTxFifoThreshold(void); + +/** + * Get the RAIL receive fifo almost full threshold value + * + * @return Configured Rx Threshold value + * + * Retrieve the configured rx threshold value + */ +uint16_t RAIL_GetRxFifoThreshold(void); + +/** + * Enable the RAIL receive fifo threshold interrupt + * + * @return void + * + * Enable the RAIL receive fifo threshold interrupt. + */ +void RAIL_EnableRxFifoThreshold(void); + +/** + * Disable the RAIL receive fifo threshold interrupt + * + * @return void + * + * Disable the RAIL receive fifo threshold interrupt. This is useful if the + * application wishes to defer reading the receive fifo into another context. + */ +void RAIL_DisableRxFifoThreshold(void); + +/** + * Reset the RAIL Fifos + * + * @param[in] txFifo If true, reset the transmit fifo + * @param[in] rxFifo If true, reset the receive fifo + * @return void + * + * This function can reset each fifo. The application should not reset the Rx + * Fifo while receiving a frame. + */ +//@TODO interrupt protect when clearing; need to check race conditions with hw team +void RAIL_ResetFifo(bool txFifo, bool rxFifo); + +/** + * Get the number of bytes in the receive fifo + * + * @return Number of bytes in the receive fifo + * + * Get the number of bytes in the receive fifo + */ +uint16_t RAIL_GetRxFifoBytesAvailable(void); + +/** + * Get the number of bytes open in the transmit fifo + * + * @return Number of bytes open in the transmit fifo + * + * Get the number of bytes open in the transmit fifo + */ +uint16_t RAIL_GetTxFifoSpaceAvailable(void); + +/** + * Callback that fires when the receive fifo exceeds the configured threshold + * value + * + * @param[in] bytesAvailable Number of bytes available in the receive fifo at + * the time of the callback dispatch + * + * @return void + * @warning You must implement a stub for this in your RAIL application. + * + * Callback that fires when the receive fifo exceeds the configured threshold + * value. Provides the number of bytes available in the receive fifo at the + * time of the callback dispatch. + */ +void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable); + +/** + * Callback that fires when the transmit fifo falls under the configured + * threshold value + * + * @param[in] spaceAvailable Number of bytes open in the transmit fifo at the + * time of the callback dispatch + * + * @return void + * @warning You must implement a stub for this in your RAIL application. + * + * Callback that fires when the transmit fifo falls under the configured + * threshold value. It only fires if a rising edge occurs across this + * threshold. This callback will not fire on initailization nor after resetting + * the transmit fifo with RAIL_ResetFifo(). + * + * Provides the number of bytes open in the transmit fifo at the time of the + * callback dispatch. + */ +void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable); /** * @} */ @@ -564,7 +953,9 @@ uint8_t RAIL_RadioConfig(void *radioConfig); * * @param[in] frameType Frame type configuration structure. * - * Currently the frame type passed in only handles packet length decoding. + * Currently the frame type passed in only handles packet length decoding. If + * NULL is passed into this function, it will clear any currently configured + * frame type settings. */ void RAIL_PacketLengthConfigFrameType(const RAIL_FrameType_t *frameType); @@ -598,7 +989,7 @@ RAIL_Status_t RAIL_ChannelExists(uint8_t channel); * * @return The symbol rate in symbols per second * - * The symbol rate is the number of symbol changes over the air. For non DSSS + * The symbol rate is the rate of symbol changes over the air. For non-DSSS * PHYs this is the same as the baudrate. For DSSS PHYs it is the baudrate * divided by the length of a chipping sequence. For more information on this * consult the modem calculator documentation. @@ -647,8 +1038,8 @@ RAIL_Status_t RAIL_PaCtuneSet(uint8_t txPaCtuneValue, uint8_t rxPaCtuneValue); /** * Set the radio transmit power level * - * @param[in] powerLevel TX Power Level defined in deci dBm (0.0 dBm) - * @return TX Power Level in deci dBm (0.0 dBm) + * @param[in] powerLevel TX Power Level defined in deci dBm (10 * dBm) + * @return TX Power Level in deci dBm (10 * dBm) * * Not all values of powerLevel are achievable, but this function will set the * power output to be close to the given powerLevel, and return the value that @@ -659,7 +1050,7 @@ int32_t RAIL_TxPowerSet(int32_t powerLevel); /** * Get the radio transmit power level * - * @return TX Power Level defined in deci dBm (0.0 dBm) + * @return TX Power Level defined in deci dBm (10 * dBm) * * This will return what the power output was actually set to, not just the * value passed into RAIL_TxPowerSet. @@ -667,19 +1058,39 @@ int32_t RAIL_TxPowerSet(int32_t powerLevel); int32_t RAIL_TxPowerGet(void); /** - * Load payload to send. + * Configure which radio transmit actions trigger callbacks + * + * @param[in] cbToEnable Define which callbacks to trigger for transmit events. + * The full list of available callabcks can be found by looking at the + * RAIL_TX_CONFIG_* set of defines. + * @return Return 0 for success or an error code + * + * Setup which receive interrupts will generate a RAILCb_TxRadioStatus() + * callback. The full list of options is any define that starts with + * RAIL_TX_CONFIG_. Before this function is called, the actions which will + * generate callbacks are: + * - \ref RAIL_TX_CONFIG_BUFFER_UNDERFLOW + * - \ref RAIL_TX_CONFIG_CHANNEL_BUSY + * - \ref RAIL_TX_CONFIG_TX_ABORTED + * - \ref RAIL_TX_CONFIG_TX_BLOCKED + */ +RAIL_Status_t RAIL_TxConfig(uint32_t cbToEnable); + +/** + * Load payload to transmit. * * @param[in] txData Pointer to a RAIL_TxData_t structure which defines the - * payload bytes and length to transmit. If the fields are configured for - * fixed length. + * payload bytes and the number of bytes to write into the transmit buffer. * @return Returns 0 on success and an error code on fail. * - * This function may overwrite current TX data held by RAIL, and should not be - * called repetitively or during TX. The recommended way to use this is to call - * RAIL_TxDataLoad() and RAIL_TxStart() almost immediately in succession. + * This function will overwrite current TX data held by RAIL, and will return + * an error if called during transmit operations. RAIL_TxData_t.dataLength + * defines the number of bytes to load into the transmit buffer from + * RAIL_TxData_t.dataPtr while the number of bytes transmitted is determined by + * the packet configuration defined in the radio configuration. * - * Will return \ref RAIL_STATUS_INVALID_CALL if the Tx buffer is in use by the - * radio and cannot be updated. + * @note This function creates a critical section while writing to the transmit + * buffer. */ uint8_t RAIL_TxDataLoad(RAIL_TxData_t *txData); @@ -692,12 +1103,14 @@ uint8_t RAIL_TxDataLoad(RAIL_TxData_t *txData); * @param[in] preTxOpParams Pointer to the pre-transmit operation's * configuration parameters, or NULL if none. * @return Returns 0 on successfully initiating the transmit process, or an - * error code on failure. If successfully initiated, transmit completion + * error code on failure. If successfully initiated, transmit completion * or failure will be reported by later callbacks RAILCb_TxPacketSent() * (success) or RAILCb_TxRadioStatus() (failure). * * Begins transmission of the payload previously loaded via RAIL_TxDataLoad(). - * Return error if currently transmitting or receiving. + * Will begin transmitting after a received packet if currently receiving a + * packet. Returns error if the radio is active and the channel needs to be + * changed. */ uint8_t RAIL_TxStart(uint8_t channel, RAIL_PreTxOp_t preTxOp, @@ -722,7 +1135,9 @@ uint8_t RAIL_TxStart(uint8_t channel, * transmit options will only be configured if the preTxOp is successful. * * Begins transmission of the payload previously loaded via RAIL_TxDataLoad(). - * Return error if currently transmitting or receiving. + * Will begin transmitting after a received packet if currently receiving a + * packet. Returns error if the radio is active and the channel needs to be + * changed. */ uint8_t RAIL_TxStartWithOptions(uint8_t channel, RAIL_TxOptions_t *options, @@ -754,6 +1169,9 @@ void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo); * - \ref RAIL_TX_CONFIG_CHANNEL_BUSY * - \ref RAIL_TX_CONFIG_TX_ABORTED * - \ref RAIL_TX_CONFIG_TX_BLOCKED + * - \ref RAIL_TX_CONFIG_CHANNEL_CLEAR + * - \ref RAIL_TX_CONFIG_CCA_RETRY + * - \ref RAIL_TX_CONFIG_START_CCA */ void RAILCb_TxRadioStatus(uint8_t status); @@ -792,7 +1210,9 @@ void RAILCb_TxRadioStatus(uint8_t status); * * A RAIL_PreTxOp_t function that schedules the transmit to occur at the * specified absolute or relative time within a RAIL_TxStart() transmit - * operation. + * operation. If RAIL is receiving a packet at the scheduled time, the transmit + * will be delayed until after the packet is received. To guarantee the time of + * the outgoing transmit, only call this function while the radio is idle. */ uint8_t RAIL_ScheduleTx(void *params); @@ -804,8 +1224,15 @@ uint8_t RAIL_ScheduleTx(void *params); * @return - Returns 0 on success and anything else on error. * * A RAIL_PreTxOp_t function that performs the CSMA algorithm when specified - * within a RAIL_TxStart() transmit operation. + * within a RAIL_TxStart() transmit operation. Packets can be received during + * CSMA backoff periods if receive is active throughout the CSMA process. This + * will happen either by starting the CSMA process while receive is already + * active, or if the ccaBackoff time in the RAIL_CsmaConfig_t is less than the + * idleToRx time (set by RAIL_SetStateTimings). If the ccaBackoff time is + * greater than the idleToRx time, then receive will only be active during the + * clear channel assessments. */ + uint8_t RAIL_CcaCsma(void *params); /** @@ -816,10 +1243,32 @@ uint8_t RAIL_CcaCsma(void *params); * @return Returns 0 on success and anything else on error. * * A RAIL_PreTxOp_t function that performs the LBT algorithm when specified - * within a RAIL_TxStart() transmit operation. + * within a RAIL_TxStart() transmit operation. Packets can be received during + * CSMA backoff periods if receive is active throughout the LBT process. This + * will happen either by starting the LBT process while receive is already + * active, or if the lbtBackoff time in the RAIL_LbtConfig_t is less than the + * idleToRx time (set by RAIL_SetStateTimings). If the lbtBackoff time is + * greater than the idleToRx time, then receive will only be active during the + * clear channel assessments. */ uint8_t RAIL_CcaLbt(void *params); +/** + * Sets the CCA threshold in dBm + * + * @param[in] ccaThresholdDbm CCA threshold in dBm. + * @return \ref RAIL_STATUS_NO_ERROR on success. + * + * A RAIL_PreTxOp_t function will normally set CCA threshold, assuming it is + * enabled either in LBT or CSMA mode. Unlike RAIL_CcaCsma and RAIL_CcaLbt, + * which are called as RAIL_PreTxOp_t functions, this function only modifies + * CCA threshold. A possible usecase for this function is to set CCA threshold + * to invalid RSSI of -128 which disables transmission by canceling + * the current CCA check. + * + */ +RAIL_Status_t RAIL_SetCcaThreshold(int8_t ccaThresholdDbm); + /** * end of group Pre-Transmit * @} @@ -850,10 +1299,23 @@ uint8_t RAIL_CcaLbt(void *params); * * Setup which receive interrupts will generate a RAILCb_RxRadioStatus() * callback. The full list of options is any define that starts with - * RAIL_RX_CONFIG_. This function cannot be called while receiving. + * RAIL_RX_CONFIG_. */ uint8_t RAIL_RxConfig(uint32_t cbToEnable, bool appendedInfoEnable); +/** + * Configure receive options + * + * @param[in] options Bitfield of options which affect recieve. The available + * options begin with RAIL_RX_OPTION. + * @return Return 0 for success or an error code + * + * Configure the radio receive flow, based on the list of available options. + * This will fail with RAIL_STATUS_INVALID_STATE if a packet is being received + * during this configuration. + */ +RAIL_Status_t RAIL_SetRxOptions(uint32_t options); + /** * Listen on a channel for a packet * @@ -861,7 +1323,7 @@ uint8_t RAIL_RxConfig(uint32_t cbToEnable, bool appendedInfoEnable); * @return Return 0 for success or an error code * * This is a non-blocking function. RAILCb_RxPacketReceived() will be called - * when a packet has been received. Returns an error is currently transmitting + * when a packet has been received. Returns an error if currently transmitting * or receiving. */ uint8_t RAIL_RxStart(uint8_t channel); @@ -878,7 +1340,7 @@ uint8_t RAIL_RxStart(uint8_t channel); * end time then you may call this API later with an end time as long as you set * the start time to disabled. You can also terminate the whole receive * operation immediately using the RAIL_RfIdle() function. Note that relative - * end times are always relative to the start unless there is not start + * end times are always relative to the start unless there is no start time * specified. */ uint8_t RAIL_ScheduleRx(uint8_t channel, RAIL_ScheduleRxConfig_t *cfg); @@ -899,6 +1361,71 @@ uint8_t RAIL_ScheduleRx(uint8_t channel, RAIL_ScheduleRxConfig_t *cfg); */ int16_t RAIL_RxGetRSSI(void); +/** + * Compute the average RSSI over a specified time in us + * + * @param[in] averageTimeUs Averaging time in microseconds. + * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled and we are + * unable to get an RSSI value, otherwise, return the RSSI in quarter dBm, + * dbm*4. + * + * This blocking function will poll the hardware for RSSI values and compute + * the average RSSI over the requested time period. If no valid readings have + * been made function will return \ref RAIL_RSSI_INVALID reading. Receiving a + * packet during the averaging will cause invalid reading(s). However, invalid + * readings during the averaging will not be included in the average. Number of + * RSSI readings per baud depends on the phy. + */ +int16_t RAIL_PollAverageRSSI(uint32_t averageTimeUs); + +/** + * Start the RSSI averaging over specified time in us + * + * @param[in] channel The physical channel to set + * @param[in] averagingTimeUs Averaging time in microseconds. + * @return Returns 0 on success, error code on error. + * + * Start a non-blocking hardware based RSSI averaging mechanism. Only a single + * instance of RSSI averaging can be run at any time and the radio must be idle + * to start. + */ +RAIL_Status_t RAIL_StartAverageRSSI(uint8_t channel, uint32_t averagingTimeUs); + +/** + * Queries whether the RSSI averaging is done + * + * @return Returns true if done and false otherwise. + * + * This function can be used to poll for completion of the RSSI averaging so + * that you do not have to rely on an interrupt based callback. + */ +bool RAIL_AverageRSSIReady(void); + +/** + * Get the RSSI averaged over specified time in us + * + * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled and we are + * unable to get an RSSI value, otherwise, return the RSSI in quarter dBm, + * dbm*4. + * + * Get the hardware RSSI average after issuing RAIL_StartAverageRSSI. Should be + * used after RAIL_StartAverageRSSI. + */ +int16_t RAIL_GetAverageRSSI(void); + +/** + * Callback for when AGC averaged RSSI is done + * + * @param avgRssi Contains the the RSSI in quarter dBm (dbm*4) on success and + * returns \ref RAIL_RSSI_INVALID if there was a problem computing the result. + * + * Called in response to RAIL_StartAverageRSSI() to indicate that the hardware + * has completed averaging. If you would like you can instead use the + * RAIL_AverageRSSIReady() to wait for completion and RAIL_GetAverageRSSI() to + * get the result. + */ +void RAILCb_RssiAverageDone(int16_t avgRssi); + /** * Receive packet callback. * @@ -912,6 +1439,9 @@ int16_t RAIL_RxGetRSSI(void); * stored. After this callback is done we will release the memory handle so you * must somehow increment a reference count or copy the data out within this * function. + * + * If \ref RAIL_IGNORE_CRC_ERRORS is set, this callback will fire for packets + * with crc errors as well. */ void RAILCb_RxPacketReceived(void *rxPacketHandle); @@ -965,6 +1495,7 @@ void RAILCb_RxRadioStatus(uint8_t status); * - \ref RAIL_RX_CONFIG_RF_SENSED * - \ref RAIL_RX_CONFIG_TIMEOUT * - \ref RAIL_RX_CONFIG_SCHEDULED_RX_END + * - \ref RAIL_RX_CONFIG_PACKET_ABORTED */ void RAILCb_RxRadioStatusExt(uint32_t status); @@ -1031,8 +1562,9 @@ void RAILCb_RxRadioStatusExt(uint32_t status); * ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD. For more complex systems you'll have to * create a valid table on your own. * - * @note When using a 38.4 MHz crystal, address filtering will not function with - * any data rate greater than 1Mbps. + * @note Address filtering does not function properly with PHYs that use a data + * rate greater than 500kbps. If you require this you must filter in software + * for the time being. * * @{ */ @@ -1139,7 +1671,7 @@ bool RAIL_AddressFilterDisableAddress(uint8_t field, uint8_t index); * * @param validFrames The frames on which to enable address filtering. Each bit * corresponds to a frame, where a 1 means to enable address filtering during - * that frame, and a 0 means to ignore addresses during that frame.. The least + * that frame, and a 0 means to ignore addresses during that frame. The least * significant bit corresponds to frame 0, and the most significant bit to * frame 7. * @return True if configuration was set properly, false otherwise @@ -1216,6 +1748,8 @@ bool RAIL_AddressFilterByFrameType(uint8_t validFrames); * @code{.c} * void RAILCb_RxPacketReceived(void *rxPacketHandle) * { + * RAIL_RxPacketInfo_t rxPacketInfo = (RAIL_RxPacketInfo_t)rxPacketHandle; + * * // If we have just received an ACK, don't respond with an ACK * if (rxPacketInfo->dataPtr[2] == 0xF1) * { @@ -1589,6 +2123,7 @@ uint8_t RAIL_TxStreamStop(void); * During BER test mode, this device will expect to receive a standard PN9 * signal (x^9 + x^5 + 1). In order to use this BER test, the selection * for BER mode should be enabled from the radio configurator. + * This function has been deprecated. */ void RAIL_BerConfigSet(RAIL_BerConfig_t *berConfig); @@ -1599,6 +2134,7 @@ void RAIL_BerConfigSet(RAIL_BerConfig_t *berConfig); * * Enter BER receive with the settings specified by RAIL_BerConfigSet(). * This also resets the BER status. + * This function has been deprecated. */ void RAIL_BerRxStart(void); @@ -1608,6 +2144,7 @@ void RAIL_BerRxStart(void); * @return void * * Halt a test early, or exit infinite BER receive mode. + * This function has been deprecated. */ void RAIL_BerRxStop(void); @@ -1618,6 +2155,7 @@ void RAIL_BerRxStop(void); * @return void * * Get status of latest BER test. + * This function has been deprecated. */ void RAIL_BerStatusGet(RAIL_BerStatus_t *status); @@ -1658,7 +2196,7 @@ uint32_t RAIL_DebugModeGet(void); * * @param[in] freq Desired frequency in Hz * - * Sets the radio to transmit at a the frequency given. This function can only + * Sets the radio to transmit at the frequency given. This function can only * be used while in RAIL_DEBUG_MODE_FREQ_OVERRIDE. The given frequency needs * to be close to the base frequency of the current PHY. */ @@ -1666,24 +2204,21 @@ RAIL_Status_t RAIL_DebugFrequencyOverride(uint32_t freq); #endif /** - * Interrupt level callback to signify when the radio changes state. This is - * for debug and __NOT__ for application use. It is not called by default but - * is required for the linking process. + * Callback function to signify when the radio changes state. * - * Create an empty function for this callback. + * @param[in] state Current state of the radio. Exact values are for internal + * use only. + * + * This is for debug and __NOT__ for application use. It is not called by + * default but is required for the linking process. + * + * Create an empty function for this callback as shown below. * * @code{.c} * RAILCb_RadioStateChanged(uint8_t state) { * } * @endcode */ -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * @param[in] state Current state of the radio, as defined by EFR32 data sheet - * TODO: Unify these states with the RAIL_RadioState_t type? (There are much - * more than just TX, RX, and IDLE) - */ -#endif void RAILCb_RadioStateChanged(uint8_t state); /** diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h index fad46dab6c..dfe2c87305 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_chip_specific.h @@ -31,13 +31,16 @@ * something that can be computed once and stored off or computed each time at * startup. It is PHY specific and provides sensitivity improvements so we * highly recommend using it. The IR calibration should only be run when the - * radio is IDLE. The temperature dependent calibrations are used to - * recalibrate the synth if the temperature falls below 0 or changes by a - * certain amount while sitting in receive. We will do this automatically upon - * entering the receive state so you may omit this calibration if you feel that - * your stack will turn receive on and off frequently enough. If you do not - * calibrate for temperature it's possible to miss receive packets due to drift - * in the carrier frequency. + * radio is IDLE. + * + * The temperature dependent calibrations are used to recalibrate the synth if + * the temperature crosses 0C or the temperature delta since the last + * calibration exceeds 70C while sitting in receive. RAIL will run VCO + * calibration automatically upon entering receive state so the application can + * omit this calibration if the stack will re-enter receive with enough + * frequency to not hit this temperature delta. If the application does not + * calibrate for temperature, it's possible to miss receive packets due to + * drift in the carrier frequency. */ /** diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h index 75de9d0e98..8578404bb7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/efr32-rf-driver/rail/rail_types.h @@ -13,7 +13,7 @@ #include #include -#include "rail/rail_chip_specific.h" +#include "rail_chip_specific.h" /** * @addtogroup RAIL_API @@ -77,7 +77,7 @@ typedef struct RAIL_Version { * @brief Initialization structure for the RAIL library. */ typedef struct RAIL_Init { - uint16_t maxPacketLength; /**< The maximum number of bytes in a packet. */ + uint16_t maxPacketLength; /**< The maximum number of bytes in a packet. UNUSED! */ const uint32_t rfXtalFreq; /**< The xtal frequency of the radio. */ RAIL_CalMask_t calEnable; /**< Mask that defines calibrations to perform in RAIL. */ } RAIL_Init_t; @@ -88,11 +88,10 @@ typedef struct RAIL_Init { */ typedef enum RAIL_PtiProtocol { RAIL_PTI_PROTOCOL_CUSTOM = 0, /**< PTI output for a custom protocol */ - RAIL_PTI_PROTOCOL_ZIGBEE = 1, /**< PTI output for the Zigbee protocol */ RAIL_PTI_PROTOCOL_THREAD = 2, /**< PTI output for the Thread protocol */ RAIL_PTI_PROTOCOL_BLE = 3, /**< PTI output for the Bluetooth Smart protocol */ RAIL_PTI_PROTOCOL_CONNECT = 4, /**< PTI output for the Connect protocol */ - RAIL_PTI_PROTOCOL_MAX = 0xF /**< Maximum possible protocol value for PTI */ + RAIL_PTI_PROTOCOL_ZIGBEE = 5, /**< PTI output for the Zigbee protocol */ } RAIL_PtiProtocol_t; /** @@ -150,9 +149,80 @@ typedef enum { * abort all current operations and cancel any pending scheduled operations. * It may also corrupt receive or transmit buffers and end up clearing them. */ - RAIL_IDLE_FORCE_SHUTDOWN + RAIL_IDLE_FORCE_SHUTDOWN, + /** + * Similar to the \ref RAIL_IDLE_FORCE_SHUTDOWN command this will quickly + * put the radio into the idle state. In addition to this it will clear any + * pending receive or transmit callbacks and clear both the receive and + * transmit storage. + */ + RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS } RAIL_RfIdleMode_t; +/** + * @} + */ + +// ----------------------------------------------------------------------------- +// Data Management Structures +// ----------------------------------------------------------------------------- + +/** + * @addtogroup Data_Management + * @{ + */ + +/** + * @enum RAIL_TxDataSource_t + * @brief Transmit data sources supported by RAIL. + */ +typedef enum{ + TX_PACKET_DATA, /**< Use the frame hardware to packetize data */ +} RAIL_TxDataSource_t; + +/** + * @enum RAIL_RxDataSource_t + * @brief Receive data sources supported by RAIL. + */ +typedef enum{ + RX_PACKET_DATA, /**< Use the frame hardware to packetize data */ + RX_DEMOD_DATA, /**< Get 8-bit data output from the demodulator */ + RX_IQDATA_FILTLSB, /**< Get lower 16 bits of I/Q data provided to demodulator */ + RX_IQDATA_FILTMSB /**< Get highest 16 bits of I/Q data provided to demodulator */ +} RAIL_RxDataSource_t; + +/** + * @enum RAIL_DataMethod_t + * @brief Methods for the application to provide and retreive data from RAIL. + */ +typedef enum{ + PACKET_MODE, /**< Packet based data method */ + FIFO_MODE, /**< FIFO based data method */ +} RAIL_DataMethod_t; + +/** + * @struct RAIL_DataConfig_t + * @brief RAIL data configuration structure + * + * This structure is used to select the transmit/receive data sources, and the + * method the application uses to provide/retreive data from RAIL. + */ +typedef struct { + RAIL_TxDataSource_t txSource; /**< Source of TX Data */ + RAIL_RxDataSource_t rxSource; /**< Source of RX Data */ + RAIL_DataMethod_t txMethod; /**< Method of providing transmit data */ + RAIL_DataMethod_t rxMethod; /**< Method of retrieving receive data */ +} RAIL_DataConfig_t; + +/** + * @def RAIL_SETFIXEDLENGTH_INVALID + * @brief Invalid return value when calling RAIL_SetFixedLength() + * + * Invalid return value when calling RAIL_SetFixedLength() while the radio is + * not in fixed length mode. + */ +#define RAIL_SETFIXEDLENGTH_INVALID (0xFFFF) + /** * @} */ @@ -203,6 +273,8 @@ typedef struct RAIL_FrameType { * channel space and the channel indexes that are valid within this range. * * * frequency = baseFrequency + channelSpacing * (channel - channelNumberStart); + * + * Each RAIL_ChannelConfigEntry_t should not span more than 64 channels. */ typedef struct RAIL_ChannelConfigEntry { uint16_t channelNumberStart; /**< RAIL Channel number in which this channel set begins.*/ @@ -214,7 +286,47 @@ typedef struct RAIL_ChannelConfigEntry { /** * @struct RAIL_ChannelConfig_t * @brief Channel configuration structure which defines the channel meaning when - * passed into RAIL functions, eg. RAIL_TxStart(), RAIL_RxStart() + * a channel number is passed into a RAIL function, eg. RAIL_TxStart(), RAIL_RxStart() + * + * A RAIL_ChannelConfig_t structure defines the channel scheme that an + * application uses when registered in RAIL_ChannelConfig(). A channel scheme + * must be in the same band, it can not span across frequencies that would + * change the divider. + * + * A few examples of different channel schemes: + * @code{.c} + * // Ten channels starting a 915 Mhz with a channel spacing of 1 Mhz + * RAIL_ChannelConfigEntry_t channels = { + * 0, 9, 1000000, 915000000 + * }; + * RAIL_ChannelConfig_t channelScheme = { + * channels, + * 1 + * }; + * + * // 120 channels starting at 915Mhz with channel spacing of 100KHz + * RAIL_ChannelConfigEntry_t channels[] = { + * {0, 63, 100000, 910000000}, + * {64, 119, 100000, 916400000}, + * }; + * RAIL_ChannelConfig_t channelScheme = { + * channels, + * 2 + * }; + * + * // 5 nonlinear channels + * RAIL_ChannelConfigEntry_t channels[] = { + * {0, 0, 0, 910123456}, + * {1, 1, 0, 911654789}, + * {2, 2, 0, 912321456}, + * {3, 3, 0, 913147852}, + * {4, 4, 0, 914567890} + * }; + * RAIL_ChannelConfig_t channelScheme = { + * channels, + * 5 + * }; + * @endcode */ typedef struct RAIL_ChannelConfig { RAIL_ChannelConfigEntry_t *configs; /**< Pointer to an array of RAIL_ChannelConfigEntry_t entries.*/ @@ -314,13 +426,39 @@ typedef struct RAIL_AddrConfig { /** * @enum RAIL_TimeMode_t - * @brief Enumeration for specifying timing offsets in RAIL for any APIs that - * use them. + * @brief This type is used to specifying a time offset in RAIL APIs. + * + * Different APIs use these same constants and may provide more specifics of how + * they're used but the general philosophy for each is described below. */ typedef enum RAIL_TimeMode { - RAIL_TIME_ABSOLUTE, /**< The time specified is an exact time in the RAIL timebase */ - RAIL_TIME_DELAY, /**< The time specified is relative to now */ - RAIL_TIME_DISABLED /**< The time specified is not intended to be used */ + /** + * The time specified is an exact time in the RAIL timebase and the given + * event should happen at exactly that time. If this time is already in the + * past we will return an error and fail. Since the RAIL timebase wraps at 32 + * bits there is no real 'past' so we instead consider any event greater than + * 3/4 of the way into the future to be in the past. + */ + RAIL_TIME_ABSOLUTE, + /** + * The time specified is relative to now and the event should occur that many + * ticks in the future. Delays are only guaranteed to be at least as long as + * the value specified. There may be some overhead between when the API is + * called and when the delay starts so we _do not_ recommend using this for + * operations that must happen at exactly a given time. For that you must use + * \ref RAIL_TIME_ABSOLUTE delays. + * + * Note that if you specify a delay of 0 we will trigger that event as soon as + * possible. This is different than specifying an absolute time of now which + * would return an error unless it was possible. + */ + RAIL_TIME_DELAY, + /** + * The specified time is invalid and should be ignored. For some APIs this can + * also indicate that any previously stored delay should be invalidated and + * disabled. + */ + RAIL_TIME_DISABLED } RAIL_TimeMode_t; /** @@ -350,8 +488,17 @@ typedef uint8_t (*RAIL_PreTxOp_t)(void *params); * must be passed as its argument. */ typedef struct RAIL_ScheduleTxConfig { - uint32_t when; /**< When to transmit this packet in the RAIL timebase. */ - RAIL_TimeMode_t mode; /**< Specifies whether when is an absolute time or an offset from now. */ + /** + * When to transmit this packet. The exact interpretation of this value + * depends on the mode specified below. + */ + uint32_t when; + /** + * They type of delay to use. See the \ref RAIL_TimeMode_t documentation for + * more information. Be sure to use \ref RAIL_TIME_ABSOLUTE delays for time + * critical protocols. + */ + RAIL_TimeMode_t mode; } RAIL_ScheduleTxConfig_t; /** @@ -368,8 +515,14 @@ typedef struct RAIL_ScheduleTxConfig { * argument. */ typedef struct RAIL_CsmaConfig { - uint8_t csmaMinBoExp; /**< Minimum (starting) exponent for CSMA backoff (2^exp - 1) */ - uint8_t csmaMaxBoExp; /**< Maximum exponent for CSMA backoff */ + /** + * Minimum (starting) exponent for CSMA backoff (2^exp - 1) + */ + uint8_t csmaMinBoExp; + /** + * Maximum exponent for CSMA backoff + */ + uint8_t csmaMaxBoExp; /** * Number of CCA failures before report CCA_FAIL. With a maximum value defined * in @ref RAIL_MAX_LBT_TRIES). A value of 0 will perform no CCA assessments, @@ -383,15 +536,16 @@ typedef struct RAIL_CsmaConfig { int8_t ccaThreshold; /** * The backoff unit period, in RAIL's microsecond time base. This is - * mulitiplied by the random backoff multiplier controlled by @ref + * mulitiplied by the random backoff exponential controlled by @ref * csmaMinBoExp and @ref csmaMaxBoExp to determine the overall backoff - * period. This value must be at least the idleToRx time (set by - * RAIL_SetStateTimings). For random backoffs, any value above 511 - * microseconds will be truncated; for fixed backoffs it can go up to 65535 - * microseconds. + * period. For random backoffs, any value above 511 microseconds will + * be truncated; for fixed backoffs it can go up to 65535 microseconds. */ uint16_t ccaBackoff; - uint16_t ccaDuration; /**< CCA check duration, in microseconds */ + /** + * CCA check duration in microseconds. + */ + uint16_t ccaDuration; /** * An overall timeout, in RAIL's microsecond time base, for the operation. If * transmission doesn't start before this timeout expires, the transmission @@ -442,14 +596,20 @@ typedef struct RAIL_CsmaConfig { * argument. */ typedef struct RAIL_LbtConfig { - uint8_t lbtMinBoRand; /**< Minimum backoff random multiplier */ - uint8_t lbtMaxBoRand; /**< Maximum backoff random multiplier */ + /** + * Maximum backoff random multiplier + */ + uint8_t lbtMinBoRand; + /** + * Maximum backoff random multiplier + */ + uint8_t lbtMaxBoRand; /** * Number of CCA failures before report CCA_FAIL. With a maximum value defined * in @ref RAIL_MAX_LBT_TRIES). A value of 0 will perform no CCA assessments, * and always transmit immediately. */ - uint8_t lbtTries; /**< Number of LBT failures before report CCA_FAIL */ + uint8_t lbtTries; /** * The CCA RSSI threshold, in dBm, above which the channel is * considered 'busy'. @@ -458,13 +618,15 @@ typedef struct RAIL_LbtConfig { /** * The backoff unit period, in RAIL's microsecond time base. This is * mulitiplied by the random backoff multiplier controlled by @ref - * csmaMinBoExp and @ref csmaMaxBoExp to determine the overall backoff - * period. For random backoffs, this value must be in the range from - * idleToRx time (set by RAIL_SetStateTimings) to 511 microseconds; for fixed - * backoffs it can go up to 65535 microseconds. + * lbtMinBoRand and @ref lbtMaxBoRand to determine the overall backoff + * period. For random backoffs, any value above 511 microseconds will + * be truncated; for fixed backoffs it can go up to 65535 microseconds. */ uint16_t lbtBackoff; - uint16_t lbtDuration; /**< LBT check duration, in microseconds */ + /** + * LBT check duration in microseconds. + */ + uint16_t lbtDuration; /** * An overall timeout, in RAIL's microsecond time base, for the * operation. If transmission doesn't start before this timeout expires, the @@ -508,6 +670,8 @@ typedef struct RAIL_LbtConfig { */ // Tx Config Callback Defines +/** Callback for a transmit buffer overflow event */ +#define RAIL_TX_CONFIG_BUFFER_OVERFLOW (0x01 << 0) /** Callback for a transmit buffer underflow event */ #define RAIL_TX_CONFIG_BUFFER_UNDERFLOW (0x01 << 1) /** Callback for CCA/CSMA/LBT failure */ @@ -516,6 +680,12 @@ typedef struct RAIL_LbtConfig { #define RAIL_TX_CONFIG_TX_ABORTED (0x01 << 3) /** Callback for when a Tx is blocked by something like PTA or RHO */ #define RAIL_TX_CONFIG_TX_BLOCKED (0x01 << 4) +/** Callback for CCA/CSMA/LBT success */ +#define RAIL_TX_CONFIG_CHANNEL_CLEAR (0x01 << 5) +/** Callback for when an CCA check is being retried */ +#define RAIL_TX_CONFIG_CCA_RETRY (0x01 << 6) +/** Callback for when a clear channel assessment (CCA) is begun */ +#define RAIL_TX_CONFIG_START_CCA (0x01 << 7) /** * @struct RAIL_TxData_t @@ -525,7 +695,7 @@ typedef struct RAIL_LbtConfig { */ typedef struct RAIL_TxData { uint8_t *dataPtr; /**< Pointer to data to transmit */ - uint16_t dataLength; /**< Number of bytes to transmit */ + uint16_t dataLength; /**< Number of bytes to load into transmit buffer */ } RAIL_TxData_t; /** @@ -534,7 +704,8 @@ typedef struct RAIL_TxData { */ typedef struct RAIL_TxPacketInfo { /** - * Time recorded when the last bit is transmitted out of the modulator. + * Timestamp of the transmitted packet in the RAIL timebase of microseconds. + * The time is the end of the last bit of the transmitted packet. */ uint32_t timeUs; } RAIL_TxPacketInfo_t; @@ -562,13 +733,21 @@ typedef struct RAIL_TxOptions { */ // Rx Config Callback Defines +/** Callback for when more is read from the Rx buffer than is available */ +#define RAIL_RX_CONFIG_BUFFER_UNDERFLOW (0x01 << 0) /** Callback for preamble detection */ #define RAIL_RX_CONFIG_PREAMBLE_DETECT (0x01 << 1) /** Callback for detection of the first sync word */ #define RAIL_RX_CONFIG_SYNC1_DETECT (0x01 << 2) /** Callback for detection of the second sync word */ #define RAIL_RX_CONFIG_SYNC2_DETECT (0x01 << 3) -/** Callback for detection of frame errors */ +/** Callback for detection of frame errors + * + * For efr32xg1x parts, frame errors include violations of variable length + * min/max limits, frame coding errors, and crc errors. If \ref + * RAIL_IGNORE_CRC_ERRORS are set, \ref RAIL_RX_CONFIG_FRAME_ERROR will not be + * asserted for crc errors. + */ #define RAIL_RX_CONFIG_FRAME_ERROR (0x01 << 4) /** Callback for when we run out of Rx buffer space */ #define RAIL_RX_CONFIG_BUFFER_OVERFLOW (0x01 << 5) @@ -580,16 +759,42 @@ typedef struct RAIL_TxOptions { #define RAIL_RX_CONFIG_TIMEOUT (0x01 << 8) /** Callback for when the scheduled Rx window ends */ #define RAIL_RX_CONFIG_SCHEDULED_RX_END (0x01 << 9) +/** Callback for an aborted packet. This is triggered when a more specific + * reason the packet was aborted, such as RAIL_RX_CONFIG_ADDRESS_FILTERED, is + * not known. */ +#define RAIL_RX_CONFIG_PACKET_ABORTED (0x01 << 10) +/** + * Callback for when the packet has passed any configured address and frame + * filtering options. + */ +#define RAIL_RX_CONFIG_FILTER_PASSED (0x01 << 11) /** To maintain backwards compatibility with RAIL 1.1, * RAIL_RX_CONFIG_INVALID_CRC is the same as RAIL_RX_CONFIG_FRAME_ERROR */ #define RAIL_RX_CONFIG_INVALID_CRC RAIL_RX_CONFIG_FRAME_ERROR +// Rx Option Defines +/** Option to configure whether the CRC portion of the packet is included in + * the dataPtr field of the RAIL_RxPacketInfo_t passed via + * RAILCb_RxPacketReceived(). Defaults to false. */ +#define RAIL_RX_OPTION_STORE_CRC (1 << 0) + // Rx Config Ignore Error Defines -/** Ignore no errors. Drop all packets with errors */ +/** + * Ignore no errors. + * + * Drop all packets with errors. With this setting, crc errors will generate a + * RAILCb_RxRadioStatus() with \ref RAIL_RX_CONFIG_FRAME_ERROR. + */ #define RAIL_IGNORE_NO_ERRORS (0x00) -/** Ignore CRC errors. Receive packets with CRC errors */ +/** + * Hardware ignores CRC errors. + * + * When this setting is enabled and a CRC error occurs, RAILCb_RxRadioStatus() + * with \ref RAIL_RX_CONFIG_FRAME_ERROR will not occur. Instead packets with crc + * errors will generate RAILCb_RxPacketReceived(). + */ #define RAIL_IGNORE_CRC_ERRORS (0x01 << 0) /** Ignore all possible errors. Receive all possible packets */ #define RAIL_IGNORE_ALL_ERRORS (0xFF) @@ -606,8 +811,8 @@ typedef struct RAIL_TxOptions { */ typedef struct RAIL_AppendedInfo { /** - * Timestamp of the received packet in the RAIL timebase of microseconds. - * This time is recorded at sync detect. + * Timestamp of the received packet in the RAIL timebase of microseconds. The + * time is the end of the sync word of the received packet. */ uint32_t timeUs; /** @@ -623,7 +828,8 @@ typedef struct RAIL_AppendedInfo { /** * Indicates if the received packet is an ack. An 'ack' is defined as a * packet received during the rx ack window when autoack is enabled. - * Set to 0 for not an ack, and 1 for is an ack. + * Set to 0 for not an ack, and 1 for is an ack. Will always be 0 if + * autoack is not enabled. */ bool isAck:1; /** @@ -632,8 +838,8 @@ typedef struct RAIL_AppendedInfo { */ int8_t rssiLatch; /** - * Link quality indicator of the received packet. This is not currently - * implemented. + * Link quality indicator of the received packet. This is calculated as the + * average correlation for the first 8 symbols in a frame. */ uint8_t lqi; /** @@ -645,26 +851,35 @@ typedef struct RAIL_AppendedInfo { /** * @struct RAIL_RxPacketInfo_t - * @brief Rx Packet Information structure passed into RAILCb_RxPacketReceived - * after a packet has been received. Contains a pointer to the data recieved, - * as well as other packet information. + * @brief Receive packet information structure + * + * The structure used to pass an over the air packet and some associated + * information up to the application code. The memory handle that you receive + * in the call to RAILCb_RxPacketReceived() will contain this data structure. */ typedef struct RAIL_RxPacketInfo { - RAIL_AppendedInfo_t appendedInfo; /**< A structure containing various extra information about the received packet. */ - uint16_t dataLength; /**< The number of bytes in the dataPtr array. */ - uint8_t dataPtr[]; /**< A variable length array holding the packet contents. */ + /** + * A structure containing the extra information associated with this received + * packet. + */ + RAIL_AppendedInfo_t appendedInfo; + /** + * The number of bytes that are in the dataPtr array. + */ + uint16_t dataLength; + /** + * A variable length array holding the receive packet data bytes. + */ + uint8_t dataPtr[]; } RAIL_RxPacketInfo_t; /** * @struct RAIL_ScheduleRxConfig_t - * @brief This structure is used to configure the Scheduled Rx algorithm. It - * allows you to define the start and end times of the window in either absolute - * or relative times. If start is set to \ref RAIL_TIME_DISABLED it will be - * assumed that we should start receive now. If end is set to \ref - * RAIL_TIME_DISABLED then the only way to end this scheduled receive is with an - * explicit call to RAIL_RfIdle(). If end is relative it is relative to the - * start time not the current time. All times are assumed to be specified in the - * RAIL timebase. + * @brief This structure is used to configure the Scheduled Rx algorithm. + * + * It allows you to define the start and end times of the receive window created + * for scheduled receive. If either start or end times are disabled then they + * will be ignored. */ typedef struct RAIL_ScheduleRxConfig { /** @@ -672,15 +887,12 @@ typedef struct RAIL_ScheduleRxConfig { * types of start times that you can specify. */ uint32_t start; - /** - * The type of time value specified in the start parameter. If this is - * \ref RAIL_TIME_ABSOLUTE then it's an exact time, if it's \ref - * RAIL_TIME_DELAY then it's an offset relative to the current time. If you - * specify \ref RAIL_TIME_DISABLED for this then the start event will be - * ignored. + * How to interpret the time value specified in the start parameter. See the + * \ref RAIL_TimeMode_t documentation for more information. Use + * \ref RAIL_TIME_ABSOLUTE for absolute times, \ref RAIL_TIME_DELAY for times + * relative to now, and \ref RAIL_TIME_DISABLED to ignore the start time. */ - RAIL_TimeMode_t startMode; /** * The time to end receive. See endMode for more information about the types @@ -688,11 +900,13 @@ typedef struct RAIL_ScheduleRxConfig { */ uint32_t end; /** - * The type of time value specified in the end parameter. If this is - * \ref RAIL_TIME_ABSOLUTE then it's an exact time, if it's \ref RAIL_TIME_DELAY then - * it's an offset relative to the start time as long as the startMode isn't - * \ref RAIL_TIME_DISABLED and if it's \ref RAIL_TIME_DISABLED we will not configure the - * end event so that this can run indefinitely. + * How to interpret the time value specified in the end parameter. See the + * \ref RAIL_TimeMode_t documentation for more information. Note that in this + * API if you specify a \ref RAIL_TIME_DELAY it will be relative to the start + * time if given and relative to now if none is specified. Also, using \ref + * RAIL_TIME_DISABLED means that this window will not end unless you + * explicitly call RAIL_RfIdle() or add an end event through a future update + * to this configuration. */ RAIL_TimeMode_t endMode; /** From 8b6451c74d7adde5ed2a11a259f8bb57d438a3fa Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Tue, 14 Mar 2017 14:16:52 +0100 Subject: [PATCH 05/10] Add new target EFM32PG12 --- ...artup_efr32mg1p.s => startup_efr32mg12p.s} | 171 +- .../TARGET_EFR32PG12/PeripheralNames.h | 69 + .../TARGET_EFR32PG12/PeripheralPins.c | 427 +++ .../TARGET_EFR32PG12/PeripheralPins.h | 53 + .../TARGET_EFM32PG12_STK3402/PinNames.h | 81 + .../device_peripherals.h | 57 + .../device/TOOLCHAIN_ARM_STD/efr32pg12b.sct | 15 + .../TOOLCHAIN_ARM_STD/startup_efm32pg12b.s | 306 +++ .../device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld | 215 ++ .../TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S | 350 +++ .../TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf | 42 + .../device/TOOLCHAIN_IAR/startup_efm32pg12b.s | 401 +++ .../device/efm32pg12b500f1024gl125.h | 2053 ++++++++++++++ .../device/efm32pg12b500f1024gm48.h | 2053 ++++++++++++++ .../device/efm32pg12b500f1024il125.h | 2053 ++++++++++++++ .../device/efm32pg12b500f1024im48.h | 2053 ++++++++++++++ .../device/efm32pg12b500f512gl125.h | 2053 ++++++++++++++ .../device/efm32pg12b500f512gm48.h | 2053 ++++++++++++++ .../TARGET_EFR32PG12/device/efm32pg12b_acmp.h | 1420 ++++++++++ .../TARGET_EFR32PG12/device/efm32pg12b_adc.h | 2371 +++++++++++++++++ .../device/efm32pg12b_af_pins.h | 166 ++ .../device/efm32pg12b_af_ports.h | 166 ++ .../TARGET_EFR32PG12/device/efm32pg12b_cmu.h | 2032 ++++++++++++++ .../device/efm32pg12b_cryotimer.h | 167 ++ .../device/efm32pg12b_crypto.h | 1216 +++++++++ .../TARGET_EFR32PG12/device/efm32pg12b_csen.h | 1003 +++++++ .../device/efm32pg12b_devinfo.h | 1274 +++++++++ .../device/efm32pg12b_dma_descriptor.h | 52 + .../device/efm32pg12b_dmareq.h | 110 + .../TARGET_EFR32PG12/device/efm32pg12b_emu.h | 1437 ++++++++++ .../TARGET_EFR32PG12/device/efm32pg12b_etm.h | 781 ++++++ .../device/efm32pg12b_fpueh.h | 192 ++ .../device/efm32pg12b_gpcrc.h | 185 ++ .../TARGET_EFR32PG12/device/efm32pg12b_gpio.h | 1538 +++++++++++ .../device/efm32pg12b_gpio_p.h | 56 + .../TARGET_EFR32PG12/device/efm32pg12b_i2c.h | 921 +++++++ .../TARGET_EFR32PG12/device/efm32pg12b_idac.h | 352 +++ .../TARGET_EFR32PG12/device/efm32pg12b_ldma.h | 643 +++++ .../device/efm32pg12b_ldma_ch.h | 53 + .../device/efm32pg12b_lesense.h | 1867 +++++++++++++ .../device/efm32pg12b_lesense_buf.h | 46 + .../device/efm32pg12b_lesense_ch.h | 49 + .../device/efm32pg12b_lesense_st.h | 47 + .../device/efm32pg12b_letimer.h | 620 +++++ .../device/efm32pg12b_leuart.h | 835 ++++++ .../TARGET_EFR32PG12/device/efm32pg12b_msc.h | 664 +++++ .../TARGET_EFR32PG12/device/efm32pg12b_pcnt.h | 706 +++++ .../TARGET_EFR32PG12/device/efm32pg12b_prs.h | 1089 ++++++++ .../device/efm32pg12b_prs_ch.h | 46 + .../device/efm32pg12b_prs_signals.h | 166 ++ .../TARGET_EFR32PG12/device/efm32pg12b_rmu.h | 191 ++ .../device/efm32pg12b_romtable.h | 72 + .../TARGET_EFR32PG12/device/efm32pg12b_rtcc.h | 695 +++++ .../device/efm32pg12b_rtcc_cc.h | 49 + .../device/efm32pg12b_rtcc_ret.h | 46 + .../TARGET_EFR32PG12/device/efm32pg12b_smu.h | 400 +++ .../device/efm32pg12b_timer.h | 1575 +++++++++++ .../device/efm32pg12b_timer_cc.h | 49 + .../TARGET_EFR32PG12/device/efm32pg12b_trng.h | 279 ++ .../device/efm32pg12b_usart.h | 1972 ++++++++++++++ .../TARGET_EFR32PG12/device/efm32pg12b_vdac.h | 1539 +++++++++++ .../device/efm32pg12b_vdac_opa.h | 53 + .../TARGET_EFR32PG12/device/efm32pg12b_wdog.h | 335 +++ .../device/efm32pg12b_wdog_pch.h | 46 + .../TARGET_EFR32PG12/device/em_device.h | 68 + .../device/system_efm32pg12b.c | 384 +++ .../device/system_efm32pg12b.h | 129 + .../TARGET_EFM32/common/mbed_overrides.c | 5 +- targets/TARGET_Silicon_Labs/mbed_rtx.h | 2 +- targets/targets.json | 52 + 70 files changed, 44677 insertions(+), 39 deletions(-) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/{startup_efr32mg1p.s => startup_efr32mg12p.s} (63%) create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralNames.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.c create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/PinNames.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gl125.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gm48.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024il125.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024im48.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gl125.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gm48.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_acmp.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_adc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_pins.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_ports.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cmu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cryotimer.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_crypto.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_csen.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_devinfo.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dma_descriptor.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dmareq.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_emu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_etm.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_fpueh.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpcrc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio_p.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_i2c.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_idac.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma_ch.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_buf.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_ch.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_st.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_letimer.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_leuart.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_msc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_pcnt.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_ch.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_signals.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rmu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_romtable.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_cc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_ret.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_smu.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer_cc.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_trng.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_usart.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac_opa.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog_pch.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/em_device.h create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.c create mode 100644 targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg1p.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s similarity index 63% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg1p.s rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s index aca5a91969..2cb725593b 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg1p.s +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s @@ -1,8 +1,8 @@ ;/**************************************************************************//** -; * @file startup_efr32mg1p.s +; * @file startup_efr32mg12p.s ; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFR32MG1P Device Series -; * @version 5.0.0 +; * Silicon Labs EFR32MG12P Device Series +; * @version 5.1.2 ; * @date 30. January 2012 ; * ; * @note @@ -82,37 +82,54 @@ __vector_table_0x1c DCD EMU_IRQHandler ; 0: EMU Interrupt DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD FRC_IRQHandler ; 3: FRC Interrupt - DCD MODEM_IRQHandler ; 4: MODEM Interrupt - DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt - DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt - DCD BUFC_IRQHandler ; 7: BUFC Interrupt - DCD LDMA_IRQHandler ; 8: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 14: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 16: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt - DCD CMU_IRQHandler ; 23: CMU Interrupt - DCD MSC_IRQHandler ; 24: MSC Interrupt - DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt - DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt - DCD AGC_IRQHandler ; 27: AGC Interrupt - DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt - DCD RTCC_IRQHandler ; 29: RTCC Interrupt - DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt - DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt - DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt - DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD FRC_IRQHandler ; 4: FRC Interrupt + DCD MODEM_IRQHandler ; 5: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 8: BUFC Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 28: AGC Interrupt + DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved Interrupt __Vectors_End __Vectors EQU __vector_table @@ -195,6 +212,11 @@ FRC_PRI_IRQHandler WDOG0_IRQHandler B WDOG0_IRQHandler + PUBWEAK WDOG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG1_IRQHandler + B WDOG1_IRQHandler + PUBWEAK FRC_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) FRC_IRQHandler @@ -305,10 +327,10 @@ CMU_IRQHandler MSC_IRQHandler B MSC_IRQHandler - PUBWEAK CRYPTO_IRQHandler + PUBWEAK CRYPTO0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO_IRQHandler - B CRYPTO_IRQHandler +CRYPTO0_IRQHandler + B CRYPTO0_IRQHandler PUBWEAK LETIMER0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) @@ -350,5 +372,80 @@ RFSENSE_IRQHandler FPUEH_IRQHandler B FPUEH_IRQHandler + PUBWEAK SMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SMU_IRQHandler + B SMU_IRQHandler + + PUBWEAK WTIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER0_IRQHandler + B WTIMER0_IRQHandler + + PUBWEAK WTIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER1_IRQHandler + B WTIMER1_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK USART3_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_RX_IRQHandler + B USART3_RX_IRQHandler + + PUBWEAK USART3_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_TX_IRQHandler + B USART3_TX_IRQHandler + + PUBWEAK VDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VDAC0_IRQHandler + B VDAC0_IRQHandler + + PUBWEAK CSEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CSEN_IRQHandler + B CSEN_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK CRYPTO1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO1_IRQHandler + B CRYPTO1_IRQHandler + + PUBWEAK TRNG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG0_IRQHandler + B TRNG0_IRQHandler + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralNames.h new file mode 100644 index 0000000000..2e5170aef5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralNames.h @@ -0,0 +1,69 @@ +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "em_adc.h" +#include "em_usart.h" +#include "em_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_0 = ADC0_BASE +} ADCName; + +typedef enum { + I2C_0 = I2C0_BASE, + I2C_1 = I2C1_BASE, +} I2CName; + +typedef enum { + PWM_CH0 = 0, + PWM_CH1 = 1, + PWM_CH2 = 2, + PWM_CH3 = 3 +} PWMName; + +typedef enum { + USART_0 = USART0_BASE, + USART_1 = USART1_BASE, + USART_2 = USART2_BASE, + USART_3 = USART3_BASE, + LEUART_0 = LEUART0_BASE, +} UARTName; + +typedef enum { + SPI_0 = USART0_BASE, + SPI_1 = USART1_BASE, + SPI_2 = USART2_BASE, + SPI_3 = USART3_BASE, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.c new file mode 100644 index 0000000000..95baad0840 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.c @@ -0,0 +1,427 @@ +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "PeripheralPins.h" + +/************ADC***************/ +/* The third "function" value is used to select the correct ADC channel */ +const PinMap PinMap_ADC[] = { + {PA0, ADC_0, adcPosSelAPORT3XCH8}, + {PA1, ADC_0, adcPosSelAPORT4XCH9}, + {PA2, ADC_0, adcPosSelAPORT3XCH10}, + {PA3, ADC_0, adcPosSelAPORT4XCH11}, + {PA4, ADC_0, adcPosSelAPORT3XCH12}, + {PA5, ADC_0, adcPosSelAPORT4XCH13}, + + {PB11, ADC_0, adcPosSelAPORT4XCH27}, + {PB12, ADC_0, adcPosSelAPORT3XCH28}, + {PB14, ADC_0, adcPosSelAPORT3XCH30}, + {PB15, ADC_0, adcPosSelAPORT4XCH31}, + + {PC6, ADC_0, adcPosSelAPORT1XCH6}, + {PC7, ADC_0, adcPosSelAPORT2XCH7}, + {PC8, ADC_0, adcPosSelAPORT1XCH8}, + {PC9, ADC_0, adcPosSelAPORT2XCH9}, + {PC10, ADC_0, adcPosSelAPORT1XCH10}, + {PC11, ADC_0, adcPosSelAPORT2XCH11}, + + {PD9, ADC_0, adcPosSelAPORT4XCH1}, + {PD10, ADC_0, adcPosSelAPORT3XCH2}, + {PD11, ADC_0, adcPosSelAPORT3YCH3}, + {PD12, ADC_0, adcPosSelAPORT3XCH4}, + {PD13, ADC_0, adcPosSelAPORT3YCH5}, + {PD14, ADC_0, adcPosSelAPORT3XCH6}, + {PD15, ADC_0, adcPosSelAPORT4XCH7}, + + {PF0, ADC_0, adcPosSelAPORT1XCH16}, + {PF1, ADC_0, adcPosSelAPORT2XCH17}, + {PF2, ADC_0, adcPosSelAPORT1XCH18}, + {PF3, ADC_0, adcPosSelAPORT2XCH19}, + {PF4, ADC_0, adcPosSelAPORT1XCH20}, + {PF5, ADC_0, adcPosSelAPORT2XCH21}, + {PF6, ADC_0, adcPosSelAPORT1XCH22}, + {PF7, ADC_0, adcPosSelAPORT2XCH23}, + {NC , NC , NC} +}; + +/************I2C SCL***********/ +const PinMap PinMap_I2C_SCL[] = { + /* I2C0 */ + {PA1, I2C_0, 0}, + {PA2, I2C_0, 1}, + {PA3, I2C_0, 2}, + {PA4, I2C_0, 3}, + {PA5, I2C_0, 4}, + {PB11, I2C_0, 5}, + {PB12, I2C_0, 6}, + {PB13, I2C_0, 7}, + {PB14, I2C_0, 8}, + {PB15, I2C_0, 9}, + {PC6, I2C_0, 10}, + {PC7, I2C_0, 11}, + {PC8, I2C_0, 12}, + {PC9, I2C_0, 13}, + {PC10, I2C_0, 14}, + {PC11, I2C_0, 15}, + {PD9, I2C_0, 16}, + {PD10, I2C_0, 17}, + {PD11, I2C_0, 18}, + {PD12, I2C_0, 19}, + {PD13, I2C_0, 20}, + {PD14, I2C_0, 21}, + {PD15, I2C_0, 22}, + {PF0, I2C_0, 23}, + {PF1, I2C_0, 24}, + {PF2, I2C_0, 25}, + {PF3, I2C_0, 26}, + {PF4, I2C_0, 27}, + {PF5, I2C_0, 28}, + {PF6, I2C_0, 29}, + {PF7, I2C_0, 30}, + {PA0, I2C_0, 31}, + + {NC , NC , NC} +}; + +/************I2C SDA***********/ +const PinMap PinMap_I2C_SDA[] = { + /* I2C0 */ + {PA0, I2C_0, 0}, + {PA1, I2C_0, 1}, + {PA2, I2C_0, 2}, + {PA3, I2C_0, 3}, + {PA4, I2C_0, 4}, + {PA5, I2C_0, 5}, + {PB11, I2C_0, 6}, + {PB12, I2C_0, 7}, + {PB13, I2C_0, 8}, + {PB14, I2C_0, 9}, + {PB15, I2C_0, 10}, + {PC6, I2C_0, 11}, + {PC7, I2C_0, 12}, + {PC8, I2C_0, 13}, + {PC9, I2C_0, 14}, + {PC10, I2C_0, 15}, + {PC11, I2C_0, 16}, + {PD9, I2C_0, 17}, + {PD10, I2C_0, 18}, + {PD11, I2C_0, 19}, + {PD12, I2C_0, 20}, + {PD13, I2C_0, 21}, + {PD14, I2C_0, 22}, + {PD15, I2C_0, 23}, + {PF0, I2C_0, 24}, + {PF1, I2C_0, 25}, + {PF2, I2C_0, 26}, + {PF3, I2C_0, 27}, + {PF4, I2C_0, 28}, + {PF5, I2C_0, 29}, + {PF6, I2C_0, 30}, + {PF7, I2C_0, 31}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PA0, PWM_CH0, 0}, + {PA1, PWM_CH1, 0}, + {PA2, PWM_CH2, 0}, + {PA3, PWM_CH3, 0}, + {PA4, PWM_CH2, 2}, + {PA5, PWM_CH3, 2}, + {PB11, PWM_CH1, 5}, + {PB12, PWM_CH2, 5}, + {PB13, PWM_CH3, 5}, + {PB14, PWM_CH0, 9}, + {PB15, PWM_CH0, 10}, + {PC6, PWM_CH0, 11}, + {PC7, PWM_CH1, 11}, + {PC8, PWM_CH2, 11}, + {PC9, PWM_CH3, 11}, + {PC10, PWM_CH2, 13}, + {PC11, PWM_CH3, 13}, + {PD9, PWM_CH3, 14}, + {PD10, PWM_CH0, 18}, + {PD11, PWM_CH1, 18}, + {PD12, PWM_CH2, 18}, + {PD13, PWM_CH3, 18}, + {PD14, PWM_CH0, 22}, + {PD15, PWM_CH1, 22}, + {PF0, PWM_CH0, 24}, + {PF1, PWM_CH1, 24}, + {PF2, PWM_CH2, 24}, + {PF3, PWM_CH3, 24}, + {PF4, PWM_CH0, 28}, + {PF5, PWM_CH1, 28}, + {PF6, PWM_CH2, 28}, + {PF7, PWM_CH3, 28}, + + {NC , NC , NC} +}; + +/*************SPI**************/ +const PinMap PinMap_SPI_MOSI[] = { + + /* USART0 */ + {PA0, SPI_0, 0}, + {PA1, SPI_0, 1}, + {PA2, SPI_0, 2}, + {PA3, SPI_0, 3}, + {PA4, SPI_0, 4}, + {PA5, SPI_0, 5}, + {PB11, SPI_0, 6}, + {PB12, SPI_0, 7}, + {PB13, SPI_0, 8}, + {PB14, SPI_0, 9}, + {PB15, SPI_0, 10}, + {PD9, SPI_0, 17}, + {PD10, SPI_0, 18}, + {PD11, SPI_0, 19}, + {PD12, SPI_0, 20}, + {PD13, SPI_0, 21}, + {PD14, SPI_0, 22}, + {PD15, SPI_0, 23}, + + /* USART1 */ + {PC6, SPI_1, 11}, + {PC7, SPI_1, 12}, + {PC8, SPI_1, 13}, + {PC9, SPI_1, 14}, + {PC10, SPI_1, 15}, + {PC11, SPI_1, 16}, + {PF0, SPI_1, 24}, + {PF1, SPI_1, 25}, + {PF2, SPI_1, 26}, + {PF3, SPI_1, 27}, + {PF4, SPI_1, 28}, + {PF5, SPI_1, 29}, + {PF6, SPI_1, 30}, + {PF7, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_MISO[] = { + + /* USART0 */ + {PA0, SPI_0, 31}, + {PA1, SPI_0, 0}, + {PA2, SPI_0, 1}, + {PA3, SPI_0, 2}, + {PA4, SPI_0, 3}, + {PA5, SPI_0, 4}, + {PB11, SPI_0, 5}, + {PB12, SPI_0, 6}, + {PB13, SPI_0, 7}, + {PB14, SPI_0, 8}, + {PB15, SPI_0, 9}, + {PD9, SPI_0, 16}, + {PD10, SPI_0, 17}, + {PD11, SPI_0, 18}, + {PD12, SPI_0, 19}, + {PD13, SPI_0, 20}, + {PD14, SPI_0, 21}, + {PD15, SPI_0, 22}, + + /* USART1 */ + {PC6, SPI_1, 10}, + {PC7, SPI_1, 11}, + {PC8, SPI_1, 12}, + {PC9, SPI_1, 13}, + {PC10, SPI_1, 14}, + {PC11, SPI_1, 15}, + {PF0, SPI_1, 23}, + {PF1, SPI_1, 24}, + {PF2, SPI_1, 25}, + {PF3, SPI_1, 26}, + {PF4, SPI_1, 27}, + {PF5, SPI_1, 28}, + {PF6, SPI_1, 29}, + {PF7, SPI_1, 30}, + {PA0, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_CLK[] = { + + /* USART0 */ + {PA0, SPI_0, 30}, + {PA1, SPI_0, 31}, + {PA2, SPI_0, 0}, + {PA3, SPI_0, 1}, + {PA4, SPI_0, 2}, + {PA5, SPI_0, 3}, + {PB11, SPI_0, 4}, + {PB12, SPI_0, 5}, + {PB13, SPI_0, 6}, + {PB14, SPI_0, 7}, + {PB15, SPI_0, 8}, + {PD9, SPI_0, 15}, + {PD10, SPI_0, 16}, + {PD11, SPI_0, 17}, + {PD12, SPI_0, 18}, + {PD13, SPI_0, 19}, + {PD14, SPI_0, 20}, + {PD15, SPI_0, 21}, + + /* USART1 */ + {PC6, SPI_1, 9}, + {PC7, SPI_1, 10}, + {PC8, SPI_1, 11}, + {PC9, SPI_1, 12}, + {PC10, SPI_1, 13}, + {PC11, SPI_1, 14}, + {PF0, SPI_1, 22}, + {PF1, SPI_1, 23}, + {PF2, SPI_1, 24}, + {PF3, SPI_1, 25}, + {PF4, SPI_1, 26}, + {PF5, SPI_1, 27}, + {PF6, SPI_1, 28}, + {PF7, SPI_1, 29}, + {PA0, SPI_1, 30}, + {PA1, SPI_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_SPI_CS[] = { + + /* USART0 */ + {PA0, SPI_0, 29}, + {PA1, SPI_0, 30}, + {PA2, SPI_0, 31}, + {PA3, SPI_0, 0}, + {PA4, SPI_0, 1}, + {PA5, SPI_0, 2}, + {PB11, SPI_0, 3}, + {PB12, SPI_0, 4}, + {PB13, SPI_0, 5}, + {PB14, SPI_0, 6}, + {PB15, SPI_0, 7}, + {PD9, SPI_0, 14}, + {PD10, SPI_0, 15}, + {PD11, SPI_0, 16}, + {PD12, SPI_0, 17}, + {PD13, SPI_0, 18}, + {PD14, SPI_0, 19}, + {PD15, SPI_0, 20}, + + /* USART1 */ + {PC6, SPI_1, 8}, + {PC7, SPI_1, 9}, + {PC8, SPI_1, 10}, + {PC9, SPI_1, 11}, + {PC10, SPI_1, 12}, + {PC11, SPI_1, 13}, + {PF0, SPI_1, 21}, + {PF1, SPI_1, 22}, + {PF2, SPI_1, 23}, + {PF3, SPI_1, 24}, + {PF4, SPI_1, 25}, + {PF5, SPI_1, 26}, + {PF6, SPI_1, 27}, + {PF7, SPI_1, 28}, + + {NC , NC , NC} +}; + +/************UART**************/ +const PinMap PinMap_UART_TX[] = { + {PA0, USART_0, 0}, + {PA1, USART_0, 1}, + {PA2, USART_0, 2}, + {PA3, USART_0, 3}, + {PA4, USART_0, 4}, + {PA5, USART_0, 5}, + {PB11, USART_0, 6}, + {PB12, USART_0, 7}, + {PB13, USART_0, 8}, + {PB14, USART_0, 9}, + {PB15, USART_0, 10}, + {PD9, LEUART_0, 17}, + {PD10, LEUART_0, 18}, + {PD11, LEUART_0, 19}, + {PD12, LEUART_0, 20}, + {PD13, LEUART_0, 21}, + {PD14, LEUART_0, 22}, + {PD15, LEUART_0, 23}, + + {PC6, USART_1, 11}, + {PC7, USART_1, 12}, + {PC8, USART_1, 13}, + {PC9, USART_1, 14}, + {PC10, USART_1, 15}, + {PC11, USART_1, 16}, + {PF0, USART_1, 24}, + {PF1, USART_1, 25}, + {PF2, USART_1, 26}, + {PF3, USART_1, 27}, + {PF4, USART_1, 28}, + {PF5, USART_1, 29}, + {PF6, USART_1, 30}, + {PF7, USART_1, 31}, + + {NC , NC , NC} +}; + +const PinMap PinMap_UART_RX[] = { + {PA0, USART_0, 31}, + {PA1, USART_0, 0}, + {PA2, USART_0, 1}, + {PA3, USART_0, 2}, + {PA4, USART_0, 3}, + {PA5, USART_0, 4}, + {PB11, USART_0, 5}, + {PB12, USART_0, 6}, + {PB13, USART_0, 7}, + {PB14, USART_0, 8}, + {PB15, USART_0, 9}, + {PD9, LEUART_0, 16}, + {PD10, LEUART_0, 17}, + {PD11, LEUART_0, 18}, + {PD12, LEUART_0, 19}, + {PD13, LEUART_0, 20}, + {PD14, LEUART_0, 21}, + {PD15, LEUART_0, 22}, + + {PC6, USART_1, 10}, + {PC7, USART_1, 11}, + {PC8, USART_1, 12}, + {PC9, USART_1, 13}, + {PC10, USART_1, 14}, + {PC11, USART_1, 15}, + {PF0, USART_1, 23}, + {PF1, USART_1, 24}, + {PF2, USART_1, 25}, + {PF3, USART_1, 26}, + {PF4, USART_1, 27}, + {PF5, USART_1, 28}, + {PF6, USART_1, 29}, + {PF7, USART_1, 30}, + + {NC , NC , NC} +}; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.h new file mode 100644 index 0000000000..79d6072e83 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.h @@ -0,0 +1,53 @@ +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************I2C SCL***********/ +extern const PinMap PinMap_I2C_SCL[]; + +/************I2C SDA***********/ +extern const PinMap PinMap_I2C_SDA[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_CLK[]; +extern const PinMap PinMap_SPI_CS[]; + +/************UART**************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +#endif + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/PinNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/PinNames.h new file mode 100644 index 0000000000..8840ceb9db --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/PinNames.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "CommonPinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + EFM32_STANDARD_PIN_DEFINITIONS, + + /* Starter Kit says LED0 and LED1, but mbed expects 1 and 2. This way using 1 and 2 or 0 and 1 will work. */ + LED0 = PF4, + LED1 = PF5, + LED2 = LED0, + LED3 = LED0, + LED4 = LED1, + + /* Push Buttons */ + SW0 = PF6, + SW1 = PF7, + BTN0 = SW0, + BTN1 = SW1, + + /* Expansion headers */ + EXP3 = PA8, + EXP4 = PC6, + EXP5 = PA9, + EXP6 = PC7, + EXP7 = PF3, + EXP8 = PC8, + EXP9 = PF4, + EXP10 = PC9, + EXP11 = PF5, + EXP12 = PA6, + EXP13 = PF6, + EXP14 = PA7, + EXP15 = PC11, + EXP16 = PC10, + + /* Serial (just some usable pins) */ + SERIAL_TX = PA6, + SERIAL_RX = PA7, + + /* Board Controller UART (USB)*/ + USBTX = PA0, + USBRX = PA1, + + /* Board Controller */ + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h new file mode 100644 index 0000000000..d9cd0fef8a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h @@ -0,0 +1,57 @@ +/***************************************************************************//** + * @file device_peripherals.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#ifndef MBED_DEVICE_PERIPHERALS_H +#define MBED_DEVICE_PERIPHERALS_H + +/* us ticker */ +#define US_TICKER_TIMER TIMER0 +#define US_TICKER_TIMER_CLOCK cmuClock_TIMER0 +#define US_TICKER_TIMER_IRQ TIMER0_IRQn + +/* PWM */ +#define PWM_TIMER TIMER1 +#define PWM_TIMER_CLOCK cmuClock_TIMER1 +#define PWM_ROUTE TIMER_ROUTE_LOCATION_LOC1 + +/* Crystal calibration */ +#if !defined(CMU_HFXOINIT_STK_DEFAULT) +#define CMU_HFXOINIT_STK_DEFAULT \ +{ \ + true, /* Low-power mode for EFM32 */ \ + false, /* Disable auto-start on EM0/1 entry */ \ + false, /* Disable auto-select on EM0/1 entry */ \ + false, /* Disable auto-start and select on RAC wakeup */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + 0x142, /* Steady-state CTUNE for STK boards without load caps */ \ + _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ + 0x20, /* Matching errata fix in CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ +} +#endif +#endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct new file mode 100644 index 0000000000..974cbb0c37 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000108 0x0003FEF8 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s new file mode 100644 index 0000000000..5405f7cc8e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s @@ -0,0 +1,306 @@ +;/**************************************************************************//** +; * @file startup_efm32pg12b.s +; * @brief CMSIS Core Device Startup File for +; * Silicon Labs EFM32PG12B Device Series +; * @version 5.1.2 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00004000 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY, ALIGN=8 + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD 0 ; 1: Reserved + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD 0 ; 4: Reserved + DCD 0 ; 5: Reserved + DCD 0 ; 6: Reserved + DCD 0 ; 7: Reserved + DCD 0 ; 8: Reserved + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD 0 ; 28: Reserved + DCD 0 ; 29: Reserved + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD 0 ; 31: Reserved + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD 0 ; 33: Reserved + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved + +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT EMU_IRQHandler [WEAK] + EXPORT WDOG0_IRQHandler [WEAK] + EXPORT WDOG1_IRQHandler [WEAK] + EXPORT LDMA_IRQHandler [WEAK] + EXPORT GPIO_EVEN_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT USART0_RX_IRQHandler [WEAK] + EXPORT USART0_TX_IRQHandler [WEAK] + EXPORT ACMP0_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT IDAC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT GPIO_ODD_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT USART1_RX_IRQHandler [WEAK] + EXPORT USART1_TX_IRQHandler [WEAK] + EXPORT LEUART0_IRQHandler [WEAK] + EXPORT PCNT0_IRQHandler [WEAK] + EXPORT CMU_IRQHandler [WEAK] + EXPORT MSC_IRQHandler [WEAK] + EXPORT CRYPTO0_IRQHandler [WEAK] + EXPORT LETIMER0_IRQHandler [WEAK] + EXPORT RTCC_IRQHandler [WEAK] + EXPORT CRYOTIMER_IRQHandler [WEAK] + EXPORT FPUEH_IRQHandler [WEAK] + EXPORT SMU_IRQHandler [WEAK] + EXPORT WTIMER0_IRQHandler [WEAK] + EXPORT WTIMER1_IRQHandler [WEAK] + EXPORT PCNT1_IRQHandler [WEAK] + EXPORT PCNT2_IRQHandler [WEAK] + EXPORT USART2_RX_IRQHandler [WEAK] + EXPORT USART2_TX_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT USART3_RX_IRQHandler [WEAK] + EXPORT USART3_TX_IRQHandler [WEAK] + EXPORT VDAC0_IRQHandler [WEAK] + EXPORT CSEN_IRQHandler [WEAK] + EXPORT LESENSE_IRQHandler [WEAK] + EXPORT CRYPTO1_IRQHandler [WEAK] + EXPORT TRNG0_IRQHandler [WEAK] + + +EMU_IRQHandler +WDOG0_IRQHandler +WDOG1_IRQHandler +LDMA_IRQHandler +GPIO_EVEN_IRQHandler +TIMER0_IRQHandler +USART0_RX_IRQHandler +USART0_TX_IRQHandler +ACMP0_IRQHandler +ADC0_IRQHandler +IDAC0_IRQHandler +I2C0_IRQHandler +GPIO_ODD_IRQHandler +TIMER1_IRQHandler +USART1_RX_IRQHandler +USART1_TX_IRQHandler +LEUART0_IRQHandler +PCNT0_IRQHandler +CMU_IRQHandler +MSC_IRQHandler +CRYPTO0_IRQHandler +LETIMER0_IRQHandler +RTCC_IRQHandler +CRYOTIMER_IRQHandler +FPUEH_IRQHandler +SMU_IRQHandler +WTIMER0_IRQHandler +WTIMER1_IRQHandler +PCNT1_IRQHandler +PCNT2_IRQHandler +USART2_RX_IRQHandler +USART2_TX_IRQHandler +I2C1_IRQHandler +USART3_RX_IRQHandler +USART3_TX_IRQHandler +VDAC0_IRQHandler +CSEN_IRQHandler +LESENSE_IRQHandler +CRYPTO1_IRQHandler +TRNG0_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld new file mode 100644 index 0000000000..492a76f10f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld @@ -0,0 +1,215 @@ +/* Linker script for Silicon Labs EFM32PG12B devices */ +/* */ +/* This file is subject to the license terms as defined in ARM's */ +/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of */ +/* Example Code. */ +/* */ +/* Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com */ +/* */ +/* Version 5.1.2 */ +/* */ + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 1048576 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 262144 +} + +/* MBED: mbed needs to be able to dynamically set the interrupt vector table. + * We make room for the table at the very beginning of RAM, i.e. at + * 0x20000000. We need (16+50 * sizeof(uint32_t) = 264 bytes for EFM32PG */ +__vector_size = 0x108; + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + PROVIDE( __start_vector_table__ = .); + . += __vector_size; + PROVIDE( __end_vector_table__ = .); + *(vtable) + *(.data*) + . = ALIGN (4); + *(.ram) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if FLASH usage exceeds FLASH size */ + ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !") +} diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S new file mode 100644 index 0000000000..0f5b748e1d --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S @@ -0,0 +1,350 @@ +/* @file startup_efm32pg12b.S + * @brief startup file for Silicon Labs EFM32PG12B devices. + * For use with GCC for ARM Embedded Processors + * @version 5.1.2 + * Date: 12 June 2014 + * + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + .syntax unified + .arch armv7-m + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00004000 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long Default_Handler /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long Default_Handler /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long EMU_IRQHandler /* 0 - EMU */ + .long Default_Handler /* 1 - Reserved */ + .long WDOG0_IRQHandler /* 2 - WDOG0 */ + .long WDOG1_IRQHandler /* 3 - WDOG1 */ + .long Default_Handler /* 4 - Reserved */ + .long Default_Handler /* 5 - Reserved */ + .long Default_Handler /* 6 - Reserved */ + .long Default_Handler /* 7 - Reserved */ + .long Default_Handler /* 8 - Reserved */ + .long LDMA_IRQHandler /* 9 - LDMA */ + .long GPIO_EVEN_IRQHandler /* 10 - GPIO_EVEN */ + .long TIMER0_IRQHandler /* 11 - TIMER0 */ + .long USART0_RX_IRQHandler /* 12 - USART0_RX */ + .long USART0_TX_IRQHandler /* 13 - USART0_TX */ + .long ACMP0_IRQHandler /* 14 - ACMP0 */ + .long ADC0_IRQHandler /* 15 - ADC0 */ + .long IDAC0_IRQHandler /* 16 - IDAC0 */ + .long I2C0_IRQHandler /* 17 - I2C0 */ + .long GPIO_ODD_IRQHandler /* 18 - GPIO_ODD */ + .long TIMER1_IRQHandler /* 19 - TIMER1 */ + .long USART1_RX_IRQHandler /* 20 - USART1_RX */ + .long USART1_TX_IRQHandler /* 21 - USART1_TX */ + .long LEUART0_IRQHandler /* 22 - LEUART0 */ + .long PCNT0_IRQHandler /* 23 - PCNT0 */ + .long CMU_IRQHandler /* 24 - CMU */ + .long MSC_IRQHandler /* 25 - MSC */ + .long CRYPTO0_IRQHandler /* 26 - CRYPTO0 */ + .long LETIMER0_IRQHandler /* 27 - LETIMER0 */ + .long Default_Handler /* 28 - Reserved */ + .long Default_Handler /* 29 - Reserved */ + .long RTCC_IRQHandler /* 30 - RTCC */ + .long Default_Handler /* 31 - Reserved */ + .long CRYOTIMER_IRQHandler /* 32 - CRYOTIMER */ + .long Default_Handler /* 33 - Reserved */ + .long FPUEH_IRQHandler /* 34 - FPUEH */ + .long SMU_IRQHandler /* 35 - SMU */ + .long WTIMER0_IRQHandler /* 36 - WTIMER0 */ + .long WTIMER1_IRQHandler /* 37 - WTIMER1 */ + .long PCNT1_IRQHandler /* 38 - PCNT1 */ + .long PCNT2_IRQHandler /* 39 - PCNT2 */ + .long USART2_RX_IRQHandler /* 40 - USART2_RX */ + .long USART2_TX_IRQHandler /* 41 - USART2_TX */ + .long I2C1_IRQHandler /* 42 - I2C1 */ + .long USART3_RX_IRQHandler /* 43 - USART3_RX */ + .long USART3_TX_IRQHandler /* 44 - USART3_TX */ + .long VDAC0_IRQHandler /* 45 - VDAC0 */ + .long CSEN_IRQHandler /* 46 - CSEN */ + .long LESENSE_IRQHandler /* 47 - LESENSE */ + .long CRYPTO1_IRQHandler /* 48 - CRYPTO1 */ + .long TRNG0_IRQHandler /* 49 - TRNG0 */ + .long Default_Handler /* 50 - Reserved */ + + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __zero_table_start__ and __zero_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + + def_irq_handler EMU_IRQHandler + def_irq_handler WDOG0_IRQHandler + def_irq_handler WDOG1_IRQHandler + def_irq_handler LDMA_IRQHandler + def_irq_handler GPIO_EVEN_IRQHandler + def_irq_handler TIMER0_IRQHandler + def_irq_handler USART0_RX_IRQHandler + def_irq_handler USART0_TX_IRQHandler + def_irq_handler ACMP0_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler IDAC0_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler GPIO_ODD_IRQHandler + def_irq_handler TIMER1_IRQHandler + def_irq_handler USART1_RX_IRQHandler + def_irq_handler USART1_TX_IRQHandler + def_irq_handler LEUART0_IRQHandler + def_irq_handler PCNT0_IRQHandler + def_irq_handler CMU_IRQHandler + def_irq_handler MSC_IRQHandler + def_irq_handler CRYPTO0_IRQHandler + def_irq_handler LETIMER0_IRQHandler + def_irq_handler RTCC_IRQHandler + def_irq_handler CRYOTIMER_IRQHandler + def_irq_handler FPUEH_IRQHandler + def_irq_handler SMU_IRQHandler + def_irq_handler WTIMER0_IRQHandler + def_irq_handler WTIMER1_IRQHandler + def_irq_handler PCNT1_IRQHandler + def_irq_handler PCNT2_IRQHandler + def_irq_handler USART2_RX_IRQHandler + def_irq_handler USART2_TX_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler USART3_RX_IRQHandler + def_irq_handler USART3_TX_IRQHandler + def_irq_handler VDAC0_IRQHandler + def_irq_handler CSEN_IRQHandler + def_irq_handler LESENSE_IRQHandler + def_irq_handler CRYPTO1_IRQHandler + def_irq_handler TRNG0_IRQHandler + + .end diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf new file mode 100644 index 0000000000..f90304bbbb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf @@ -0,0 +1,42 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/* Version 5.1.1 */ + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = (0x00000000+0x00100000-1); +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000107; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000108; +define symbol __ICFEDIT_region_RAM_end__ = (0x20000000+0x00040000-1); + +/*-Sizes-*/ +if ( !isdefinedsymbol( __ICFEDIT_size_cstack__ ) ) +{ define symbol __ICFEDIT_size_cstack__ = 0x1000; } + +if ( !isdefinedsymbol( __ICFEDIT_size_heap__ ) ) +{ define symbol __ICFEDIT_size_heap__ = 0x4000; } + +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, + block HEAP }; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s new file mode 100644 index 0000000000..7a10da7f80 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s @@ -0,0 +1,401 @@ +;/**************************************************************************//** +; * @file startup_efm32pg12b.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32PG12B Device Series +; * @version 5.1.2 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD 0 ; 1: Reserved Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD 0 ; 4: Reserved Interrupt + DCD 0 ; 5: Reserved Interrupt + DCD 0 ; 6: Reserved Interrupt + DCD 0 ; 7: Reserved Interrupt + DCD 0 ; 8: Reserved Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD 0 ; 28: Reserved Interrupt + DCD 0 ; 29: Reserved Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD 0 ; 31: Reserved Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD 0 ; 33: Reserved Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK WDOG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG1_IRQHandler + B WDOG1_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO0_IRQHandler + B CRYPTO0_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + PUBWEAK SMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SMU_IRQHandler + B SMU_IRQHandler + + PUBWEAK WTIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER0_IRQHandler + B WTIMER0_IRQHandler + + PUBWEAK WTIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER1_IRQHandler + B WTIMER1_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK USART3_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_RX_IRQHandler + B USART3_RX_IRQHandler + + PUBWEAK USART3_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_TX_IRQHandler + B USART3_TX_IRQHandler + + PUBWEAK VDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VDAC0_IRQHandler + B VDAC0_IRQHandler + + PUBWEAK CSEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CSEN_IRQHandler + B CSEN_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK CRYPTO1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO1_IRQHandler + B CRYPTO1_IRQHandler + + PUBWEAK TRNG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG0_IRQHandler + B TRNG0_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gl125.h new file mode 100644 index 0000000000..d319a85855 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gl125.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f1024gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F1024GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F1024GL125_H +#define EFM32PG12B500F1024GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125 EFM32PG12B500F1024GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Core EFM32PG12B500F1024GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F1024GL125_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F1024GL125_Part EFM32PG12B500F1024GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F1024GL125) +#define EFM32PG12B500F1024GL125 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F1024GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F1024GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F1024GL125_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Peripheral_TypeDefs EFM32PG12B500F1024GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F1024GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Peripheral_Base EFM32PG12B500F1024GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F1024GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Peripheral_Declaration EFM32PG12B500F1024GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F1024GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Peripheral_Offsets EFM32PG12B500F1024GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F1024GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_BitFields EFM32PG12B500F1024GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_WTIMER_BitFields EFM32PG12B500F1024GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F1024GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_SYSTICK_BitFields EFM32PG12B500F1024GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F1024GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_UNLOCK EFM32PG12B500F1024GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F1024GL125_UNLOCK */ + +/** @} End of group EFM32PG12B500F1024GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GL125_Alternate_Function EFM32PG12B500F1024GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F1024GL125_Alternate_Function */ + +/** @} End of group EFM32PG12B500F1024GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F1024GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gm48.h new file mode 100644 index 0000000000..ebaeb37b56 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gm48.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f1024gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F1024GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F1024GM48_H +#define EFM32PG12B500F1024GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48 EFM32PG12B500F1024GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Core EFM32PG12B500F1024GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F1024GM48_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F1024GM48_Part EFM32PG12B500F1024GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F1024GM48) +#define EFM32PG12B500F1024GM48 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F1024GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F1024GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F1024GM48_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Peripheral_TypeDefs EFM32PG12B500F1024GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F1024GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Peripheral_Base EFM32PG12B500F1024GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F1024GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Peripheral_Declaration EFM32PG12B500F1024GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F1024GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Peripheral_Offsets EFM32PG12B500F1024GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F1024GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_BitFields EFM32PG12B500F1024GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_WTIMER_BitFields EFM32PG12B500F1024GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F1024GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_SYSTICK_BitFields EFM32PG12B500F1024GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F1024GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_UNLOCK EFM32PG12B500F1024GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F1024GM48_UNLOCK */ + +/** @} End of group EFM32PG12B500F1024GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024GM48_Alternate_Function EFM32PG12B500F1024GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F1024GM48_Alternate_Function */ + +/** @} End of group EFM32PG12B500F1024GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F1024GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024il125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024il125.h new file mode 100644 index 0000000000..e10fd5e3fc --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024il125.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f1024il125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F1024IL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F1024IL125_H +#define EFM32PG12B500F1024IL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125 EFM32PG12B500F1024IL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Core EFM32PG12B500F1024IL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F1024IL125_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F1024IL125_Part EFM32PG12B500F1024IL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F1024IL125) +#define EFM32PG12B500F1024IL125 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F1024IL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F1024IL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F1024IL125_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Peripheral_TypeDefs EFM32PG12B500F1024IL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F1024IL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Peripheral_Base EFM32PG12B500F1024IL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F1024IL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Peripheral_Declaration EFM32PG12B500F1024IL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F1024IL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Peripheral_Offsets EFM32PG12B500F1024IL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F1024IL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_BitFields EFM32PG12B500F1024IL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_WTIMER_BitFields EFM32PG12B500F1024IL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F1024IL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_SYSTICK_BitFields EFM32PG12B500F1024IL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F1024IL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_UNLOCK EFM32PG12B500F1024IL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F1024IL125_UNLOCK */ + +/** @} End of group EFM32PG12B500F1024IL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IL125_Alternate_Function EFM32PG12B500F1024IL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F1024IL125_Alternate_Function */ + +/** @} End of group EFM32PG12B500F1024IL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F1024IL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024im48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024im48.h new file mode 100644 index 0000000000..03d8ba59e1 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024im48.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f1024im48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F1024IM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F1024IM48_H +#define EFM32PG12B500F1024IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48 EFM32PG12B500F1024IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Core EFM32PG12B500F1024IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F1024IM48_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F1024IM48_Part EFM32PG12B500F1024IM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F1024IM48) +#define EFM32PG12B500F1024IM48 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F1024IM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F1024IM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F1024IM48_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Peripheral_TypeDefs EFM32PG12B500F1024IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F1024IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Peripheral_Base EFM32PG12B500F1024IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F1024IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Peripheral_Declaration EFM32PG12B500F1024IM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F1024IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Peripheral_Offsets EFM32PG12B500F1024IM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F1024IM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_BitFields EFM32PG12B500F1024IM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_WTIMER_BitFields EFM32PG12B500F1024IM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F1024IM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_SYSTICK_BitFields EFM32PG12B500F1024IM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F1024IM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_UNLOCK EFM32PG12B500F1024IM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F1024IM48_UNLOCK */ + +/** @} End of group EFM32PG12B500F1024IM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F1024IM48_Alternate_Function EFM32PG12B500F1024IM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F1024IM48_Alternate_Function */ + +/** @} End of group EFM32PG12B500F1024IM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F1024IM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gl125.h new file mode 100644 index 0000000000..bad099c847 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gl125.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f512gl125.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F512GL125 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F512GL125_H +#define EFM32PG12B500F512GL125_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125 EFM32PG12B500F512GL125 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Core EFM32PG12B500F512GL125 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F512GL125_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F512GL125_Part EFM32PG12B500F512GL125 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F512GL125) +#define EFM32PG12B500F512GL125 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F512GL125" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F512GL125 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F512GL125_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Peripheral_TypeDefs EFM32PG12B500F512GL125 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F512GL125_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Peripheral_Base EFM32PG12B500F512GL125 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F512GL125_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Peripheral_Declaration EFM32PG12B500F512GL125 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F512GL125_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Peripheral_Offsets EFM32PG12B500F512GL125 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F512GL125_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_BitFields EFM32PG12B500F512GL125 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_WTIMER_BitFields EFM32PG12B500F512GL125_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F512GL125_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_SYSTICK_BitFields EFM32PG12B500F512GL125_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F512GL125_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_UNLOCK EFM32PG12B500F512GL125 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F512GL125_UNLOCK */ + +/** @} End of group EFM32PG12B500F512GL125_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GL125_Alternate_Function EFM32PG12B500F512GL125 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F512GL125_Alternate_Function */ + +/** @} End of group EFM32PG12B500F512GL125 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F512GL125_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gm48.h new file mode 100644 index 0000000000..3d2789f77f --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gm48.h @@ -0,0 +1,2053 @@ +/**************************************************************************//** + * @file efm32pg12b500f512gm48.h + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFM32PG12B500F512GM48 + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EFM32PG12B500F512GM48_H +#define EFM32PG12B500F512GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48 EFM32PG12B500F512GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ********************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ + +/****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ + + EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ + WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ + WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ + LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ + GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ + TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ + USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ + USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ + ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ + ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ + IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ + I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ + GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ + TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ + USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ + USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ + LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ + PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ + CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ + MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ + CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ + LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ + RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ + CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ + FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ + SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ + WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ + WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ + PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ + PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ + USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ + USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ + I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ + USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ + USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ + VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ + CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ + LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ + CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ + TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ +} IRQn_Type; + +#define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Core EFM32PG12B500F512GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ +#define __MPU_PRESENT 1 /**< Presence of MPU */ +#define __FPU_PRESENT 1 /**< Presence of FPU */ +#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFM32PG12B500F512GM48_Core */ + +/**************************************************************************//** +* @defgroup EFM32PG12B500F512GM48_Part EFM32PG12B500F512GM48 Part +* @{ +******************************************************************************/ + +/** Part family */ +#define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ +#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ +#define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ +#define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ +#define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFM32PG12B500F512GM48) +#define EFM32PG12B500F512GM48 1 /**< PEARL Gecko Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFM32PG12B500F512GM48" /**< Part Number */ + +/** Memory Base addresses and limits */ +#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ +#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ + +/** Bit banding area */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ + +/** Flash and SRAM limits for EFM32PG12B500F512GM48 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ +#define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ +#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ +#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ + +/** AF channels connect the different on-chip peripherals with the af-mux */ +#define AFCHAN_MAX 136 +#define AFCHANLOC_MAX 32 +/** Analog AF channels */ +#define AFACHAN_MAX 125 + +/* Part number capabilities */ + +#define CRYPTO_PRESENT /**< CRYPTO is available in this part */ +#define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ +#define TIMER_PRESENT /**< TIMER is available in this part */ +#define TIMER_COUNT 2 /**< 2 TIMERs available */ +#define WTIMER_PRESENT /**< WTIMER is available in this part */ +#define WTIMER_COUNT 2 /**< 2 WTIMERs available */ +#define USART_PRESENT /**< USART is available in this part */ +#define USART_COUNT 4 /**< 4 USARTs available */ +#define LEUART_PRESENT /**< LEUART is available in this part */ +#define LEUART_COUNT 1 /**< 1 LEUARTs available */ +#define LETIMER_PRESENT /**< LETIMER is available in this part */ +#define LETIMER_COUNT 1 /**< 1 LETIMERs available */ +#define PCNT_PRESENT /**< PCNT is available in this part */ +#define PCNT_COUNT 3 /**< 3 PCNTs available */ +#define I2C_PRESENT /**< I2C is available in this part */ +#define I2C_COUNT 2 /**< 2 I2Cs available */ +#define ADC_PRESENT /**< ADC is available in this part */ +#define ADC_COUNT 1 /**< 1 ADCs available */ +#define ACMP_PRESENT /**< ACMP is available in this part */ +#define ACMP_COUNT 2 /**< 2 ACMPs available */ +#define IDAC_PRESENT /**< IDAC is available in this part */ +#define IDAC_COUNT 1 /**< 1 IDACs available */ +#define VDAC_PRESENT /**< VDAC is available in this part */ +#define VDAC_COUNT 1 /**< 1 VDACs available */ +#define WDOG_PRESENT /**< WDOG is available in this part */ +#define WDOG_COUNT 2 /**< 2 WDOGs available */ +#define TRNG_PRESENT /**< TRNG is available in this part */ +#define TRNG_COUNT 1 /**< 1 TRNGs available */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 +#define MSC_PRESENT +#define MSC_COUNT 1 +#define EMU_PRESENT +#define EMU_COUNT 1 +#define RMU_PRESENT +#define RMU_COUNT 1 +#define CMU_PRESENT +#define CMU_COUNT 1 +#define GPIO_PRESENT +#define GPIO_COUNT 1 +#define PRS_PRESENT +#define PRS_COUNT 1 +#define LDMA_PRESENT +#define LDMA_COUNT 1 +#define FPUEH_PRESENT +#define FPUEH_COUNT 1 +#define GPCRC_PRESENT +#define GPCRC_COUNT 1 +#define CRYOTIMER_PRESENT +#define CRYOTIMER_COUNT 1 +#define CSEN_PRESENT +#define CSEN_COUNT 1 +#define LESENSE_PRESENT +#define LESENSE_COUNT 1 +#define RTCC_PRESENT +#define RTCC_COUNT 1 +#define ETM_PRESENT +#define ETM_COUNT 1 +#define BOOTLOADER_PRESENT +#define BOOTLOADER_COUNT 1 +#define SMU_PRESENT +#define SMU_COUNT 1 + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_efm32pg12b.h" /* System Header File */ + +/** @} End of group EFM32PG12B500F512GM48_Part */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Peripheral_TypeDefs EFM32PG12B500F512GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ + +#include "efm32pg12b_msc.h" +#include "efm32pg12b_emu.h" +#include "efm32pg12b_rmu.h" +#include "efm32pg12b_cmu.h" +#include "efm32pg12b_crypto.h" +#include "efm32pg12b_gpio_p.h" +#include "efm32pg12b_gpio.h" +#include "efm32pg12b_prs_ch.h" +#include "efm32pg12b_prs.h" +#include "efm32pg12b_ldma_ch.h" +#include "efm32pg12b_ldma.h" +#include "efm32pg12b_fpueh.h" +#include "efm32pg12b_gpcrc.h" +#include "efm32pg12b_timer_cc.h" +#include "efm32pg12b_timer.h" +#include "efm32pg12b_usart.h" +#include "efm32pg12b_leuart.h" +#include "efm32pg12b_letimer.h" +#include "efm32pg12b_cryotimer.h" +#include "efm32pg12b_pcnt.h" +#include "efm32pg12b_i2c.h" +#include "efm32pg12b_adc.h" +#include "efm32pg12b_acmp.h" +#include "efm32pg12b_idac.h" +#include "efm32pg12b_vdac_opa.h" +#include "efm32pg12b_vdac.h" +#include "efm32pg12b_csen.h" +#include "efm32pg12b_lesense_st.h" +#include "efm32pg12b_lesense_buf.h" +#include "efm32pg12b_lesense_ch.h" +#include "efm32pg12b_lesense.h" +#include "efm32pg12b_rtcc_cc.h" +#include "efm32pg12b_rtcc_ret.h" +#include "efm32pg12b_rtcc.h" +#include "efm32pg12b_wdog_pch.h" +#include "efm32pg12b_wdog.h" +#include "efm32pg12b_etm.h" +#include "efm32pg12b_smu.h" +#include "efm32pg12b_trng.h" +#include "efm32pg12b_dma_descriptor.h" +#include "efm32pg12b_devinfo.h" +#include "efm32pg12b_romtable.h" + +/** @} End of group EFM32PG12B500F512GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Peripheral_Base EFM32PG12B500F512GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define MSC_BASE (0x400E0000UL) /**< MSC base address */ +#define EMU_BASE (0x400E3000UL) /**< EMU base address */ +#define RMU_BASE (0x400E5000UL) /**< RMU base address */ +#define CMU_BASE (0x400E4000UL) /**< CMU base address */ +#define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ +#define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ +#define PRS_BASE (0x400E6000UL) /**< PRS base address */ +#define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ +#define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ +#define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ +#define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ +#define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ +#define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ +#define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ +#define USART0_BASE (0x40010000UL) /**< USART0 base address */ +#define USART1_BASE (0x40010400UL) /**< USART1 base address */ +#define USART2_BASE (0x40010800UL) /**< USART2 base address */ +#define USART3_BASE (0x40010C00UL) /**< USART3 base address */ +#define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ +#define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ +#define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ +#define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ +#define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ +#define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ +#define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ +#define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ +#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ +#define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ +#define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ +#define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ +#define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ +#define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ +#define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ +#define RTCC_BASE (0x40042000UL) /**< RTCC base address */ +#define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ +#define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ +#define ETM_BASE (0xE0041000UL) /**< ETM base address */ +#define SMU_BASE (0x40022000UL) /**< SMU base address */ +#define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ +#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ +#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ +#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ +#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ + +/** @} End of group EFM32PG12B500F512GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Peripheral_Declaration EFM32PG12B500F512GM48 Peripheral Declarations + * @{ + *****************************************************************************/ + +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ +#define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ +#define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ +#define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ +#define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ +#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ +#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ + +/** @} End of group EFM32PG12B500F512GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Peripheral_Offsets EFM32PG12B500F512GM48 Peripheral Offsets + * @{ + *****************************************************************************/ + +#define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ +#define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ +#define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ +#define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ +#define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ +#define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ +#define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ +#define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ +#define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ +#define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ +#define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ +#define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ +#define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ +#define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ + +/** @} End of group EFM32PG12B500F512GM48_Peripheral_Offsets */ + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_BitFields EFM32PG12B500F512GM48 Bit Fields + * @{ + *****************************************************************************/ + +#include "efm32pg12b_prs_signals.h" +#include "efm32pg12b_dmareq.h" + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_WTIMER_BitFields EFM32PG12B500F512GM48_WTIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WTIMER CTRL */ +#define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ +#define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ +#define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ +#define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ +#define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ +#define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ +#define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ +#define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ +#define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ +#define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ +#define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ + +/* Bit fields for WTIMER CMD */ +#define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ +#define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ +#define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ +#define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ + +/* Bit fields for WTIMER STATUS */ +#define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ +#define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ +#define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ +#define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ +#define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ +#define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ + +/* Bit fields for WTIMER IF */ +#define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ +#define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ +#define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ +#define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ + +/* Bit fields for WTIMER IFS */ +#define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ +#define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ +#define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ +#define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ + +/* Bit fields for WTIMER IFC */ +#define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ +#define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ +#define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ +#define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ + +/* Bit fields for WTIMER IEN */ +#define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ +#define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ +#define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ +#define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ + +/* Bit fields for WTIMER TOP */ +#define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ +#define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ +#define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ +#define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ + +/* Bit fields for WTIMER TOPB */ +#define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ +#define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ +#define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ + +/* Bit fields for WTIMER CNT */ +#define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ +#define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ +#define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ +#define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ + +/* Bit fields for WTIMER LOCK */ +#define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ +#define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ +#define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ +#define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ + +/* Bit fields for WTIMER ROUTEPEN */ +#define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ +#define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ +#define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ + +/* Bit fields for WTIMER ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ +#define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ +#define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ + +/* Bit fields for WTIMER ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ +#define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ +#define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ + +/* Bit fields for WTIMER CC_CTRL */ +#define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ +#define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ +#define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ + +/* Bit fields for WTIMER CC_CCV */ +#define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ +#define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ +#define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ +#define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ + +/* Bit fields for WTIMER CC_CCVP */ +#define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ +#define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ + +/* Bit fields for WTIMER CC_CCVB */ +#define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ +#define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ + +/* Bit fields for WTIMER DTCTRL */ +#define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ +#define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ +#define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ + +/* Bit fields for WTIMER DTTIME */ +#define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ +#define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ +#define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ + +/* Bit fields for WTIMER DTFC */ +#define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ +#define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ +#define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ +#define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ +#define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ + +/* Bit fields for WTIMER DTOGEN */ +#define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ +#define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ +#define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ + +/* Bit fields for WTIMER DTFAULT */ +#define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ +#define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ +#define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ + +/* Bit fields for WTIMER DTFAULTC */ +#define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ +#define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ +#define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ + +/* Bit fields for WTIMER DTLOCK */ +#define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ +#define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ +#define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ + +/** @} End of group EFM32PG12B500F512GM48_WTIMER */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_SYSTICK_BitFields EFM32PG12B500F512GM48_SYSTICK Bit Fields + * @{ + *****************************************************************************/ + +/** @} End of group EFM32PG12B500F512GM48_SYSTICK */ + + + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_UNLOCK EFM32PG12B500F512GM48 Unlock Codes + * @{ + *****************************************************************************/ +#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ +#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ +#define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ +#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ +#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ +#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ +#define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ + +/** @} End of group EFM32PG12B500F512GM48_UNLOCK */ + +/** @} End of group EFM32PG12B500F512GM48_BitFields */ + +/**************************************************************************//** + * @defgroup EFM32PG12B500F512GM48_Alternate_Function EFM32PG12B500F512GM48 Alternate Function + * @{ + *****************************************************************************/ + +#include "efm32pg12b_af_ports.h" +#include "efm32pg12b_af_pins.h" + +/** @} End of group EFM32PG12B500F512GM48_Alternate_Function */ + +/** @} End of group EFM32PG12B500F512GM48 */ + +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* EFM32PG12B500F512GM48_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_acmp.h new file mode 100644 index 0000000000..42353250e5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_acmp.h @@ -0,0 +1,1420 @@ +/**************************************************************************//** + * @file efm32pg12b_acmp.h + * @brief EFM32PG12B_ACMP register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_ACMP + * @{ + * @brief EFM32PG12B_ACMP Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTSEL; /**< Input Selection Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IOM uint32_t HYSTERESIS0; /**< Hysteresis 0 Register */ + __IOM uint32_t HYSTERESIS1; /**< Hysteresis 1 Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pine Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t EXTIFCTRL; /**< External override interface control */ +} ACMP_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_ACMP_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x07000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0xBF3CF70DUL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */ +#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ +#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ +#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS (0x1UL << 8) /**< APORT Bus X Master Disable */ +#define _ACMP_CTRL_APORTXMASTERDIS_SHIFT 8 /**< Shift value for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_MASK 0x100UL /**< Bit mask for ACMP_APORTXMASTERDIS */ +#define _ACMP_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTXMASTERDIS_DEFAULT (_ACMP_CTRL_APORTXMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS (0x1UL << 9) /**< APORT Bus Y Master Disable */ +#define _ACMP_CTRL_APORTYMASTERDIS_SHIFT 9 /**< Shift value for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_MASK 0x200UL /**< Bit mask for ACMP_APORTYMASTERDIS */ +#define _ACMP_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTYMASTERDIS_DEFAULT (_ACMP_CTRL_APORTYMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS (0x1UL << 10) /**< APORT Bus Master Disable for Bus selected by VASEL */ +#define _ACMP_CTRL_APORTVMASTERDIS_SHIFT 10 /**< Shift value for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_MASK 0x400UL /**< Bit mask for ACMP_APORTVMASTERDIS */ +#define _ACMP_CTRL_APORTVMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_APORTVMASTERDIS_DEFAULT (_ACMP_CTRL_APORTVMASTERDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_SHIFT 12 /**< Shift value for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_MASK 0x7000UL /**< Bit mask for ACMP_PWRSEL */ +#define _ACMP_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_AVDD 0x00000000UL /**< Mode AVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_VREGVDD 0x00000001UL /**< Mode VREGVDD for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD0 0x00000002UL /**< Mode IOVDD0 for ACMP_CTRL */ +#define _ACMP_CTRL_PWRSEL_IOVDD1 0x00000004UL /**< Mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_DEFAULT (_ACMP_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_AVDD (_ACMP_CTRL_PWRSEL_AVDD << 12) /**< Shifted mode AVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_VREGVDD (_ACMP_CTRL_PWRSEL_VREGVDD << 12) /**< Shifted mode VREGVDD for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD0 (_ACMP_CTRL_PWRSEL_IOVDD0 << 12) /**< Shifted mode IOVDD0 for ACMP_CTRL */ +#define ACMP_CTRL_PWRSEL_IOVDD1 (_ACMP_CTRL_PWRSEL_IOVDD1 << 12) /**< Shifted mode IOVDD1 for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY (0x1UL << 15) /**< ACMP accuracy mode */ +#define _ACMP_CTRL_ACCURACY_SHIFT 15 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_MASK 0x8000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CTRL_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_DEFAULT (_ACMP_CTRL_ACCURACY_DEFAULT << 15) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_LOW (_ACMP_CTRL_ACCURACY_LOW << 15) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_ACCURACY_HIGH (_ACMP_CTRL_ACCURACY_HIGH << 15) /**< Shifted mode HIGH for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_SHIFT 18 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_MASK 0xC0000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CTRL_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_GTVDDDIV2 0x00000001UL /**< Mode GTVDDDIV2 for ACMP_CTRL */ +#define _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 0x00000002UL /**< Mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_DEFAULT (_ACMP_CTRL_INPUTRANGE_DEFAULT << 18) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_FULL (_ACMP_CTRL_INPUTRANGE_FULL << 18) /**< Shifted mode FULL for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_GTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_GTVDDDIV2 << 18) /**< Shifted mode GTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_INPUTRANGE_LTVDDDIV2 (_ACMP_CTRL_INPUTRANGE_LTVDDDIV2 << 18) /**< Shifted mode LTVDDDIV2 for ACMP_CTRL */ +#define ACMP_CTRL_IRISE (0x1UL << 20) /**< Rising Edge Interrupt Sense */ +#define _ACMP_CTRL_IRISE_SHIFT 20 /**< Shift value for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_MASK 0x100000UL /**< Bit mask for ACMP_IRISE */ +#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 20) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 20) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 20) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL (0x1UL << 21) /**< Falling Edge Interrupt Sense */ +#define _ACMP_CTRL_IFALL_SHIFT 21 /**< Shift value for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_MASK 0x200000UL /**< Bit mask for ACMP_IFALL */ +#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ +#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 21) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 21) /**< Shifted mode DISABLED for ACMP_CTRL */ +#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 21) /**< Shifted mode ENABLED for ACMP_CTRL */ +#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_MASK 0x3F000000UL /**< Bit mask for ACMP_BIASPROG */ +#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */ +#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ +#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTSEL */ +#define _ACMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_MASK 0x757FFFFFUL /**< Mask for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH0 (_ACMP_INPUTSEL_POSSEL_APORT0XCH0 << 0) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH1 (_ACMP_INPUTSEL_POSSEL_APORT0XCH1 << 0) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH2 (_ACMP_INPUTSEL_POSSEL_APORT0XCH2 << 0) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH3 (_ACMP_INPUTSEL_POSSEL_APORT0XCH3 << 0) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH4 (_ACMP_INPUTSEL_POSSEL_APORT0XCH4 << 0) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH5 (_ACMP_INPUTSEL_POSSEL_APORT0XCH5 << 0) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH6 (_ACMP_INPUTSEL_POSSEL_APORT0XCH6 << 0) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH7 (_ACMP_INPUTSEL_POSSEL_APORT0XCH7 << 0) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH8 (_ACMP_INPUTSEL_POSSEL_APORT0XCH8 << 0) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH9 (_ACMP_INPUTSEL_POSSEL_APORT0XCH9 << 0) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH10 (_ACMP_INPUTSEL_POSSEL_APORT0XCH10 << 0) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH11 (_ACMP_INPUTSEL_POSSEL_APORT0XCH11 << 0) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH12 (_ACMP_INPUTSEL_POSSEL_APORT0XCH12 << 0) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH13 (_ACMP_INPUTSEL_POSSEL_APORT0XCH13 << 0) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH14 (_ACMP_INPUTSEL_POSSEL_APORT0XCH14 << 0) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0XCH15 (_ACMP_INPUTSEL_POSSEL_APORT0XCH15 << 0) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH0 (_ACMP_INPUTSEL_POSSEL_APORT0YCH0 << 0) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH1 (_ACMP_INPUTSEL_POSSEL_APORT0YCH1 << 0) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH2 (_ACMP_INPUTSEL_POSSEL_APORT0YCH2 << 0) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH3 (_ACMP_INPUTSEL_POSSEL_APORT0YCH3 << 0) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH4 (_ACMP_INPUTSEL_POSSEL_APORT0YCH4 << 0) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH5 (_ACMP_INPUTSEL_POSSEL_APORT0YCH5 << 0) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH6 (_ACMP_INPUTSEL_POSSEL_APORT0YCH6 << 0) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH7 (_ACMP_INPUTSEL_POSSEL_APORT0YCH7 << 0) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH8 (_ACMP_INPUTSEL_POSSEL_APORT0YCH8 << 0) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH9 (_ACMP_INPUTSEL_POSSEL_APORT0YCH9 << 0) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH10 (_ACMP_INPUTSEL_POSSEL_APORT0YCH10 << 0) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH11 (_ACMP_INPUTSEL_POSSEL_APORT0YCH11 << 0) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH12 (_ACMP_INPUTSEL_POSSEL_APORT0YCH12 << 0) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH13 (_ACMP_INPUTSEL_POSSEL_APORT0YCH13 << 0) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH14 (_ACMP_INPUTSEL_POSSEL_APORT0YCH14 << 0) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT0YCH15 (_ACMP_INPUTSEL_POSSEL_APORT0YCH15 << 0) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH0 (_ACMP_INPUTSEL_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH1 (_ACMP_INPUTSEL_POSSEL_APORT1YCH1 << 0) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH2 (_ACMP_INPUTSEL_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH3 (_ACMP_INPUTSEL_POSSEL_APORT1YCH3 << 0) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH4 (_ACMP_INPUTSEL_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH5 (_ACMP_INPUTSEL_POSSEL_APORT1YCH5 << 0) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH6 (_ACMP_INPUTSEL_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH7 (_ACMP_INPUTSEL_POSSEL_APORT1YCH7 << 0) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH8 (_ACMP_INPUTSEL_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH9 (_ACMP_INPUTSEL_POSSEL_APORT1YCH9 << 0) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH10 (_ACMP_INPUTSEL_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH11 (_ACMP_INPUTSEL_POSSEL_APORT1YCH11 << 0) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH12 (_ACMP_INPUTSEL_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH13 (_ACMP_INPUTSEL_POSSEL_APORT1YCH13 << 0) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH14 (_ACMP_INPUTSEL_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH15 (_ACMP_INPUTSEL_POSSEL_APORT1YCH15 << 0) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH16 (_ACMP_INPUTSEL_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH17 (_ACMP_INPUTSEL_POSSEL_APORT1YCH17 << 0) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH18 (_ACMP_INPUTSEL_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH19 (_ACMP_INPUTSEL_POSSEL_APORT1YCH19 << 0) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH20 (_ACMP_INPUTSEL_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH21 (_ACMP_INPUTSEL_POSSEL_APORT1YCH21 << 0) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH22 (_ACMP_INPUTSEL_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH23 (_ACMP_INPUTSEL_POSSEL_APORT1YCH23 << 0) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH24 (_ACMP_INPUTSEL_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH25 (_ACMP_INPUTSEL_POSSEL_APORT1YCH25 << 0) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH26 (_ACMP_INPUTSEL_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH27 (_ACMP_INPUTSEL_POSSEL_APORT1YCH27 << 0) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH28 (_ACMP_INPUTSEL_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH29 (_ACMP_INPUTSEL_POSSEL_APORT1YCH29 << 0) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1XCH30 (_ACMP_INPUTSEL_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT1YCH31 (_ACMP_INPUTSEL_POSSEL_APORT1YCH31 << 0) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH0 (_ACMP_INPUTSEL_POSSEL_APORT2YCH0 << 0) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH1 (_ACMP_INPUTSEL_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH2 (_ACMP_INPUTSEL_POSSEL_APORT2YCH2 << 0) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH3 (_ACMP_INPUTSEL_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH4 (_ACMP_INPUTSEL_POSSEL_APORT2YCH4 << 0) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH5 (_ACMP_INPUTSEL_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH6 (_ACMP_INPUTSEL_POSSEL_APORT2YCH6 << 0) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH7 (_ACMP_INPUTSEL_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH8 (_ACMP_INPUTSEL_POSSEL_APORT2YCH8 << 0) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH9 (_ACMP_INPUTSEL_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH10 (_ACMP_INPUTSEL_POSSEL_APORT2YCH10 << 0) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH11 (_ACMP_INPUTSEL_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH12 (_ACMP_INPUTSEL_POSSEL_APORT2YCH12 << 0) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH13 (_ACMP_INPUTSEL_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH14 (_ACMP_INPUTSEL_POSSEL_APORT2YCH14 << 0) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH15 (_ACMP_INPUTSEL_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH16 (_ACMP_INPUTSEL_POSSEL_APORT2YCH16 << 0) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH17 (_ACMP_INPUTSEL_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH18 (_ACMP_INPUTSEL_POSSEL_APORT2YCH18 << 0) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH19 (_ACMP_INPUTSEL_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH20 (_ACMP_INPUTSEL_POSSEL_APORT2YCH20 << 0) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH21 (_ACMP_INPUTSEL_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH22 (_ACMP_INPUTSEL_POSSEL_APORT2YCH22 << 0) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH23 (_ACMP_INPUTSEL_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH24 (_ACMP_INPUTSEL_POSSEL_APORT2YCH24 << 0) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH25 (_ACMP_INPUTSEL_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH26 (_ACMP_INPUTSEL_POSSEL_APORT2YCH26 << 0) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH27 (_ACMP_INPUTSEL_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH28 (_ACMP_INPUTSEL_POSSEL_APORT2YCH28 << 0) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH29 (_ACMP_INPUTSEL_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2YCH30 (_ACMP_INPUTSEL_POSSEL_APORT2YCH30 << 0) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT2XCH31 (_ACMP_INPUTSEL_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH0 (_ACMP_INPUTSEL_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH1 (_ACMP_INPUTSEL_POSSEL_APORT3YCH1 << 0) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH2 (_ACMP_INPUTSEL_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH3 (_ACMP_INPUTSEL_POSSEL_APORT3YCH3 << 0) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH4 (_ACMP_INPUTSEL_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH5 (_ACMP_INPUTSEL_POSSEL_APORT3YCH5 << 0) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH6 (_ACMP_INPUTSEL_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH7 (_ACMP_INPUTSEL_POSSEL_APORT3YCH7 << 0) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH8 (_ACMP_INPUTSEL_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH9 (_ACMP_INPUTSEL_POSSEL_APORT3YCH9 << 0) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH10 (_ACMP_INPUTSEL_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH11 (_ACMP_INPUTSEL_POSSEL_APORT3YCH11 << 0) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH12 (_ACMP_INPUTSEL_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH13 (_ACMP_INPUTSEL_POSSEL_APORT3YCH13 << 0) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH14 (_ACMP_INPUTSEL_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH15 (_ACMP_INPUTSEL_POSSEL_APORT3YCH15 << 0) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH16 (_ACMP_INPUTSEL_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH17 (_ACMP_INPUTSEL_POSSEL_APORT3YCH17 << 0) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH18 (_ACMP_INPUTSEL_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH19 (_ACMP_INPUTSEL_POSSEL_APORT3YCH19 << 0) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH20 (_ACMP_INPUTSEL_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH21 (_ACMP_INPUTSEL_POSSEL_APORT3YCH21 << 0) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH22 (_ACMP_INPUTSEL_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH23 (_ACMP_INPUTSEL_POSSEL_APORT3YCH23 << 0) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH24 (_ACMP_INPUTSEL_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH25 (_ACMP_INPUTSEL_POSSEL_APORT3YCH25 << 0) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH26 (_ACMP_INPUTSEL_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH27 (_ACMP_INPUTSEL_POSSEL_APORT3YCH27 << 0) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH28 (_ACMP_INPUTSEL_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH29 (_ACMP_INPUTSEL_POSSEL_APORT3YCH29 << 0) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3XCH30 (_ACMP_INPUTSEL_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT3YCH31 (_ACMP_INPUTSEL_POSSEL_APORT3YCH31 << 0) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH0 (_ACMP_INPUTSEL_POSSEL_APORT4YCH0 << 0) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH1 (_ACMP_INPUTSEL_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH2 (_ACMP_INPUTSEL_POSSEL_APORT4YCH2 << 0) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH3 (_ACMP_INPUTSEL_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH4 (_ACMP_INPUTSEL_POSSEL_APORT4YCH4 << 0) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH5 (_ACMP_INPUTSEL_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH6 (_ACMP_INPUTSEL_POSSEL_APORT4YCH6 << 0) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH7 (_ACMP_INPUTSEL_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH8 (_ACMP_INPUTSEL_POSSEL_APORT4YCH8 << 0) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH9 (_ACMP_INPUTSEL_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH10 (_ACMP_INPUTSEL_POSSEL_APORT4YCH10 << 0) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH11 (_ACMP_INPUTSEL_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH12 (_ACMP_INPUTSEL_POSSEL_APORT4YCH12 << 0) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH13 (_ACMP_INPUTSEL_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH16 (_ACMP_INPUTSEL_POSSEL_APORT4YCH16 << 0) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH17 (_ACMP_INPUTSEL_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH18 (_ACMP_INPUTSEL_POSSEL_APORT4YCH18 << 0) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH19 (_ACMP_INPUTSEL_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH20 (_ACMP_INPUTSEL_POSSEL_APORT4YCH20 << 0) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH21 (_ACMP_INPUTSEL_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH22 (_ACMP_INPUTSEL_POSSEL_APORT4YCH22 << 0) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH23 (_ACMP_INPUTSEL_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH24 (_ACMP_INPUTSEL_POSSEL_APORT4YCH24 << 0) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH25 (_ACMP_INPUTSEL_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH26 (_ACMP_INPUTSEL_POSSEL_APORT4YCH26 << 0) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH27 (_ACMP_INPUTSEL_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH28 (_ACMP_INPUTSEL_POSSEL_APORT4YCH28 << 0) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH29 (_ACMP_INPUTSEL_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH30 (_ACMP_INPUTSEL_POSSEL_APORT4YCH30 << 0) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4YCH14 (_ACMP_INPUTSEL_POSSEL_APORT4YCH14 << 0) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH15 (_ACMP_INPUTSEL_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_APORT4XCH31 (_ACMP_INPUTSEL_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT0 (_ACMP_INPUTSEL_POSSEL_DACOUT0 << 0) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_DACOUT1 (_ACMP_INPUTSEL_POSSEL_DACOUT1 << 0) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VLP (_ACMP_INPUTSEL_POSSEL_VLP << 0) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VBDIV (_ACMP_INPUTSEL_POSSEL_VBDIV << 0) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VADIV (_ACMP_INPUTSEL_POSSEL_VADIV << 0) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VDD (_ACMP_INPUTSEL_POSSEL_VDD << 0) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_POSSEL_VSS (_ACMP_INPUTSEL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4YCH14 0x0000009EUL /**< Mode APORT4YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH15 0x0000009FUL /**< Mode APORT4XCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT0 0x000000F2UL /**< Mode DACOUT0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_DACOUT1 0x000000F3UL /**< Mode DACOUT1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VLP 0x000000FBUL /**< Mode VLP for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VBDIV 0x000000FCUL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VADIV 0x000000FDUL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VDD 0x000000FEUL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT0YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT1YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT2XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH0 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH1 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH2 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH3 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH4 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH5 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH6 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH7 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH8 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH9 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH10 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH11 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH12 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH13 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH14 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH15 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH16 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH17 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH18 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH19 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH20 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH21 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH22 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH23 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH24 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH25 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH26 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH27 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH28 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH29 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3XCH30 (_ACMP_INPUTSEL_NEGSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT3YCH31 (_ACMP_INPUTSEL_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH0 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH1 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH2 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH3 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH4 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH5 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH6 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH7 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH8 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH9 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH10 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH11 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH12 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH13 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH16 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH17 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH18 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH19 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH20 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH21 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH22 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH23 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH24 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH25 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH26 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH27 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH28 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH29 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH30 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4YCH14 (_ACMP_INPUTSEL_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH15 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_APORT4XCH31 (_ACMP_INPUTSEL_NEGSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT0 (_ACMP_INPUTSEL_NEGSEL_DACOUT0 << 8) /**< Shifted mode DACOUT0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_DACOUT1 (_ACMP_INPUTSEL_NEGSEL_DACOUT1 << 8) /**< Shifted mode DACOUT1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VLP (_ACMP_INPUTSEL_NEGSEL_VLP << 8) /**< Shifted mode VLP for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VBDIV (_ACMP_INPUTSEL_NEGSEL_VBDIV << 8) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VADIV (_ACMP_INPUTSEL_NEGSEL_VADIV << 8) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 8) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_NEGSEL_VSS (_ACMP_INPUTSEL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_SHIFT 16 /**< Shift value for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_MASK 0x3F0000UL /**< Bit mask for ACMP_VASEL */ +#define _ACMP_INPUTSEL_VASEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_VDD 0x00000000UL /**< Mode VDD for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH0 0x00000001UL /**< Mode APORT2YCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH2 0x00000003UL /**< Mode APORT2YCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH4 0x00000005UL /**< Mode APORT2YCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH6 0x00000007UL /**< Mode APORT2YCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH8 0x00000009UL /**< Mode APORT2YCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH10 0x0000000BUL /**< Mode APORT2YCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH12 0x0000000DUL /**< Mode APORT2YCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH14 0x0000000FUL /**< Mode APORT2YCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH16 0x00000011UL /**< Mode APORT2YCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH18 0x00000013UL /**< Mode APORT2YCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH20 0x00000015UL /**< Mode APORT2YCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH22 0x00000017UL /**< Mode APORT2YCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH24 0x00000019UL /**< Mode APORT2YCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH26 0x0000001BUL /**< Mode APORT2YCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH28 0x0000001DUL /**< Mode APORT2YCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT2YCH30 0x0000001FUL /**< Mode APORT2YCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VASEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_DEFAULT (_ACMP_INPUTSEL_VASEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_VDD (_ACMP_INPUTSEL_VASEL_VDD << 16) /**< Shifted mode VDD for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH0 (_ACMP_INPUTSEL_VASEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH2 (_ACMP_INPUTSEL_VASEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH4 (_ACMP_INPUTSEL_VASEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH6 (_ACMP_INPUTSEL_VASEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH8 (_ACMP_INPUTSEL_VASEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH10 (_ACMP_INPUTSEL_VASEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH12 (_ACMP_INPUTSEL_VASEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH14 (_ACMP_INPUTSEL_VASEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH16 (_ACMP_INPUTSEL_VASEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH18 (_ACMP_INPUTSEL_VASEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH20 (_ACMP_INPUTSEL_VASEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH22 (_ACMP_INPUTSEL_VASEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH24 (_ACMP_INPUTSEL_VASEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH26 (_ACMP_INPUTSEL_VASEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH28 (_ACMP_INPUTSEL_VASEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT2YCH30 (_ACMP_INPUTSEL_VASEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH0 (_ACMP_INPUTSEL_VASEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH1 (_ACMP_INPUTSEL_VASEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH2 (_ACMP_INPUTSEL_VASEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH3 (_ACMP_INPUTSEL_VASEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH4 (_ACMP_INPUTSEL_VASEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH5 (_ACMP_INPUTSEL_VASEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH6 (_ACMP_INPUTSEL_VASEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH7 (_ACMP_INPUTSEL_VASEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH8 (_ACMP_INPUTSEL_VASEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH9 (_ACMP_INPUTSEL_VASEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH10 (_ACMP_INPUTSEL_VASEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH11 (_ACMP_INPUTSEL_VASEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH12 (_ACMP_INPUTSEL_VASEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH13 (_ACMP_INPUTSEL_VASEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH14 (_ACMP_INPUTSEL_VASEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH15 (_ACMP_INPUTSEL_VASEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH16 (_ACMP_INPUTSEL_VASEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH17 (_ACMP_INPUTSEL_VASEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH18 (_ACMP_INPUTSEL_VASEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH19 (_ACMP_INPUTSEL_VASEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH20 (_ACMP_INPUTSEL_VASEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH21 (_ACMP_INPUTSEL_VASEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH22 (_ACMP_INPUTSEL_VASEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH23 (_ACMP_INPUTSEL_VASEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH24 (_ACMP_INPUTSEL_VASEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH25 (_ACMP_INPUTSEL_VASEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH26 (_ACMP_INPUTSEL_VASEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH27 (_ACMP_INPUTSEL_VASEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH28 (_ACMP_INPUTSEL_VASEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH29 (_ACMP_INPUTSEL_VASEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1XCH30 (_ACMP_INPUTSEL_VASEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VASEL_APORT1YCH31 (_ACMP_INPUTSEL_VASEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL (0x1UL << 22) /**< VB Selection */ +#define _ACMP_INPUTSEL_VBSEL_SHIFT 22 /**< Shift value for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_MASK 0x400000UL /**< Bit mask for ACMP_VBSEL */ +#define _ACMP_INPUTSEL_VBSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_1V25 0x00000000UL /**< Mode 1V25 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VBSEL_2V5 0x00000001UL /**< Mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_DEFAULT (_ACMP_INPUTSEL_VBSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_1V25 (_ACMP_INPUTSEL_VBSEL_1V25 << 22) /**< Shifted mode 1V25 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VBSEL_2V5 (_ACMP_INPUTSEL_VBSEL_2V5 << 22) /**< Shifted mode 2V5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL (0x1UL << 24) /**< Low-Power Sampled Voltage Selection */ +#define _ACMP_INPUTSEL_VLPSEL_SHIFT 24 /**< Shift value for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_MASK 0x1000000UL /**< Bit mask for ACMP_VLPSEL */ +#define _ACMP_INPUTSEL_VLPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VADIV 0x00000000UL /**< Mode VADIV for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_VLPSEL_VBDIV 0x00000001UL /**< Mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_DEFAULT (_ACMP_INPUTSEL_VLPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VADIV (_ACMP_INPUTSEL_VLPSEL_VADIV << 24) /**< Shifted mode VADIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_VLPSEL_VBDIV (_ACMP_INPUTSEL_VLPSEL_VBDIV << 24) /**< Shifted mode VBDIV for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN (0x1UL << 26) /**< Capacitive Sense Mode Internal Resistor Enable */ +#define _ACMP_INPUTSEL_CSRESEN_SHIFT 26 /**< Shift value for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_MASK 0x4000000UL /**< Bit mask for ACMP_CSRESEN */ +#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 26) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTSEL */ +#define _ACMP_INPUTSEL_CSRESSEL_RES7 0x00000007UL /**< Mode RES7 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES4 (_ACMP_INPUTSEL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES5 (_ACMP_INPUTSEL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES6 (_ACMP_INPUTSEL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_RES7 (_ACMP_INPUTSEL_CSRESSEL_RES7 << 28) /**< Shifted mode RES7 for ACMP_INPUTSEL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000000FUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */ +#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ +#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Output */ +#define _ACMP_STATUS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_APORTCONFLICT_DEFAULT (_ACMP_STATUS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT (0x1UL << 3) /**< External override interface active. */ +#define _ACMP_STATUS_EXTIFACT_SHIFT 3 /**< Shift value for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_MASK 0x8UL /**< Bit mask for ACMP_EXTIFACT */ +#define _ACMP_STATUS_EXTIFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_EXTIFACT_DEFAULT (_ACMP_STATUS_EXTIFACT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x00000007UL /**< Mask for ACMP_IF */ +#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ +#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT (0x1UL << 2) /**< APORT Conflict Interrupt Flag */ +#define _ACMP_IF_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_APORTCONFLICT_DEFAULT (_ACMP_IF_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IFS */ +#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ +#define _ACMP_IFS_MASK 0x00000007UL /**< Mask for ACMP_IFS */ +#define ACMP_IFS_EDGE (0x1UL << 0) /**< Set EDGE Interrupt Flag */ +#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Set WARMUP Interrupt Flag */ +#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT (0x1UL << 2) /**< Set APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFS_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ +#define ACMP_IFS_APORTCONFLICT_DEFAULT (_ACMP_IFS_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFS */ + +/* Bit fields for ACMP IFC */ +#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ +#define _ACMP_IFC_MASK 0x00000007UL /**< Mask for ACMP_IFC */ +#define ACMP_IFC_EDGE (0x1UL << 0) /**< Clear EDGE Interrupt Flag */ +#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Clear WARMUP Interrupt Flag */ +#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT (0x1UL << 2) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _ACMP_IFC_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ +#define ACMP_IFC_APORTCONFLICT_DEFAULT (_ACMP_IFC_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IFC */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x00000007UL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_EDGE (0x1UL << 0) /**< EDGE Interrupt Enable */ +#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ +#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP (0x1UL << 1) /**< WARMUP Interrupt Enable */ +#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ +#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT (0x1UL << 2) /**< APORTCONFLICT Interrupt Enable */ +#define _ACMP_IEN_APORTCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORTCONFLICT */ +#define _ACMP_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_APORTCONFLICT_DEFAULT (_ACMP_IEN_APORTCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP APORTREQ */ +#define _ACMP_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTREQ */ +#define _ACMP_APORTREQ_MASK 0x000003FFUL /**< Mask for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */ +#define _ACMP_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ACMP_APORT0XREQ */ +#define _ACMP_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0XREQ_DEFAULT (_ACMP_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */ +#define _ACMP_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ACMP_APORT0YREQ */ +#define _ACMP_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT0YREQ_DEFAULT (_ACMP_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _ACMP_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ACMP_APORT1XREQ */ +#define _ACMP_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1XREQ_DEFAULT (_ACMP_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _ACMP_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ACMP_APORT1YREQ */ +#define _ACMP_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT1YREQ_DEFAULT (_ACMP_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _ACMP_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ACMP_APORT2XREQ */ +#define _ACMP_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2XREQ_DEFAULT (_ACMP_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _ACMP_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ACMP_APORT2YREQ */ +#define _ACMP_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT2YREQ_DEFAULT (_ACMP_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _ACMP_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ACMP_APORT3XREQ */ +#define _ACMP_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3XREQ_DEFAULT (_ACMP_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _ACMP_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ACMP_APORT3YREQ */ +#define _ACMP_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT3YREQ_DEFAULT (_ACMP_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _ACMP_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ACMP_APORT4XREQ */ +#define _ACMP_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4XREQ_DEFAULT (_ACMP_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _ACMP_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ACMP_APORT4YREQ */ +#define _ACMP_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTREQ */ +#define ACMP_APORTREQ_APORT4YREQ_DEFAULT (_ACMP_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTREQ */ + +/* Bit fields for ACMP APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ACMP_APORTCONFLICT */ +#define _ACMP_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ACMP_APORT0XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ACMP_APORT0YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ACMP_APORT1XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_APORT1YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ACMP_APORT2XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ACMP_APORT2YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ACMP_APORT3XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ACMP_APORT3YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ACMP_APORT4XCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ACMP_APORT4YCONFLICT */ +#define _ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_APORTCONFLICT */ +#define ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ACMP_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ACMP_APORTCONFLICT */ + +/* Bit fields for ACMP HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS0_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_DEFAULT (_ACMP_HYSTERESIS0_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST0 (_ACMP_HYSTERESIS0_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST1 (_ACMP_HYSTERESIS0_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST2 (_ACMP_HYSTERESIS0_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST3 (_ACMP_HYSTERESIS0_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST4 (_ACMP_HYSTERESIS0_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST5 (_ACMP_HYSTERESIS0_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST6 (_ACMP_HYSTERESIS0_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST7 (_ACMP_HYSTERESIS0_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST8 (_ACMP_HYSTERESIS0_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST9 (_ACMP_HYSTERESIS0_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST10 (_ACMP_HYSTERESIS0_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST11 (_ACMP_HYSTERESIS0_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST12 (_ACMP_HYSTERESIS0_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST13 (_ACMP_HYSTERESIS0_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST14 (_ACMP_HYSTERESIS0_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_HYST_HYST15 (_ACMP_HYSTERESIS0_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS0_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVA_DEFAULT (_ACMP_HYSTERESIS0_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ +#define _ACMP_HYSTERESIS0_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS0_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS0 */ +#define ACMP_HYSTERESIS0_DIVVB_DEFAULT (_ACMP_HYSTERESIS0_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS0 */ + +/* Bit fields for ACMP HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_RESETVALUE 0x00000000UL /**< Default value for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_MASK 0x3F3F000FUL /**< Mask for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_SHIFT 0 /**< Shift value for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_MASK 0xFUL /**< Bit mask for ACMP_HYST */ +#define _ACMP_HYSTERESIS1_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST8 0x00000008UL /**< Mode HYST8 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST9 0x00000009UL /**< Mode HYST9 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST10 0x0000000AUL /**< Mode HYST10 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST11 0x0000000BUL /**< Mode HYST11 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST12 0x0000000CUL /**< Mode HYST12 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST13 0x0000000DUL /**< Mode HYST13 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST14 0x0000000EUL /**< Mode HYST14 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_HYST_HYST15 0x0000000FUL /**< Mode HYST15 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_DEFAULT (_ACMP_HYSTERESIS1_HYST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST0 (_ACMP_HYSTERESIS1_HYST_HYST0 << 0) /**< Shifted mode HYST0 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST1 (_ACMP_HYSTERESIS1_HYST_HYST1 << 0) /**< Shifted mode HYST1 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST2 (_ACMP_HYSTERESIS1_HYST_HYST2 << 0) /**< Shifted mode HYST2 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST3 (_ACMP_HYSTERESIS1_HYST_HYST3 << 0) /**< Shifted mode HYST3 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST4 (_ACMP_HYSTERESIS1_HYST_HYST4 << 0) /**< Shifted mode HYST4 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST5 (_ACMP_HYSTERESIS1_HYST_HYST5 << 0) /**< Shifted mode HYST5 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST6 (_ACMP_HYSTERESIS1_HYST_HYST6 << 0) /**< Shifted mode HYST6 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST7 (_ACMP_HYSTERESIS1_HYST_HYST7 << 0) /**< Shifted mode HYST7 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST8 (_ACMP_HYSTERESIS1_HYST_HYST8 << 0) /**< Shifted mode HYST8 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST9 (_ACMP_HYSTERESIS1_HYST_HYST9 << 0) /**< Shifted mode HYST9 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST10 (_ACMP_HYSTERESIS1_HYST_HYST10 << 0) /**< Shifted mode HYST10 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST11 (_ACMP_HYSTERESIS1_HYST_HYST11 << 0) /**< Shifted mode HYST11 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST12 (_ACMP_HYSTERESIS1_HYST_HYST12 << 0) /**< Shifted mode HYST12 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST13 (_ACMP_HYSTERESIS1_HYST_HYST13 << 0) /**< Shifted mode HYST13 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST14 (_ACMP_HYSTERESIS1_HYST_HYST14 << 0) /**< Shifted mode HYST14 for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_HYST_HYST15 (_ACMP_HYSTERESIS1_HYST_HYST15 << 0) /**< Shifted mode HYST15 for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVA_SHIFT 16 /**< Shift value for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_MASK 0x3F0000UL /**< Bit mask for ACMP_DIVVA */ +#define _ACMP_HYSTERESIS1_DIVVA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVA_DEFAULT (_ACMP_HYSTERESIS1_DIVVA_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ +#define _ACMP_HYSTERESIS1_DIVVB_SHIFT 24 /**< Shift value for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_MASK 0x3F000000UL /**< Bit mask for ACMP_DIVVB */ +#define _ACMP_HYSTERESIS1_DIVVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_HYSTERESIS1 */ +#define ACMP_HYSTERESIS1_DIVVB_DEFAULT (_ACMP_HYSTERESIS1_DIVVB_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_HYSTERESIS1 */ + +/* Bit fields for ACMP ROUTEPEN */ +#define _ACMP_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTEPEN */ +#define _ACMP_ROUTEPEN_MASK 0x00000001UL /**< Mask for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN (0x1UL << 0) /**< ACMP Output Pin Enable */ +#define _ACMP_ROUTEPEN_OUTPEN_SHIFT 0 /**< Shift value for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_MASK 0x1UL /**< Bit mask for ACMP_OUTPEN */ +#define _ACMP_ROUTEPEN_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTEPEN */ +#define ACMP_ROUTEPEN_OUTPEN_DEFAULT (_ACMP_ROUTEPEN_OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTEPEN */ + +/* Bit fields for ACMP ROUTELOC0 */ +#define _ACMP_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_MASK 0x0000001FUL /**< Mask for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_SHIFT 0 /**< Shift value for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_MASK 0x1FUL /**< Bit mask for ACMP_OUTLOC */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC4 0x00000004UL /**< Mode LOC4 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC5 0x00000005UL /**< Mode LOC5 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC6 0x00000006UL /**< Mode LOC6 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC7 0x00000007UL /**< Mode LOC7 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC8 0x00000008UL /**< Mode LOC8 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC9 0x00000009UL /**< Mode LOC9 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC10 0x0000000AUL /**< Mode LOC10 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC11 0x0000000BUL /**< Mode LOC11 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC12 0x0000000CUL /**< Mode LOC12 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC13 0x0000000DUL /**< Mode LOC13 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC14 0x0000000EUL /**< Mode LOC14 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC15 0x0000000FUL /**< Mode LOC15 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC16 0x00000010UL /**< Mode LOC16 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC17 0x00000011UL /**< Mode LOC17 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC18 0x00000012UL /**< Mode LOC18 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC19 0x00000013UL /**< Mode LOC19 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC20 0x00000014UL /**< Mode LOC20 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC21 0x00000015UL /**< Mode LOC21 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC22 0x00000016UL /**< Mode LOC22 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC23 0x00000017UL /**< Mode LOC23 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC24 0x00000018UL /**< Mode LOC24 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC25 0x00000019UL /**< Mode LOC25 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC26 0x0000001AUL /**< Mode LOC26 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC27 0x0000001BUL /**< Mode LOC27 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC28 0x0000001CUL /**< Mode LOC28 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC29 0x0000001DUL /**< Mode LOC29 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC30 0x0000001EUL /**< Mode LOC30 for ACMP_ROUTELOC0 */ +#define _ACMP_ROUTELOC0_OUTLOC_LOC31 0x0000001FUL /**< Mode LOC31 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC0 (_ACMP_ROUTELOC0_OUTLOC_LOC0 << 0) /**< Shifted mode LOC0 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_DEFAULT (_ACMP_ROUTELOC0_OUTLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC1 (_ACMP_ROUTELOC0_OUTLOC_LOC1 << 0) /**< Shifted mode LOC1 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC2 (_ACMP_ROUTELOC0_OUTLOC_LOC2 << 0) /**< Shifted mode LOC2 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC3 (_ACMP_ROUTELOC0_OUTLOC_LOC3 << 0) /**< Shifted mode LOC3 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC4 (_ACMP_ROUTELOC0_OUTLOC_LOC4 << 0) /**< Shifted mode LOC4 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC5 (_ACMP_ROUTELOC0_OUTLOC_LOC5 << 0) /**< Shifted mode LOC5 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC6 (_ACMP_ROUTELOC0_OUTLOC_LOC6 << 0) /**< Shifted mode LOC6 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC7 (_ACMP_ROUTELOC0_OUTLOC_LOC7 << 0) /**< Shifted mode LOC7 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC8 (_ACMP_ROUTELOC0_OUTLOC_LOC8 << 0) /**< Shifted mode LOC8 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC9 (_ACMP_ROUTELOC0_OUTLOC_LOC9 << 0) /**< Shifted mode LOC9 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC10 (_ACMP_ROUTELOC0_OUTLOC_LOC10 << 0) /**< Shifted mode LOC10 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC11 (_ACMP_ROUTELOC0_OUTLOC_LOC11 << 0) /**< Shifted mode LOC11 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC12 (_ACMP_ROUTELOC0_OUTLOC_LOC12 << 0) /**< Shifted mode LOC12 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC13 (_ACMP_ROUTELOC0_OUTLOC_LOC13 << 0) /**< Shifted mode LOC13 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC14 (_ACMP_ROUTELOC0_OUTLOC_LOC14 << 0) /**< Shifted mode LOC14 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC15 (_ACMP_ROUTELOC0_OUTLOC_LOC15 << 0) /**< Shifted mode LOC15 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC16 (_ACMP_ROUTELOC0_OUTLOC_LOC16 << 0) /**< Shifted mode LOC16 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC17 (_ACMP_ROUTELOC0_OUTLOC_LOC17 << 0) /**< Shifted mode LOC17 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC18 (_ACMP_ROUTELOC0_OUTLOC_LOC18 << 0) /**< Shifted mode LOC18 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC19 (_ACMP_ROUTELOC0_OUTLOC_LOC19 << 0) /**< Shifted mode LOC19 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC20 (_ACMP_ROUTELOC0_OUTLOC_LOC20 << 0) /**< Shifted mode LOC20 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC21 (_ACMP_ROUTELOC0_OUTLOC_LOC21 << 0) /**< Shifted mode LOC21 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC22 (_ACMP_ROUTELOC0_OUTLOC_LOC22 << 0) /**< Shifted mode LOC22 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC23 (_ACMP_ROUTELOC0_OUTLOC_LOC23 << 0) /**< Shifted mode LOC23 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC24 (_ACMP_ROUTELOC0_OUTLOC_LOC24 << 0) /**< Shifted mode LOC24 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC25 (_ACMP_ROUTELOC0_OUTLOC_LOC25 << 0) /**< Shifted mode LOC25 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC26 (_ACMP_ROUTELOC0_OUTLOC_LOC26 << 0) /**< Shifted mode LOC26 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC27 (_ACMP_ROUTELOC0_OUTLOC_LOC27 << 0) /**< Shifted mode LOC27 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC28 (_ACMP_ROUTELOC0_OUTLOC_LOC28 << 0) /**< Shifted mode LOC28 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC29 (_ACMP_ROUTELOC0_OUTLOC_LOC29 << 0) /**< Shifted mode LOC29 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC30 (_ACMP_ROUTELOC0_OUTLOC_LOC30 << 0) /**< Shifted mode LOC30 for ACMP_ROUTELOC0 */ +#define ACMP_ROUTELOC0_OUTLOC_LOC31 (_ACMP_ROUTELOC0_OUTLOC_LOC31 << 0) /**< Shifted mode LOC31 for ACMP_ROUTELOC0 */ + +/* Bit fields for ACMP EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_MASK 0x000000F1UL /**< Mask for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN (0x1UL << 0) /**< Enable external interface. */ +#define _ACMP_EXTIFCTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EXTIFCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_EN_DEFAULT (_ACMP_EXTIFCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_SHIFT 4 /**< Shift value for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_MASK 0xF0UL /**< Bit mask for ACMP_APORTSEL */ +#define _ACMP_EXTIFCTRL_APORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0X 0x00000000UL /**< Mode APORT0X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT0Y 0x00000001UL /**< Mode APORT0Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1X 0x00000002UL /**< Mode APORT1X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1Y 0x00000003UL /**< Mode APORT1Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT1XY 0x00000004UL /**< Mode APORT1XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2X 0x00000005UL /**< Mode APORT2X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2Y 0x00000006UL /**< Mode APORT2Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT2YX 0x00000007UL /**< Mode APORT2YX for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3X 0x00000008UL /**< Mode APORT3X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3Y 0x00000009UL /**< Mode APORT3Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT3XY 0x0000000AUL /**< Mode APORT3XY for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4X 0x0000000BUL /**< Mode APORT4X for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4Y 0x0000000CUL /**< Mode APORT4Y for ACMP_EXTIFCTRL */ +#define _ACMP_EXTIFCTRL_APORTSEL_APORT4YX 0x0000000DUL /**< Mode APORT4YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_DEFAULT (_ACMP_EXTIFCTRL_APORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0X (_ACMP_EXTIFCTRL_APORTSEL_APORT0X << 4) /**< Shifted mode APORT0X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT0Y (_ACMP_EXTIFCTRL_APORTSEL_APORT0Y << 4) /**< Shifted mode APORT0Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1X (_ACMP_EXTIFCTRL_APORTSEL_APORT1X << 4) /**< Shifted mode APORT1X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1Y (_ACMP_EXTIFCTRL_APORTSEL_APORT1Y << 4) /**< Shifted mode APORT1Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT1XY (_ACMP_EXTIFCTRL_APORTSEL_APORT1XY << 4) /**< Shifted mode APORT1XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2X (_ACMP_EXTIFCTRL_APORTSEL_APORT2X << 4) /**< Shifted mode APORT2X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2Y (_ACMP_EXTIFCTRL_APORTSEL_APORT2Y << 4) /**< Shifted mode APORT2Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT2YX (_ACMP_EXTIFCTRL_APORTSEL_APORT2YX << 4) /**< Shifted mode APORT2YX for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3X (_ACMP_EXTIFCTRL_APORTSEL_APORT3X << 4) /**< Shifted mode APORT3X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3Y (_ACMP_EXTIFCTRL_APORTSEL_APORT3Y << 4) /**< Shifted mode APORT3Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT3XY (_ACMP_EXTIFCTRL_APORTSEL_APORT3XY << 4) /**< Shifted mode APORT3XY for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4X (_ACMP_EXTIFCTRL_APORTSEL_APORT4X << 4) /**< Shifted mode APORT4X for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4Y (_ACMP_EXTIFCTRL_APORTSEL_APORT4Y << 4) /**< Shifted mode APORT4Y for ACMP_EXTIFCTRL */ +#define ACMP_EXTIFCTRL_APORTSEL_APORT4YX (_ACMP_EXTIFCTRL_APORTSEL_APORT4YX << 4) /**< Shifted mode APORT4YX for ACMP_EXTIFCTRL */ + +/** @} End of group EFM32PG12B_ACMP */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_adc.h new file mode 100644 index 0000000000..0d48931955 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_adc.h @@ -0,0 +1,2371 @@ +/**************************************************************************//** + * @file efm32pg12b_adc.h + * @brief EFM32PG12B_ADC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_ADC + * @{ + * @brief EFM32PG12B_ADC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t SINGLECTRL; /**< Single Channel Control Register */ + __IOM uint32_t SINGLECTRLX; /**< Single Channel Control Register continued */ + __IOM uint32_t SCANCTRL; /**< Scan Control Register */ + __IOM uint32_t SCANCTRLX; /**< Scan Control Register continued */ + __IOM uint32_t SCANMASK; /**< Scan Sequence Input Mask Register */ + __IOM uint32_t SCANINPUTSEL; /**< Input Selection register for Scan mode */ + __IOM uint32_t SCANNEGSEL; /**< Negative Input select register for Scan */ + __IOM uint32_t CMPTHR; /**< Compare Threshold Register */ + __IOM uint32_t BIASPROG; /**< Bias Programming Register for various analog blocks used in ADC operation. */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SINGLEDATA; /**< Single Conversion Result Data */ + __IM uint32_t SCANDATA; /**< Scan Conversion Result Data */ + __IM uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */ + __IM uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */ + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IM uint32_t SCANDATAX; /**< Scan Sequence Result Data + Data Source Register */ + __IM uint32_t SCANDATAXP; /**< Scan Sequence Result Data + Data Source Peek Register */ + + uint32_t RESERVED2[3]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Conflict Status Register */ + __IM uint32_t SINGLEFIFOCOUNT; /**< Single FIFO Count Register */ + __IM uint32_t SCANFIFOCOUNT; /**< Scan FIFO Count Register */ + __IOM uint32_t SINGLEFIFOCLEAR; /**< Single FIFO Clear Register */ + __IOM uint32_t SCANFIFOCLEAR; /**< Scan FIFO Clear Register */ + __IOM uint32_t APORTMASTERDIS; /**< APORT Bus Master Disable Register */ +} ADC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_ADC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ADC CTRL */ +#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */ +#define _ADC_CTRL_MASK 0xFF7F7FDFUL /**< Mask for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */ +#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPINSLOWACC 0x00000002UL /**< Mode KEEPINSLOWACC for ADC_CTRL */ +#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_ADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 0) /**< Shifted mode KEEPINSTANDBY for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPINSLOWACC (_ADC_CTRL_WARMUPMODE_KEEPINSLOWACC << 0) /**< Shifted mode KEEPINSLOWACC for ADC_CTRL */ +#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU (0x1UL << 2) /**< SINGLEFIFO DMA Wakeup */ +#define _ADC_CTRL_SINGLEDMAWU_SHIFT 2 /**< Shift value for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_MASK 0x4UL /**< Bit mask for ADC_SINGLEDMAWU */ +#define _ADC_CTRL_SINGLEDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SINGLEDMAWU_DEFAULT (_ADC_CTRL_SINGLEDMAWU_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU (0x1UL << 3) /**< SCANFIFO DMA Wakeup */ +#define _ADC_CTRL_SCANDMAWU_SHIFT 3 /**< Shift value for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_MASK 0x8UL /**< Bit mask for ADC_SCANDMAWU */ +#define _ADC_CTRL_SCANDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_SCANDMAWU_DEFAULT (_ADC_CTRL_SCANDMAWU_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE (0x1UL << 4) /**< Conversion Tailgating */ +#define _ADC_CTRL_TAILGATE_SHIFT 4 /**< Shift value for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_MASK 0x10UL /**< Bit mask for ADC_TAILGATE */ +#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN (0x1UL << 6) /**< Selects ASYNC CLK enable mode when ADCCLKMODE=1 */ +#define _ADC_CTRL_ASYNCCLKEN_SHIFT 6 /**< Shift value for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_MASK 0x40UL /**< Bit mask for ADC_ASYNCCLKEN */ +#define _ADC_CTRL_ASYNCCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ASNEEDED 0x00000000UL /**< Mode ASNEEDED for ADC_CTRL */ +#define _ADC_CTRL_ASYNCCLKEN_ALWAYSON 0x00000001UL /**< Mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_DEFAULT (_ADC_CTRL_ASYNCCLKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ASNEEDED (_ADC_CTRL_ASYNCCLKEN_ASNEEDED << 6) /**< Shifted mode ASNEEDED for ADC_CTRL */ +#define ADC_CTRL_ASYNCCLKEN_ALWAYSON (_ADC_CTRL_ASYNCCLKEN_ALWAYSON << 6) /**< Shifted mode ALWAYSON for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE (0x1UL << 7) /**< ADC Clock Mode */ +#define _ADC_CTRL_ADCCLKMODE_SHIFT 7 /**< Shift value for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_MASK 0x80UL /**< Bit mask for ADC_ADCCLKMODE */ +#define _ADC_CTRL_ADCCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for ADC_CTRL */ +#define _ADC_CTRL_ADCCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_DEFAULT (_ADC_CTRL_ADCCLKMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_SYNC (_ADC_CTRL_ADCCLKMODE_SYNC << 7) /**< Shifted mode SYNC for ADC_CTRL */ +#define ADC_CTRL_ADCCLKMODE_ASYNC (_ADC_CTRL_ADCCLKMODE_ASYNC << 7) /**< Shifted mode ASYNC for ADC_CTRL */ +#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */ +#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */ +#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */ +#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */ +#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for ADC_TIMEBASE */ +#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */ +#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */ +#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */ +#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */ +#define ADC_CTRL_DBGHALT (0x1UL << 28) /**< Debug Mode Halt Enable */ +#define _ADC_CTRL_DBGHALT_SHIFT 28 /**< Shift value for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_MASK 0x10000000UL /**< Bit mask for ADC_DBGHALT */ +#define _ADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_DBGHALT_DEFAULT (_ADC_CTRL_DBGHALT_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE (0x1UL << 29) /**< Channel Connect */ +#define _ADC_CTRL_CHCONMODE_SHIFT 29 /**< Shift value for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_MASK 0x20000000UL /**< Bit mask for ADC_CHCONMODE */ +#define _ADC_CTRL_CHCONMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXSETTLE 0x00000000UL /**< Mode MAXSETTLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONMODE_MAXRESP 0x00000001UL /**< Mode MAXRESP for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_DEFAULT (_ADC_CTRL_CHCONMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXSETTLE (_ADC_CTRL_CHCONMODE_MAXSETTLE << 29) /**< Shifted mode MAXSETTLE for ADC_CTRL */ +#define ADC_CTRL_CHCONMODE_MAXRESP (_ADC_CTRL_CHCONMODE_MAXRESP << 29) /**< Shifted mode MAXRESP for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_SHIFT 30 /**< Shift value for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_MASK 0xC0000000UL /**< Bit mask for ADC_CHCONREFWARMIDLE */ +#define _ADC_CTRL_CHCONREFWARMIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN 0x00000000UL /**< Mode PREFSCAN for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE 0x00000001UL /**< Mode PREFSINGLE for ADC_CTRL */ +#define _ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV 0x00000002UL /**< Mode KEEPPREV for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_DEFAULT (_ADC_CTRL_CHCONREFWARMIDLE_DEFAULT << 30) /**< Shifted mode DEFAULT for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN (_ADC_CTRL_CHCONREFWARMIDLE_PREFSCAN << 30) /**< Shifted mode PREFSCAN for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE (_ADC_CTRL_CHCONREFWARMIDLE_PREFSINGLE << 30) /**< Shifted mode PREFSINGLE for ADC_CTRL */ +#define ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV (_ADC_CTRL_CHCONREFWARMIDLE_KEEPPREV << 30) /**< Shifted mode KEEPPREV for ADC_CTRL */ + +/* Bit fields for ADC CMD */ +#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */ +#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */ +#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Channel Conversion Start */ +#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */ +#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Channel Conversion Stop */ +#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */ +#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */ +#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */ +#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */ +#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */ +#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */ +#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */ + +/* Bit fields for ADC STATUS */ +#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */ +#define _ADC_STATUS_MASK 0x00031F07UL /**< Mask for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Channel Conversion Active */ +#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */ +#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */ +#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */ +#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING (0x1UL << 2) /**< Scan Conversion Pending */ +#define _ADC_STATUS_SCANPENDING_SHIFT 2 /**< Shift value for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_MASK 0x4UL /**< Bit mask for ADC_SCANPENDING */ +#define _ADC_STATUS_SCANPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANPENDING_DEFAULT (_ADC_STATUS_SCANPENDING_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Channel Reference Warmed Up */ +#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */ +#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */ +#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */ +#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_SHIFT 10 /**< Shift value for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_MASK 0xC00UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_STATUS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_BUSCONF 0x00000001UL /**< Mode BUSCONF for ADC_STATUS */ +#define _ADC_STATUS_PROGERR_NEGSELCONF 0x00000002UL /**< Mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_DEFAULT (_ADC_STATUS_PROGERR_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_PROGERR_BUSCONF (_ADC_STATUS_PROGERR_BUSCONF << 10) /**< Shifted mode BUSCONF for ADC_STATUS */ +#define ADC_STATUS_PROGERR_NEGSELCONF (_ADC_STATUS_PROGERR_NEGSELCONF << 10) /**< Shifted mode NEGSELCONF for ADC_STATUS */ +#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */ +#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */ +#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */ +#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Channel Data Valid */ +#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */ +#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */ +#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */ +#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */ +#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */ + +/* Bit fields for ADC SINGLECTRL */ +#define _ADC_SINGLECTRL_RESETVALUE 0x00FFFF00UL /**< Default value for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_MASK 0xAFFFFFFFUL /**< Mask for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Channel Repetitive Mode */ +#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Channel Differential Mode */ +#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Channel Result Adjustment */ +#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SINGLECTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SINGLECTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_5V (_ADC_SINGLECTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_REF_CONF (_ADC_SINGLECTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SHIFT 8 /**< Shift value for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_MASK 0xFF00UL /**< Bit mask for ADC_POSSEL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AVDD 0x000000E0UL /**< Mode AVDD for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_BU 0x000000E1UL /**< Mode BU for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_AREG 0x000000E2UL /**< Mode AREG for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VREGOUTPA 0x000000E3UL /**< Mode VREGOUTPA for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_PDBU 0x000000E4UL /**< Mode PDBU for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IO0 0x000000E5UL /**< Mode IO0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_IO1 0x000000E6UL /**< Mode IO1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSP 0x000000E7UL /**< Mode VSP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA2 0x000000F2UL /**< Mode OPA2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TEMP 0x000000F3UL /**< Mode TEMP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT0 0x000000F4UL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_TESTP 0x000000F5UL /**< Mode TESTP for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP1 0x000000F6UL /**< Mode SP1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SP2 0x000000F7UL /**< Mode SP2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DAC0OUT1 0x000000F8UL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_SUBLSB 0x000000F9UL /**< Mode SUBLSB for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_OPA3 0x000000FAUL /**< Mode OPA3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_POSSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH0 (_ADC_SINGLECTRL_POSSEL_APORT0XCH0 << 8) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH1 (_ADC_SINGLECTRL_POSSEL_APORT0XCH1 << 8) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH2 (_ADC_SINGLECTRL_POSSEL_APORT0XCH2 << 8) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH3 (_ADC_SINGLECTRL_POSSEL_APORT0XCH3 << 8) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH4 (_ADC_SINGLECTRL_POSSEL_APORT0XCH4 << 8) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH5 (_ADC_SINGLECTRL_POSSEL_APORT0XCH5 << 8) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH6 (_ADC_SINGLECTRL_POSSEL_APORT0XCH6 << 8) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH7 (_ADC_SINGLECTRL_POSSEL_APORT0XCH7 << 8) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH8 (_ADC_SINGLECTRL_POSSEL_APORT0XCH8 << 8) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH9 (_ADC_SINGLECTRL_POSSEL_APORT0XCH9 << 8) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH10 (_ADC_SINGLECTRL_POSSEL_APORT0XCH10 << 8) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH11 (_ADC_SINGLECTRL_POSSEL_APORT0XCH11 << 8) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH12 (_ADC_SINGLECTRL_POSSEL_APORT0XCH12 << 8) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH13 (_ADC_SINGLECTRL_POSSEL_APORT0XCH13 << 8) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH14 (_ADC_SINGLECTRL_POSSEL_APORT0XCH14 << 8) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0XCH15 (_ADC_SINGLECTRL_POSSEL_APORT0XCH15 << 8) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH0 (_ADC_SINGLECTRL_POSSEL_APORT0YCH0 << 8) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH1 (_ADC_SINGLECTRL_POSSEL_APORT0YCH1 << 8) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH2 (_ADC_SINGLECTRL_POSSEL_APORT0YCH2 << 8) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH3 (_ADC_SINGLECTRL_POSSEL_APORT0YCH3 << 8) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH4 (_ADC_SINGLECTRL_POSSEL_APORT0YCH4 << 8) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH5 (_ADC_SINGLECTRL_POSSEL_APORT0YCH5 << 8) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH6 (_ADC_SINGLECTRL_POSSEL_APORT0YCH6 << 8) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH7 (_ADC_SINGLECTRL_POSSEL_APORT0YCH7 << 8) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH8 (_ADC_SINGLECTRL_POSSEL_APORT0YCH8 << 8) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH9 (_ADC_SINGLECTRL_POSSEL_APORT0YCH9 << 8) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH10 (_ADC_SINGLECTRL_POSSEL_APORT0YCH10 << 8) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH11 (_ADC_SINGLECTRL_POSSEL_APORT0YCH11 << 8) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH12 (_ADC_SINGLECTRL_POSSEL_APORT0YCH12 << 8) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH13 (_ADC_SINGLECTRL_POSSEL_APORT0YCH13 << 8) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH14 (_ADC_SINGLECTRL_POSSEL_APORT0YCH14 << 8) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT0YCH15 (_ADC_SINGLECTRL_POSSEL_APORT0YCH15 << 8) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH0 (_ADC_SINGLECTRL_POSSEL_APORT1XCH0 << 8) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH1 (_ADC_SINGLECTRL_POSSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH2 (_ADC_SINGLECTRL_POSSEL_APORT1XCH2 << 8) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH3 (_ADC_SINGLECTRL_POSSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH4 (_ADC_SINGLECTRL_POSSEL_APORT1XCH4 << 8) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH5 (_ADC_SINGLECTRL_POSSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH6 (_ADC_SINGLECTRL_POSSEL_APORT1XCH6 << 8) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH7 (_ADC_SINGLECTRL_POSSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH8 (_ADC_SINGLECTRL_POSSEL_APORT1XCH8 << 8) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH9 (_ADC_SINGLECTRL_POSSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH10 (_ADC_SINGLECTRL_POSSEL_APORT1XCH10 << 8) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH11 (_ADC_SINGLECTRL_POSSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH12 (_ADC_SINGLECTRL_POSSEL_APORT1XCH12 << 8) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH13 (_ADC_SINGLECTRL_POSSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH14 (_ADC_SINGLECTRL_POSSEL_APORT1XCH14 << 8) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH15 (_ADC_SINGLECTRL_POSSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH16 (_ADC_SINGLECTRL_POSSEL_APORT1XCH16 << 8) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH17 (_ADC_SINGLECTRL_POSSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH18 (_ADC_SINGLECTRL_POSSEL_APORT1XCH18 << 8) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH19 (_ADC_SINGLECTRL_POSSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH20 (_ADC_SINGLECTRL_POSSEL_APORT1XCH20 << 8) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH21 (_ADC_SINGLECTRL_POSSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH22 (_ADC_SINGLECTRL_POSSEL_APORT1XCH22 << 8) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH23 (_ADC_SINGLECTRL_POSSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH24 (_ADC_SINGLECTRL_POSSEL_APORT1XCH24 << 8) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH25 (_ADC_SINGLECTRL_POSSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH26 (_ADC_SINGLECTRL_POSSEL_APORT1XCH26 << 8) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH27 (_ADC_SINGLECTRL_POSSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH28 (_ADC_SINGLECTRL_POSSEL_APORT1XCH28 << 8) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH29 (_ADC_SINGLECTRL_POSSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1XCH30 (_ADC_SINGLECTRL_POSSEL_APORT1XCH30 << 8) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT1YCH31 (_ADC_SINGLECTRL_POSSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH0 (_ADC_SINGLECTRL_POSSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH1 (_ADC_SINGLECTRL_POSSEL_APORT2XCH1 << 8) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH2 (_ADC_SINGLECTRL_POSSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH3 (_ADC_SINGLECTRL_POSSEL_APORT2XCH3 << 8) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH4 (_ADC_SINGLECTRL_POSSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH5 (_ADC_SINGLECTRL_POSSEL_APORT2XCH5 << 8) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH6 (_ADC_SINGLECTRL_POSSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH7 (_ADC_SINGLECTRL_POSSEL_APORT2XCH7 << 8) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH8 (_ADC_SINGLECTRL_POSSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH9 (_ADC_SINGLECTRL_POSSEL_APORT2XCH9 << 8) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH10 (_ADC_SINGLECTRL_POSSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH11 (_ADC_SINGLECTRL_POSSEL_APORT2XCH11 << 8) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH12 (_ADC_SINGLECTRL_POSSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH13 (_ADC_SINGLECTRL_POSSEL_APORT2XCH13 << 8) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH14 (_ADC_SINGLECTRL_POSSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH15 (_ADC_SINGLECTRL_POSSEL_APORT2XCH15 << 8) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH16 (_ADC_SINGLECTRL_POSSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH17 (_ADC_SINGLECTRL_POSSEL_APORT2XCH17 << 8) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH18 (_ADC_SINGLECTRL_POSSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH19 (_ADC_SINGLECTRL_POSSEL_APORT2XCH19 << 8) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH20 (_ADC_SINGLECTRL_POSSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH21 (_ADC_SINGLECTRL_POSSEL_APORT2XCH21 << 8) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH22 (_ADC_SINGLECTRL_POSSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH23 (_ADC_SINGLECTRL_POSSEL_APORT2XCH23 << 8) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH24 (_ADC_SINGLECTRL_POSSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH25 (_ADC_SINGLECTRL_POSSEL_APORT2XCH25 << 8) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH26 (_ADC_SINGLECTRL_POSSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH27 (_ADC_SINGLECTRL_POSSEL_APORT2XCH27 << 8) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH28 (_ADC_SINGLECTRL_POSSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH29 (_ADC_SINGLECTRL_POSSEL_APORT2XCH29 << 8) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2YCH30 (_ADC_SINGLECTRL_POSSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT2XCH31 (_ADC_SINGLECTRL_POSSEL_APORT2XCH31 << 8) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH0 (_ADC_SINGLECTRL_POSSEL_APORT3XCH0 << 8) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH1 (_ADC_SINGLECTRL_POSSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH2 (_ADC_SINGLECTRL_POSSEL_APORT3XCH2 << 8) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH3 (_ADC_SINGLECTRL_POSSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH4 (_ADC_SINGLECTRL_POSSEL_APORT3XCH4 << 8) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH5 (_ADC_SINGLECTRL_POSSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH6 (_ADC_SINGLECTRL_POSSEL_APORT3XCH6 << 8) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH7 (_ADC_SINGLECTRL_POSSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH8 (_ADC_SINGLECTRL_POSSEL_APORT3XCH8 << 8) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH9 (_ADC_SINGLECTRL_POSSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH10 (_ADC_SINGLECTRL_POSSEL_APORT3XCH10 << 8) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH11 (_ADC_SINGLECTRL_POSSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH12 (_ADC_SINGLECTRL_POSSEL_APORT3XCH12 << 8) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH13 (_ADC_SINGLECTRL_POSSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH14 (_ADC_SINGLECTRL_POSSEL_APORT3XCH14 << 8) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH15 (_ADC_SINGLECTRL_POSSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH16 (_ADC_SINGLECTRL_POSSEL_APORT3XCH16 << 8) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH17 (_ADC_SINGLECTRL_POSSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH18 (_ADC_SINGLECTRL_POSSEL_APORT3XCH18 << 8) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH19 (_ADC_SINGLECTRL_POSSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH20 (_ADC_SINGLECTRL_POSSEL_APORT3XCH20 << 8) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH21 (_ADC_SINGLECTRL_POSSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH22 (_ADC_SINGLECTRL_POSSEL_APORT3XCH22 << 8) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH23 (_ADC_SINGLECTRL_POSSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH24 (_ADC_SINGLECTRL_POSSEL_APORT3XCH24 << 8) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH25 (_ADC_SINGLECTRL_POSSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH26 (_ADC_SINGLECTRL_POSSEL_APORT3XCH26 << 8) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH27 (_ADC_SINGLECTRL_POSSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH28 (_ADC_SINGLECTRL_POSSEL_APORT3XCH28 << 8) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH29 (_ADC_SINGLECTRL_POSSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3XCH30 (_ADC_SINGLECTRL_POSSEL_APORT3XCH30 << 8) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT3YCH31 (_ADC_SINGLECTRL_POSSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH0 (_ADC_SINGLECTRL_POSSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH1 (_ADC_SINGLECTRL_POSSEL_APORT4XCH1 << 8) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH2 (_ADC_SINGLECTRL_POSSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH3 (_ADC_SINGLECTRL_POSSEL_APORT4XCH3 << 8) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH4 (_ADC_SINGLECTRL_POSSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH5 (_ADC_SINGLECTRL_POSSEL_APORT4XCH5 << 8) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH6 (_ADC_SINGLECTRL_POSSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH7 (_ADC_SINGLECTRL_POSSEL_APORT4XCH7 << 8) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH8 (_ADC_SINGLECTRL_POSSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH9 (_ADC_SINGLECTRL_POSSEL_APORT4XCH9 << 8) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH10 (_ADC_SINGLECTRL_POSSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH11 (_ADC_SINGLECTRL_POSSEL_APORT4XCH11 << 8) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH12 (_ADC_SINGLECTRL_POSSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH13 (_ADC_SINGLECTRL_POSSEL_APORT4XCH13 << 8) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH14 (_ADC_SINGLECTRL_POSSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH15 (_ADC_SINGLECTRL_POSSEL_APORT4XCH15 << 8) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH16 (_ADC_SINGLECTRL_POSSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH17 (_ADC_SINGLECTRL_POSSEL_APORT4XCH17 << 8) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH18 (_ADC_SINGLECTRL_POSSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH19 (_ADC_SINGLECTRL_POSSEL_APORT4XCH19 << 8) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH20 (_ADC_SINGLECTRL_POSSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH21 (_ADC_SINGLECTRL_POSSEL_APORT4XCH21 << 8) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH22 (_ADC_SINGLECTRL_POSSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH23 (_ADC_SINGLECTRL_POSSEL_APORT4XCH23 << 8) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH24 (_ADC_SINGLECTRL_POSSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH25 (_ADC_SINGLECTRL_POSSEL_APORT4XCH25 << 8) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH26 (_ADC_SINGLECTRL_POSSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH27 (_ADC_SINGLECTRL_POSSEL_APORT4XCH27 << 8) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH28 (_ADC_SINGLECTRL_POSSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH29 (_ADC_SINGLECTRL_POSSEL_APORT4XCH29 << 8) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4YCH30 (_ADC_SINGLECTRL_POSSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_APORT4XCH31 (_ADC_SINGLECTRL_POSSEL_APORT4XCH31 << 8) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AVDD (_ADC_SINGLECTRL_POSSEL_AVDD << 8) /**< Shifted mode AVDD for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_BU (_ADC_SINGLECTRL_POSSEL_BU << 8) /**< Shifted mode BU for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_AREG (_ADC_SINGLECTRL_POSSEL_AREG << 8) /**< Shifted mode AREG for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VREGOUTPA (_ADC_SINGLECTRL_POSSEL_VREGOUTPA << 8) /**< Shifted mode VREGOUTPA for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_PDBU (_ADC_SINGLECTRL_POSSEL_PDBU << 8) /**< Shifted mode PDBU for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IO0 (_ADC_SINGLECTRL_POSSEL_IO0 << 8) /**< Shifted mode IO0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_IO1 (_ADC_SINGLECTRL_POSSEL_IO1 << 8) /**< Shifted mode IO1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSP (_ADC_SINGLECTRL_POSSEL_VSP << 8) /**< Shifted mode VSP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA2 (_ADC_SINGLECTRL_POSSEL_OPA2 << 8) /**< Shifted mode OPA2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TEMP (_ADC_SINGLECTRL_POSSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT0 (_ADC_SINGLECTRL_POSSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_TESTP (_ADC_SINGLECTRL_POSSEL_TESTP << 8) /**< Shifted mode TESTP for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP1 (_ADC_SINGLECTRL_POSSEL_SP1 << 8) /**< Shifted mode SP1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SP2 (_ADC_SINGLECTRL_POSSEL_SP2 << 8) /**< Shifted mode SP2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DAC0OUT1 (_ADC_SINGLECTRL_POSSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_SUBLSB (_ADC_SINGLECTRL_POSSEL_SUBLSB << 8) /**< Shifted mode SUBLSB for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_OPA3 (_ADC_SINGLECTRL_POSSEL_OPA3 << 8) /**< Shifted mode OPA3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_DEFAULT (_ADC_SINGLECTRL_POSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_POSSEL_VSS (_ADC_SINGLECTRL_POSSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_SHIFT 16 /**< Shift value for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_MASK 0xFF0000UL /**< Bit mask for ADC_NEGSEL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH0 0x00000000UL /**< Mode APORT0XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH1 0x00000001UL /**< Mode APORT0XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH2 0x00000002UL /**< Mode APORT0XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH3 0x00000003UL /**< Mode APORT0XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH4 0x00000004UL /**< Mode APORT0XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH5 0x00000005UL /**< Mode APORT0XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH6 0x00000006UL /**< Mode APORT0XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH7 0x00000007UL /**< Mode APORT0XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH8 0x00000008UL /**< Mode APORT0XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH9 0x00000009UL /**< Mode APORT0XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH10 0x0000000AUL /**< Mode APORT0XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH11 0x0000000BUL /**< Mode APORT0XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH12 0x0000000CUL /**< Mode APORT0XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH13 0x0000000DUL /**< Mode APORT0XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH14 0x0000000EUL /**< Mode APORT0XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0XCH15 0x0000000FUL /**< Mode APORT0XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH0 0x00000010UL /**< Mode APORT0YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH1 0x00000011UL /**< Mode APORT0YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH2 0x00000012UL /**< Mode APORT0YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH3 0x00000013UL /**< Mode APORT0YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH4 0x00000014UL /**< Mode APORT0YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH5 0x00000015UL /**< Mode APORT0YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH6 0x00000016UL /**< Mode APORT0YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH7 0x00000017UL /**< Mode APORT0YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH8 0x00000018UL /**< Mode APORT0YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH9 0x00000019UL /**< Mode APORT0YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH10 0x0000001AUL /**< Mode APORT0YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH11 0x0000001BUL /**< Mode APORT0YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH12 0x0000001CUL /**< Mode APORT0YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH13 0x0000001DUL /**< Mode APORT0YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH14 0x0000001EUL /**< Mode APORT0YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT0YCH15 0x0000001FUL /**< Mode APORT0YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH0 0x00000040UL /**< Mode APORT2YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH1 0x00000041UL /**< Mode APORT2XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH2 0x00000042UL /**< Mode APORT2YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH3 0x00000043UL /**< Mode APORT2XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH4 0x00000044UL /**< Mode APORT2YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH5 0x00000045UL /**< Mode APORT2XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH6 0x00000046UL /**< Mode APORT2YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH7 0x00000047UL /**< Mode APORT2XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH8 0x00000048UL /**< Mode APORT2YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH9 0x00000049UL /**< Mode APORT2XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH10 0x0000004AUL /**< Mode APORT2YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH11 0x0000004BUL /**< Mode APORT2XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH12 0x0000004CUL /**< Mode APORT2YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH13 0x0000004DUL /**< Mode APORT2XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH14 0x0000004EUL /**< Mode APORT2YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH15 0x0000004FUL /**< Mode APORT2XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH16 0x00000050UL /**< Mode APORT2YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH17 0x00000051UL /**< Mode APORT2XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH18 0x00000052UL /**< Mode APORT2YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH19 0x00000053UL /**< Mode APORT2XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH20 0x00000054UL /**< Mode APORT2YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH21 0x00000055UL /**< Mode APORT2XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH22 0x00000056UL /**< Mode APORT2YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH23 0x00000057UL /**< Mode APORT2XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH24 0x00000058UL /**< Mode APORT2YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH25 0x00000059UL /**< Mode APORT2XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH26 0x0000005AUL /**< Mode APORT2YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH27 0x0000005BUL /**< Mode APORT2XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH28 0x0000005CUL /**< Mode APORT2YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH29 0x0000005DUL /**< Mode APORT2XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2YCH30 0x0000005EUL /**< Mode APORT2YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT2XCH31 0x0000005FUL /**< Mode APORT2XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH0 0x00000080UL /**< Mode APORT4YCH0 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH1 0x00000081UL /**< Mode APORT4XCH1 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH2 0x00000082UL /**< Mode APORT4YCH2 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH3 0x00000083UL /**< Mode APORT4XCH3 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH4 0x00000084UL /**< Mode APORT4YCH4 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH5 0x00000085UL /**< Mode APORT4XCH5 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH6 0x00000086UL /**< Mode APORT4YCH6 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH7 0x00000087UL /**< Mode APORT4XCH7 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH8 0x00000088UL /**< Mode APORT4YCH8 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH9 0x00000089UL /**< Mode APORT4XCH9 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH10 0x0000008AUL /**< Mode APORT4YCH10 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH11 0x0000008BUL /**< Mode APORT4XCH11 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH12 0x0000008CUL /**< Mode APORT4YCH12 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH13 0x0000008DUL /**< Mode APORT4XCH13 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH14 0x0000008EUL /**< Mode APORT4YCH14 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH15 0x0000008FUL /**< Mode APORT4XCH15 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH16 0x00000090UL /**< Mode APORT4YCH16 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH17 0x00000091UL /**< Mode APORT4XCH17 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH18 0x00000092UL /**< Mode APORT4YCH18 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH19 0x00000093UL /**< Mode APORT4XCH19 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH20 0x00000094UL /**< Mode APORT4YCH20 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH21 0x00000095UL /**< Mode APORT4XCH21 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH22 0x00000096UL /**< Mode APORT4YCH22 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH23 0x00000097UL /**< Mode APORT4XCH23 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH24 0x00000098UL /**< Mode APORT4YCH24 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH25 0x00000099UL /**< Mode APORT4XCH25 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH26 0x0000009AUL /**< Mode APORT4YCH26 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH27 0x0000009BUL /**< Mode APORT4XCH27 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH28 0x0000009CUL /**< Mode APORT4YCH28 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH29 0x0000009DUL /**< Mode APORT4XCH29 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4YCH30 0x0000009EUL /**< Mode APORT4YCH30 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_APORT4XCH31 0x0000009FUL /**< Mode APORT4XCH31 for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_TESTN 0x000000F5UL /**< Mode TESTN for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_DEFAULT 0x000000FFUL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_NEGSEL_VSS 0x000000FFUL /**< Mode VSS for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH0 << 16) /**< Shifted mode APORT0XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH1 << 16) /**< Shifted mode APORT0XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH2 << 16) /**< Shifted mode APORT0XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH3 << 16) /**< Shifted mode APORT0XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH4 << 16) /**< Shifted mode APORT0XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH5 << 16) /**< Shifted mode APORT0XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH6 << 16) /**< Shifted mode APORT0XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH7 << 16) /**< Shifted mode APORT0XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH8 << 16) /**< Shifted mode APORT0XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH9 << 16) /**< Shifted mode APORT0XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH10 << 16) /**< Shifted mode APORT0XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH11 << 16) /**< Shifted mode APORT0XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH12 << 16) /**< Shifted mode APORT0XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH13 << 16) /**< Shifted mode APORT0XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH14 << 16) /**< Shifted mode APORT0XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0XCH15 << 16) /**< Shifted mode APORT0XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH0 << 16) /**< Shifted mode APORT0YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH1 << 16) /**< Shifted mode APORT0YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH2 << 16) /**< Shifted mode APORT0YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH3 << 16) /**< Shifted mode APORT0YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH4 << 16) /**< Shifted mode APORT0YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH5 << 16) /**< Shifted mode APORT0YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH6 << 16) /**< Shifted mode APORT0YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH7 << 16) /**< Shifted mode APORT0YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH8 << 16) /**< Shifted mode APORT0YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH9 << 16) /**< Shifted mode APORT0YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH10 << 16) /**< Shifted mode APORT0YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH11 << 16) /**< Shifted mode APORT0YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH12 << 16) /**< Shifted mode APORT0YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH13 << 16) /**< Shifted mode APORT0YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH14 << 16) /**< Shifted mode APORT0YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT0YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT0YCH15 << 16) /**< Shifted mode APORT0YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH0 << 16) /**< Shifted mode APORT1XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH2 << 16) /**< Shifted mode APORT1XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH4 << 16) /**< Shifted mode APORT1XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH6 << 16) /**< Shifted mode APORT1XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH8 << 16) /**< Shifted mode APORT1XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH10 << 16) /**< Shifted mode APORT1XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH12 << 16) /**< Shifted mode APORT1XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH14 << 16) /**< Shifted mode APORT1XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH16 << 16) /**< Shifted mode APORT1XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH18 << 16) /**< Shifted mode APORT1XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH20 << 16) /**< Shifted mode APORT1XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH22 << 16) /**< Shifted mode APORT1XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH24 << 16) /**< Shifted mode APORT1XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH26 << 16) /**< Shifted mode APORT1XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH28 << 16) /**< Shifted mode APORT1XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT1XCH30 << 16) /**< Shifted mode APORT1XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT1YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH1 << 16) /**< Shifted mode APORT2XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH3 << 16) /**< Shifted mode APORT2XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH5 << 16) /**< Shifted mode APORT2XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH7 << 16) /**< Shifted mode APORT2XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH9 << 16) /**< Shifted mode APORT2XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH11 << 16) /**< Shifted mode APORT2XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH13 << 16) /**< Shifted mode APORT2XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH15 << 16) /**< Shifted mode APORT2XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH17 << 16) /**< Shifted mode APORT2XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH19 << 16) /**< Shifted mode APORT2XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH21 << 16) /**< Shifted mode APORT2XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH23 << 16) /**< Shifted mode APORT2XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH25 << 16) /**< Shifted mode APORT2XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH27 << 16) /**< Shifted mode APORT2XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH29 << 16) /**< Shifted mode APORT2XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT2XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT2XCH31 << 16) /**< Shifted mode APORT2XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH0 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH0 << 16) /**< Shifted mode APORT3XCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH1 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH2 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH2 << 16) /**< Shifted mode APORT3XCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH3 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH4 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH4 << 16) /**< Shifted mode APORT3XCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH5 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH6 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH6 << 16) /**< Shifted mode APORT3XCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH7 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH8 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH8 << 16) /**< Shifted mode APORT3XCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH9 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH10 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH10 << 16) /**< Shifted mode APORT3XCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH11 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH12 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH12 << 16) /**< Shifted mode APORT3XCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH13 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH14 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH14 << 16) /**< Shifted mode APORT3XCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH15 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH16 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH16 << 16) /**< Shifted mode APORT3XCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH17 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH18 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH18 << 16) /**< Shifted mode APORT3XCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH19 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH20 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH20 << 16) /**< Shifted mode APORT3XCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH21 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH22 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH22 << 16) /**< Shifted mode APORT3XCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH23 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH24 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH24 << 16) /**< Shifted mode APORT3XCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH25 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH26 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH26 << 16) /**< Shifted mode APORT3XCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH27 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH28 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH28 << 16) /**< Shifted mode APORT3XCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH29 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3XCH30 (_ADC_SINGLECTRL_NEGSEL_APORT3XCH30 << 16) /**< Shifted mode APORT3XCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT3YCH31 (_ADC_SINGLECTRL_NEGSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH0 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH1 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH1 << 16) /**< Shifted mode APORT4XCH1 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH2 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH3 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH3 << 16) /**< Shifted mode APORT4XCH3 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH4 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH5 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH5 << 16) /**< Shifted mode APORT4XCH5 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH6 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH7 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH7 << 16) /**< Shifted mode APORT4XCH7 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH8 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH9 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH9 << 16) /**< Shifted mode APORT4XCH9 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH10 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH11 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH11 << 16) /**< Shifted mode APORT4XCH11 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH12 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH13 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH13 << 16) /**< Shifted mode APORT4XCH13 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH14 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH15 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH15 << 16) /**< Shifted mode APORT4XCH15 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH16 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH17 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH17 << 16) /**< Shifted mode APORT4XCH17 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH18 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH19 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH19 << 16) /**< Shifted mode APORT4XCH19 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH20 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH21 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH21 << 16) /**< Shifted mode APORT4XCH21 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH22 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH23 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH23 << 16) /**< Shifted mode APORT4XCH23 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH24 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH25 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH25 << 16) /**< Shifted mode APORT4XCH25 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH26 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH27 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH27 << 16) /**< Shifted mode APORT4XCH27 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH28 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH29 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH29 << 16) /**< Shifted mode APORT4XCH29 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4YCH30 (_ADC_SINGLECTRL_NEGSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_APORT4XCH31 (_ADC_SINGLECTRL_NEGSEL_APORT4XCH31 << 16) /**< Shifted mode APORT4XCH31 for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_TESTN (_ADC_SINGLECTRL_NEGSEL_TESTN << 16) /**< Shifted mode TESTN for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_DEFAULT (_ADC_SINGLECTRL_NEGSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_NEGSEL_VSS (_ADC_SINGLECTRL_NEGSEL_VSS << 16) /**< Shifted mode VSS for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SINGLECTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SINGLECTRL */ +#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_3CYCLES (_ADC_SINGLECTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN (0x1UL << 29) /**< Single Channel PRS Trigger Enable */ +#define _ADC_SINGLECTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Single Channel */ +#define _ADC_SINGLECTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SINGLECTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_CMPEN_DEFAULT (_ADC_SINGLECTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */ + +/* Bit fields for ADC SINGLECTRLX */ +#define _ADC_SINGLECTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SINGLECTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VENTROPY 0x00000004UL /**< Mode VENTROPY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_DEFAULT (_ADC_SINGLECTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGR (_ADC_SINGLECTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VDDXWATT (_ADC_SINGLECTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFP (_ADC_SINGLECTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VENTROPY (_ADC_SINGLECTRLX_VREFSEL_VENTROPY << 0) /**< Shifted mode VENTROPY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPNWATT (_ADC_SINGLECTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VREFPN (_ADC_SINGLECTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFSEL_VBGRLOW (_ADC_SINGLECTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */ +#define _ADC_SINGLECTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SINGLECTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATTFIX_DEFAULT (_ADC_SINGLECTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SINGLECTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VREFATT_DEFAULT (_ADC_SINGLECTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SINGLECTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_VINATT_DEFAULT (_ADC_SINGLECTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SINGLECTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_DVL_DEFAULT (_ADC_SINGLECTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT (0x1UL << 14) /**< Single Channel FIFO Overflow Action */ +#define _ADC_SINGLECTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DEFAULT (_ADC_SINGLECTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_DISCARD (_ADC_SINGLECTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE (_ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE (0x1UL << 16) /**< Single Channel PRS Trigger Mode */ +#define _ADC_SINGLECTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SINGLECTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_DEFAULT (_ADC_SINGLECTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_PULSED (_ADC_SINGLECTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSMODE_TIMED (_ADC_SINGLECTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SINGLECTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_DEFAULT (_ADC_SINGLECTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH0 (_ADC_SINGLECTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH1 (_ADC_SINGLECTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH2 (_ADC_SINGLECTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH3 (_ADC_SINGLECTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH4 (_ADC_SINGLECTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH5 (_ADC_SINGLECTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH6 (_ADC_SINGLECTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH7 (_ADC_SINGLECTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH8 (_ADC_SINGLECTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH9 (_ADC_SINGLECTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH10 (_ADC_SINGLECTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_PRSSEL_PRSCH11 (_ADC_SINGLECTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SINGLECTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SINGLECTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SINGLECTRLX */ +#define _ADC_SINGLECTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_DEFAULT (_ADC_SINGLECTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_NODELAY (_ADC_SINGLECTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_4CYCLES (_ADC_SINGLECTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_8CYCLES (_ADC_SINGLECTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_16CYCLES (_ADC_SINGLECTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_32CYCLES (_ADC_SINGLECTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_64CYCLES (_ADC_SINGLECTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_128CYCLES (_ADC_SINGLECTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SINGLECTRLX */ +#define ADC_SINGLECTRLX_REPDELAY_256CYCLES (_ADC_SINGLECTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SINGLECTRLX */ + +/* Bit fields for ADC SCANCTRL */ +#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_MASK 0xAF0000FFUL /**< Mask for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */ +#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */ +#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */ +#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */ +#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */ +#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */ +#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */ +#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_SHIFT 3 /**< Shift value for ADC_RES */ +#define _ADC_SCANCTRL_RES_MASK 0x18UL /**< Bit mask for ADC_RES */ +#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 3) /**< Shifted mode 12BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 3) /**< Shifted mode 8BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 3) /**< Shifted mode 6BIT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 3) /**< Shifted mode OVS for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_SHIFT 5 /**< Shift value for ADC_REF */ +#define _ADC_SCANCTRL_REF_MASK 0xE0UL /**< Bit mask for ADC_REF */ +#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_5V 0x00000003UL /**< Mode 5V for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_REF_CONF 0x00000007UL /**< Mode CONF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 5) /**< Shifted mode 1V25 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 5) /**< Shifted mode 2V5 for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 5) /**< Shifted mode VDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_5V (_ADC_SCANCTRL_REF_5V << 5) /**< Shifted mode 5V for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 5) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 5) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 5) /**< Shifted mode 2XVDD for ADC_SCANCTRL */ +#define ADC_SCANCTRL_REF_CONF (_ADC_SCANCTRL_REF_CONF << 5) /**< Shifted mode CONF for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_SHIFT 24 /**< Shift value for ADC_AT */ +#define _ADC_SCANCTRL_AT_MASK 0xF000000UL /**< Bit mask for ADC_AT */ +#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_3CYCLES 0x00000002UL /**< Mode 3CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_4CYCLES 0x00000003UL /**< Mode 4CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_8CYCLES 0x00000004UL /**< Mode 8CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_16CYCLES 0x00000005UL /**< Mode 16CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_32CYCLES 0x00000006UL /**< Mode 32CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_64CYCLES 0x00000007UL /**< Mode 64CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_128CYCLES 0x00000008UL /**< Mode 128CYCLES for ADC_SCANCTRL */ +#define _ADC_SCANCTRL_AT_256CYCLES 0x00000009UL /**< Mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 24) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 24) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_3CYCLES (_ADC_SCANCTRL_AT_3CYCLES << 24) /**< Shifted mode 3CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 24) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 24) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 24) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 24) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 24) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 24) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 24) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN (0x1UL << 29) /**< Scan Sequence PRS Trigger Enable */ +#define _ADC_SCANCTRL_PRSEN_SHIFT 29 /**< Shift value for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_MASK 0x20000000UL /**< Bit mask for ADC_PRSEN */ +#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN (0x1UL << 31) /**< Compare Logic Enable for Scan */ +#define _ADC_SCANCTRL_CMPEN_SHIFT 31 /**< Shift value for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_MASK 0x80000000UL /**< Bit mask for ADC_CMPEN */ +#define _ADC_SCANCTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */ +#define ADC_SCANCTRL_CMPEN_DEFAULT (_ADC_SCANCTRL_CMPEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_SCANCTRL */ + +/* Bit fields for ADC SCANCTRLX */ +#define _ADC_SCANCTRLX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_MASK 0xEFDF7FFFUL /**< Mask for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_SHIFT 0 /**< Shift value for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_MASK 0x7UL /**< Bit mask for ADC_VREFSEL */ +#define _ADC_SCANCTRLX_VREFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGR 0x00000000UL /**< Mode VBGR for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VDDXWATT 0x00000001UL /**< Mode VDDXWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPWATT 0x00000002UL /**< Mode VREFPWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFP 0x00000003UL /**< Mode VREFP for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPNWATT 0x00000005UL /**< Mode VREFPNWATT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VREFPN 0x00000006UL /**< Mode VREFPN for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFSEL_VBGRLOW 0x00000007UL /**< Mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_DEFAULT (_ADC_SCANCTRLX_VREFSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGR (_ADC_SCANCTRLX_VREFSEL_VBGR << 0) /**< Shifted mode VBGR for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VDDXWATT (_ADC_SCANCTRLX_VREFSEL_VDDXWATT << 0) /**< Shifted mode VDDXWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPWATT (_ADC_SCANCTRLX_VREFSEL_VREFPWATT << 0) /**< Shifted mode VREFPWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFP (_ADC_SCANCTRLX_VREFSEL_VREFP << 0) /**< Shifted mode VREFP for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPNWATT (_ADC_SCANCTRLX_VREFSEL_VREFPNWATT << 0) /**< Shifted mode VREFPNWATT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VREFPN (_ADC_SCANCTRLX_VREFSEL_VREFPN << 0) /**< Shifted mode VREFPN for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFSEL_VBGRLOW (_ADC_SCANCTRLX_VREFSEL_VBGRLOW << 0) /**< Shifted mode VBGRLOW for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX (0x1UL << 3) /**< Enable fixed scaling on VREF */ +#define _ADC_SCANCTRLX_VREFATTFIX_SHIFT 3 /**< Shift value for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_MASK 0x8UL /**< Bit mask for ADC_VREFATTFIX */ +#define _ADC_SCANCTRLX_VREFATTFIX_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATTFIX_DEFAULT (_ADC_SCANCTRLX_VREFATTFIX_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VREFATT_SHIFT 4 /**< Shift value for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_MASK 0xF0UL /**< Bit mask for ADC_VREFATT */ +#define _ADC_SCANCTRLX_VREFATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VREFATT_DEFAULT (_ADC_SCANCTRLX_VREFATT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_VINATT_SHIFT 8 /**< Shift value for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_MASK 0xF00UL /**< Bit mask for ADC_VINATT */ +#define _ADC_SCANCTRLX_VINATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_VINATT_DEFAULT (_ADC_SCANCTRLX_VINATT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_DVL_SHIFT 12 /**< Shift value for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_MASK 0x3000UL /**< Bit mask for ADC_DVL */ +#define _ADC_SCANCTRLX_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_DVL_DEFAULT (_ADC_SCANCTRLX_DVL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT (0x1UL << 14) /**< Scan FIFO Overflow Action */ +#define _ADC_SCANCTRLX_FIFOOFACT_SHIFT 14 /**< Shift value for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_MASK 0x4000UL /**< Bit mask for ADC_FIFOOFACT */ +#define _ADC_SCANCTRLX_FIFOOFACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_DISCARD 0x00000000UL /**< Mode DISCARD for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_FIFOOFACT_OVERWRITE 0x00000001UL /**< Mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DEFAULT (_ADC_SCANCTRLX_FIFOOFACT_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_DISCARD (_ADC_SCANCTRLX_FIFOOFACT_DISCARD << 14) /**< Shifted mode DISCARD for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_FIFOOFACT_OVERWRITE (_ADC_SCANCTRLX_FIFOOFACT_OVERWRITE << 14) /**< Shifted mode OVERWRITE for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE (0x1UL << 16) /**< Scan PRS Trigger Mode */ +#define _ADC_SCANCTRLX_PRSMODE_SHIFT 16 /**< Shift value for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_MASK 0x10000UL /**< Bit mask for ADC_PRSMODE */ +#define _ADC_SCANCTRLX_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_DEFAULT (_ADC_SCANCTRLX_PRSMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_PULSED (_ADC_SCANCTRLX_PRSMODE_PULSED << 16) /**< Shifted mode PULSED for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSMODE_TIMED (_ADC_SCANCTRLX_PRSMODE_TIMED << 16) /**< Shifted mode TIMED for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_SHIFT 17 /**< Shift value for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_MASK 0x1E0000UL /**< Bit mask for ADC_PRSSEL */ +#define _ADC_SCANCTRLX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_DEFAULT (_ADC_SCANCTRLX_PRSSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH0 (_ADC_SCANCTRLX_PRSSEL_PRSCH0 << 17) /**< Shifted mode PRSCH0 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH1 (_ADC_SCANCTRLX_PRSSEL_PRSCH1 << 17) /**< Shifted mode PRSCH1 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH2 (_ADC_SCANCTRLX_PRSSEL_PRSCH2 << 17) /**< Shifted mode PRSCH2 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH3 (_ADC_SCANCTRLX_PRSSEL_PRSCH3 << 17) /**< Shifted mode PRSCH3 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH4 (_ADC_SCANCTRLX_PRSSEL_PRSCH4 << 17) /**< Shifted mode PRSCH4 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH5 (_ADC_SCANCTRLX_PRSSEL_PRSCH5 << 17) /**< Shifted mode PRSCH5 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH6 (_ADC_SCANCTRLX_PRSSEL_PRSCH6 << 17) /**< Shifted mode PRSCH6 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH7 (_ADC_SCANCTRLX_PRSSEL_PRSCH7 << 17) /**< Shifted mode PRSCH7 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH8 (_ADC_SCANCTRLX_PRSSEL_PRSCH8 << 17) /**< Shifted mode PRSCH8 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH9 (_ADC_SCANCTRLX_PRSSEL_PRSCH9 << 17) /**< Shifted mode PRSCH9 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH10 (_ADC_SCANCTRLX_PRSSEL_PRSCH10 << 17) /**< Shifted mode PRSCH10 for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_PRSSEL_PRSCH11 (_ADC_SCANCTRLX_PRSSEL_PRSCH11 << 17) /**< Shifted mode PRSCH11 for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_SHIFT 22 /**< Shift value for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_MASK 0x7C00000UL /**< Bit mask for ADC_CONVSTARTDELAY */ +#define _ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAY_DEFAULT << 22) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN (0x1UL << 27) /**< Enable delaying next conversion start */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_SHIFT 27 /**< Shift value for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_MASK 0x8000000UL /**< Bit mask for ADC_CONVSTARTDELAYEN */ +#define _ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT (_ADC_SCANCTRLX_CONVSTARTDELAYEN_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_SHIFT 29 /**< Shift value for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_MASK 0xE0000000UL /**< Bit mask for ADC_REPDELAY */ +#define _ADC_SCANCTRLX_REPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_NODELAY 0x00000000UL /**< Mode NODELAY for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_4CYCLES 0x00000001UL /**< Mode 4CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_8CYCLES 0x00000002UL /**< Mode 8CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_16CYCLES 0x00000003UL /**< Mode 16CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_32CYCLES 0x00000004UL /**< Mode 32CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_64CYCLES 0x00000005UL /**< Mode 64CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_128CYCLES 0x00000006UL /**< Mode 128CYCLES for ADC_SCANCTRLX */ +#define _ADC_SCANCTRLX_REPDELAY_256CYCLES 0x00000007UL /**< Mode 256CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_DEFAULT (_ADC_SCANCTRLX_REPDELAY_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_NODELAY (_ADC_SCANCTRLX_REPDELAY_NODELAY << 29) /**< Shifted mode NODELAY for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_4CYCLES (_ADC_SCANCTRLX_REPDELAY_4CYCLES << 29) /**< Shifted mode 4CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_8CYCLES (_ADC_SCANCTRLX_REPDELAY_8CYCLES << 29) /**< Shifted mode 8CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_16CYCLES (_ADC_SCANCTRLX_REPDELAY_16CYCLES << 29) /**< Shifted mode 16CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_32CYCLES (_ADC_SCANCTRLX_REPDELAY_32CYCLES << 29) /**< Shifted mode 32CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_64CYCLES (_ADC_SCANCTRLX_REPDELAY_64CYCLES << 29) /**< Shifted mode 64CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_128CYCLES (_ADC_SCANCTRLX_REPDELAY_128CYCLES << 29) /**< Shifted mode 128CYCLES for ADC_SCANCTRLX */ +#define ADC_SCANCTRLX_REPDELAY_256CYCLES (_ADC_SCANCTRLX_REPDELAY_256CYCLES << 29) /**< Shifted mode 256CYCLES for ADC_SCANCTRLX */ + +/* Bit fields for ADC SCANMASK */ +#define _ADC_SCANMASK_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANMASK */ +#define _ADC_SCANMASK_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_SHIFT 0 /**< Shift value for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_SCANINPUTEN */ +#define _ADC_SCANMASK_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL 0x00000001UL /**< Mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT0 0x00000001UL /**< Mode INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1 0x00000002UL /**< Mode INPUT1 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 0x00000002UL /**< Mode INPUT1INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2 0x00000004UL /**< Mode INPUT2 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL 0x00000004UL /**< Mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3 0x00000008UL /**< Mode INPUT3 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 0x00000008UL /**< Mode INPUT3INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4 0x00000010UL /**< Mode INPUT4 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL 0x00000010UL /**< Mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 0x00000020UL /**< Mode INPUT5INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT5 0x00000020UL /**< Mode INPUT5 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL 0x00000040UL /**< Mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT6 0x00000040UL /**< Mode INPUT6 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7 0x00000080UL /**< Mode INPUT7 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 0x00000080UL /**< Mode INPUT7INPUT0 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 0x00000100UL /**< Mode INPUT8INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT8 0x00000100UL /**< Mode INPUT8 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9 0x00000200UL /**< Mode INPUT9 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL 0x00000200UL /**< Mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 0x00000400UL /**< Mode INPUT10INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT10 0x00000400UL /**< Mode INPUT10 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL 0x00000800UL /**< Mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT11 0x00000800UL /**< Mode INPUT11 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 0x00001000UL /**< Mode INPUT12INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT12 0x00001000UL /**< Mode INPUT12 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL 0x00002000UL /**< Mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT13 0x00002000UL /**< Mode INPUT13 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 0x00004000UL /**< Mode INPUT14INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT14 0x00004000UL /**< Mode INPUT14 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL 0x00008000UL /**< Mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT15 0x00008000UL /**< Mode INPUT15 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 0x00010000UL /**< Mode INPUT16INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT16 0x00010000UL /**< Mode INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 0x00020000UL /**< Mode INPUT17INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT17 0x00020000UL /**< Mode INPUT17 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 0x00040000UL /**< Mode INPUT18INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT18 0x00040000UL /**< Mode INPUT18 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19 0x00080000UL /**< Mode INPUT19 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 0x00080000UL /**< Mode INPUT19INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 0x00100000UL /**< Mode INPUT20INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT20 0x00100000UL /**< Mode INPUT20 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21 0x00200000UL /**< Mode INPUT21 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 0x00200000UL /**< Mode INPUT21INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 0x00400000UL /**< Mode INPUT22INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT22 0x00400000UL /**< Mode INPUT22 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 0x00800000UL /**< Mode INPUT23INPUT16 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT23 0x00800000UL /**< Mode INPUT23 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24 0x01000000UL /**< Mode INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 0x01000000UL /**< Mode INPUT24INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 0x02000000UL /**< Mode INPUT25INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT25 0x02000000UL /**< Mode INPUT25 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26 0x04000000UL /**< Mode INPUT26 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 0x04000000UL /**< Mode INPUT26INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 0x08000000UL /**< Mode INPUT27INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT27 0x08000000UL /**< Mode INPUT27 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 0x10000000UL /**< Mode INPUT28INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT28 0x10000000UL /**< Mode INPUT28 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29 0x20000000UL /**< Mode INPUT29 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 0x20000000UL /**< Mode INPUT29INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30 0x40000000UL /**< Mode INPUT30 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 0x40000000UL /**< Mode INPUT30INPUT31 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 0x80000000UL /**< Mode INPUT31INPUT24 for ADC_SCANMASK */ +#define _ADC_SCANMASK_SCANINPUTEN_INPUT31 0x80000000UL /**< Mode INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_DEFAULT (_ADC_SCANMASK_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT0INPUT0NEGSEL << 0) /**< Shifted mode INPUT0INPUT0NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT0 << 0) /**< Shifted mode INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1 (_ADC_SCANMASK_SCANINPUTEN_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT1INPUT2 << 0) /**< Shifted mode INPUT1INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2 (_ADC_SCANMASK_SCANINPUTEN_INPUT2 << 0) /**< Shifted mode INPUT2 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT2INPUT2NEGSEL << 0) /**< Shifted mode INPUT2INPUT2NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3 (_ADC_SCANMASK_SCANINPUTEN_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT3INPUT4 << 0) /**< Shifted mode INPUT3INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4 (_ADC_SCANMASK_SCANINPUTEN_INPUT4 << 0) /**< Shifted mode INPUT4 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT4INPUT4NEGSEL << 0) /**< Shifted mode INPUT4INPUT4NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT5INPUT6 << 0) /**< Shifted mode INPUT5INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT5 (_ADC_SCANMASK_SCANINPUTEN_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT6INPUT6NEGSEL << 0) /**< Shifted mode INPUT6INPUT6NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT6 (_ADC_SCANMASK_SCANINPUTEN_INPUT6 << 0) /**< Shifted mode INPUT6 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7 (_ADC_SCANMASK_SCANINPUTEN_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 (_ADC_SCANMASK_SCANINPUTEN_INPUT7INPUT0 << 0) /**< Shifted mode INPUT7INPUT0 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT8INPUT9 << 0) /**< Shifted mode INPUT8INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT8 (_ADC_SCANMASK_SCANINPUTEN_INPUT8 << 0) /**< Shifted mode INPUT8 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9 (_ADC_SCANMASK_SCANINPUTEN_INPUT9 << 0) /**< Shifted mode INPUT9 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT9INPUT9NEGSEL << 0) /**< Shifted mode INPUT9INPUT9NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT10INPUT11 << 0) /**< Shifted mode INPUT10INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT10 (_ADC_SCANMASK_SCANINPUTEN_INPUT10 << 0) /**< Shifted mode INPUT10 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT11INPUT11NEGSEL << 0) /**< Shifted mode INPUT11INPUT11NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT11 (_ADC_SCANMASK_SCANINPUTEN_INPUT11 << 0) /**< Shifted mode INPUT11 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT12INPUT13 << 0) /**< Shifted mode INPUT12INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT12 (_ADC_SCANMASK_SCANINPUTEN_INPUT12 << 0) /**< Shifted mode INPUT12 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT13INPUT13NEGSEL << 0) /**< Shifted mode INPUT13INPUT13NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT13 (_ADC_SCANMASK_SCANINPUTEN_INPUT13 << 0) /**< Shifted mode INPUT13 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT14INPUT15 << 0) /**< Shifted mode INPUT14INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT14 (_ADC_SCANMASK_SCANINPUTEN_INPUT14 << 0) /**< Shifted mode INPUT14 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL (_ADC_SCANMASK_SCANINPUTEN_INPUT15INPUT15NEGSEL << 0) /**< Shifted mode INPUT15INPUT15NEGSEL for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT15 (_ADC_SCANMASK_SCANINPUTEN_INPUT15 << 0) /**< Shifted mode INPUT15 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT16INPUT17 << 0) /**< Shifted mode INPUT16INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT16 << 0) /**< Shifted mode INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT17INPUT18 << 0) /**< Shifted mode INPUT17INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT17 (_ADC_SCANMASK_SCANINPUTEN_INPUT17 << 0) /**< Shifted mode INPUT17 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT18INPUT19 << 0) /**< Shifted mode INPUT18INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT18 (_ADC_SCANMASK_SCANINPUTEN_INPUT18 << 0) /**< Shifted mode INPUT18 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19 (_ADC_SCANMASK_SCANINPUTEN_INPUT19 << 0) /**< Shifted mode INPUT19 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT19INPUT20 << 0) /**< Shifted mode INPUT19INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT20INPUT21 << 0) /**< Shifted mode INPUT20INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT20 (_ADC_SCANMASK_SCANINPUTEN_INPUT20 << 0) /**< Shifted mode INPUT20 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21 (_ADC_SCANMASK_SCANINPUTEN_INPUT21 << 0) /**< Shifted mode INPUT21 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT21INPUT22 << 0) /**< Shifted mode INPUT21INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT22INPUT23 << 0) /**< Shifted mode INPUT22INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT22 (_ADC_SCANMASK_SCANINPUTEN_INPUT22 << 0) /**< Shifted mode INPUT22 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 (_ADC_SCANMASK_SCANINPUTEN_INPUT23INPUT16 << 0) /**< Shifted mode INPUT23INPUT16 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT23 (_ADC_SCANMASK_SCANINPUTEN_INPUT23 << 0) /**< Shifted mode INPUT23 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT24 << 0) /**< Shifted mode INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT24INPUT25 << 0) /**< Shifted mode INPUT24INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT25INPUT26 << 0) /**< Shifted mode INPUT25INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT25 (_ADC_SCANMASK_SCANINPUTEN_INPUT25 << 0) /**< Shifted mode INPUT25 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26 (_ADC_SCANMASK_SCANINPUTEN_INPUT26 << 0) /**< Shifted mode INPUT26 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT26INPUT27 << 0) /**< Shifted mode INPUT26INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT27INPUT28 << 0) /**< Shifted mode INPUT27INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT27 (_ADC_SCANMASK_SCANINPUTEN_INPUT27 << 0) /**< Shifted mode INPUT27 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT28INPUT29 << 0) /**< Shifted mode INPUT28INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT28 (_ADC_SCANMASK_SCANINPUTEN_INPUT28 << 0) /**< Shifted mode INPUT28 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29 (_ADC_SCANMASK_SCANINPUTEN_INPUT29 << 0) /**< Shifted mode INPUT29 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT29INPUT30 << 0) /**< Shifted mode INPUT29INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30 (_ADC_SCANMASK_SCANINPUTEN_INPUT30 << 0) /**< Shifted mode INPUT30 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT30INPUT31 << 0) /**< Shifted mode INPUT30INPUT31 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 (_ADC_SCANMASK_SCANINPUTEN_INPUT31INPUT24 << 0) /**< Shifted mode INPUT31INPUT24 for ADC_SCANMASK */ +#define ADC_SCANMASK_SCANINPUTEN_INPUT31 (_ADC_SCANMASK_SCANINPUTEN_INPUT31 << 0) /**< Shifted mode INPUT31 for ADC_SCANMASK */ + +/* Bit fields for ADC SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_MASK 0x1F1F1F1FUL /**< Mask for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_SHIFT 0 /**< Shift value for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_MASK 0x1FUL /**< Bit mask for ADC_INPUT0TO7SEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH0TO7 << 0) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT0CH8TO15 << 0) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH0TO7 << 0) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH8TO15 << 0) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH16TO23 << 0) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT2CH24TO31 << 0) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH0TO7 << 0) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH8TO15 << 0) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH16TO23 << 0) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT0TO7SEL_APORT4CH24TO31 << 0) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_SHIFT 8 /**< Shift value for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_MASK 0x1F00UL /**< Bit mask for ADC_INPUT8TO15SEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH0TO7 << 8) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT0CH8TO15 << 8) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH0TO7 << 8) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH8TO15 << 8) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH16TO23 << 8) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT2CH24TO31 << 8) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH0TO7 << 8) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH8TO15 << 8) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH16TO23 << 8) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT8TO15SEL_APORT4CH24TO31 << 8) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_SHIFT 16 /**< Shift value for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_MASK 0x1F0000UL /**< Bit mask for ADC_INPUT16TO23SEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH0TO7 << 16) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT0CH8TO15 << 16) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH0TO7 << 16) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH8TO15 << 16) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH16TO23 << 16) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT2CH24TO31 << 16) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH0TO7 << 16) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH8TO15 << 16) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH16TO23 << 16) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT16TO23SEL_APORT4CH24TO31 << 16) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_SHIFT 24 /**< Shift value for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_MASK 0x1F000000UL /**< Bit mask for ADC_INPUT24TO31SEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 0x00000000UL /**< Mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 0x00000001UL /**< Mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 0x00000008UL /**< Mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 0x00000009UL /**< Mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 0x0000000AUL /**< Mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 0x0000000BUL /**< Mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 0x00000010UL /**< Mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 0x00000011UL /**< Mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 0x00000012UL /**< Mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define _ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 0x00000013UL /**< Mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT (_ADC_SCANINPUTSEL_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH0TO7 << 24) /**< Shifted mode APORT0CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT0CH8TO15 << 24) /**< Shifted mode APORT0CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH0TO7 << 24) /**< Shifted mode APORT2CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH8TO15 << 24) /**< Shifted mode APORT2CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH16TO23 << 24) /**< Shifted mode APORT2CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT2CH24TO31 << 24) /**< Shifted mode APORT2CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH0TO7 << 24) /**< Shifted mode APORT4CH0TO7 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH8TO15 << 24) /**< Shifted mode APORT4CH8TO15 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH16TO23 << 24) /**< Shifted mode APORT4CH16TO23 for ADC_SCANINPUTSEL */ +#define ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 (_ADC_SCANINPUTSEL_INPUT24TO31SEL_APORT4CH24TO31 << 24) /**< Shifted mode APORT4CH24TO31 for ADC_SCANINPUTSEL */ + +/* Bit fields for ADC SCANNEGSEL */ +#define _ADC_SCANNEGSEL_RESETVALUE 0x000039E4UL /**< Default value for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_MASK 0x0000FFFFUL /**< Mask for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT 0 /**< Shift value for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK 0x3UL /**< Bit mask for ADC_INPUT0NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT0NEGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1 << 0) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3 << 0) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5 << 0) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7 << 0) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT 2 /**< Shift value for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK 0xCUL /**< Bit mask for ADC_INPUT2NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT1 << 2) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT2NEGSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT3 << 2) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT5 << 2) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT2NEGSEL_INPUT7 << 2) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT 4 /**< Shift value for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK 0x30UL /**< Bit mask for ADC_INPUT4NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT1 << 4) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT3 << 4) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT4NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT5 << 4) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT4NEGSEL_INPUT7 << 4) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT 6 /**< Shift value for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK 0xC0UL /**< Bit mask for ADC_INPUT6NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 0x00000000UL /**< Mode INPUT1 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 0x00000001UL /**< Mode INPUT3 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 0x00000002UL /**< Mode INPUT5 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 0x00000003UL /**< Mode INPUT7 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT1 << 6) /**< Shifted mode INPUT1 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT3 << 6) /**< Shifted mode INPUT3 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT5 << 6) /**< Shifted mode INPUT5 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT6NEGSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 (_ADC_SCANNEGSEL_INPUT6NEGSEL_INPUT7 << 6) /**< Shifted mode INPUT7 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT 8 /**< Shift value for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK 0x300UL /**< Bit mask for ADC_INPUT9NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8 << 8) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT9NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10 << 8) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12 << 8) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14 << 8) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT 10 /**< Shift value for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK 0xC00UL /**< Bit mask for ADC_INPUT11NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT8 << 10) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT10 << 10) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT11NEGSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT12 << 10) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT11NEGSEL_INPUT14 << 10) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT 12 /**< Shift value for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK 0x3000UL /**< Bit mask for ADC_INPUT13NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT8 << 12) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT10 << 12) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT12 << 12) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT13NEGSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT13NEGSEL_INPUT14 << 12) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT 14 /**< Shift value for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK 0xC000UL /**< Bit mask for ADC_INPUT15NEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 0x00000000UL /**< Mode INPUT8 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 0x00000001UL /**< Mode INPUT10 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 0x00000002UL /**< Mode INPUT12 for ADC_SCANNEGSEL */ +#define _ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 0x00000003UL /**< Mode INPUT14 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT (_ADC_SCANNEGSEL_INPUT15NEGSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT8 << 14) /**< Shifted mode INPUT8 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT10 << 14) /**< Shifted mode INPUT10 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT12 << 14) /**< Shifted mode INPUT12 for ADC_SCANNEGSEL */ +#define ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 (_ADC_SCANNEGSEL_INPUT15NEGSEL_INPUT14 << 14) /**< Shifted mode INPUT14 for ADC_SCANNEGSEL */ + +/* Bit fields for ADC CMPTHR */ +#define _ADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for ADC_CMPTHR */ +#define _ADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for ADC_ADLT */ +#define _ADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADLT_DEFAULT (_ADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMPTHR */ +#define _ADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for ADC_ADGT */ +#define _ADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMPTHR */ +#define ADC_CMPTHR_ADGT_DEFAULT (_ADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CMPTHR */ + +/* Bit fields for ADC BIASPROG */ +#define _ADC_BIASPROG_RESETVALUE 0x00000000UL /**< Default value for ADC_BIASPROG */ +#define _ADC_BIASPROG_MASK 0x0001100FUL /**< Mask for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SHIFT 0 /**< Shift value for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_MASK 0xFUL /**< Bit mask for ADC_ADCBIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE2 0x00000004UL /**< Mode SCALE2 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE4 0x00000008UL /**< Mode SCALE4 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE8 0x0000000CUL /**< Mode SCALE8 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE16 0x0000000EUL /**< Mode SCALE16 for ADC_BIASPROG */ +#define _ADC_BIASPROG_ADCBIASPROG_SCALE32 0x0000000FUL /**< Mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_DEFAULT (_ADC_BIASPROG_ADCBIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_NORMAL (_ADC_BIASPROG_ADCBIASPROG_NORMAL << 0) /**< Shifted mode NORMAL for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE2 (_ADC_BIASPROG_ADCBIASPROG_SCALE2 << 0) /**< Shifted mode SCALE2 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE4 (_ADC_BIASPROG_ADCBIASPROG_SCALE4 << 0) /**< Shifted mode SCALE4 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE8 (_ADC_BIASPROG_ADCBIASPROG_SCALE8 << 0) /**< Shifted mode SCALE8 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE16 (_ADC_BIASPROG_ADCBIASPROG_SCALE16 << 0) /**< Shifted mode SCALE16 for ADC_BIASPROG */ +#define ADC_BIASPROG_ADCBIASPROG_SCALE32 (_ADC_BIASPROG_ADCBIASPROG_SCALE32 << 0) /**< Shifted mode SCALE32 for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR (0x1UL << 12) /**< Clear VREFOF flag */ +#define _ADC_BIASPROG_VFAULTCLR_SHIFT 12 /**< Shift value for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_MASK 0x1000UL /**< Bit mask for ADC_VFAULTCLR */ +#define _ADC_BIASPROG_VFAULTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_VFAULTCLR_DEFAULT (_ADC_BIASPROG_VFAULTCLR_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC (0x1UL << 16) /**< Accuracy setting for the system bias during ADC operation */ +#define _ADC_BIASPROG_GPBIASACC_SHIFT 16 /**< Shift value for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_MASK 0x10000UL /**< Bit mask for ADC_GPBIASACC */ +#define _ADC_BIASPROG_GPBIASACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_HIGHACC 0x00000000UL /**< Mode HIGHACC for ADC_BIASPROG */ +#define _ADC_BIASPROG_GPBIASACC_LOWACC 0x00000001UL /**< Mode LOWACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_DEFAULT (_ADC_BIASPROG_GPBIASACC_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_HIGHACC (_ADC_BIASPROG_GPBIASACC_HIGHACC << 16) /**< Shifted mode HIGHACC for ADC_BIASPROG */ +#define ADC_BIASPROG_GPBIASACC_LOWACC (_ADC_BIASPROG_GPBIASACC_LOWACC << 16) /**< Shifted mode LOWACC for ADC_BIASPROG */ + +/* Bit fields for ADC CAL */ +#define _ADC_CAL_RESETVALUE 0x40784078UL /**< Default value for ADC_CAL */ +#define _ADC_CAL_MASK 0xFFFFFFFFUL /**< Mask for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_MASK 0xFUL /**< Bit mask for ADC_SINGLEOFFSET */ +#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEOFFSETINV_SHIFT 4 /**< Shift value for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_MASK 0xF0UL /**< Bit mask for ADC_SINGLEOFFSETINV */ +#define _ADC_CAL_SINGLEOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEOFFSETINV_DEFAULT (_ADC_CAL_SINGLEOFFSETINV_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */ +#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE (0x1UL << 15) /**< Negative single-ended offset calibration is enabled */ +#define _ADC_CAL_OFFSETINVMODE_SHIFT 15 /**< Shift value for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_MASK 0x8000UL /**< Bit mask for ADC_OFFSETINVMODE */ +#define _ADC_CAL_OFFSETINVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_OFFSETINVMODE_DEFAULT (_ADC_CAL_OFFSETINVMODE_DEFAULT << 15) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_MASK 0xF0000UL /**< Bit mask for ADC_SCANOFFSET */ +#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000008UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANOFFSETINV_SHIFT 20 /**< Shift value for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_MASK 0xF00000UL /**< Bit mask for ADC_SCANOFFSETINV */ +#define _ADC_CAL_SCANOFFSETINV_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANOFFSETINV_DEFAULT (_ADC_CAL_SCANOFFSETINV_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_CAL */ +#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */ +#define _ADC_CAL_SCANGAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN (0x1UL << 31) /**< Calibration mode is enabled */ +#define _ADC_CAL_CALEN_SHIFT 31 /**< Shift value for ADC_CALEN */ +#define _ADC_CAL_CALEN_MASK 0x80000000UL /**< Bit mask for ADC_CALEN */ +#define _ADC_CAL_CALEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */ +#define ADC_CAL_CALEN_DEFAULT (_ADC_CAL_CALEN_DEFAULT << 31) /**< Shifted mode DEFAULT for ADC_CAL */ + +/* Bit fields for ADC IF */ +#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */ +#define _ADC_IF_MASK 0x3F030F03UL /**< Mask for ADC_IF */ +#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */ +#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */ +#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan FIFO Overflow Interrupt Flag */ +#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF (0x1UL << 10) /**< Single FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IF_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLEUF_DEFAULT (_ADC_IF_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF (0x1UL << 11) /**< Scan FIFO Underflow Interrupt Flag */ +#define _ADC_IF_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IF_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IF_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANUF_DEFAULT (_ADC_IF_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP (0x1UL << 16) /**< Single Result Compare Match Interrupt Flag */ +#define _ADC_IF_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SINGLECMP_DEFAULT (_ADC_IF_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP (0x1UL << 17) /**< Scan Result Compare Match Interrupt Flag */ +#define _ADC_IF_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANCMP_DEFAULT (_ADC_IF_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV (0x1UL << 24) /**< VREF Over Voltage Interrupt Flag */ +#define _ADC_IF_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IF_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IF_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_VREFOV_DEFAULT (_ADC_IF_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR (0x1UL << 25) /**< Programming Error Interrupt Flag */ +#define _ADC_IF_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IF_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IF_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PROGERR_DEFAULT (_ADC_IF_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND (0x1UL << 26) /**< External Scan Trigger Pending Flag */ +#define _ADC_IF_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IF_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANEXTPEND_DEFAULT (_ADC_IF_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND (0x1UL << 27) /**< Scan Trigger Pending Flag */ +#define _ADC_IF_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IF_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_SCANPEND_DEFAULT (_ADC_IF_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR (0x1UL << 28) /**< PRS Timed Mode Error Flag */ +#define _ADC_IF_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IF_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_PRSTIMEDERR_DEFAULT (_ADC_IF_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR (0x1UL << 29) /**< EM23 Entry Error Flag */ +#define _ADC_IF_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */ +#define ADC_IF_EM23ERR_DEFAULT (_ADC_IF_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IF */ + +/* Bit fields for ADC IFS */ +#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */ +#define _ADC_IFS_MASK 0x3F030F00UL /**< Mask for ADC_IFS */ +#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Set SINGLEOF Interrupt Flag */ +#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF (0x1UL << 9) /**< Set SCANOF Interrupt Flag */ +#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF (0x1UL << 10) /**< Set SINGLEUF Interrupt Flag */ +#define _ADC_IFS_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFS_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLEUF_DEFAULT (_ADC_IFS_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF (0x1UL << 11) /**< Set SCANUF Interrupt Flag */ +#define _ADC_IFS_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFS_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANUF_DEFAULT (_ADC_IFS_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP (0x1UL << 16) /**< Set SINGLECMP Interrupt Flag */ +#define _ADC_IFS_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFS_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SINGLECMP_DEFAULT (_ADC_IFS_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP (0x1UL << 17) /**< Set SCANCMP Interrupt Flag */ +#define _ADC_IFS_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFS_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANCMP_DEFAULT (_ADC_IFS_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV (0x1UL << 24) /**< Set VREFOV Interrupt Flag */ +#define _ADC_IFS_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFS_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_VREFOV_DEFAULT (_ADC_IFS_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR (0x1UL << 25) /**< Set PROGERR Interrupt Flag */ +#define _ADC_IFS_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFS_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PROGERR_DEFAULT (_ADC_IFS_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND (0x1UL << 26) /**< Set SCANEXTPEND Interrupt Flag */ +#define _ADC_IFS_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFS_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANEXTPEND_DEFAULT (_ADC_IFS_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND (0x1UL << 27) /**< Set SCANPEND Interrupt Flag */ +#define _ADC_IFS_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFS_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_SCANPEND_DEFAULT (_ADC_IFS_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR (0x1UL << 28) /**< Set PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFS_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFS_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_PRSTIMEDERR_DEFAULT (_ADC_IFS_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR (0x1UL << 29) /**< Set EM23ERR Interrupt Flag */ +#define _ADC_IFS_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */ +#define ADC_IFS_EM23ERR_DEFAULT (_ADC_IFS_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFS */ + +/* Bit fields for ADC IFC */ +#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */ +#define _ADC_IFC_MASK 0x3F030F00UL /**< Mask for ADC_IFC */ +#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Clear SINGLEOF Interrupt Flag */ +#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF (0x1UL << 9) /**< Clear SCANOF Interrupt Flag */ +#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF (0x1UL << 10) /**< Clear SINGLEUF Interrupt Flag */ +#define _ADC_IFC_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IFC_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLEUF_DEFAULT (_ADC_IFC_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF (0x1UL << 11) /**< Clear SCANUF Interrupt Flag */ +#define _ADC_IFC_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IFC_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANUF_DEFAULT (_ADC_IFC_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP (0x1UL << 16) /**< Clear SINGLECMP Interrupt Flag */ +#define _ADC_IFC_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IFC_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SINGLECMP_DEFAULT (_ADC_IFC_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP (0x1UL << 17) /**< Clear SCANCMP Interrupt Flag */ +#define _ADC_IFC_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IFC_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANCMP_DEFAULT (_ADC_IFC_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV (0x1UL << 24) /**< Clear VREFOV Interrupt Flag */ +#define _ADC_IFC_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IFC_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_VREFOV_DEFAULT (_ADC_IFC_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR (0x1UL << 25) /**< Clear PROGERR Interrupt Flag */ +#define _ADC_IFC_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IFC_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PROGERR_DEFAULT (_ADC_IFC_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND (0x1UL << 26) /**< Clear SCANEXTPEND Interrupt Flag */ +#define _ADC_IFC_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IFC_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANEXTPEND_DEFAULT (_ADC_IFC_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND (0x1UL << 27) /**< Clear SCANPEND Interrupt Flag */ +#define _ADC_IFC_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IFC_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_SCANPEND_DEFAULT (_ADC_IFC_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR (0x1UL << 28) /**< Clear PRSTIMEDERR Interrupt Flag */ +#define _ADC_IFC_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IFC_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_PRSTIMEDERR_DEFAULT (_ADC_IFC_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR (0x1UL << 29) /**< Clear EM23ERR Interrupt Flag */ +#define _ADC_IFC_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */ +#define ADC_IFC_EM23ERR_DEFAULT (_ADC_IFC_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IFC */ + +/* Bit fields for ADC IEN */ +#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */ +#define _ADC_IEN_MASK 0x3F030F03UL /**< Mask for ADC_IEN */ +#define ADC_IEN_SINGLE (0x1UL << 0) /**< SINGLE Interrupt Enable */ +#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */ +#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN (0x1UL << 1) /**< SCAN Interrupt Enable */ +#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */ +#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */ +#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< SINGLEOF Interrupt Enable */ +#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */ +#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF (0x1UL << 9) /**< SCANOF Interrupt Enable */ +#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */ +#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF (0x1UL << 10) /**< SINGLEUF Interrupt Enable */ +#define _ADC_IEN_SINGLEUF_SHIFT 10 /**< Shift value for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_MASK 0x400UL /**< Bit mask for ADC_SINGLEUF */ +#define _ADC_IEN_SINGLEUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLEUF_DEFAULT (_ADC_IEN_SINGLEUF_DEFAULT << 10) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF (0x1UL << 11) /**< SCANUF Interrupt Enable */ +#define _ADC_IEN_SCANUF_SHIFT 11 /**< Shift value for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_MASK 0x800UL /**< Bit mask for ADC_SCANUF */ +#define _ADC_IEN_SCANUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANUF_DEFAULT (_ADC_IEN_SCANUF_DEFAULT << 11) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP (0x1UL << 16) /**< SINGLECMP Interrupt Enable */ +#define _ADC_IEN_SINGLECMP_SHIFT 16 /**< Shift value for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_MASK 0x10000UL /**< Bit mask for ADC_SINGLECMP */ +#define _ADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SINGLECMP_DEFAULT (_ADC_IEN_SINGLECMP_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP (0x1UL << 17) /**< SCANCMP Interrupt Enable */ +#define _ADC_IEN_SCANCMP_SHIFT 17 /**< Shift value for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_MASK 0x20000UL /**< Bit mask for ADC_SCANCMP */ +#define _ADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANCMP_DEFAULT (_ADC_IEN_SCANCMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV (0x1UL << 24) /**< VREFOV Interrupt Enable */ +#define _ADC_IEN_VREFOV_SHIFT 24 /**< Shift value for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_MASK 0x1000000UL /**< Bit mask for ADC_VREFOV */ +#define _ADC_IEN_VREFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_VREFOV_DEFAULT (_ADC_IEN_VREFOV_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR (0x1UL << 25) /**< PROGERR Interrupt Enable */ +#define _ADC_IEN_PROGERR_SHIFT 25 /**< Shift value for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_MASK 0x2000000UL /**< Bit mask for ADC_PROGERR */ +#define _ADC_IEN_PROGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PROGERR_DEFAULT (_ADC_IEN_PROGERR_DEFAULT << 25) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND (0x1UL << 26) /**< SCANEXTPEND Interrupt Enable */ +#define _ADC_IEN_SCANEXTPEND_SHIFT 26 /**< Shift value for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_MASK 0x4000000UL /**< Bit mask for ADC_SCANEXTPEND */ +#define _ADC_IEN_SCANEXTPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANEXTPEND_DEFAULT (_ADC_IEN_SCANEXTPEND_DEFAULT << 26) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND (0x1UL << 27) /**< SCANPEND Interrupt Enable */ +#define _ADC_IEN_SCANPEND_SHIFT 27 /**< Shift value for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_MASK 0x8000000UL /**< Bit mask for ADC_SCANPEND */ +#define _ADC_IEN_SCANPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_SCANPEND_DEFAULT (_ADC_IEN_SCANPEND_DEFAULT << 27) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR (0x1UL << 28) /**< PRSTIMEDERR Interrupt Enable */ +#define _ADC_IEN_PRSTIMEDERR_SHIFT 28 /**< Shift value for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_MASK 0x10000000UL /**< Bit mask for ADC_PRSTIMEDERR */ +#define _ADC_IEN_PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_PRSTIMEDERR_DEFAULT (_ADC_IEN_PRSTIMEDERR_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR (0x1UL << 29) /**< EM23ERR Interrupt Enable */ +#define _ADC_IEN_EM23ERR_SHIFT 29 /**< Shift value for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_MASK 0x20000000UL /**< Bit mask for ADC_EM23ERR */ +#define _ADC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */ +#define ADC_IEN_EM23ERR_DEFAULT (_ADC_IEN_EM23ERR_DEFAULT << 29) /**< Shifted mode DEFAULT for ADC_IEN */ + +/* Bit fields for ADC SINGLEDATA */ +#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */ +#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */ +#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */ + +/* Bit fields for ADC SCANDATA */ +#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */ +#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */ +#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */ +#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */ + +/* Bit fields for ADC SINGLEDATAP */ +#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */ +#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */ +#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */ + +/* Bit fields for ADC SCANDATAP */ +#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */ +#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */ +#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */ + +/* Bit fields for ADC SCANDATAX */ +#define _ADC_SCANDATAX_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_DATA_SHIFT 0 /**< Shift value for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_MASK 0xFFFFUL /**< Bit mask for ADC_DATA */ +#define _ADC_SCANDATAX_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_DATA_DEFAULT (_ADC_SCANDATAX_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ +#define _ADC_SCANDATAX_SCANINPUTID_SHIFT 16 /**< Shift value for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTID */ +#define _ADC_SCANDATAX_SCANINPUTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAX */ +#define ADC_SCANDATAX_SCANINPUTID_DEFAULT (_ADC_SCANDATAX_SCANINPUTID_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAX */ + +/* Bit fields for ADC SCANDATAXP */ +#define _ADC_SCANDATAXP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_MASK 0x001FFFFFUL /**< Mask for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_MASK 0xFFFFUL /**< Bit mask for ADC_DATAP */ +#define _ADC_SCANDATAXP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_DATAP_DEFAULT (_ADC_SCANDATAXP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_SHIFT 16 /**< Shift value for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_MASK 0x1F0000UL /**< Bit mask for ADC_SCANINPUTIDPEEK */ +#define _ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAXP */ +#define ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT (_ADC_SCANDATAXP_SCANINPUTIDPEEK_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANDATAXP */ + +/* Bit fields for ADC APORTREQ */ +#define _ADC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTREQ */ +#define _ADC_APORTREQ_MASK 0x000003FFUL /**< Mask for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ (0x1UL << 0) /**< 1 if the bus connected to APORT0X is requested */ +#define _ADC_APORTREQ_APORT0XREQ_SHIFT 0 /**< Shift value for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_MASK 0x1UL /**< Bit mask for ADC_APORT0XREQ */ +#define _ADC_APORTREQ_APORT0XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0XREQ_DEFAULT (_ADC_APORTREQ_APORT0XREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is requested */ +#define _ADC_APORTREQ_APORT0YREQ_SHIFT 1 /**< Shift value for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_MASK 0x2UL /**< Bit mask for ADC_APORT0YREQ */ +#define _ADC_APORTREQ_APORT0YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT0YREQ_DEFAULT (_ADC_APORTREQ_APORT0YREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT1X is requested */ +#define _ADC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for ADC_APORT1XREQ */ +#define _ADC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1XREQ_DEFAULT (_ADC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ +#define _ADC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for ADC_APORT1YREQ */ +#define _ADC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT1YREQ_DEFAULT (_ADC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _ADC_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for ADC_APORT2XREQ */ +#define _ADC_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2XREQ_DEFAULT (_ADC_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _ADC_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for ADC_APORT2YREQ */ +#define _ADC_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT2YREQ_DEFAULT (_ADC_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _ADC_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for ADC_APORT3XREQ */ +#define _ADC_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3XREQ_DEFAULT (_ADC_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _ADC_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for ADC_APORT3YREQ */ +#define _ADC_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT3YREQ_DEFAULT (_ADC_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _ADC_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for ADC_APORT4XREQ */ +#define _ADC_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4XREQ_DEFAULT (_ADC_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _ADC_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for ADC_APORT4YREQ */ +#define _ADC_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTREQ */ +#define ADC_APORTREQ_APORT4YREQ_DEFAULT (_ADC_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTREQ */ + +/* Bit fields for ADC APORTCONFLICT */ +#define _ADC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTCONFLICT */ +#define _ADC_APORTCONFLICT_MASK 0x000003FFUL /**< Mask for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT (0x1UL << 0) /**< 1 if the bus connected to APORT0X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_SHIFT 0 /**< Shift value for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_MASK 0x1UL /**< Bit mask for ADC_APORT0XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0XCONFLICT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT (0x1UL << 1) /**< 1 if the bus connected to APORT0Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_SHIFT 1 /**< Shift value for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_MASK 0x2UL /**< Bit mask for ADC_APORT0YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT0YCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for ADC_APORT1XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for ADC_APORT1YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for ADC_APORT2XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for ADC_APORT2YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for ADC_APORT3XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for ADC_APORT3YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for ADC_APORT4XCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for ADC_APORT4YCONFLICT */ +#define _ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTCONFLICT */ +#define ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_ADC_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTCONFLICT */ + +/* Bit fields for ADC SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SINGLEFIFOCOUNT */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_SHIFT 0 /**< Shift value for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_MASK 0x7UL /**< Bit mask for ADC_SINGLEDC */ +#define _ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCOUNT */ +#define ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT (_ADC_SINGLEFIFOCOUNT_SINGLEDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCOUNT */ + +/* Bit fields for ADC SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_MASK 0x00000007UL /**< Mask for ADC_SCANFIFOCOUNT */ +#define _ADC_SCANFIFOCOUNT_SCANDC_SHIFT 0 /**< Shift value for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_MASK 0x7UL /**< Bit mask for ADC_SCANDC */ +#define _ADC_SCANFIFOCOUNT_SCANDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCOUNT */ +#define ADC_SCANFIFOCOUNT_SCANDC_DEFAULT (_ADC_SCANFIFOCOUNT_SCANDC_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCOUNT */ + +/* Bit fields for ADC SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR (0x1UL << 0) /**< Clear Single FIFO content */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SINGLEFIFOCLEAR */ +#define _ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEFIFOCLEAR */ +#define ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT (_ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEFIFOCLEAR */ + +/* Bit fields for ADC SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_MASK 0x00000001UL /**< Mask for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR (0x1UL << 0) /**< Clear Scan FIFO content */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_SHIFT 0 /**< Shift value for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_MASK 0x1UL /**< Bit mask for ADC_SCANFIFOCLEAR */ +#define _ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANFIFOCLEAR */ +#define ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT (_ADC_SCANFIFOCLEAR_SCANFIFOCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANFIFOCLEAR */ + +/* Bit fields for ADC APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_RESETVALUE 0x00000000UL /**< Default value for ADC_APORTMASTERDIS */ +#define _ADC_APORTMASTERDIS_MASK 0x000003FCUL /**< Mask for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS (0x1UL << 2) /**< APORT1X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_SHIFT 2 /**< Shift value for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_MASK 0x4UL /**< Bit mask for ADC_APORT1XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1XMASTERDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS (0x1UL << 3) /**< APORT1Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_SHIFT 3 /**< Shift value for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_MASK 0x8UL /**< Bit mask for ADC_APORT1YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT1YMASTERDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS (0x1UL << 4) /**< APORT2X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_SHIFT 4 /**< Shift value for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_MASK 0x10UL /**< Bit mask for ADC_APORT2XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2XMASTERDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS (0x1UL << 5) /**< APORT2Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_SHIFT 5 /**< Shift value for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_MASK 0x20UL /**< Bit mask for ADC_APORT2YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT2YMASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS (0x1UL << 6) /**< APORT3X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_SHIFT 6 /**< Shift value for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_MASK 0x40UL /**< Bit mask for ADC_APORT3XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3XMASTERDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS (0x1UL << 7) /**< APORT3Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_SHIFT 7 /**< Shift value for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_MASK 0x80UL /**< Bit mask for ADC_APORT3YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT3YMASTERDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS (0x1UL << 8) /**< APORT4X Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_SHIFT 8 /**< Shift value for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_MASK 0x100UL /**< Bit mask for ADC_APORT4XMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4XMASTERDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS (0x1UL << 9) /**< APORT4Y Master Disable */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_SHIFT 9 /**< Shift value for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_MASK 0x200UL /**< Bit mask for ADC_APORT4YMASTERDIS */ +#define _ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_APORTMASTERDIS */ +#define ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT (_ADC_APORTMASTERDIS_APORT4YMASTERDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_APORTMASTERDIS */ + +/** @} End of group EFM32PG12B_ADC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_pins.h new file mode 100644 index 0000000000..37d8e7466e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_pins.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efm32pg12b_af_pins.h + * @brief EFM32PG12B_AF_PINS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_AF_Pins + * @{ + *****************************************************************************/ + +/** AF pin number for location number i */ +#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1) +#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) +#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : -1) +#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1) +#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1) +#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) +#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1) +#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1) +#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1) +#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1) +#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1) +#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1) +#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1) +#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1) +#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_TIMER0_CC3_PIN(i) (-1) +#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_TIMER0_CDTI3_PIN(i) (-1) +#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_TIMER1_CDTI0_PIN(i) (-1) +#define AF_TIMER1_CDTI1_PIN(i) (-1) +#define AF_TIMER1_CDTI2_PIN(i) (-1) +#define AF_TIMER1_CDTI3_PIN(i) (-1) +#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER0_CC3_PIN(i) (-1) +#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1) +#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 8 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CDTI3_PIN(i) (-1) +#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 4 : (i) == 9 ? 5 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 5 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 8 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 11 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 12 : (i) == 31 ? 13 : -1) +#define AF_WTIMER1_CDTI0_PIN(i) (-1) +#define AF_WTIMER1_CDTI1_PIN(i) (-1) +#define AF_WTIMER1_CDTI2_PIN(i) (-1) +#define AF_WTIMER1_CDTI3_PIN(i) (-1) +#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1) +#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1) +#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1) +#define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 9 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART2_RX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 5 : -1) +#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? 8 : (i) == 20 ? 9 : (i) == 21 ? 10 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 5 : (i) == 31 ? 6 : -1) +#define AF_USART2_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? 8 : (i) == 18 ? 9 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 8 : -1) +#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_USART3_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 2 : (i) == 9 ? 3 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_USART3_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 14 : (i) == 16 ? 15 : (i) == 17 ? 0 : (i) == 18 ? 1 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 4 : (i) == 22 ? 5 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 8 : -1) +#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1) +#define AF_USART3_CS_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 13 : (i) == 3 ? 14 : (i) == 4 ? 15 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 14 : (i) == 14 ? 15 : (i) == 15 ? 0 : (i) == 16 ? 1 : (i) == 17 ? 2 : (i) == 18 ? 3 : (i) == 19 ? 4 : (i) == 20 ? 5 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 8 : (i) == 30 ? 9 : (i) == 31 ? 10 : -1) +#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 14 : (i) == 13 ? 15 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 4 : (i) == 19 ? 5 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1) +#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 8 : (i) == 28 ? 9 : (i) == 29 ? 10 : (i) == 30 ? 11 : (i) == 31 ? 12 : -1) +#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1) +#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1) +#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1) +#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1) +#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1) +#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1) +#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1) +#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1) +#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1) +#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1) +#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1) +#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1) +#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 6 : -1) +#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 7 : -1) +#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 14 : -1) +#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 15 : -1) +#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1) +#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) +#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1) +#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) +#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) +#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 6 : -1) +#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 7 : -1) +#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 8 : -1) +#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 9 : -1) +#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 8 : (i) == 3 ? 10 : -1) + +/** @} End of group EFM32PG12B_AF_Pins */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_ports.h new file mode 100644 index 0000000000..8bc4adc9b7 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_ports.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efm32pg12b_af_ports.h + * @brief EFM32PG12B_AF_PORTS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_AF_Ports + * @{ + *****************************************************************************/ + +/** AF port number for location number i */ +#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1) +#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1) +#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) +#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1) +#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) +#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1) +#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1) +#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1) +#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1) +#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) +#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) +#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CC3_PORT(i) (-1) +#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER0_CDTI3_PORT(i) (-1) +#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_TIMER1_CDTI0_PORT(i) (-1) +#define AF_TIMER1_CDTI1_PORT(i) (-1) +#define AF_TIMER1_CDTI2_PORT(i) (-1) +#define AF_TIMER1_CDTI3_PORT(i) (-1) +#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1) +#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CC3_PORT(i) (-1) +#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER0_CDTI3_PORT(i) (-1) +#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_WTIMER1_CDTI0_PORT(i) (-1) +#define AF_WTIMER1_CDTI1_PORT(i) (-1) +#define AF_WTIMER1_CDTI2_PORT(i) (-1) +#define AF_WTIMER1_CDTI3_PORT(i) (-1) +#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_USART2_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1) +#define AF_USART3_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : (i) == 8 ? 8 : (i) == 9 ? 8 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 9 : (i) == 17 ? 9 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_USART3_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 9 : (i) == 16 ? 9 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 3 : -1) +#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 9 : (i) == 15 ? 9 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_CS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 9 : (i) == 14 ? 9 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 9 : (i) == 13 ? 9 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1) +#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1) +#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1) +#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1) +#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1) +#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1) +#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 0 : -1) +#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 9 : -1) +#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 8 : -1) +#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1) +#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) +#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) +#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) + +/** @} End of group EFM32PG12B_AF_Ports */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cmu.h new file mode 100644 index 0000000000..6dac0d32cb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cmu.h @@ -0,0 +1,2032 @@ +/**************************************************************************//** + * @file efm32pg12b_cmu.h + * @brief EFM32PG12B_CMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_CMU + * @{ + * @brief EFM32PG12B_CMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CMU Control Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ + + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ + __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ + __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State control */ + __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ + __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ + + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ + __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ + uint32_t RESERVED5[2]; /**< Reserved for future use **/ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IOM uint32_t CALCNT; /**< Calibration Counter Register */ + uint32_t RESERVED6[2]; /**< Reserved for future use **/ + __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED7[2]; /**< Reserved for future use **/ + __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ + __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ + uint32_t RESERVED8[2]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ + __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ + __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ + + uint32_t RESERVED9[1]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ + uint32_t RESERVED10[1]; /**< Reserved for future use **/ + __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ + + uint32_t RESERVED11[3]; /**< Reserved for future use **/ + __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ + + uint32_t RESERVED12[7]; /**< Reserved for future use **/ + __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED13[1]; /**< Reserved for future use **/ + __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ + + uint32_t RESERVED14[1]; /**< Reserved for future use **/ + __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ + uint32_t RESERVED15[3]; /**< Reserved for future use **/ + __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ + + uint32_t RESERVED16[1]; /**< Reserved for future use **/ + __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ + __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ + + uint32_t RESERVED17[1]; /**< Reserved for future use **/ + __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ + + uint32_t RESERVED18[2]; /**< Reserved for future use **/ + __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED19[1]; /**< Reserved for future use **/ + __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ + uint32_t RESERVED20[1]; /**< Reserved for future use **/ + __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect */ + + uint32_t RESERVED21[3]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t FREEZE; /**< Freeze Register */ + uint32_t RESERVED22[2]; /**< Reserved for future use **/ + __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ + + uint32_t RESERVED23[2]; /**< Reserved for future use **/ + __IOM uint32_t ADCCTRL; /**< ADC Control Register */ + + uint32_t RESERVED24[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + uint32_t RESERVED25[1]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ +} CMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_CMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU CTRL */ +#define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */ +#define _CMU_CTRL_MASK 0x001101EFUL /**< Mask for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_MASK 0x1E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ +#define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ +#define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ +#define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ +#define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ +#define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ +#define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ +#define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ +#define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ + +/* Bit fields for CMU HFRCOCTRL */ +#define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ +#define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ +#define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ + +/* Bit fields for CMU AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ +#define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ +#define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ +#define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ +#define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ +#define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable reference for fine tuning */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ +#define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ +#define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ + +/* Bit fields for CMU LFRCOCTRL */ +#define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable duty cycling of vref */ +#define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ +#define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable comparator chopping */ +#define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ +#define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable dynamic element matching */ +#define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ +#define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ +#define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ +#define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ + +/* Bit fields for CMU HFXOCTRL */ +#define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */ +#define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low power mode control. PSR performance is reduced to enable low current consumption. */ +#define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */ +#define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */ +#define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N pin to ground when HFXO oscillator is off. */ +#define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */ +#define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */ +#define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P pin to ground when HFXO oscillator is off. */ +#define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */ +#define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */ +#define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ +#define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ +#define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically start of HFXO upon EM0/EM1 entry from EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically start and select of HFXO upon EM0/EM1 entry from EM2/EM3 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ +#define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ +#define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ + +/* Bit fields for CMU HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL /**< Default value for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ +#define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ + +/* Bit fields for CMU HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ +#define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */ +#define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables oscillator peak detectors */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ +#define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */ +#define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ +#define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ + +/* Bit fields for CMU HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL /**< Default value for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ +#define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ + +/* Bit fields for CMU LFXOCTRL */ +#define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ +#define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ +#define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ +#define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ +#define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ +#define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ +#define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ +#define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ +#define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ +#define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ +#define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ +#define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ +#define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ +#define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ + +/* Bit fields for CMU DPLLCTRL */ +#define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MASK 0x0000001FUL /**< Mask for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ +#define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ +#define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< automatic recovery ctrl */ +#define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ +#define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ +#define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ +#define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ +#define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ + +/* Bit fields for CMU DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ +#define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ +#define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ +#define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ +#define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ +#define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ +#define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0x0F0F0177UL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0x70UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */ +#define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */ +#define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ +#define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ +#define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU OSCENCMD */ +#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ +#define _CMU_OSCENCMD_MASK 0x000033FFUL /**< Mask for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ +#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ +#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ +#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ +#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ +#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ +#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ +#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ +#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ +#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ +#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ +#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ +#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ +#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ +#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ +#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ +#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ +#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ +#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ +#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ +#define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ +#define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ +#define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ +#define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ +#define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ + +/* Bit fields for CMU CMD */ +#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ +#define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */ +#define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ +#define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ +#define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */ +#define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ +#define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */ + +/* Bit fields for CMU DBGCLKSEL */ +#define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */ +#define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ +#define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ +#define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ + +/* Bit fields for CMU HFCLKSEL */ +#define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ +#define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ +#define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ +#define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ +#define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ + +/* Bit fields for CMU LFACLKSEL */ +#define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ +#define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ +#define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ +#define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ + +/* Bit fields for CMU LFBCLKSEL */ +#define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ +#define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ +#define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ +#define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ + +/* Bit fields for CMU LFECLKSEL */ +#define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ +#define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ +#define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ +#define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0x07E133FFUL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ +#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ +#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ +#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ +#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ +#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ +#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ +#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ +#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ +#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ +#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ +#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ +#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ +#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ +#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ +#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ +#define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ +#define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ +#define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required by Hardware (e.g. RAC) */ +#define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ +#define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ +#define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization ready */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO oscillation amplitude is too high */ +#define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */ +#define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */ +#define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO amplitude tuning value too low */ +#define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ +#define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO regulator shunt current too low */ +#define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */ +#define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */ +#define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ + +/* Bit fields for CMU HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ +#define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ +#define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ + +/* Bit fields for CMU HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ +#define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ +#define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ +#define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ +#define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x8003FF7FUL /**< Mask for CMU_IF */ +#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ +#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ +#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ +#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ +#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ +#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ +#define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ +#define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ +#define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */ +#define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ +#define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ +#define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ +#define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ +#define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ +#define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IFS */ +#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ +#define _CMU_IFS_MASK 0x8003FF7FUL /**< Mask for CMU_IFS */ +#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ +#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ +#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ +#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ +#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ +#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ +#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ +#define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ +#define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ +#define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ +#define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ +#define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ + +/* Bit fields for CMU IFC */ +#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ +#define _CMU_IFC_MASK 0x8003FF7FUL /**< Mask for CMU_IFC */ +#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ +#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ +#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ +#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ +#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ +#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ +#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ +#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ +#define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ +#define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ +#define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ +#define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ +#define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ +#define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ +#define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ +#define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x8003FF7FUL /**< Mask for CMU_IEN */ +#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ +#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ +#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ +#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ +#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ +#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ +#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ +#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ +#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ +#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ +#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ +#define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ +#define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ +#define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ +#define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ +#define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ +#define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ +#define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ +#define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ +#define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ +#define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ +#define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ +#define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ +#define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ +#define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ +#define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ +#define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ +#define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ +#define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ +#define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL /**< Mask for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0) /**< Advanced Encryption Standard Accelerator 0 Clock Enable */ +#define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0 /**< Alias for CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0 /**< Shift value for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL /**< Bit mask for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT /**< Alias for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK /**< Alias for CMU_CRYPTO0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT */ +#define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT*/ +#define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator 1 Clock Enable */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1 /**< Shift value for CMU_CRYPTO1 */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL /**< Bit mask for CMU_CRYPTO1 */ +#define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ +#define _CMU_HFBUSCLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ +#define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3) /**< General purpose Input/Output Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3 /**< Shift value for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL /**< Bit mask for CMU_GPIO */ +#define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */ +#define _CMU_HFBUSCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */ +#define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5) /**< Linked Direct Memory Access Controller Clock Enable */ +#define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5 /**< Shift value for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL /**< Bit mask for CMU_LDMA */ +#define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6) /**< General Purpose CRC Clock Enable */ +#define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6 /**< Shift value for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ +#define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ + +/* Bit fields for CMU HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ +#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */ +#define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER1 (0x1UL << 3) /**< Wide Timer 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_WTIMER1_SHIFT 3 /**< Shift value for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN0_WTIMER1_MASK 0x8UL /**< Bit mask for CMU_WTIMER1 */ +#define _CMU_HFPERCLKEN0_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_WTIMER1_DEFAULT (_CMU_HFPERCLKEN0_WTIMER1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART0_SHIFT 4 /**< Shift value for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_MASK 0x10UL /**< Bit mask for CMU_USART0 */ +#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1 (0x1UL << 5) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART1_SHIFT 5 /**< Shift value for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_MASK 0x20UL /**< Bit mask for CMU_USART1 */ +#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2 (0x1UL << 6) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART2_SHIFT 6 /**< Shift value for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_MASK 0x40UL /**< Bit mask for CMU_USART2 */ +#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ +#define _CMU_HFPERCLKEN0_USART3_SHIFT 7 /**< Shift value for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_MASK 0x80UL /**< Bit mask for CMU_USART3 */ +#define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 8) /**< I2C 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C0_SHIFT 8 /**< Shift value for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_MASK 0x100UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 9) /**< I2C 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_I2C1_SHIFT 9 /**< Shift value for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_MASK 0x200UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 10) /**< Analog Comparator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 10 /**< Shift value for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x400UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 11) /**< Analog Comparator 1 Clock Enable */ +#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 11 /**< Shift value for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x800UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CryoTimer Clock Enable */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 12 /**< Shift value for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x1000UL /**< Bit mask for CMU_CRYOTIMER */ +#define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 13) /**< Analog to Digital Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_ADC0_SHIFT 13 /**< Shift value for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_MASK 0x2000UL /**< Bit mask for CMU_ADC0 */ +#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14) /**< Current Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14 /**< Shift value for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL /**< Bit mask for CMU_IDAC0 */ +#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 15) /**< Digital to Analog Converter 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_VDAC0_SHIFT 15 /**< Shift value for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN0_VDAC0_MASK 0x8000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CSEN (0x1UL << 16) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_HFPERCLKEN0_CSEN_SHIFT 16 /**< Shift value for CMU_CSEN */ +#define _CMU_HFPERCLKEN0_CSEN_MASK 0x10000UL /**< Bit mask for CMU_CSEN */ +#define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 17) /**< True Random Number Generator 0 Clock Enable */ +#define _CMU_HFPERCLKEN0_TRNG0_SHIFT 17 /**< Shift value for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_MASK 0x20000UL /**< Bit mask for CMU_TRNG0 */ +#define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ + +/* Bit fields for CMU LFACLKEN0 */ +#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ +#define _CMU_LFACLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ +#define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE (0x1UL << 1) /**< Low Energy Sensor Interface Clock Enable */ +#define _CMU_LFACLKEN0_LESENSE_SHIFT 1 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ + +/* Bit fields for CMU LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ +#define _CMU_LFBCLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0) /**< Clock Enable */ +#define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1) /**< Low Energy UART 0 Clock Enable */ +#define _CMU_LFBCLKEN0_LEUART0_SHIFT 1 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN (0x1UL << 2) /**< Capacitive touch sense module Clock Enable */ +#define _CMU_LFBCLKEN0_CSEN_SHIFT 2 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ + +/* Bit fields for CMU LFECLKEN0 */ +#define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ +#define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ +#define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ +#define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ + +/* Bit fields for CMU HFPRESC */ +#define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ +#define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ +#define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ +#define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ + +/* Bit fields for CMU HFCOREPRESC */ +#define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ +#define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ +#define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ + +/* Bit fields for CMU HFPERPRESC */ +#define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ +#define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ +#define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ + +/* Bit fields for CMU HFEXPPRESC */ +#define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ +#define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ +#define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ +#define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ + +/* Bit fields for CMU LFAPRESC0 */ +#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_MASK 0x0000003FUL /**< Mask for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_SHIFT 4 /**< Shift value for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ +#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ + +/* Bit fields for CMU LFBPRESC0 */ +#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_MASK 0x0000033FUL /**< Mask for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL /**< Bit mask for CMU_SYSTICK */ +#define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_SHIFT 4 /**< Shift value for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL /**< Bit mask for CMU_LEUART0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_SHIFT 8 /**< Shift value for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_MASK 0x300UL /**< Bit mask for CMU_CSEN */ +#define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ +#define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ + +/* Bit fields for CMU LFEPRESC0 */ +#define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ +#define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ +#define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ +#define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ + +/* Bit fields for CMU SYNCBUSY */ +#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ +#define _CMU_SYNCBUSY_MASK 0x3F050055UL /**< Mask for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ +#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ +#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ +#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ +#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ +#define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ +#define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ +#define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ +#define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ +#define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ +#define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ +#define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ +#define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ +#define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ +#define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ +#define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ +#define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ +#define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ +#define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ + +/* Bit fields for CMU FREEZE */ +#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ +#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ +#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ +#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ + +/* Bit fields for CMU PCNTCTRL */ +#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ +#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ +#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ +#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ +#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ + +/* Bit fields for CMU ADCCTRL */ +#define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ +#define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert clock selected by ADC0CLKSEL */ +#define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ +#define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ +#define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ + +/* Bit fields for CMU ROUTEPEN */ +#define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ +#define _CMU_ROUTEPEN_MASK 0x10000003UL /**< Mask for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ +#define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ +#define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ +#define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ +#define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ +#define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ + +/* Bit fields for CMU ROUTELOC0 */ +#define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ +#define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ +#define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ + +/* Bit fields for CMU ROUTELOC1 */ +#define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ +#define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ +#define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU HFRCOSS */ +#define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ +#define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ +#define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ +#define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ +#define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ + +/** @} End of group EFM32PG12B_CMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cryotimer.h new file mode 100644 index 0000000000..90b5be3765 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cryotimer.h @@ -0,0 +1,167 @@ +/**************************************************************************//** + * @file efm32pg12b_cryotimer.h + * @brief EFM32PG12B_CRYOTIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_CRYOTIMER + * @{ + * @brief EFM32PG12B_CRYOTIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PERIODSEL; /**< Interrupt Duration */ + __IM uint32_t CNT; /**< Counter Value */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CRYOTIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_CRYOTIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYOTIMER CTRL */ +#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */ +#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */ +#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */ +#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */ +#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */ +#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */ +#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */ +#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */ + +/* Bit fields for CRYOTIMER PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */ +#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */ +#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */ + +/* Bit fields for CRYOTIMER CNT */ +#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */ +#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */ +#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */ + +/* Bit fields for CRYOTIMER EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */ +#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ +#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */ +#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */ +#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */ + +/* Bit fields for CRYOTIMER IF */ +#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */ +#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup event/Interrupt */ +#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */ +#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */ + +/* Bit fields for CRYOTIMER IFS */ +#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */ +#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */ +#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */ + +/* Bit fields for CRYOTIMER IFC */ +#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */ +#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */ +#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */ +#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */ + +/* Bit fields for CRYOTIMER IEN */ +#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */ +#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */ +#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */ +#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */ +#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */ + +/** @} End of group EFM32PG12B_CRYOTIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_crypto.h new file mode 100644 index 0000000000..1b88ff6478 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_crypto.h @@ -0,0 +1,1216 @@ +/**************************************************************************//** + * @file efm32pg12b_crypto.h + * @brief EFM32PG12B_CRYPTO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_CRYPTO + * @{ + * @brief EFM32PG12B_CRYPTO Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t WAC; /**< Wide Arithmetic Configuration */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t DSTATUS; /**< Data Status Register */ + __IM uint32_t CSTATUS; /**< Control Status Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t KEY; /**< KEY Register Access */ + __IOM uint32_t KEYBUF; /**< KEY Buffer Register Access */ + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IOM uint32_t SEQCTRL; /**< Sequence Control */ + __IOM uint32_t SEQCTRLB; /**< Sequence Control B */ + uint32_t RESERVED3[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< AES Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t SEQ0; /**< Sequence register 0 */ + __IOM uint32_t SEQ1; /**< Sequence Register 1 */ + __IOM uint32_t SEQ2; /**< Sequence Register 2 */ + __IOM uint32_t SEQ3; /**< Sequence Register 3 */ + __IOM uint32_t SEQ4; /**< Sequence Register 4 */ + uint32_t RESERVED4[7]; /**< Reserved for future use **/ + __IOM uint32_t DATA0; /**< DATA0 Register Access */ + __IOM uint32_t DATA1; /**< DATA1 Register Access */ + __IOM uint32_t DATA2; /**< DATA2 Register Access */ + __IOM uint32_t DATA3; /**< DATA3 Register Access */ + uint32_t RESERVED5[4]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XOR; /**< DATA0XOR Register Access */ + uint32_t RESERVED6[3]; /**< Reserved for future use **/ + __IOM uint32_t DATA0BYTE; /**< DATA0 Register Byte Access */ + __IOM uint32_t DATA1BYTE; /**< DATA1 Register Byte Access */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IOM uint32_t DATA0XORBYTE; /**< DATA0 Register Byte XOR Access */ + __IOM uint32_t DATA0BYTE12; /**< DATA0 Register Byte 12 Access */ + __IOM uint32_t DATA0BYTE13; /**< DATA0 Register Byte 13 Access */ + __IOM uint32_t DATA0BYTE14; /**< DATA0 Register Byte 14 Access */ + __IOM uint32_t DATA0BYTE15; /**< DATA0 Register Byte 15 Access */ + uint32_t RESERVED8[12]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0; /**< DDATA0 Register Access */ + __IOM uint32_t DDATA1; /**< DDATA1 Register Access */ + __IOM uint32_t DDATA2; /**< DDATA2 Register Access */ + __IOM uint32_t DDATA3; /**< DDATA3 Register Access */ + __IOM uint32_t DDATA4; /**< DDATA4 Register Access */ + uint32_t RESERVED9[7]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BIG; /**< DDATA0 Register Big Endian Access */ + uint32_t RESERVED10[3]; /**< Reserved for future use **/ + __IOM uint32_t DDATA0BYTE; /**< DDATA0 Register Byte Access */ + __IOM uint32_t DDATA1BYTE; /**< DDATA1 Register Byte Access */ + __IOM uint32_t DDATA0BYTE32; /**< DDATA0 Register Byte 32 access. */ + uint32_t RESERVED11[13]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0; /**< QDATA0 Register Access */ + __IOM uint32_t QDATA1; /**< QDATA1 Register Access */ + uint32_t RESERVED12[7]; /**< Reserved for future use **/ + __IOM uint32_t QDATA1BIG; /**< QDATA1 Register Big Endian Access */ + uint32_t RESERVED13[6]; /**< Reserved for future use **/ + __IOM uint32_t QDATA0BYTE; /**< QDATA0 Register Byte Access */ + __IOM uint32_t QDATA1BYTE; /**< QDATA1 Register Byte Access */ +} CRYPTO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_CRYPTO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYPTO CTRL */ +#define _CRYPTO_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_MASK 0xB333C407UL /**< Mask for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES (0x1UL << 0) /**< AES Mode */ +#define _CRYPTO_CTRL_AES_SHIFT 0 /**< Shift value for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_MASK 0x1UL /**< Bit mask for CRYPTO_AES */ +#define _CRYPTO_CTRL_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES128 0x00000000UL /**< Mode AES128 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_AES_AES256 0x00000001UL /**< Mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_DEFAULT (_CRYPTO_CTRL_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES128 (_CRYPTO_CTRL_AES_AES128 << 0) /**< Shifted mode AES128 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_AES_AES256 (_CRYPTO_CTRL_AES_AES256 << 0) /**< Shifted mode AES256 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS (0x1UL << 1) /**< Key Buffer Disable */ +#define _CRYPTO_CTRL_KEYBUFDIS_SHIFT 1 /**< Shift value for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_MASK 0x2UL /**< Bit mask for CRYPTO_KEYBUFDIS */ +#define _CRYPTO_CTRL_KEYBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_KEYBUFDIS_DEFAULT (_CRYPTO_CTRL_KEYBUFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA (0x1UL << 2) /**< SHA Mode */ +#define _CRYPTO_CTRL_SHA_SHIFT 2 /**< Shift value for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_MASK 0x4UL /**< Bit mask for CRYPTO_SHA */ +#define _CRYPTO_CTRL_SHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA1 0x00000000UL /**< Mode SHA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_SHA_SHA2 0x00000001UL /**< Mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_DEFAULT (_CRYPTO_CTRL_SHA_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA1 (_CRYPTO_CTRL_SHA_SHA1 << 2) /**< Shifted mode SHA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_SHA_SHA2 (_CRYPTO_CTRL_SHA_SHA2 << 2) /**< Shifted mode SHA2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL (0x1UL << 10) /**< No Stalling of Bus When Busy */ +#define _CRYPTO_CTRL_NOBUSYSTALL_SHIFT 10 /**< Shift value for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_MASK 0x400UL /**< Bit mask for CRYPTO_NOBUSYSTALL */ +#define _CRYPTO_CTRL_NOBUSYSTALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_NOBUSYSTALL_DEFAULT (_CRYPTO_CTRL_NOBUSYSTALL_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_SHIFT 14 /**< Shift value for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_MASK 0xC000UL /**< Bit mask for CRYPTO_INCWIDTH */ +#define _CRYPTO_CTRL_INCWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH1 0x00000000UL /**< Mode INCWIDTH1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH2 0x00000001UL /**< Mode INCWIDTH2 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH3 0x00000002UL /**< Mode INCWIDTH3 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_INCWIDTH_INCWIDTH4 0x00000003UL /**< Mode INCWIDTH4 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_DEFAULT (_CRYPTO_CTRL_INCWIDTH_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH1 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH1 << 14) /**< Shifted mode INCWIDTH1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH2 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH2 << 14) /**< Shifted mode INCWIDTH2 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH3 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH3 << 14) /**< Shifted mode INCWIDTH3 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_INCWIDTH_INCWIDTH4 (_CRYPTO_CTRL_INCWIDTH_INCWIDTH4 << 14) /**< Shifted mode INCWIDTH4 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_SHIFT 16 /**< Shift value for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_MASK 0x30000UL /**< Bit mask for CRYPTO_DMA0MODE */ +#define _CRYPTO_CTRL_DMA0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_DEFAULT (_CRYPTO_CTRL_DMA0MODE_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULL (_CRYPTO_CTRL_DMA0MODE_FULL << 16) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMIT (_CRYPTO_CTRL_DMA0MODE_LENLIMIT << 16) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_FULLBYTE (_CRYPTO_CTRL_DMA0MODE_FULLBYTE << 16) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA0MODE_LENLIMITBYTE << 16) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_SHIFT 20 /**< Shift value for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_MASK 0x300000UL /**< Bit mask for CRYPTO_DMA0RSEL */ +#define _CRYPTO_CTRL_DMA0RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DATA0 0x00000000UL /**< Mode DATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0 0x00000001UL /**< Mode DDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_DDATA0BIG 0x00000002UL /**< Mode DDATA0BIG for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA0RSEL_QDATA0 0x00000003UL /**< Mode QDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DEFAULT (_CRYPTO_CTRL_DMA0RSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DATA0 (_CRYPTO_CTRL_DMA0RSEL_DATA0 << 20) /**< Shifted mode DATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0 (_CRYPTO_CTRL_DMA0RSEL_DDATA0 << 20) /**< Shifted mode DDATA0 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_DDATA0BIG (_CRYPTO_CTRL_DMA0RSEL_DDATA0BIG << 20) /**< Shifted mode DDATA0BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA0RSEL_QDATA0 (_CRYPTO_CTRL_DMA0RSEL_QDATA0 << 20) /**< Shifted mode QDATA0 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_SHIFT 24 /**< Shift value for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA1MODE */ +#define _CRYPTO_CTRL_DMA1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULL 0x00000000UL /**< Mode FULL for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMIT 0x00000001UL /**< Mode LENLIMIT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_FULLBYTE 0x00000002UL /**< Mode FULLBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE 0x00000003UL /**< Mode LENLIMITBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_DEFAULT (_CRYPTO_CTRL_DMA1MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULL (_CRYPTO_CTRL_DMA1MODE_FULL << 24) /**< Shifted mode FULL for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMIT (_CRYPTO_CTRL_DMA1MODE_LENLIMIT << 24) /**< Shifted mode LENLIMIT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_FULLBYTE (_CRYPTO_CTRL_DMA1MODE_FULLBYTE << 24) /**< Shifted mode FULLBYTE for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE (_CRYPTO_CTRL_DMA1MODE_LENLIMITBYTE << 24) /**< Shifted mode LENLIMITBYTE for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_SHIFT 28 /**< Shift value for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_MASK 0x30000000UL /**< Bit mask for CRYPTO_DMA1RSEL */ +#define _CRYPTO_CTRL_DMA1RSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DATA1 0x00000000UL /**< Mode DATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1 0x00000002UL /**< Mode QDATA1 for CRYPTO_CTRL */ +#define _CRYPTO_CTRL_DMA1RSEL_QDATA1BIG 0x00000003UL /**< Mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DEFAULT (_CRYPTO_CTRL_DMA1RSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DATA1 (_CRYPTO_CTRL_DMA1RSEL_DATA1 << 28) /**< Shifted mode DATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_DDATA1 (_CRYPTO_CTRL_DMA1RSEL_DDATA1 << 28) /**< Shifted mode DDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1 (_CRYPTO_CTRL_DMA1RSEL_QDATA1 << 28) /**< Shifted mode QDATA1 for CRYPTO_CTRL */ +#define CRYPTO_CTRL_DMA1RSEL_QDATA1BIG (_CRYPTO_CTRL_DMA1RSEL_QDATA1BIG << 28) /**< Shifted mode QDATA1BIG for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ (0x1UL << 31) /**< Combined Data0 Write DMA Request */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_SHIFT 31 /**< Shift value for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_MASK 0x80000000UL /**< Bit mask for CRYPTO_COMBDMA0WEREQ */ +#define _CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CTRL */ +#define CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT (_CRYPTO_CTRL_COMBDMA0WEREQ_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_CTRL */ + +/* Bit fields for CRYPTO WAC */ +#define _CRYPTO_WAC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_WAC */ +#define _CRYPTO_WAC_MASK 0x00000F1FUL /**< Mask for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_SHIFT 0 /**< Shift value for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_MASK 0xFUL /**< Bit mask for CRYPTO_MODULUS */ +#define _CRYPTO_WAC_MODULUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN256 0x00000000UL /**< Mode BIN256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_BIN128 0x00000001UL /**< Mode BIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233P 0x00000002UL /**< Mode ECCBIN233P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163P 0x00000003UL /**< Mode ECCBIN163P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_GCMBIN128 0x00000004UL /**< Mode GCMBIN128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256P 0x00000005UL /**< Mode ECCPRIME256P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224P 0x00000006UL /**< Mode ECCPRIME224P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192P 0x00000007UL /**< Mode ECCPRIME192P for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233N 0x00000008UL /**< Mode ECCBIN233N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN233KN 0x00000009UL /**< Mode ECCBIN233KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163N 0x0000000AUL /**< Mode ECCBIN163N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCBIN163KN 0x0000000BUL /**< Mode ECCBIN163KN for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME256N 0x0000000CUL /**< Mode ECCPRIME256N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME224N 0x0000000DUL /**< Mode ECCPRIME224N for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODULUS_ECCPRIME192N 0x0000000EUL /**< Mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_DEFAULT (_CRYPTO_WAC_MODULUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN256 (_CRYPTO_WAC_MODULUS_BIN256 << 0) /**< Shifted mode BIN256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_BIN128 (_CRYPTO_WAC_MODULUS_BIN128 << 0) /**< Shifted mode BIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233P (_CRYPTO_WAC_MODULUS_ECCBIN233P << 0) /**< Shifted mode ECCBIN233P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163P (_CRYPTO_WAC_MODULUS_ECCBIN163P << 0) /**< Shifted mode ECCBIN163P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_GCMBIN128 (_CRYPTO_WAC_MODULUS_GCMBIN128 << 0) /**< Shifted mode GCMBIN128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256P (_CRYPTO_WAC_MODULUS_ECCPRIME256P << 0) /**< Shifted mode ECCPRIME256P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224P (_CRYPTO_WAC_MODULUS_ECCPRIME224P << 0) /**< Shifted mode ECCPRIME224P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192P (_CRYPTO_WAC_MODULUS_ECCPRIME192P << 0) /**< Shifted mode ECCPRIME192P for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233N (_CRYPTO_WAC_MODULUS_ECCBIN233N << 0) /**< Shifted mode ECCBIN233N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN233KN (_CRYPTO_WAC_MODULUS_ECCBIN233KN << 0) /**< Shifted mode ECCBIN233KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163N (_CRYPTO_WAC_MODULUS_ECCBIN163N << 0) /**< Shifted mode ECCBIN163N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCBIN163KN (_CRYPTO_WAC_MODULUS_ECCBIN163KN << 0) /**< Shifted mode ECCBIN163KN for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME256N (_CRYPTO_WAC_MODULUS_ECCPRIME256N << 0) /**< Shifted mode ECCPRIME256N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME224N (_CRYPTO_WAC_MODULUS_ECCPRIME224N << 0) /**< Shifted mode ECCPRIME224N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODULUS_ECCPRIME192N (_CRYPTO_WAC_MODULUS_ECCPRIME192N << 0) /**< Shifted mode ECCPRIME192N for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP (0x1UL << 4) /**< Modular Operation Field Type */ +#define _CRYPTO_WAC_MODOP_SHIFT 4 /**< Shift value for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_MASK 0x10UL /**< Bit mask for CRYPTO_MODOP */ +#define _CRYPTO_WAC_MODOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_BINARY 0x00000000UL /**< Mode BINARY for CRYPTO_WAC */ +#define _CRYPTO_WAC_MODOP_REGULAR 0x00000001UL /**< Mode REGULAR for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_DEFAULT (_CRYPTO_WAC_MODOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_BINARY (_CRYPTO_WAC_MODOP_BINARY << 4) /**< Shifted mode BINARY for CRYPTO_WAC */ +#define CRYPTO_WAC_MODOP_REGULAR (_CRYPTO_WAC_MODOP_REGULAR << 4) /**< Shifted mode REGULAR for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_SHIFT 8 /**< Shift value for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_MASK 0x300UL /**< Bit mask for CRYPTO_MULWIDTH */ +#define _CRYPTO_WAC_MULWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL256 0x00000000UL /**< Mode MUL256 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MUL128 0x00000001UL /**< Mode MUL128 for CRYPTO_WAC */ +#define _CRYPTO_WAC_MULWIDTH_MULMOD 0x00000002UL /**< Mode MULMOD for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_DEFAULT (_CRYPTO_WAC_MULWIDTH_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL256 (_CRYPTO_WAC_MULWIDTH_MUL256 << 8) /**< Shifted mode MUL256 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MUL128 (_CRYPTO_WAC_MULWIDTH_MUL128 << 8) /**< Shifted mode MUL128 for CRYPTO_WAC */ +#define CRYPTO_WAC_MULWIDTH_MULMOD (_CRYPTO_WAC_MULWIDTH_MULMOD << 8) /**< Shifted mode MULMOD for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_SHIFT 10 /**< Shift value for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_MASK 0xC00UL /**< Bit mask for CRYPTO_RESULTWIDTH */ +#define _CRYPTO_WAC_RESULTWIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_256BIT 0x00000000UL /**< Mode 256BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_128BIT 0x00000001UL /**< Mode 128BIT for CRYPTO_WAC */ +#define _CRYPTO_WAC_RESULTWIDTH_260BIT 0x00000002UL /**< Mode 260BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_DEFAULT (_CRYPTO_WAC_RESULTWIDTH_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_256BIT (_CRYPTO_WAC_RESULTWIDTH_256BIT << 10) /**< Shifted mode 256BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_128BIT (_CRYPTO_WAC_RESULTWIDTH_128BIT << 10) /**< Shifted mode 128BIT for CRYPTO_WAC */ +#define CRYPTO_WAC_RESULTWIDTH_260BIT (_CRYPTO_WAC_RESULTWIDTH_260BIT << 10) /**< Shifted mode 260BIT for CRYPTO_WAC */ + +/* Bit fields for CRYPTO CMD */ +#define _CRYPTO_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_CMD */ +#define _CRYPTO_CMD_MASK 0x00000EFFUL /**< Mask for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHIFT 0 /**< Shift value for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR */ +#define _CRYPTO_CMD_INSTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_END 0x00000000UL /**< Mode END for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXEC 0x00000001UL /**< Mode EXEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INC 0x00000003UL /**< Mode DATA1INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1INCCLR 0x00000004UL /**< Mode DATA1INCCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESENC 0x00000005UL /**< Mode AESENC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_AESDEC 0x00000006UL /**< Mode AESDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHA 0x00000007UL /**< Mode SHA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADD 0x00000008UL /**< Mode ADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDC 0x00000009UL /**< Mode ADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADD 0x0000000AUL /**< Mode LADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDC 0x0000000BUL /**< Mode LADDC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD 0x0000000CUL /**< Mode MADD for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MADD32 0x0000000DUL /**< Mode MADD32 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUB 0x00000010UL /**< Mode SUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SUBC 0x00000011UL /**< Mode SUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUB 0x00000012UL /**< Mode LSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LSUBC 0x00000013UL /**< Mode LSUBC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MSUB 0x00000014UL /**< Mode MSUB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MUL 0x00000018UL /**< Mode MUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULC 0x00000019UL /**< Mode MULC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMUL 0x0000001AUL /**< Mode LMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MMUL 0x0000001CUL /**< Mode MMUL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_MULO 0x0000001DUL /**< Mode MULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LMULO 0x0000001FUL /**< Mode LMULO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL 0x00000020UL /**< Mode SHL for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLC 0x00000021UL /**< Mode SHLC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHLB 0x00000022UL /**< Mode SHLB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHL1 0x00000023UL /**< Mode SHL1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR 0x00000024UL /**< Mode SHR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRC 0x00000025UL /**< Mode SHRC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRB 0x00000026UL /**< Mode SHRB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHR1 0x00000027UL /**< Mode SHR1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDO 0x00000028UL /**< Mode ADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_ADDIC 0x00000029UL /**< Mode ADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDO 0x0000002AUL /**< Mode LADDO for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LADDIC 0x0000002BUL /**< Mode LADDIC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CLR 0x00000030UL /**< Mode CLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_XOR 0x00000031UL /**< Mode XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INV 0x00000032UL /**< Mode INV for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CSET 0x00000034UL /**< Mode CSET for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_CCLR 0x00000035UL /**< Mode CCLR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BBSWAP128 0x00000036UL /**< Mode BBSWAP128 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_INC 0x00000038UL /**< Mode INC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DEC 0x00000039UL /**< Mode DEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LINC 0x0000003AUL /**< Mode LINC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_LDEC 0x0000003BUL /**< Mode LDEC for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SHRA 0x0000003EUL /**< Mode SHRA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0 0x00000040UL /**< Mode DATA0TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XOR 0x00000041UL /**< Mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN 0x00000042UL /**< Mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA1 0x00000044UL /**< Mode DATA0TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA2 0x00000045UL /**< Mode DATA0TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODATA3 0x00000046UL /**< Mode DATA0TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0 0x00000048UL /**< Mode DATA1TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XOR 0x00000049UL /**< Mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN 0x0000004AUL /**< Mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA2 0x0000004DUL /**< Mode DATA1TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODATA3 0x0000004EUL /**< Mode DATA1TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0 0x00000050UL /**< Mode DATA2TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XOR 0x00000051UL /**< Mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN 0x00000052UL /**< Mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA1 0x00000054UL /**< Mode DATA2TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODATA3 0x00000056UL /**< Mode DATA2TODATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0 0x00000058UL /**< Mode DATA3TODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XOR 0x00000059UL /**< Mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN 0x0000005AUL /**< Mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA1 0x0000005CUL /**< Mode DATA3TODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA3TODATA2 0x0000005DUL /**< Mode DATA3TODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA0 0x00000063UL /**< Mode DATATODMA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TOBUF 0x00000064UL /**< Mode DATA0TOBUF for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TOBUFXOR 0x00000065UL /**< Mode DATA0TOBUFXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATATODMA1 0x0000006BUL /**< Mode DATATODMA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TOBUF 0x0000006CUL /**< Mode DATA1TOBUF for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TOBUFXOR 0x0000006DUL /**< Mode DATA1TOBUFXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATA 0x00000070UL /**< Mode DMA0TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA0TODATAXOR 0x00000071UL /**< Mode DMA0TODATAXOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DMA1TODATA 0x00000072UL /**< Mode DMA1TODATA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA0 0x00000078UL /**< Mode BUFTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA0XOR 0x00000079UL /**< Mode BUFTODATA0XOR for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_BUFTODATA1 0x0000007AUL /**< Mode BUFTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA1 0x00000081UL /**< Mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA2 0x00000082UL /**< Mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA3 0x00000083UL /**< Mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0TODDATA4 0x00000084UL /**< Mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA0 0x00000085UL /**< Mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0HTODATA1 0x00000086UL /**< Mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA0LTODATA2 0x00000087UL /**< Mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA0 0x00000088UL /**< Mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA2 0x0000008AUL /**< Mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA3 0x0000008BUL /**< Mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1TODDATA4 0x0000008CUL /**< Mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA0 0x0000008DUL /**< Mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1HTODATA1 0x0000008EUL /**< Mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA1LTODATA2 0x0000008FUL /**< Mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA0 0x00000090UL /**< Mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA1 0x00000091UL /**< Mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA3 0x00000093UL /**< Mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2TODDATA4 0x00000094UL /**< Mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA2LTODATA2 0x00000097UL /**< Mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA0 0x00000098UL /**< Mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA1 0x00000099UL /**< Mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA2 0x0000009AUL /**< Mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3TODDATA4 0x0000009CUL /**< Mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3LTODATA0 0x0000009DUL /**< Mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA3HTODATA1 0x0000009EUL /**< Mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA0 0x000000A0UL /**< Mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA1 0x000000A1UL /**< Mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA2 0x000000A2UL /**< Mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4TODDATA3 0x000000A3UL /**< Mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA0 0x000000A5UL /**< Mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4HTODATA1 0x000000A6UL /**< Mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DDATA4LTODATA2 0x000000A7UL /**< Mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA0 0x000000A8UL /**< Mode DATA0TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA0TODDATA1 0x000000A9UL /**< Mode DATA0TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA0 0x000000B0UL /**< Mode DATA1TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA1TODDATA1 0x000000B1UL /**< Mode DATA1TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA0 0x000000B8UL /**< Mode DATA2TODDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA1 0x000000B9UL /**< Mode DATA2TODDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_DATA2TODDATA2 0x000000BAUL /**< Mode DATA2TODDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA0 0x000000C0UL /**< Mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA0 0x000000C1UL /**< Mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA0 0x000000C2UL /**< Mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA0 0x000000C3UL /**< Mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA0 0x000000C4UL /**< Mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA0 0x000000C5UL /**< Mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA0 0x000000C6UL /**< Mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA0 0x000000C7UL /**< Mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA1 0x000000C8UL /**< Mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA1 0x000000C9UL /**< Mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA1 0x000000CAUL /**< Mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA1 0x000000CBUL /**< Mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA1 0x000000CCUL /**< Mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA1 0x000000CDUL /**< Mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA1 0x000000CEUL /**< Mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA1 0x000000CFUL /**< Mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA2 0x000000D0UL /**< Mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA2 0x000000D1UL /**< Mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA2 0x000000D2UL /**< Mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA2 0x000000D3UL /**< Mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA2 0x000000D4UL /**< Mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA2 0x000000D5UL /**< Mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA2 0x000000D6UL /**< Mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA2 0x000000D7UL /**< Mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA3 0x000000D8UL /**< Mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA3 0x000000D9UL /**< Mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA3 0x000000DAUL /**< Mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA3 0x000000DBUL /**< Mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA3 0x000000DCUL /**< Mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA3 0x000000DDUL /**< Mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA3 0x000000DEUL /**< Mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA3 0x000000DFUL /**< Mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DDATA4 0x000000E0UL /**< Mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DDATA4 0x000000E1UL /**< Mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DDATA4 0x000000E2UL /**< Mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DDATA4 0x000000E3UL /**< Mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DDATA4 0x000000E4UL /**< Mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DDATA4 0x000000E5UL /**< Mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DDATA4 0x000000E6UL /**< Mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DDATA4 0x000000E7UL /**< Mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA0 0x000000E8UL /**< Mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA0 0x000000E9UL /**< Mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA0 0x000000EAUL /**< Mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA0 0x000000EBUL /**< Mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA0 0x000000ECUL /**< Mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA0 0x000000EDUL /**< Mode SELDATA0DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA0 0x000000EEUL /**< Mode SELDATA1DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA0 0x000000EFUL /**< Mode SELDATA2DATA0 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA0DATA1 0x000000F0UL /**< Mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA1DATA1 0x000000F1UL /**< Mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA2DATA1 0x000000F2UL /**< Mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA3DATA1 0x000000F3UL /**< Mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDDATA4DATA1 0x000000F4UL /**< Mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA0DATA1 0x000000F5UL /**< Mode SELDATA0DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA1DATA1 0x000000F6UL /**< Mode SELDATA1DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_SELDATA2DATA1 0x000000F7UL /**< Mode SELDATA2DATA1 for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFA 0x000000F8UL /**< Mode EXECIFA for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFB 0x000000F9UL /**< Mode EXECIFB for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNLAST 0x000000FAUL /**< Mode EXECIFNLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFLAST 0x000000FBUL /**< Mode EXECIFLAST for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFCARRY 0x000000FCUL /**< Mode EXECIFCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECIFNCARRY 0x000000FDUL /**< Mode EXECIFNCARRY for CRYPTO_CMD */ +#define _CRYPTO_CMD_INSTR_EXECALWAYS 0x000000FEUL /**< Mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEFAULT (_CRYPTO_CMD_INSTR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_END (_CRYPTO_CMD_INSTR_END << 0) /**< Shifted mode END for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXEC (_CRYPTO_CMD_INSTR_EXEC << 0) /**< Shifted mode EXEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INC (_CRYPTO_CMD_INSTR_DATA1INC << 0) /**< Shifted mode DATA1INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1INCCLR (_CRYPTO_CMD_INSTR_DATA1INCCLR << 0) /**< Shifted mode DATA1INCCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESENC (_CRYPTO_CMD_INSTR_AESENC << 0) /**< Shifted mode AESENC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_AESDEC (_CRYPTO_CMD_INSTR_AESDEC << 0) /**< Shifted mode AESDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHA (_CRYPTO_CMD_INSTR_SHA << 0) /**< Shifted mode SHA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADD (_CRYPTO_CMD_INSTR_ADD << 0) /**< Shifted mode ADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDC (_CRYPTO_CMD_INSTR_ADDC << 0) /**< Shifted mode ADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADD (_CRYPTO_CMD_INSTR_LADD << 0) /**< Shifted mode LADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDC (_CRYPTO_CMD_INSTR_LADDC << 0) /**< Shifted mode LADDC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD (_CRYPTO_CMD_INSTR_MADD << 0) /**< Shifted mode MADD for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MADD32 (_CRYPTO_CMD_INSTR_MADD32 << 0) /**< Shifted mode MADD32 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUB (_CRYPTO_CMD_INSTR_SUB << 0) /**< Shifted mode SUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SUBC (_CRYPTO_CMD_INSTR_SUBC << 0) /**< Shifted mode SUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUB (_CRYPTO_CMD_INSTR_LSUB << 0) /**< Shifted mode LSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LSUBC (_CRYPTO_CMD_INSTR_LSUBC << 0) /**< Shifted mode LSUBC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MSUB (_CRYPTO_CMD_INSTR_MSUB << 0) /**< Shifted mode MSUB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MUL (_CRYPTO_CMD_INSTR_MUL << 0) /**< Shifted mode MUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULC (_CRYPTO_CMD_INSTR_MULC << 0) /**< Shifted mode MULC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMUL (_CRYPTO_CMD_INSTR_LMUL << 0) /**< Shifted mode LMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MMUL (_CRYPTO_CMD_INSTR_MMUL << 0) /**< Shifted mode MMUL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_MULO (_CRYPTO_CMD_INSTR_MULO << 0) /**< Shifted mode MULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LMULO (_CRYPTO_CMD_INSTR_LMULO << 0) /**< Shifted mode LMULO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL (_CRYPTO_CMD_INSTR_SHL << 0) /**< Shifted mode SHL for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLC (_CRYPTO_CMD_INSTR_SHLC << 0) /**< Shifted mode SHLC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHLB (_CRYPTO_CMD_INSTR_SHLB << 0) /**< Shifted mode SHLB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHL1 (_CRYPTO_CMD_INSTR_SHL1 << 0) /**< Shifted mode SHL1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR (_CRYPTO_CMD_INSTR_SHR << 0) /**< Shifted mode SHR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRC (_CRYPTO_CMD_INSTR_SHRC << 0) /**< Shifted mode SHRC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRB (_CRYPTO_CMD_INSTR_SHRB << 0) /**< Shifted mode SHRB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHR1 (_CRYPTO_CMD_INSTR_SHR1 << 0) /**< Shifted mode SHR1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDO (_CRYPTO_CMD_INSTR_ADDO << 0) /**< Shifted mode ADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_ADDIC (_CRYPTO_CMD_INSTR_ADDIC << 0) /**< Shifted mode ADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDO (_CRYPTO_CMD_INSTR_LADDO << 0) /**< Shifted mode LADDO for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LADDIC (_CRYPTO_CMD_INSTR_LADDIC << 0) /**< Shifted mode LADDIC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CLR (_CRYPTO_CMD_INSTR_CLR << 0) /**< Shifted mode CLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_XOR (_CRYPTO_CMD_INSTR_XOR << 0) /**< Shifted mode XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INV (_CRYPTO_CMD_INSTR_INV << 0) /**< Shifted mode INV for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CSET (_CRYPTO_CMD_INSTR_CSET << 0) /**< Shifted mode CSET for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_CCLR (_CRYPTO_CMD_INSTR_CCLR << 0) /**< Shifted mode CCLR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BBSWAP128 (_CRYPTO_CMD_INSTR_BBSWAP128 << 0) /**< Shifted mode BBSWAP128 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_INC (_CRYPTO_CMD_INSTR_INC << 0) /**< Shifted mode INC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DEC (_CRYPTO_CMD_INSTR_DEC << 0) /**< Shifted mode DEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LINC (_CRYPTO_CMD_INSTR_LINC << 0) /**< Shifted mode LINC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_LDEC (_CRYPTO_CMD_INSTR_LDEC << 0) /**< Shifted mode LDEC for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SHRA (_CRYPTO_CMD_INSTR_SHRA << 0) /**< Shifted mode SHRA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0 (_CRYPTO_CMD_INSTR_DATA0TODATA0 << 0) /**< Shifted mode DATA0TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XOR (_CRYPTO_CMD_INSTR_DATA0TODATA0XOR << 0) /**< Shifted mode DATA0TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA0TODATA0XORLEN << 0) /**< Shifted mode DATA0TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA1 (_CRYPTO_CMD_INSTR_DATA0TODATA1 << 0) /**< Shifted mode DATA0TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA2 (_CRYPTO_CMD_INSTR_DATA0TODATA2 << 0) /**< Shifted mode DATA0TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODATA3 (_CRYPTO_CMD_INSTR_DATA0TODATA3 << 0) /**< Shifted mode DATA0TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0 (_CRYPTO_CMD_INSTR_DATA1TODATA0 << 0) /**< Shifted mode DATA1TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XOR (_CRYPTO_CMD_INSTR_DATA1TODATA0XOR << 0) /**< Shifted mode DATA1TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA1TODATA0XORLEN << 0) /**< Shifted mode DATA1TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA2 (_CRYPTO_CMD_INSTR_DATA1TODATA2 << 0) /**< Shifted mode DATA1TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODATA3 (_CRYPTO_CMD_INSTR_DATA1TODATA3 << 0) /**< Shifted mode DATA1TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0 (_CRYPTO_CMD_INSTR_DATA2TODATA0 << 0) /**< Shifted mode DATA2TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XOR (_CRYPTO_CMD_INSTR_DATA2TODATA0XOR << 0) /**< Shifted mode DATA2TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA2TODATA0XORLEN << 0) /**< Shifted mode DATA2TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA1 (_CRYPTO_CMD_INSTR_DATA2TODATA1 << 0) /**< Shifted mode DATA2TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODATA3 (_CRYPTO_CMD_INSTR_DATA2TODATA3 << 0) /**< Shifted mode DATA2TODATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0 (_CRYPTO_CMD_INSTR_DATA3TODATA0 << 0) /**< Shifted mode DATA3TODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XOR (_CRYPTO_CMD_INSTR_DATA3TODATA0XOR << 0) /**< Shifted mode DATA3TODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN (_CRYPTO_CMD_INSTR_DATA3TODATA0XORLEN << 0) /**< Shifted mode DATA3TODATA0XORLEN for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA1 (_CRYPTO_CMD_INSTR_DATA3TODATA1 << 0) /**< Shifted mode DATA3TODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA3TODATA2 (_CRYPTO_CMD_INSTR_DATA3TODATA2 << 0) /**< Shifted mode DATA3TODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA0 (_CRYPTO_CMD_INSTR_DATATODMA0 << 0) /**< Shifted mode DATATODMA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TOBUF (_CRYPTO_CMD_INSTR_DATA0TOBUF << 0) /**< Shifted mode DATA0TOBUF for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TOBUFXOR (_CRYPTO_CMD_INSTR_DATA0TOBUFXOR << 0) /**< Shifted mode DATA0TOBUFXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATATODMA1 (_CRYPTO_CMD_INSTR_DATATODMA1 << 0) /**< Shifted mode DATATODMA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TOBUF (_CRYPTO_CMD_INSTR_DATA1TOBUF << 0) /**< Shifted mode DATA1TOBUF for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TOBUFXOR (_CRYPTO_CMD_INSTR_DATA1TOBUFXOR << 0) /**< Shifted mode DATA1TOBUFXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATA (_CRYPTO_CMD_INSTR_DMA0TODATA << 0) /**< Shifted mode DMA0TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA0TODATAXOR (_CRYPTO_CMD_INSTR_DMA0TODATAXOR << 0) /**< Shifted mode DMA0TODATAXOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DMA1TODATA (_CRYPTO_CMD_INSTR_DMA1TODATA << 0) /**< Shifted mode DMA1TODATA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA0 (_CRYPTO_CMD_INSTR_BUFTODATA0 << 0) /**< Shifted mode BUFTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA0XOR (_CRYPTO_CMD_INSTR_BUFTODATA0XOR << 0) /**< Shifted mode BUFTODATA0XOR for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_BUFTODATA1 (_CRYPTO_CMD_INSTR_BUFTODATA1 << 0) /**< Shifted mode BUFTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA1 (_CRYPTO_CMD_INSTR_DDATA0TODDATA1 << 0) /**< Shifted mode DDATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA2 (_CRYPTO_CMD_INSTR_DDATA0TODDATA2 << 0) /**< Shifted mode DDATA0TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA3 (_CRYPTO_CMD_INSTR_DDATA0TODDATA3 << 0) /**< Shifted mode DDATA0TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0TODDATA4 (_CRYPTO_CMD_INSTR_DDATA0TODDATA4 << 0) /**< Shifted mode DDATA0TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA0 (_CRYPTO_CMD_INSTR_DDATA0LTODATA0 << 0) /**< Shifted mode DDATA0LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0HTODATA1 (_CRYPTO_CMD_INSTR_DDATA0HTODATA1 << 0) /**< Shifted mode DDATA0HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA0LTODATA2 (_CRYPTO_CMD_INSTR_DDATA0LTODATA2 << 0) /**< Shifted mode DDATA0LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA0 (_CRYPTO_CMD_INSTR_DDATA1TODDATA0 << 0) /**< Shifted mode DDATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA2 (_CRYPTO_CMD_INSTR_DDATA1TODDATA2 << 0) /**< Shifted mode DDATA1TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA3 (_CRYPTO_CMD_INSTR_DDATA1TODDATA3 << 0) /**< Shifted mode DDATA1TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1TODDATA4 (_CRYPTO_CMD_INSTR_DDATA1TODDATA4 << 0) /**< Shifted mode DDATA1TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA0 (_CRYPTO_CMD_INSTR_DDATA1LTODATA0 << 0) /**< Shifted mode DDATA1LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1HTODATA1 (_CRYPTO_CMD_INSTR_DDATA1HTODATA1 << 0) /**< Shifted mode DDATA1HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA1LTODATA2 (_CRYPTO_CMD_INSTR_DDATA1LTODATA2 << 0) /**< Shifted mode DDATA1LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA0 (_CRYPTO_CMD_INSTR_DDATA2TODDATA0 << 0) /**< Shifted mode DDATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA1 (_CRYPTO_CMD_INSTR_DDATA2TODDATA1 << 0) /**< Shifted mode DDATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA3 (_CRYPTO_CMD_INSTR_DDATA2TODDATA3 << 0) /**< Shifted mode DDATA2TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2TODDATA4 (_CRYPTO_CMD_INSTR_DDATA2TODDATA4 << 0) /**< Shifted mode DDATA2TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA2LTODATA2 (_CRYPTO_CMD_INSTR_DDATA2LTODATA2 << 0) /**< Shifted mode DDATA2LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA0 (_CRYPTO_CMD_INSTR_DDATA3TODDATA0 << 0) /**< Shifted mode DDATA3TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA1 (_CRYPTO_CMD_INSTR_DDATA3TODDATA1 << 0) /**< Shifted mode DDATA3TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA2 (_CRYPTO_CMD_INSTR_DDATA3TODDATA2 << 0) /**< Shifted mode DDATA3TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3TODDATA4 (_CRYPTO_CMD_INSTR_DDATA3TODDATA4 << 0) /**< Shifted mode DDATA3TODDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3LTODATA0 (_CRYPTO_CMD_INSTR_DDATA3LTODATA0 << 0) /**< Shifted mode DDATA3LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA3HTODATA1 (_CRYPTO_CMD_INSTR_DDATA3HTODATA1 << 0) /**< Shifted mode DDATA3HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA0 (_CRYPTO_CMD_INSTR_DDATA4TODDATA0 << 0) /**< Shifted mode DDATA4TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA1 (_CRYPTO_CMD_INSTR_DDATA4TODDATA1 << 0) /**< Shifted mode DDATA4TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA2 (_CRYPTO_CMD_INSTR_DDATA4TODDATA2 << 0) /**< Shifted mode DDATA4TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4TODDATA3 (_CRYPTO_CMD_INSTR_DDATA4TODDATA3 << 0) /**< Shifted mode DDATA4TODDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA0 (_CRYPTO_CMD_INSTR_DDATA4LTODATA0 << 0) /**< Shifted mode DDATA4LTODATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4HTODATA1 (_CRYPTO_CMD_INSTR_DDATA4HTODATA1 << 0) /**< Shifted mode DDATA4HTODATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DDATA4LTODATA2 (_CRYPTO_CMD_INSTR_DDATA4LTODATA2 << 0) /**< Shifted mode DDATA4LTODATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA0 (_CRYPTO_CMD_INSTR_DATA0TODDATA0 << 0) /**< Shifted mode DATA0TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA0TODDATA1 (_CRYPTO_CMD_INSTR_DATA0TODDATA1 << 0) /**< Shifted mode DATA0TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA0 (_CRYPTO_CMD_INSTR_DATA1TODDATA0 << 0) /**< Shifted mode DATA1TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA1TODDATA1 (_CRYPTO_CMD_INSTR_DATA1TODDATA1 << 0) /**< Shifted mode DATA1TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA0 (_CRYPTO_CMD_INSTR_DATA2TODDATA0 << 0) /**< Shifted mode DATA2TODDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA1 (_CRYPTO_CMD_INSTR_DATA2TODDATA1 << 0) /**< Shifted mode DATA2TODDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_DATA2TODDATA2 (_CRYPTO_CMD_INSTR_DATA2TODDATA2 << 0) /**< Shifted mode DATA2TODDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA0 << 0) /**< Shifted mode SELDDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA0 << 0) /**< Shifted mode SELDDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA0 << 0) /**< Shifted mode SELDDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA0 << 0) /**< Shifted mode SELDDATA3DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA0 << 0) /**< Shifted mode SELDDATA4DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA0 (_CRYPTO_CMD_INSTR_SELDATA0DDATA0 << 0) /**< Shifted mode SELDATA0DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA0 (_CRYPTO_CMD_INSTR_SELDATA1DDATA0 << 0) /**< Shifted mode SELDATA1DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA0 (_CRYPTO_CMD_INSTR_SELDATA2DDATA0 << 0) /**< Shifted mode SELDATA2DDATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA1 << 0) /**< Shifted mode SELDDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA1 << 0) /**< Shifted mode SELDDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA1 << 0) /**< Shifted mode SELDDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA1 << 0) /**< Shifted mode SELDDATA3DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA1 << 0) /**< Shifted mode SELDDATA4DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA1 (_CRYPTO_CMD_INSTR_SELDATA0DDATA1 << 0) /**< Shifted mode SELDATA0DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA1 (_CRYPTO_CMD_INSTR_SELDATA1DDATA1 << 0) /**< Shifted mode SELDATA1DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA1 (_CRYPTO_CMD_INSTR_SELDATA2DDATA1 << 0) /**< Shifted mode SELDATA2DDATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA2 << 0) /**< Shifted mode SELDDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA2 << 0) /**< Shifted mode SELDDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA2 << 0) /**< Shifted mode SELDDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA2 << 0) /**< Shifted mode SELDDATA3DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA2 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA2 << 0) /**< Shifted mode SELDDATA4DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA2 (_CRYPTO_CMD_INSTR_SELDATA0DDATA2 << 0) /**< Shifted mode SELDATA0DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA2 (_CRYPTO_CMD_INSTR_SELDATA1DDATA2 << 0) /**< Shifted mode SELDATA1DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA2 (_CRYPTO_CMD_INSTR_SELDATA2DDATA2 << 0) /**< Shifted mode SELDATA2DDATA2 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA3 << 0) /**< Shifted mode SELDDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA3 << 0) /**< Shifted mode SELDDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA3 << 0) /**< Shifted mode SELDDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA3 << 0) /**< Shifted mode SELDDATA3DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA3 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA3 << 0) /**< Shifted mode SELDDATA4DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA3 (_CRYPTO_CMD_INSTR_SELDATA0DDATA3 << 0) /**< Shifted mode SELDATA0DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA3 (_CRYPTO_CMD_INSTR_SELDATA1DDATA3 << 0) /**< Shifted mode SELDATA1DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA3 (_CRYPTO_CMD_INSTR_SELDATA2DDATA3 << 0) /**< Shifted mode SELDATA2DDATA3 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA0DDATA4 << 0) /**< Shifted mode SELDDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA1DDATA4 << 0) /**< Shifted mode SELDDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA2DDATA4 << 0) /**< Shifted mode SELDDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA3DDATA4 << 0) /**< Shifted mode SELDDATA3DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DDATA4 (_CRYPTO_CMD_INSTR_SELDDATA4DDATA4 << 0) /**< Shifted mode SELDDATA4DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DDATA4 (_CRYPTO_CMD_INSTR_SELDATA0DDATA4 << 0) /**< Shifted mode SELDATA0DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DDATA4 (_CRYPTO_CMD_INSTR_SELDATA1DDATA4 << 0) /**< Shifted mode SELDATA1DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DDATA4 (_CRYPTO_CMD_INSTR_SELDATA2DDATA4 << 0) /**< Shifted mode SELDATA2DDATA4 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDDATA0DATA0 << 0) /**< Shifted mode SELDDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDDATA1DATA0 << 0) /**< Shifted mode SELDDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDDATA2DATA0 << 0) /**< Shifted mode SELDDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA0 (_CRYPTO_CMD_INSTR_SELDDATA3DATA0 << 0) /**< Shifted mode SELDDATA3DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA0 (_CRYPTO_CMD_INSTR_SELDDATA4DATA0 << 0) /**< Shifted mode SELDDATA4DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA0 (_CRYPTO_CMD_INSTR_SELDATA0DATA0 << 0) /**< Shifted mode SELDATA0DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA0 (_CRYPTO_CMD_INSTR_SELDATA1DATA0 << 0) /**< Shifted mode SELDATA1DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA0 (_CRYPTO_CMD_INSTR_SELDATA2DATA0 << 0) /**< Shifted mode SELDATA2DATA0 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDDATA0DATA1 << 0) /**< Shifted mode SELDDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDDATA1DATA1 << 0) /**< Shifted mode SELDDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDDATA2DATA1 << 0) /**< Shifted mode SELDDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA3DATA1 (_CRYPTO_CMD_INSTR_SELDDATA3DATA1 << 0) /**< Shifted mode SELDDATA3DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDDATA4DATA1 (_CRYPTO_CMD_INSTR_SELDDATA4DATA1 << 0) /**< Shifted mode SELDDATA4DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA0DATA1 (_CRYPTO_CMD_INSTR_SELDATA0DATA1 << 0) /**< Shifted mode SELDATA0DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA1DATA1 (_CRYPTO_CMD_INSTR_SELDATA1DATA1 << 0) /**< Shifted mode SELDATA1DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_SELDATA2DATA1 (_CRYPTO_CMD_INSTR_SELDATA2DATA1 << 0) /**< Shifted mode SELDATA2DATA1 for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFA (_CRYPTO_CMD_INSTR_EXECIFA << 0) /**< Shifted mode EXECIFA for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFB (_CRYPTO_CMD_INSTR_EXECIFB << 0) /**< Shifted mode EXECIFB for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNLAST (_CRYPTO_CMD_INSTR_EXECIFNLAST << 0) /**< Shifted mode EXECIFNLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFLAST (_CRYPTO_CMD_INSTR_EXECIFLAST << 0) /**< Shifted mode EXECIFLAST for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFCARRY (_CRYPTO_CMD_INSTR_EXECIFCARRY << 0) /**< Shifted mode EXECIFCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECIFNCARRY (_CRYPTO_CMD_INSTR_EXECIFNCARRY << 0) /**< Shifted mode EXECIFNCARRY for CRYPTO_CMD */ +#define CRYPTO_CMD_INSTR_EXECALWAYS (_CRYPTO_CMD_INSTR_EXECALWAYS << 0) /**< Shifted mode EXECALWAYS for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART (0x1UL << 9) /**< Encryption/Decryption SEQUENCE Start */ +#define _CRYPTO_CMD_SEQSTART_SHIFT 9 /**< Shift value for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_MASK 0x200UL /**< Bit mask for CRYPTO_SEQSTART */ +#define _CRYPTO_CMD_SEQSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTART_DEFAULT (_CRYPTO_CMD_SEQSTART_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP (0x1UL << 10) /**< Sequence Stop */ +#define _CRYPTO_CMD_SEQSTOP_SHIFT 10 /**< Shift value for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_MASK 0x400UL /**< Bit mask for CRYPTO_SEQSTOP */ +#define _CRYPTO_CMD_SEQSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTOP_DEFAULT (_CRYPTO_CMD_SEQSTOP_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP (0x1UL << 11) /**< Sequence Step */ +#define _CRYPTO_CMD_SEQSTEP_SHIFT 11 /**< Shift value for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_MASK 0x800UL /**< Bit mask for CRYPTO_SEQSTEP */ +#define _CRYPTO_CMD_SEQSTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CMD */ +#define CRYPTO_CMD_SEQSTEP_DEFAULT (_CRYPTO_CMD_SEQSTEP_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTO_CMD */ + +/* Bit fields for CRYPTO STATUS */ +#define _CRYPTO_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_STATUS */ +#define _CRYPTO_STATUS_MASK 0x00000007UL /**< Mask for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING (0x1UL << 0) /**< AES SEQUENCE Running */ +#define _CRYPTO_STATUS_SEQRUNNING_SHIFT 0 /**< Shift value for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_MASK 0x1UL /**< Bit mask for CRYPTO_SEQRUNNING */ +#define _CRYPTO_STATUS_SEQRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_SEQRUNNING_DEFAULT (_CRYPTO_STATUS_SEQRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING (0x1UL << 1) /**< Action is active */ +#define _CRYPTO_STATUS_INSTRRUNNING_SHIFT 1 /**< Shift value for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_MASK 0x2UL /**< Bit mask for CRYPTO_INSTRRUNNING */ +#define _CRYPTO_STATUS_INSTRRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_INSTRRUNNING_DEFAULT (_CRYPTO_STATUS_INSTRRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE (0x1UL << 2) /**< DMA Action is active */ +#define _CRYPTO_STATUS_DMAACTIVE_SHIFT 2 /**< Shift value for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_MASK 0x4UL /**< Bit mask for CRYPTO_DMAACTIVE */ +#define _CRYPTO_STATUS_DMAACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_STATUS */ +#define CRYPTO_STATUS_DMAACTIVE_DEFAULT (_CRYPTO_STATUS_DMAACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTO_STATUS */ + +/* Bit fields for CRYPTO DSTATUS */ +#define _CRYPTO_DSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_MASK 0x011F0F0FUL /**< Mask for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_SHIFT 0 /**< Shift value for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_MASK 0xFUL /**< Bit mask for CRYPTO_DATA0ZERO */ +#define _CRYPTO_DSTATUS_DATA0ZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 0x00000001UL /**< Mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 0x00000002UL /**< Mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 0x00000004UL /**< Mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 0x00000008UL /**< Mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_DEFAULT (_CRYPTO_DSTATUS_DATA0ZERO_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO0TO31 << 0) /**< Shifted mode ZERO0TO31 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO32TO63 << 0) /**< Shifted mode ZERO32TO63 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO64TO95 << 0) /**< Shifted mode ZERO64TO95 for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 (_CRYPTO_DSTATUS_DATA0ZERO_ZERO96TO127 << 0) /**< Shifted mode ZERO96TO127 for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT 8 /**< Shift value for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_MASK 0xF00UL /**< Bit mask for CRYPTO_DDATA0LSBS */ +#define _CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0LSBS_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_SHIFT 16 /**< Shift value for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_MASK 0xF0000UL /**< Bit mask for CRYPTO_DDATA0MSBS */ +#define _CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT (_CRYPTO_DSTATUS_DDATA0MSBS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB (0x1UL << 20) /**< MSB in DDATA1 */ +#define _CRYPTO_DSTATUS_DDATA1MSB_SHIFT 20 /**< Shift value for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_MASK 0x100000UL /**< Bit mask for CRYPTO_DDATA1MSB */ +#define _CRYPTO_DSTATUS_DDATA1MSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_DDATA1MSB_DEFAULT (_CRYPTO_DSTATUS_DDATA1MSB_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY (0x1UL << 24) /**< Carry From Arithmetic Operation */ +#define _CRYPTO_DSTATUS_CARRY_SHIFT 24 /**< Shift value for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_MASK 0x1000000UL /**< Bit mask for CRYPTO_CARRY */ +#define _CRYPTO_DSTATUS_CARRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DSTATUS */ +#define CRYPTO_DSTATUS_CARRY_DEFAULT (_CRYPTO_DSTATUS_CARRY_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_DSTATUS */ + +/* Bit fields for CRYPTO CSTATUS */ +#define _CRYPTO_CSTATUS_RESETVALUE 0x00000201UL /**< Default value for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_MASK 0x01F30707UL /**< Mask for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_SHIFT 0 /**< Shift value for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_MASK 0x7UL /**< Bit mask for CRYPTO_V0 */ +#define _CRYPTO_CSTATUS_V0_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V0_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA0 (_CRYPTO_CSTATUS_V0_DDATA0 << 0) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DEFAULT (_CRYPTO_CSTATUS_V0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA1 (_CRYPTO_CSTATUS_V0_DDATA1 << 0) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA2 (_CRYPTO_CSTATUS_V0_DDATA2 << 0) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA3 (_CRYPTO_CSTATUS_V0_DDATA3 << 0) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DDATA4 (_CRYPTO_CSTATUS_V0_DDATA4 << 0) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA0 (_CRYPTO_CSTATUS_V0_DATA0 << 0) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA1 (_CRYPTO_CSTATUS_V0_DATA1 << 0) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V0_DATA2 (_CRYPTO_CSTATUS_V0_DATA2 << 0) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_SHIFT 8 /**< Shift value for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_MASK 0x700UL /**< Bit mask for CRYPTO_V1 */ +#define _CRYPTO_CSTATUS_V1_DDATA0 0x00000000UL /**< Mode DDATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA1 0x00000001UL /**< Mode DDATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DEFAULT 0x00000002UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA2 0x00000002UL /**< Mode DDATA2 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA3 0x00000003UL /**< Mode DDATA3 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DDATA4 0x00000004UL /**< Mode DDATA4 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA0 0x00000005UL /**< Mode DATA0 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA1 0x00000006UL /**< Mode DATA1 for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_V1_DATA2 0x00000007UL /**< Mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA0 (_CRYPTO_CSTATUS_V1_DDATA0 << 8) /**< Shifted mode DDATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA1 (_CRYPTO_CSTATUS_V1_DDATA1 << 8) /**< Shifted mode DDATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DEFAULT (_CRYPTO_CSTATUS_V1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA2 (_CRYPTO_CSTATUS_V1_DDATA2 << 8) /**< Shifted mode DDATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA3 (_CRYPTO_CSTATUS_V1_DDATA3 << 8) /**< Shifted mode DDATA3 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DDATA4 (_CRYPTO_CSTATUS_V1_DDATA4 << 8) /**< Shifted mode DDATA4 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA0 (_CRYPTO_CSTATUS_V1_DATA0 << 8) /**< Shifted mode DATA0 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA1 (_CRYPTO_CSTATUS_V1_DATA1 << 8) /**< Shifted mode DATA1 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_V1_DATA2 (_CRYPTO_CSTATUS_V1_DATA2 << 8) /**< Shifted mode DATA2 for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART (0x1UL << 16) /**< Sequence Part */ +#define _CRYPTO_CSTATUS_SEQPART_SHIFT 16 /**< Shift value for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_MASK 0x10000UL /**< Bit mask for CRYPTO_SEQPART */ +#define _CRYPTO_CSTATUS_SEQPART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQA 0x00000000UL /**< Mode SEQA for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQPART_SEQB 0x00000001UL /**< Mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_DEFAULT (_CRYPTO_CSTATUS_SEQPART_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQA (_CRYPTO_CSTATUS_SEQPART_SEQA << 16) /**< Shifted mode SEQA for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQPART_SEQB (_CRYPTO_CSTATUS_SEQPART_SEQB << 16) /**< Shifted mode SEQB for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP (0x1UL << 17) /**< Sequence Skip Next Instruction */ +#define _CRYPTO_CSTATUS_SEQSKIP_SHIFT 17 /**< Shift value for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_MASK 0x20000UL /**< Bit mask for CRYPTO_SEQSKIP */ +#define _CRYPTO_CSTATUS_SEQSKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQSKIP_DEFAULT (_CRYPTO_CSTATUS_SEQSKIP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ +#define _CRYPTO_CSTATUS_SEQIP_SHIFT 20 /**< Shift value for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_MASK 0x1F00000UL /**< Bit mask for CRYPTO_SEQIP */ +#define _CRYPTO_CSTATUS_SEQIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_CSTATUS */ +#define CRYPTO_CSTATUS_SEQIP_DEFAULT (_CRYPTO_CSTATUS_SEQIP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_CSTATUS */ + +/* Bit fields for CRYPTO KEY */ +#define _CRYPTO_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEY */ +#define _CRYPTO_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEY */ +#define _CRYPTO_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEY */ +#define CRYPTO_KEY_KEY_DEFAULT (_CRYPTO_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEY */ + +/* Bit fields for CRYPTO KEYBUF */ +#define _CRYPTO_KEYBUF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_SHIFT 0 /**< Shift value for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_KEYBUF */ +#define _CRYPTO_KEYBUF_KEYBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_KEYBUF */ +#define CRYPTO_KEYBUF_KEYBUF_DEFAULT (_CRYPTO_KEYBUF_KEYBUF_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_KEYBUF */ + +/* Bit fields for CRYPTO SEQCTRL */ +#define _CRYPTO_SEQCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_MASK 0xBF303FFFUL /**< Mask for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_LENGTHA_SHIFT 0 /**< Shift value for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHA */ +#define _CRYPTO_SEQCTRL_LENGTHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_LENGTHA_DEFAULT (_CRYPTO_SEQCTRL_LENGTHA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_SHIFT 20 /**< Shift value for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_MASK 0x300000UL /**< Bit mask for CRYPTO_BLOCKSIZE */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES 0x00000000UL /**< Mode 16BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES 0x00000001UL /**< Mode 32BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES 0x00000002UL /**< Mode 64BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT (_CRYPTO_SEQCTRL_BLOCKSIZE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_16BYTES << 20) /**< Shifted mode 16BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES << 20) /**< Shifted mode 32BYTES for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES (_CRYPTO_SEQCTRL_BLOCKSIZE_64BYTES << 20) /**< Shifted mode 64BYTES for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_SHIFT 24 /**< Shift value for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_MASK 0x3000000UL /**< Bit mask for CRYPTO_DMA0SKIP */ +#define _CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA0SKIP_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_SHIFT 26 /**< Shift value for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_MASK 0xC000000UL /**< Bit mask for CRYPTO_DMA1SKIP */ +#define _CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT (_CRYPTO_SEQCTRL_DMA1SKIP_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA (0x1UL << 28) /**< DMA0 Preserve A */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESA */ +#define _CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA0PRESA_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA (0x1UL << 29) /**< DMA1 Preserve A */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESA */ +#define _CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT (_CRYPTO_SEQCTRL_DMA1PRESA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT (0x1UL << 31) /**< Halt Sequence */ +#define _CRYPTO_SEQCTRL_HALT_SHIFT 31 /**< Shift value for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_MASK 0x80000000UL /**< Bit mask for CRYPTO_HALT */ +#define _CRYPTO_SEQCTRL_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRL */ +#define CRYPTO_SEQCTRL_HALT_DEFAULT (_CRYPTO_SEQCTRL_HALT_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRL */ + +/* Bit fields for CRYPTO SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_MASK 0x30003FFFUL /**< Mask for CRYPTO_SEQCTRLB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_SHIFT 0 /**< Shift value for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_MASK 0x3FFFUL /**< Bit mask for CRYPTO_LENGTHB */ +#define _CRYPTO_SEQCTRLB_LENGTHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_LENGTHB_DEFAULT (_CRYPTO_SEQCTRLB_LENGTHB_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB (0x1UL << 28) /**< DMA0 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_SHIFT 28 /**< Shift value for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_MASK 0x10000000UL /**< Bit mask for CRYPTO_DMA0PRESB */ +#define _CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA0PRESB_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB (0x1UL << 29) /**< DMA1 Preserve B */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_SHIFT 29 /**< Shift value for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_MASK 0x20000000UL /**< Bit mask for CRYPTO_DMA1PRESB */ +#define _CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQCTRLB */ +#define CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT (_CRYPTO_SEQCTRLB_DMA1PRESB_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTO_SEQCTRLB */ + +/* Bit fields for CRYPTO IF */ +#define _CRYPTO_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IF */ +#define _CRYPTO_IF_MASK 0x00000003UL /**< Mask for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE (0x1UL << 0) /**< Instruction done */ +#define _CRYPTO_IF_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IF_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_INSTRDONE_DEFAULT (_CRYPTO_IF_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE (0x1UL << 1) /**< Sequence Done */ +#define _CRYPTO_IF_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IF_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IF */ +#define CRYPTO_IF_SEQDONE_DEFAULT (_CRYPTO_IF_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IF */ + +/* Bit fields for CRYPTO IFS */ +#define _CRYPTO_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFS */ +#define _CRYPTO_IFS_MASK 0x00000003UL /**< Mask for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE (0x1UL << 0) /**< Set INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFS_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFS_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_INSTRDONE_DEFAULT (_CRYPTO_IFS_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE (0x1UL << 1) /**< Set SEQDONE Interrupt Flag */ +#define _CRYPTO_IFS_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFS_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFS */ +#define CRYPTO_IFS_SEQDONE_DEFAULT (_CRYPTO_IFS_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFS */ + +/* Bit fields for CRYPTO IFC */ +#define _CRYPTO_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IFC */ +#define _CRYPTO_IFC_MASK 0x00000003UL /**< Mask for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE (0x1UL << 0) /**< Clear INSTRDONE Interrupt Flag */ +#define _CRYPTO_IFC_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IFC_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_INSTRDONE_DEFAULT (_CRYPTO_IFC_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE (0x1UL << 1) /**< Clear SEQDONE Interrupt Flag */ +#define _CRYPTO_IFC_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IFC_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IFC */ +#define CRYPTO_IFC_SEQDONE_DEFAULT (_CRYPTO_IFC_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IFC */ + +/* Bit fields for CRYPTO IEN */ +#define _CRYPTO_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_IEN */ +#define _CRYPTO_IEN_MASK 0x00000003UL /**< Mask for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE (0x1UL << 0) /**< INSTRDONE Interrupt Enable */ +#define _CRYPTO_IEN_INSTRDONE_SHIFT 0 /**< Shift value for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_MASK 0x1UL /**< Bit mask for CRYPTO_INSTRDONE */ +#define _CRYPTO_IEN_INSTRDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_INSTRDONE_DEFAULT (_CRYPTO_IEN_INSTRDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE (0x1UL << 1) /**< SEQDONE Interrupt Enable */ +#define _CRYPTO_IEN_SEQDONE_SHIFT 1 /**< Shift value for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_MASK 0x2UL /**< Bit mask for CRYPTO_SEQDONE */ +#define _CRYPTO_IEN_SEQDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_IEN */ +#define CRYPTO_IEN_SEQDONE_DEFAULT (_CRYPTO_IEN_SEQDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTO_IEN */ + +/* Bit fields for CRYPTO SEQ0 */ +#define _CRYPTO_SEQ0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR0_SHIFT 0 /**< Shift value for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR0 */ +#define _CRYPTO_SEQ0_INSTR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR0_DEFAULT (_CRYPTO_SEQ0_INSTR0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR1_SHIFT 8 /**< Shift value for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR1 */ +#define _CRYPTO_SEQ0_INSTR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR1_DEFAULT (_CRYPTO_SEQ0_INSTR1_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR2_SHIFT 16 /**< Shift value for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR2 */ +#define _CRYPTO_SEQ0_INSTR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR2_DEFAULT (_CRYPTO_SEQ0_INSTR2_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ +#define _CRYPTO_SEQ0_INSTR3_SHIFT 24 /**< Shift value for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR3 */ +#define _CRYPTO_SEQ0_INSTR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ0 */ +#define CRYPTO_SEQ0_INSTR3_DEFAULT (_CRYPTO_SEQ0_INSTR3_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ0 */ + +/* Bit fields for CRYPTO SEQ1 */ +#define _CRYPTO_SEQ1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR4_SHIFT 0 /**< Shift value for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR4 */ +#define _CRYPTO_SEQ1_INSTR4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR4_DEFAULT (_CRYPTO_SEQ1_INSTR4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR5_SHIFT 8 /**< Shift value for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR5 */ +#define _CRYPTO_SEQ1_INSTR5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR5_DEFAULT (_CRYPTO_SEQ1_INSTR5_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR6_SHIFT 16 /**< Shift value for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR6 */ +#define _CRYPTO_SEQ1_INSTR6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR6_DEFAULT (_CRYPTO_SEQ1_INSTR6_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ +#define _CRYPTO_SEQ1_INSTR7_SHIFT 24 /**< Shift value for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR7 */ +#define _CRYPTO_SEQ1_INSTR7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ1 */ +#define CRYPTO_SEQ1_INSTR7_DEFAULT (_CRYPTO_SEQ1_INSTR7_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ1 */ + +/* Bit fields for CRYPTO SEQ2 */ +#define _CRYPTO_SEQ2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR8_SHIFT 0 /**< Shift value for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR8 */ +#define _CRYPTO_SEQ2_INSTR8_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR8_DEFAULT (_CRYPTO_SEQ2_INSTR8_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR9_SHIFT 8 /**< Shift value for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR9 */ +#define _CRYPTO_SEQ2_INSTR9_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR9_DEFAULT (_CRYPTO_SEQ2_INSTR9_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR10_SHIFT 16 /**< Shift value for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR10 */ +#define _CRYPTO_SEQ2_INSTR10_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR10_DEFAULT (_CRYPTO_SEQ2_INSTR10_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ +#define _CRYPTO_SEQ2_INSTR11_SHIFT 24 /**< Shift value for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR11 */ +#define _CRYPTO_SEQ2_INSTR11_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ2 */ +#define CRYPTO_SEQ2_INSTR11_DEFAULT (_CRYPTO_SEQ2_INSTR11_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ2 */ + +/* Bit fields for CRYPTO SEQ3 */ +#define _CRYPTO_SEQ3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR12_SHIFT 0 /**< Shift value for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR12 */ +#define _CRYPTO_SEQ3_INSTR12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR12_DEFAULT (_CRYPTO_SEQ3_INSTR12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR13_SHIFT 8 /**< Shift value for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR13 */ +#define _CRYPTO_SEQ3_INSTR13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR13_DEFAULT (_CRYPTO_SEQ3_INSTR13_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR14_SHIFT 16 /**< Shift value for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR14 */ +#define _CRYPTO_SEQ3_INSTR14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR14_DEFAULT (_CRYPTO_SEQ3_INSTR14_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ +#define _CRYPTO_SEQ3_INSTR15_SHIFT 24 /**< Shift value for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR15 */ +#define _CRYPTO_SEQ3_INSTR15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ3 */ +#define CRYPTO_SEQ3_INSTR15_DEFAULT (_CRYPTO_SEQ3_INSTR15_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ3 */ + +/* Bit fields for CRYPTO SEQ4 */ +#define _CRYPTO_SEQ4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR16_SHIFT 0 /**< Shift value for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_MASK 0xFFUL /**< Bit mask for CRYPTO_INSTR16 */ +#define _CRYPTO_SEQ4_INSTR16_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR16_DEFAULT (_CRYPTO_SEQ4_INSTR16_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR17_SHIFT 8 /**< Shift value for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_MASK 0xFF00UL /**< Bit mask for CRYPTO_INSTR17 */ +#define _CRYPTO_SEQ4_INSTR17_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR17_DEFAULT (_CRYPTO_SEQ4_INSTR17_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR18_SHIFT 16 /**< Shift value for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_MASK 0xFF0000UL /**< Bit mask for CRYPTO_INSTR18 */ +#define _CRYPTO_SEQ4_INSTR18_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR18_DEFAULT (_CRYPTO_SEQ4_INSTR18_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ +#define _CRYPTO_SEQ4_INSTR19_SHIFT 24 /**< Shift value for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_MASK 0xFF000000UL /**< Bit mask for CRYPTO_INSTR19 */ +#define _CRYPTO_SEQ4_INSTR19_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_SEQ4 */ +#define CRYPTO_SEQ4_INSTR19_DEFAULT (_CRYPTO_SEQ4_INSTR19_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTO_SEQ4 */ + +/* Bit fields for CRYPTO DATA0 */ +#define _CRYPTO_DATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_SHIFT 0 /**< Shift value for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0 */ +#define _CRYPTO_DATA0_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0 */ +#define CRYPTO_DATA0_DATA0_DEFAULT (_CRYPTO_DATA0_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0 */ + +/* Bit fields for CRYPTO DATA1 */ +#define _CRYPTO_DATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_SHIFT 0 /**< Shift value for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA1 */ +#define _CRYPTO_DATA1_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1 */ +#define CRYPTO_DATA1_DATA1_DEFAULT (_CRYPTO_DATA1_DATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1 */ + +/* Bit fields for CRYPTO DATA2 */ +#define _CRYPTO_DATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_SHIFT 0 /**< Shift value for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA2 */ +#define _CRYPTO_DATA2_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA2 */ +#define CRYPTO_DATA2_DATA2_DEFAULT (_CRYPTO_DATA2_DATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA2 */ + +/* Bit fields for CRYPTO DATA3 */ +#define _CRYPTO_DATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_SHIFT 0 /**< Shift value for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA3 */ +#define _CRYPTO_DATA3_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA3 */ +#define CRYPTO_DATA3_DATA3_DEFAULT (_CRYPTO_DATA3_DATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA3 */ + +/* Bit fields for CRYPTO DATA0XOR */ +#define _CRYPTO_DATA0XOR_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_SHIFT 0 /**< Shift value for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DATA0XOR */ +#define _CRYPTO_DATA0XOR_DATA0XOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XOR */ +#define CRYPTO_DATA0XOR_DATA0XOR_DEFAULT (_CRYPTO_DATA0XOR_DATA0XOR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XOR */ + +/* Bit fields for CRYPTO DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE */ +#define _CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE */ +#define CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT (_CRYPTO_DATA0BYTE_DATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE */ + +/* Bit fields for CRYPTO DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA1BYTE */ +#define _CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA1BYTE */ +#define CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT (_CRYPTO_DATA1BYTE_DATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA1BYTE */ + +/* Bit fields for CRYPTO DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_SHIFT 0 /**< Shift value for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0XORBYTE */ +#define _CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0XORBYTE */ +#define CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT (_CRYPTO_DATA0XORBYTE_DATA0XORBYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0XORBYTE */ + +/* Bit fields for CRYPTO DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE12 */ +#define _CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE12 */ +#define CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT (_CRYPTO_DATA0BYTE12_DATA0BYTE12_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE12 */ + +/* Bit fields for CRYPTO DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE13 */ +#define _CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE13 */ +#define CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT (_CRYPTO_DATA0BYTE13_DATA0BYTE13_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE13 */ + +/* Bit fields for CRYPTO DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE14 */ +#define _CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE14 */ +#define CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT (_CRYPTO_DATA0BYTE14_DATA0BYTE14_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE14 */ + +/* Bit fields for CRYPTO DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_MASK 0x000000FFUL /**< Mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_SHIFT 0 /**< Shift value for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_MASK 0xFFUL /**< Bit mask for CRYPTO_DATA0BYTE15 */ +#define _CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DATA0BYTE15 */ +#define CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT (_CRYPTO_DATA0BYTE15_DATA0BYTE15_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DATA0BYTE15 */ + +/* Bit fields for CRYPTO DDATA0 */ +#define _CRYPTO_DDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_SHIFT 0 /**< Shift value for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0 */ +#define _CRYPTO_DDATA0_DDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0 */ +#define CRYPTO_DDATA0_DDATA0_DEFAULT (_CRYPTO_DDATA0_DDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0 */ + +/* Bit fields for CRYPTO DDATA1 */ +#define _CRYPTO_DDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_SHIFT 0 /**< Shift value for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA1 */ +#define _CRYPTO_DDATA1_DDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1 */ +#define CRYPTO_DDATA1_DDATA1_DEFAULT (_CRYPTO_DDATA1_DDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1 */ + +/* Bit fields for CRYPTO DDATA2 */ +#define _CRYPTO_DDATA2_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_SHIFT 0 /**< Shift value for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA2 */ +#define _CRYPTO_DDATA2_DDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA2 */ +#define CRYPTO_DDATA2_DDATA2_DEFAULT (_CRYPTO_DDATA2_DDATA2_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA2 */ + +/* Bit fields for CRYPTO DDATA3 */ +#define _CRYPTO_DDATA3_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_SHIFT 0 /**< Shift value for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA3 */ +#define _CRYPTO_DDATA3_DDATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA3 */ +#define CRYPTO_DDATA3_DDATA3_DEFAULT (_CRYPTO_DDATA3_DDATA3_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA3 */ + +/* Bit fields for CRYPTO DDATA4 */ +#define _CRYPTO_DDATA4_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_SHIFT 0 /**< Shift value for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA4 */ +#define _CRYPTO_DDATA4_DDATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA4 */ +#define CRYPTO_DDATA4_DDATA4_DEFAULT (_CRYPTO_DDATA4_DDATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA4 */ + +/* Bit fields for CRYPTO DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_DDATA0BIG */ +#define _CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BIG */ +#define CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT (_CRYPTO_DDATA0BIG_DDATA0BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BIG */ + +/* Bit fields for CRYPTO DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA0BYTE */ +#define _CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE */ +#define CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT (_CRYPTO_DDATA0BYTE_DDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE */ + +/* Bit fields for CRYPTO DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_DDATA1BYTE */ +#define _CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA1BYTE */ +#define CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT (_CRYPTO_DDATA1BYTE_DDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA1BYTE */ + +/* Bit fields for CRYPTO DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_MASK 0x0000000FUL /**< Mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_SHIFT 0 /**< Shift value for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_MASK 0xFUL /**< Bit mask for CRYPTO_DDATA0BYTE32 */ +#define _CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_DDATA0BYTE32 */ +#define CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT (_CRYPTO_DDATA0BYTE32_DDATA0BYTE32_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_DDATA0BYTE32 */ + +/* Bit fields for CRYPTO QDATA0 */ +#define _CRYPTO_QDATA0_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_SHIFT 0 /**< Shift value for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA0 */ +#define _CRYPTO_QDATA0_QDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0 */ +#define CRYPTO_QDATA0_QDATA0_DEFAULT (_CRYPTO_QDATA0_QDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0 */ + +/* Bit fields for CRYPTO QDATA1 */ +#define _CRYPTO_QDATA1_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_SHIFT 0 /**< Shift value for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1 */ +#define _CRYPTO_QDATA1_QDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1 */ +#define CRYPTO_QDATA1_QDATA1_DEFAULT (_CRYPTO_QDATA1_QDATA1_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1 */ + +/* Bit fields for CRYPTO QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTO_QDATA1BIG */ +#define _CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BIG */ +#define CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT (_CRYPTO_QDATA1BIG_QDATA1BIG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BIG */ + +/* Bit fields for CRYPTO QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA0BYTE */ +#define _CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA0BYTE */ +#define CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT (_CRYPTO_QDATA0BYTE_QDATA0BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA0BYTE */ + +/* Bit fields for CRYPTO QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_RESETVALUE 0x00000000UL /**< Default value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_MASK 0x000000FFUL /**< Mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_SHIFT 0 /**< Shift value for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_MASK 0xFFUL /**< Bit mask for CRYPTO_QDATA1BYTE */ +#define _CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTO_QDATA1BYTE */ +#define CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT (_CRYPTO_QDATA1BYTE_QDATA1BYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTO_QDATA1BYTE */ + +/** @} End of group EFM32PG12B_CRYPTO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_csen.h new file mode 100644 index 0000000000..0ebc373d11 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_csen.h @@ -0,0 +1,1003 @@ +/**************************************************************************//** + * @file efm32pg12b_csen.h + * @brief EFM32PG12B_CSEN register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_CSEN + * @{ + * @brief EFM32PG12B_CSEN Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t PRSSEL; /**< Control Register */ + __IOM uint32_t DATA; /**< Control Register */ + __IOM uint32_t SCANMASK0; /**< CSEN Channel Scan Mask */ + __IOM uint32_t SCANINPUTSEL0; /**< Input Channel Configuration register for Scan mode */ + __IOM uint32_t SCANMASK1; /**< CSEN Channel Scan Mask */ + __IOM uint32_t SCANINPUTSEL1; /**< Input Channel Configuration register for Scan mode */ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ + __IOM uint32_t CMPTHR; /**< CSEN Comparator Threshold */ + __IOM uint32_t EMA; /**< Exponential Moving Average */ + __IOM uint32_t EMACTRL; /**< Exponential Moving Average */ + __IOM uint32_t SINGLECTRL; /**< CSEN Single Conversion Control Register */ + __IOM uint32_t DMBASELINE; /**< Control Register */ + __IOM uint32_t DMCFG; /**< Control Register */ + __IOM uint32_t ANACTRL; /**< Analog Control Register */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} CSEN_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_CSEN_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for CSEN CTRL */ +#define _CSEN_CTRL_RESETVALUE 0x00030000UL /**< Default value for CSEN_CTRL */ +#define _CSEN_CTRL_MASK 0x1FFFF336UL /**< Mask for CSEN_CTRL */ +#define CSEN_CTRL_EN (0x1UL << 1) /**< CSEN Enable */ +#define _CSEN_CTRL_EN_SHIFT 1 /**< Shift value for CSEN_EN */ +#define _CSEN_CTRL_EN_MASK 0x2UL /**< Bit mask for CSEN_EN */ +#define _CSEN_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_DEFAULT (_CSEN_CTRL_EN_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EN_DISABLE (_CSEN_CTRL_EN_DISABLE << 1) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_EN_ENABLE (_CSEN_CTRL_EN_ENABLE << 1) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL (0x1UL << 2) /**< CSEN Digital Comparator Polarity Select */ +#define _CSEN_CTRL_CMPPOL_SHIFT 2 /**< Shift value for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_MASK 0x4UL /**< Bit mask for CSEN_CMPPOL */ +#define _CSEN_CTRL_CMPPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_GT 0x00000000UL /**< Mode GT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPPOL_LTE 0x00000001UL /**< Mode LTE for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_DEFAULT (_CSEN_CTRL_CMPPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_GT (_CSEN_CTRL_CMPPOL_GT << 2) /**< Shifted mode GT for CSEN_CTRL */ +#define CSEN_CTRL_CMPPOL_LTE (_CSEN_CTRL_CMPPOL_LTE << 2) /**< Shifted mode LTE for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SHIFT 4 /**< Shift value for CSEN_CM */ +#define _CSEN_CTRL_CM_MASK 0x30UL /**< Bit mask for CSEN_CM */ +#define _CSEN_CTRL_CM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SGL 0x00000000UL /**< Mode SGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_SCAN 0x00000001UL /**< Mode SCAN for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSGL 0x00000002UL /**< Mode CONTSGL for CSEN_CTRL */ +#define _CSEN_CTRL_CM_CONTSCAN 0x00000003UL /**< Mode CONTSCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_DEFAULT (_CSEN_CTRL_CM_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CM_SGL (_CSEN_CTRL_CM_SGL << 4) /**< Shifted mode SGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_SCAN (_CSEN_CTRL_CM_SCAN << 4) /**< Shifted mode SCAN for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSGL (_CSEN_CTRL_CM_CONTSGL << 4) /**< Shifted mode CONTSGL for CSEN_CTRL */ +#define CSEN_CTRL_CM_CONTSCAN (_CSEN_CTRL_CM_CONTSCAN << 4) /**< Shifted mode CONTSCAN for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_SHIFT 8 /**< Shift value for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_MASK 0x300UL /**< Bit mask for CSEN_SARCR */ +#define _CSEN_CTRL_SARCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK10 0x00000000UL /**< Mode CLK10 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK12 0x00000001UL /**< Mode CLK12 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK14 0x00000002UL /**< Mode CLK14 for CSEN_CTRL */ +#define _CSEN_CTRL_SARCR_CLK16 0x00000003UL /**< Mode CLK16 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_DEFAULT (_CSEN_CTRL_SARCR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK10 (_CSEN_CTRL_SARCR_CLK10 << 8) /**< Shifted mode CLK10 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK12 (_CSEN_CTRL_SARCR_CLK12 << 8) /**< Shifted mode CLK12 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK14 (_CSEN_CTRL_SARCR_CLK14 << 8) /**< Shifted mode CLK14 for CSEN_CTRL */ +#define CSEN_CTRL_SARCR_CLK16 (_CSEN_CTRL_SARCR_CLK16 << 8) /**< Shifted mode CLK16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_SHIFT 12 /**< Shift value for CSEN_ACU */ +#define _CSEN_CTRL_ACU_MASK 0x7000UL /**< Bit mask for CSEN_ACU */ +#define _CSEN_CTRL_ACU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC1 0x00000000UL /**< Mode ACC1 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC2 0x00000001UL /**< Mode ACC2 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC4 0x00000002UL /**< Mode ACC4 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC8 0x00000003UL /**< Mode ACC8 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC16 0x00000004UL /**< Mode ACC16 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC32 0x00000005UL /**< Mode ACC32 for CSEN_CTRL */ +#define _CSEN_CTRL_ACU_ACC64 0x00000006UL /**< Mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_DEFAULT (_CSEN_CTRL_ACU_DEFAULT << 12) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC1 (_CSEN_CTRL_ACU_ACC1 << 12) /**< Shifted mode ACC1 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC2 (_CSEN_CTRL_ACU_ACC2 << 12) /**< Shifted mode ACC2 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC4 (_CSEN_CTRL_ACU_ACC4 << 12) /**< Shifted mode ACC4 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC8 (_CSEN_CTRL_ACU_ACC8 << 12) /**< Shifted mode ACC8 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC16 (_CSEN_CTRL_ACU_ACC16 << 12) /**< Shifted mode ACC16 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC32 (_CSEN_CTRL_ACU_ACC32 << 12) /**< Shifted mode ACC32 for CSEN_CTRL */ +#define CSEN_CTRL_ACU_ACC64 (_CSEN_CTRL_ACU_ACC64 << 12) /**< Shifted mode ACC64 for CSEN_CTRL */ +#define CSEN_CTRL_MCEN (0x1UL << 15) /**< CSEN Multiple Channel Enable. */ +#define _CSEN_CTRL_MCEN_SHIFT 15 /**< Shift value for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_MASK 0x8000UL /**< Bit mask for CSEN_MCEN */ +#define _CSEN_CTRL_MCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_MCEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DEFAULT (_CSEN_CTRL_MCEN_DEFAULT << 15) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_DISABLE (_CSEN_CTRL_MCEN_DISABLE << 15) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_MCEN_ENABLE (_CSEN_CTRL_MCEN_ENABLE << 15) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define _CSEN_CTRL_STM_SHIFT 16 /**< Shift value for CSEN_STM */ +#define _CSEN_CTRL_STM_MASK 0x30000UL /**< Bit mask for CSEN_STM */ +#define _CSEN_CTRL_STM_PRS 0x00000000UL /**< Mode PRS for CSEN_CTRL */ +#define _CSEN_CTRL_STM_TIMER 0x00000001UL /**< Mode TIMER for CSEN_CTRL */ +#define _CSEN_CTRL_STM_START 0x00000002UL /**< Mode START for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_STM_DEFAULT 0x00000003UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_PRS (_CSEN_CTRL_STM_PRS << 16) /**< Shifted mode PRS for CSEN_CTRL */ +#define CSEN_CTRL_STM_TIMER (_CSEN_CTRL_STM_TIMER << 16) /**< Shifted mode TIMER for CSEN_CTRL */ +#define CSEN_CTRL_STM_START (_CSEN_CTRL_STM_START << 16) /**< Shifted mode START for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_STM_DEFAULT (_CSEN_CTRL_STM_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN (0x1UL << 18) /**< CSEN Digital Comparator Enable Bit. */ +#define _CSEN_CTRL_CMPEN_SHIFT 18 /**< Shift value for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_MASK 0x40000UL /**< Bit mask for CSEN_CMPEN */ +#define _CSEN_CTRL_CMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CMPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DEFAULT (_CSEN_CTRL_CMPEN_DEFAULT << 18) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_DISABLE (_CSEN_CTRL_CMPEN_DISABLE << 18) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CMPEN_ENABLE (_CSEN_CTRL_CMPEN_ENABLE << 18) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF (0x1UL << 19) /**< CSEN Disable Right-Shift. */ +#define _CSEN_CTRL_DRSF_SHIFT 19 /**< Shift value for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_MASK 0x80000UL /**< Bit mask for CSEN_DRSF */ +#define _CSEN_CTRL_DRSF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DRSF_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DEFAULT (_CSEN_CTRL_DRSF_DEFAULT << 19) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_DISABLE (_CSEN_CTRL_DRSF_DISABLE << 19) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DRSF_ENABLE (_CSEN_CTRL_DRSF_ENABLE << 19) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN (0x1UL << 20) /**< CSEN DMA Enable Bit. */ +#define _CSEN_CTRL_DMAEN_SHIFT 20 /**< Shift value for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_MASK 0x100000UL /**< Bit mask for CSEN_DMAEN */ +#define _CSEN_CTRL_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_DMAEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DEFAULT (_CSEN_CTRL_DMAEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_DISABLE (_CSEN_CTRL_DMAEN_DISABLE << 20) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_DMAEN_ENABLE (_CSEN_CTRL_DMAEN_ENABLE << 20) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL (0x1UL << 21) /**< CSEN Converter Select */ +#define _CSEN_CTRL_CONVSEL_SHIFT 21 /**< Shift value for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_MASK 0x200000UL /**< Bit mask for CSEN_CONVSEL */ +#define _CSEN_CTRL_CONVSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_SAR 0x00000000UL /**< Mode SAR for CSEN_CTRL */ +#define _CSEN_CTRL_CONVSEL_DM 0x00000001UL /**< Mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DEFAULT (_CSEN_CTRL_CONVSEL_DEFAULT << 21) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_SAR (_CSEN_CTRL_CONVSEL_SAR << 21) /**< Shifted mode SAR for CSEN_CTRL */ +#define CSEN_CTRL_CONVSEL_DM (_CSEN_CTRL_CONVSEL_DM << 21) /**< Shifted mode DM for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN (0x1UL << 22) /**< CSEN Chop Enable */ +#define _CSEN_CTRL_CHOPEN_SHIFT 22 /**< Shift value for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_MASK 0x400000UL /**< Bit mask for CSEN_CHOPEN */ +#define _CSEN_CTRL_CHOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_CHOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DEFAULT (_CSEN_CTRL_CHOPEN_DEFAULT << 22) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_DISABLE (_CSEN_CTRL_CHOPEN_DISABLE << 22) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_CHOPEN_ENABLE (_CSEN_CTRL_CHOPEN_ENABLE << 22) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND (0x1UL << 23) /**< CSEN auto ground enable */ +#define _CSEN_CTRL_AUTOGND_SHIFT 23 /**< Shift value for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_MASK 0x800000UL /**< Bit mask for CSEN_AUTOGND */ +#define _CSEN_CTRL_AUTOGND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_DISABLE 0x00000000UL /**< Mode DISABLE for CSEN_CTRL */ +#define _CSEN_CTRL_AUTOGND_ENABLE 0x00000001UL /**< Mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DEFAULT (_CSEN_CTRL_AUTOGND_DEFAULT << 23) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_DISABLE (_CSEN_CTRL_AUTOGND_DISABLE << 23) /**< Shifted mode DISABLE for CSEN_CTRL */ +#define CSEN_CTRL_AUTOGND_ENABLE (_CSEN_CTRL_AUTOGND_ENABLE << 23) /**< Shifted mode ENABLE for CSEN_CTRL */ +#define CSEN_CTRL_MXUC (0x1UL << 24) /**< CSEN Mux Disconnect. */ +#define _CSEN_CTRL_MXUC_SHIFT 24 /**< Shift value for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_MASK 0x1000000UL /**< Bit mask for CSEN_MXUC */ +#define _CSEN_CTRL_MXUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_CONN 0x00000000UL /**< Mode CONN for CSEN_CTRL */ +#define _CSEN_CTRL_MXUC_UNC 0x00000001UL /**< Mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_DEFAULT (_CSEN_CTRL_MXUC_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_CONN (_CSEN_CTRL_MXUC_CONN << 24) /**< Shifted mode CONN for CSEN_CTRL */ +#define CSEN_CTRL_MXUC_UNC (_CSEN_CTRL_MXUC_UNC << 24) /**< Shifted mode UNC for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN (0x1UL << 25) /**< Greater and less than comparison using the exponential moving average (EMA) is enabled. */ +#define _CSEN_CTRL_EMACMPEN_SHIFT 25 /**< Shift value for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_MASK 0x2000000UL /**< Bit mask for CSEN_EMACMPEN */ +#define _CSEN_CTRL_EMACMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_EMACMPEN_DEFAULT (_CSEN_CTRL_EMACMPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE (0x1UL << 26) /**< Select Warmup mode for CSEN */ +#define _CSEN_CTRL_WARMUPMODE_SHIFT 26 /**< Shift value for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_MASK 0x4000000UL /**< Bit mask for CSEN_WARMUPMODE */ +#define _CSEN_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for CSEN_CTRL */ +#define _CSEN_CTRL_WARMUPMODE_KEEPCSENWARM 0x00000001UL /**< Mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_DEFAULT (_CSEN_CTRL_WARMUPMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_NORMAL (_CSEN_CTRL_WARMUPMODE_NORMAL << 26) /**< Shifted mode NORMAL for CSEN_CTRL */ +#define CSEN_CTRL_WARMUPMODE_KEEPCSENWARM (_CSEN_CTRL_WARMUPMODE_KEEPCSENWARM << 26) /**< Shifted mode KEEPCSENWARM for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS (0x1UL << 27) /**< Sense local cap connection instead of the external kelvin connection. */ +#define _CSEN_CTRL_LOCALSENS_SHIFT 27 /**< Shift value for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_MASK 0x8000000UL /**< Bit mask for CSEN_LOCALSENS */ +#define _CSEN_CTRL_LOCALSENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_LOCALSENS_DEFAULT (_CSEN_CTRL_LOCALSENS_DEFAULT << 27) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY (0x1UL << 28) /**< Sets the accuracy of the charge pump. */ +#define _CSEN_CTRL_CPACCURACY_SHIFT 28 /**< Shift value for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_MASK 0x10000000UL /**< Bit mask for CSEN_CPACCURACY */ +#define _CSEN_CTRL_CPACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_LO 0x00000000UL /**< Mode LO for CSEN_CTRL */ +#define _CSEN_CTRL_CPACCURACY_HI 0x00000001UL /**< Mode HI for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_DEFAULT (_CSEN_CTRL_CPACCURACY_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_LO (_CSEN_CTRL_CPACCURACY_LO << 28) /**< Shifted mode LO for CSEN_CTRL */ +#define CSEN_CTRL_CPACCURACY_HI (_CSEN_CTRL_CPACCURACY_HI << 28) /**< Shifted mode HI for CSEN_CTRL */ + +/* Bit fields for CSEN TIMCTRL */ +#define _CSEN_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_MASK 0x0003FF07UL /**< Mask for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_SHIFT 0 /**< Shift value for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_MASK 0x7UL /**< Bit mask for CSEN_PCPRESC */ +#define _CSEN_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DEFAULT (_CSEN_TIMCTRL_PCPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV1 (_CSEN_TIMCTRL_PCPRESC_DIV1 << 0) /**< Shifted mode DIV1 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV2 (_CSEN_TIMCTRL_PCPRESC_DIV2 << 0) /**< Shifted mode DIV2 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV4 (_CSEN_TIMCTRL_PCPRESC_DIV4 << 0) /**< Shifted mode DIV4 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV8 (_CSEN_TIMCTRL_PCPRESC_DIV8 << 0) /**< Shifted mode DIV8 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV16 (_CSEN_TIMCTRL_PCPRESC_DIV16 << 0) /**< Shifted mode DIV16 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV32 (_CSEN_TIMCTRL_PCPRESC_DIV32 << 0) /**< Shifted mode DIV32 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV64 (_CSEN_TIMCTRL_PCPRESC_DIV64 << 0) /**< Shifted mode DIV64 for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCPRESC_DIV128 (_CSEN_TIMCTRL_PCPRESC_DIV128 << 0) /**< Shifted mode DIV128 for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_PCTOP_SHIFT 8 /**< Shift value for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_MASK 0xFF00UL /**< Bit mask for CSEN_PCTOP */ +#define _CSEN_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_PCTOP_DEFAULT (_CSEN_TIMCTRL_PCTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ +#define _CSEN_TIMCTRL_WARMUPCNT_SHIFT 16 /**< Shift value for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_MASK 0x30000UL /**< Bit mask for CSEN_WARMUPCNT */ +#define _CSEN_TIMCTRL_WARMUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_TIMCTRL */ +#define CSEN_TIMCTRL_WARMUPCNT_DEFAULT (_CSEN_TIMCTRL_WARMUPCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_TIMCTRL */ + +/* Bit fields for CSEN CMD */ +#define _CSEN_CMD_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMD */ +#define _CSEN_CMD_MASK 0x00000001UL /**< Mask for CSEN_CMD */ +#define CSEN_CMD_START (0x1UL << 0) /**< Start a CSEN conversion. */ +#define _CSEN_CMD_START_SHIFT 0 /**< Shift value for CSEN_START */ +#define _CSEN_CMD_START_MASK 0x1UL /**< Bit mask for CSEN_START */ +#define _CSEN_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMD */ +#define CSEN_CMD_START_DEFAULT (_CSEN_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMD */ + +/* Bit fields for CSEN STATUS */ +#define _CSEN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CSEN_STATUS */ +#define _CSEN_STATUS_MASK 0x00000001UL /**< Mask for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY (0x1UL << 0) /**< CSEN Busy */ +#define _CSEN_STATUS_CSENBUSY_SHIFT 0 /**< Shift value for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_MASK 0x1UL /**< Bit mask for CSEN_CSENBUSY */ +#define _CSEN_STATUS_CSENBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_IDLE 0x00000000UL /**< Mode IDLE for CSEN_STATUS */ +#define _CSEN_STATUS_CSENBUSY_BUSY 0x00000001UL /**< Mode BUSY for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_DEFAULT (_CSEN_STATUS_CSENBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_IDLE (_CSEN_STATUS_CSENBUSY_IDLE << 0) /**< Shifted mode IDLE for CSEN_STATUS */ +#define CSEN_STATUS_CSENBUSY_BUSY (_CSEN_STATUS_CSENBUSY_BUSY << 0) /**< Shifted mode BUSY for CSEN_STATUS */ + +/* Bit fields for CSEN PRSSEL */ +#define _CSEN_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_MASK 0x0000000FUL /**< Mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_SHIFT 0 /**< Shift value for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_MASK 0xFUL /**< Bit mask for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CSEN_PRSSEL */ +#define _CSEN_PRSSEL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_DEFAULT (_CSEN_PRSSEL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH0 (_CSEN_PRSSEL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH1 (_CSEN_PRSSEL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH2 (_CSEN_PRSSEL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH3 (_CSEN_PRSSEL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH4 (_CSEN_PRSSEL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH5 (_CSEN_PRSSEL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH6 (_CSEN_PRSSEL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH7 (_CSEN_PRSSEL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH8 (_CSEN_PRSSEL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH9 (_CSEN_PRSSEL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH10 (_CSEN_PRSSEL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for CSEN_PRSSEL */ +#define CSEN_PRSSEL_PRSSEL_PRSCH11 (_CSEN_PRSSEL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for CSEN_PRSSEL */ + +/* Bit fields for CSEN DATA */ +#define _CSEN_DATA_RESETVALUE 0x00000000UL /**< Default value for CSEN_DATA */ +#define _CSEN_DATA_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_SHIFT 0 /**< Shift value for CSEN_DATA */ +#define _CSEN_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_DATA */ +#define _CSEN_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DATA */ +#define CSEN_DATA_DATA_DEFAULT (_CSEN_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DATA */ + +/* Bit fields for CSEN SCANMASK0 */ +#define _CSEN_SCANMASK0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK0 */ +#define _CSEN_SCANMASK0_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK0_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK0 */ +#define CSEN_SCANMASK0_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK0_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK0 */ + +/* Bit fields for CSEN SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_SHIFT 0 /**< Shift value for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT0TO7SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_SHIFT 8 /**< Shift value for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT8TO15SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT8TO15SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_SHIFT 16 /**< Shift value for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT16TO23SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT16TO23SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_SHIFT 24 /**< Shift value for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT24TO31SEL */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define _CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL0 */ +#define CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL0_INPUT24TO31SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL0 */ + +/* Bit fields for CSEN SCANMASK1 */ +#define _CSEN_SCANMASK1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_MASK 0xFFFFFFFFUL /**< Mask for CSEN_SCANMASK1 */ +#define _CSEN_SCANMASK1_SCANINPUTEN_SHIFT 0 /**< Shift value for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_MASK 0xFFFFFFFFUL /**< Bit mask for CSEN_SCANINPUTEN */ +#define _CSEN_SCANMASK1_SCANINPUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANMASK1 */ +#define CSEN_SCANMASK1_SCANINPUTEN_DEFAULT (_CSEN_SCANMASK1_SCANINPUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANMASK1 */ + +/* Bit fields for CSEN SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_RESETVALUE 0x00000000UL /**< Default value for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_MASK 0x0F0F0F0FUL /**< Mask for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_SHIFT 0 /**< Shift value for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_MASK 0xFUL /**< Bit mask for CSEN_INPUT32TO39SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH0TO7 << 0) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH8TO15 << 0) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH16TO23 << 0) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT1CH24TO31 << 0) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH0TO7 << 0) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH8TO15 << 0) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH16TO23 << 0) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT32TO39SEL_APORT3CH24TO31 << 0) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_SHIFT 8 /**< Shift value for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_MASK 0xF00UL /**< Bit mask for CSEN_INPUT40TO47SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH0TO7 << 8) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH8TO15 << 8) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH16TO23 << 8) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT1CH24TO31 << 8) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH0TO7 << 8) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH8TO15 << 8) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH16TO23 << 8) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT40TO47SEL_APORT3CH24TO31 << 8) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_SHIFT 16 /**< Shift value for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_MASK 0xF0000UL /**< Bit mask for CSEN_INPUT48TO55SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH0TO7 << 16) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH8TO15 << 16) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH16TO23 << 16) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT1CH24TO31 << 16) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH0TO7 << 16) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH8TO15 << 16) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH16TO23 << 16) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT48TO55SEL_APORT3CH24TO31 << 16) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_SHIFT 24 /**< Shift value for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_MASK 0xF000000UL /**< Bit mask for CSEN_INPUT56TO63SEL */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 0x00000004UL /**< Mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 0x00000005UL /**< Mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 0x00000006UL /**< Mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 0x00000007UL /**< Mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 0x0000000CUL /**< Mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 0x0000000DUL /**< Mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 0x0000000EUL /**< Mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define _CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 0x0000000FUL /**< Mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH0TO7 << 24) /**< Shifted mode APORT1CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH8TO15 << 24) /**< Shifted mode APORT1CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH16TO23 << 24) /**< Shifted mode APORT1CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT1CH24TO31 << 24) /**< Shifted mode APORT1CH24TO31 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH0TO7 << 24) /**< Shifted mode APORT3CH0TO7 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH8TO15 << 24) /**< Shifted mode APORT3CH8TO15 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH16TO23 << 24) /**< Shifted mode APORT3CH16TO23 for CSEN_SCANINPUTSEL1 */ +#define CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 (_CSEN_SCANINPUTSEL1_INPUT56TO63SEL_APORT3CH24TO31 << 24) /**< Shifted mode APORT3CH24TO31 for CSEN_SCANINPUTSEL1 */ + +/* Bit fields for CSEN APORTREQ */ +#define _CSEN_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTREQ */ +#define _CSEN_APORTREQ_MASK 0x000003FCUL /**< Mask for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _CSEN_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for CSEN_APORT1XREQ */ +#define _CSEN_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1XREQ_DEFAULT (_CSEN_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _CSEN_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for CSEN_APORT1YREQ */ +#define _CSEN_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT1YREQ_DEFAULT (_CSEN_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _CSEN_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for CSEN_APORT2XREQ */ +#define _CSEN_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2XREQ_DEFAULT (_CSEN_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _CSEN_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for CSEN_APORT2YREQ */ +#define _CSEN_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT2YREQ_DEFAULT (_CSEN_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _CSEN_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for CSEN_APORT3XREQ */ +#define _CSEN_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3XREQ_DEFAULT (_CSEN_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _CSEN_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for CSEN_APORT3YREQ */ +#define _CSEN_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT3YREQ_DEFAULT (_CSEN_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _CSEN_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for CSEN_APORT4XREQ */ +#define _CSEN_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4XREQ_DEFAULT (_CSEN_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _CSEN_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for CSEN_APORT4YREQ */ +#define _CSEN_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTREQ */ +#define CSEN_APORTREQ_APORT4YREQ_DEFAULT (_CSEN_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTREQ */ + +/* Bit fields for CSEN APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for CSEN_APORTCONFLICT */ +#define _CSEN_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for CSEN_APORT1XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for CSEN_APORT1YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORT2XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for CSEN_APORT2YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for CSEN_APORT3XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for CSEN_APORT3YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for CSEN_APORT4XCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for CSEN_APORT4YCONFLICT */ +#define _CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_APORTCONFLICT */ +#define CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_CSEN_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for CSEN_APORTCONFLICT */ + +/* Bit fields for CSEN CMPTHR */ +#define _CSEN_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_MASK 0x0000FFFFUL /**< Mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_SHIFT 0 /**< Shift value for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_MASK 0xFFFFUL /**< Bit mask for CSEN_CMPTHR */ +#define _CSEN_CMPTHR_CMPTHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_CMPTHR */ +#define CSEN_CMPTHR_CMPTHR_DEFAULT (_CSEN_CMPTHR_CMPTHR_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_CMPTHR */ + +/* Bit fields for CSEN EMA */ +#define _CSEN_EMA_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMA */ +#define _CSEN_EMA_MASK 0x003FFFFFUL /**< Mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_SHIFT 0 /**< Shift value for CSEN_EMA */ +#define _CSEN_EMA_EMA_MASK 0x3FFFFFUL /**< Bit mask for CSEN_EMA */ +#define _CSEN_EMA_EMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMA */ +#define CSEN_EMA_EMA_DEFAULT (_CSEN_EMA_EMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMA */ + +/* Bit fields for CSEN EMACTRL */ +#define _CSEN_EMACTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_MASK 0x00000007UL /**< Mask for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_SHIFT 0 /**< Shift value for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_MASK 0x7UL /**< Bit mask for CSEN_EMASAMPLE */ +#define _CSEN_EMACTRL_EMASAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W1 0x00000000UL /**< Mode W1 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W2 0x00000001UL /**< Mode W2 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W4 0x00000002UL /**< Mode W4 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W8 0x00000003UL /**< Mode W8 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W16 0x00000004UL /**< Mode W16 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W32 0x00000005UL /**< Mode W32 for CSEN_EMACTRL */ +#define _CSEN_EMACTRL_EMASAMPLE_W64 0x00000006UL /**< Mode W64 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_DEFAULT (_CSEN_EMACTRL_EMASAMPLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W1 (_CSEN_EMACTRL_EMASAMPLE_W1 << 0) /**< Shifted mode W1 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W2 (_CSEN_EMACTRL_EMASAMPLE_W2 << 0) /**< Shifted mode W2 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W4 (_CSEN_EMACTRL_EMASAMPLE_W4 << 0) /**< Shifted mode W4 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W8 (_CSEN_EMACTRL_EMASAMPLE_W8 << 0) /**< Shifted mode W8 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W16 (_CSEN_EMACTRL_EMASAMPLE_W16 << 0) /**< Shifted mode W16 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W32 (_CSEN_EMACTRL_EMASAMPLE_W32 << 0) /**< Shifted mode W32 for CSEN_EMACTRL */ +#define CSEN_EMACTRL_EMASAMPLE_W64 (_CSEN_EMACTRL_EMASAMPLE_W64 << 0) /**< Shifted mode W64 for CSEN_EMACTRL */ + +/* Bit fields for CSEN SINGLECTRL */ +#define _CSEN_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_MASK 0x000007F0UL /**< Mask for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_SHIFT 4 /**< Shift value for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_MASK 0x7F0UL /**< Bit mask for CSEN_SINGLESEL */ +#define _CSEN_SINGLECTRL_SINGLESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 0x00000061UL /**< Mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 0x00000062UL /**< Mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 0x00000063UL /**< Mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 0x00000064UL /**< Mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 0x00000065UL /**< Mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 0x00000066UL /**< Mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 0x00000067UL /**< Mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 0x00000068UL /**< Mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 0x00000069UL /**< Mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 0x0000006AUL /**< Mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 0x0000006BUL /**< Mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 0x0000006CUL /**< Mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 0x0000006DUL /**< Mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 0x0000006EUL /**< Mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 0x0000006FUL /**< Mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 0x00000070UL /**< Mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 0x00000071UL /**< Mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 0x00000072UL /**< Mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 0x00000073UL /**< Mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 0x00000074UL /**< Mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 0x00000075UL /**< Mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 0x00000076UL /**< Mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 0x00000077UL /**< Mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 0x00000078UL /**< Mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 0x00000079UL /**< Mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 0x0000007AUL /**< Mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 0x0000007BUL /**< Mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 0x0000007CUL /**< Mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 0x0000007DUL /**< Mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 0x0000007EUL /**< Mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_DEFAULT (_CSEN_SINGLECTRL_SINGLESEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0 << 4) /**< Shifted mode APORT3XCH0 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1 << 4) /**< Shifted mode APORT3YCH1 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2 << 4) /**< Shifted mode APORT3XCH2 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3 << 4) /**< Shifted mode APORT3YCH3 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4 << 4) /**< Shifted mode APORT3XCH4 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5 << 4) /**< Shifted mode APORT3YCH5 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6 << 4) /**< Shifted mode APORT3XCH6 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7 << 4) /**< Shifted mode APORT3YCH7 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8 << 4) /**< Shifted mode APORT3XCH8 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9 << 4) /**< Shifted mode APORT3YCH9 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10 << 4) /**< Shifted mode APORT3XCH10 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11 << 4) /**< Shifted mode APORT3YCH11 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12 << 4) /**< Shifted mode APORT3XCH12 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13 << 4) /**< Shifted mode APORT3YCH13 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14 << 4) /**< Shifted mode APORT3XCH14 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15 << 4) /**< Shifted mode APORT3YCH15 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16 << 4) /**< Shifted mode APORT3XCH16 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17 << 4) /**< Shifted mode APORT3YCH17 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18 << 4) /**< Shifted mode APORT3XCH18 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19 << 4) /**< Shifted mode APORT3YCH19 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20 << 4) /**< Shifted mode APORT3XCH20 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21 << 4) /**< Shifted mode APORT3YCH21 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22 << 4) /**< Shifted mode APORT3XCH22 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23 << 4) /**< Shifted mode APORT3YCH23 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24 << 4) /**< Shifted mode APORT3XCH24 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25 << 4) /**< Shifted mode APORT3YCH25 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26 << 4) /**< Shifted mode APORT3XCH26 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27 << 4) /**< Shifted mode APORT3YCH27 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28 << 4) /**< Shifted mode APORT3XCH28 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29 << 4) /**< Shifted mode APORT3YCH29 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 (_CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30 << 4) /**< Shifted mode APORT3XCH30 for CSEN_SINGLECTRL */ +#define CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 (_CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31 << 4) /**< Shifted mode APORT3YCH31 for CSEN_SINGLECTRL */ + +/* Bit fields for CSEN DMBASELINE */ +#define _CSEN_DMBASELINE_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_MASK 0xFFFFFFFFUL /**< Mask for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEUP_SHIFT 0 /**< Shift value for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_MASK 0xFFFFUL /**< Bit mask for CSEN_BASELINEUP */ +#define _CSEN_DMBASELINE_BASELINEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEUP_DEFAULT (_CSEN_DMBASELINE_BASELINEUP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ +#define _CSEN_DMBASELINE_BASELINEDN_SHIFT 16 /**< Shift value for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_MASK 0xFFFF0000UL /**< Bit mask for CSEN_BASELINEDN */ +#define _CSEN_DMBASELINE_BASELINEDN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMBASELINE */ +#define CSEN_DMBASELINE_BASELINEDN_DEFAULT (_CSEN_DMBASELINE_BASELINEDN_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMBASELINE */ + +/* Bit fields for CSEN DMCFG */ +#define _CSEN_DMCFG_RESETVALUE 0x00000000UL /**< Default value for CSEN_DMCFG */ +#define _CSEN_DMCFG_MASK 0x103F0FFFUL /**< Mask for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMG_SHIFT 0 /**< Shift value for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_MASK 0xFFUL /**< Bit mask for CSEN_DMG */ +#define _CSEN_DMCFG_DMG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMG_DEFAULT (_CSEN_DMCFG_DMG_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMR_SHIFT 8 /**< Shift value for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_MASK 0xF00UL /**< Bit mask for CSEN_DMR */ +#define _CSEN_DMCFG_DMR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMR_DEFAULT (_CSEN_DMCFG_DMR_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_DMCR_SHIFT 16 /**< Shift value for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_MASK 0xF0000UL /**< Bit mask for CSEN_DMCR */ +#define _CSEN_DMCFG_DMCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMCR_DEFAULT (_CSEN_DMCFG_DMCR_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_SHIFT 20 /**< Shift value for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_MASK 0x300000UL /**< Bit mask for CSEN_CRMODE */ +#define _CSEN_DMCFG_CRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM10 0x00000000UL /**< Mode DM10 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM12 0x00000001UL /**< Mode DM12 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM14 0x00000002UL /**< Mode DM14 for CSEN_DMCFG */ +#define _CSEN_DMCFG_CRMODE_DM16 0x00000003UL /**< Mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DEFAULT (_CSEN_DMCFG_CRMODE_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM10 (_CSEN_DMCFG_CRMODE_DM10 << 20) /**< Shifted mode DM10 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM12 (_CSEN_DMCFG_CRMODE_DM12 << 20) /**< Shifted mode DM12 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM14 (_CSEN_DMCFG_CRMODE_DM14 << 20) /**< Shifted mode DM14 for CSEN_DMCFG */ +#define CSEN_DMCFG_CRMODE_DM16 (_CSEN_DMCFG_CRMODE_DM16 << 20) /**< Shifted mode DM16 for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS (0x1UL << 28) /**< Disable delta modulator gain reduction. */ +#define _CSEN_DMCFG_DMGRDIS_SHIFT 28 /**< Shift value for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_MASK 0x10000000UL /**< Bit mask for CSEN_DMGRDIS */ +#define _CSEN_DMCFG_DMGRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_DMCFG */ +#define CSEN_DMCFG_DMGRDIS_DEFAULT (_CSEN_DMCFG_DMGRDIS_DEFAULT << 28) /**< Shifted mode DEFAULT for CSEN_DMCFG */ + +/* Bit fields for CSEN ANACTRL */ +#define _CSEN_ANACTRL_RESETVALUE 0x00000070UL /**< Default value for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_MASK 0x03730771UL /**< Mask for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF (0x1UL << 0) /**< Reference capacitor divide by half. */ +#define _CSEN_ANACTRL_CREFHALF_SHIFT 0 /**< Shift value for CSEN_CREFHALF */ +#define _CSEN_ANACTRL_CREFHALF_MASK 0x1UL /**< Bit mask for CSEN_CREFHALF */ +#define _CSEN_ANACTRL_CREFHALF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_CREFHALF_FULL 0x00000000UL /**< Mode FULL for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_CREFHALF_HALF 0x00000001UL /**< Mode HALF for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_DEFAULT (_CSEN_ANACTRL_CREFHALF_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_FULL (_CSEN_ANACTRL_CREFHALF_FULL << 0) /**< Shifted mode FULL for CSEN_ANACTRL */ +#define CSEN_ANACTRL_CREFHALF_HALF (_CSEN_ANACTRL_CREFHALF_HALF << 0) /**< Shifted mode HALF for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IREFPROG_SHIFT 4 /**< Shift value for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_MASK 0x70UL /**< Bit mask for CSEN_IREFPROG */ +#define _CSEN_ANACTRL_IREFPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IREFPROG_DEFAULT (_CSEN_ANACTRL_IREFPROG_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_IDACIREFS_SHIFT 8 /**< Shift value for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_MASK 0x700UL /**< Bit mask for CSEN_IDACIREFS */ +#define _CSEN_ANACTRL_IDACIREFS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_IDACIREFS_DEFAULT (_CSEN_ANACTRL_IDACIREFS_DEFAULT << 8) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_SHIFT 16 /**< Shift value for CSEN_DUTYSCALE */ +#define _CSEN_ANACTRL_DUTYSCALE_MASK 0x30000UL /**< Bit mask for CSEN_DUTYSCALE */ +#define _CSEN_ANACTRL_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV1 0x00000000UL /**< Mode DIV1 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV2 0x00000001UL /**< Mode DIV2 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV4 0x00000002UL /**< Mode DIV4 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_DUTYSCALE_DIV8 0x00000003UL /**< Mode DIV8 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DEFAULT (_CSEN_ANACTRL_DUTYSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV1 (_CSEN_ANACTRL_DUTYSCALE_DIV1 << 16) /**< Shifted mode DIV1 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV2 (_CSEN_ANACTRL_DUTYSCALE_DIV2 << 16) /**< Shifted mode DIV2 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV4 (_CSEN_ANACTRL_DUTYSCALE_DIV4 << 16) /**< Shifted mode DIV4 for CSEN_ANACTRL */ +#define CSEN_ANACTRL_DUTYSCALE_DIV8 (_CSEN_ANACTRL_DUTYSCALE_DIV8 << 16) /**< Shifted mode DIV8 for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_TRSTPROG_SHIFT 20 /**< Shift value for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_MASK 0x700000UL /**< Bit mask for CSEN_TRSTPROG */ +#define _CSEN_ANACTRL_TRSTPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_TRSTPROG_DEFAULT (_CSEN_ANACTRL_TRSTPROG_DEFAULT << 20) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_SHIFT 24 /**< Shift value for CSEN_BIASPROG */ +#define _CSEN_ANACTRL_BIASPROG_MASK 0x3000000UL /**< Bit mask for CSEN_BIASPROG */ +#define _CSEN_ANACTRL_BIASPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_ONEX 0x00000000UL /**< Mode ONEX for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_TWOX 0x00000001UL /**< Mode TWOX for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_ONETENTH 0x00000002UL /**< Mode ONETENTH for CSEN_ANACTRL */ +#define _CSEN_ANACTRL_BIASPROG_HALF 0x00000003UL /**< Mode HALF for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_DEFAULT (_CSEN_ANACTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_ONEX (_CSEN_ANACTRL_BIASPROG_ONEX << 24) /**< Shifted mode ONEX for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_TWOX (_CSEN_ANACTRL_BIASPROG_TWOX << 24) /**< Shifted mode TWOX for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_ONETENTH (_CSEN_ANACTRL_BIASPROG_ONETENTH << 24) /**< Shifted mode ONETENTH for CSEN_ANACTRL */ +#define CSEN_ANACTRL_BIASPROG_HALF (_CSEN_ANACTRL_BIASPROG_HALF << 24) /**< Shifted mode HALF for CSEN_ANACTRL */ + +/* Bit fields for CSEN IF */ +#define _CSEN_IF_RESETVALUE 0x00000000UL /**< Default value for CSEN_IF */ +#define _CSEN_IF_MASK 0x0000001FUL /**< Mask for CSEN_IF */ +#define CSEN_IF_CMP (0x1UL << 0) /**< CSEN Digital Comparator Interrupt Flag */ +#define _CSEN_IF_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IF_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IF_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CMP_DEFAULT (_CSEN_IF_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV (0x1UL << 1) /**< CSEN Conversion Done Interrupt Flag */ +#define _CSEN_IF_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IF_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IF_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_CONV_DEFAULT (_CSEN_IF_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS (0x1UL << 2) /**< CSEN End of Scan Interrupt Flag. */ +#define _CSEN_IF_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IF_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IF_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_EOS_DEFAULT (_CSEN_IF_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF (0x1UL << 3) /**< CSEN DMA Overflow Interrupt Flag. */ +#define _CSEN_IF_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IF_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_DMAOF_DEFAULT (_CSEN_IF_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT (0x1UL << 4) /**< APORT Conflict Interrupt Flag */ +#define _CSEN_IF_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IF */ +#define CSEN_IF_APORTCONFLICT_DEFAULT (_CSEN_IF_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IF */ + +/* Bit fields for CSEN IFS */ +#define _CSEN_IFS_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFS */ +#define _CSEN_IFS_MASK 0x0000001FUL /**< Mask for CSEN_IFS */ +#define CSEN_IFS_CMP (0x1UL << 0) /**< Set CMP Interrupt Flag */ +#define _CSEN_IFS_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFS_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFS_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CMP_DEFAULT (_CSEN_IFS_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV (0x1UL << 1) /**< Set CONV Interrupt Flag */ +#define _CSEN_IFS_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFS_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFS_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_CONV_DEFAULT (_CSEN_IFS_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS (0x1UL << 2) /**< Set EOS Interrupt Flag */ +#define _CSEN_IFS_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFS_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFS_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_EOS_DEFAULT (_CSEN_IFS_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF (0x1UL << 3) /**< Set DMAOF Interrupt Flag */ +#define _CSEN_IFS_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFS_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_DMAOF_DEFAULT (_CSEN_IFS_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT (0x1UL << 4) /**< Set APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFS_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFS */ +#define CSEN_IFS_APORTCONFLICT_DEFAULT (_CSEN_IFS_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFS */ + +/* Bit fields for CSEN IFC */ +#define _CSEN_IFC_RESETVALUE 0x00000000UL /**< Default value for CSEN_IFC */ +#define _CSEN_IFC_MASK 0x0000001FUL /**< Mask for CSEN_IFC */ +#define CSEN_IFC_CMP (0x1UL << 0) /**< Clear CMP Interrupt Flag */ +#define _CSEN_IFC_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IFC_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IFC_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CMP_DEFAULT (_CSEN_IFC_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV (0x1UL << 1) /**< Clear CONV Interrupt Flag */ +#define _CSEN_IFC_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IFC_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IFC_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_CONV_DEFAULT (_CSEN_IFC_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS (0x1UL << 2) /**< Clear EOS Interrupt Flag */ +#define _CSEN_IFC_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IFC_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IFC_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_EOS_DEFAULT (_CSEN_IFC_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF (0x1UL << 3) /**< Clear DMAOF Interrupt Flag */ +#define _CSEN_IFC_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IFC_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_DMAOF_DEFAULT (_CSEN_IFC_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT (0x1UL << 4) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _CSEN_IFC_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IFC */ +#define CSEN_IFC_APORTCONFLICT_DEFAULT (_CSEN_IFC_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IFC */ + +/* Bit fields for CSEN IEN */ +#define _CSEN_IEN_RESETVALUE 0x00000000UL /**< Default value for CSEN_IEN */ +#define _CSEN_IEN_MASK 0x0000001FUL /**< Mask for CSEN_IEN */ +#define CSEN_IEN_CMP (0x1UL << 0) /**< CMP Interrupt Enable */ +#define _CSEN_IEN_CMP_SHIFT 0 /**< Shift value for CSEN_CMP */ +#define _CSEN_IEN_CMP_MASK 0x1UL /**< Bit mask for CSEN_CMP */ +#define _CSEN_IEN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CMP_DEFAULT (_CSEN_IEN_CMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV (0x1UL << 1) /**< CONV Interrupt Enable */ +#define _CSEN_IEN_CONV_SHIFT 1 /**< Shift value for CSEN_CONV */ +#define _CSEN_IEN_CONV_MASK 0x2UL /**< Bit mask for CSEN_CONV */ +#define _CSEN_IEN_CONV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_CONV_DEFAULT (_CSEN_IEN_CONV_DEFAULT << 1) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS (0x1UL << 2) /**< EOS Interrupt Enable */ +#define _CSEN_IEN_EOS_SHIFT 2 /**< Shift value for CSEN_EOS */ +#define _CSEN_IEN_EOS_MASK 0x4UL /**< Bit mask for CSEN_EOS */ +#define _CSEN_IEN_EOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_EOS_DEFAULT (_CSEN_IEN_EOS_DEFAULT << 2) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF (0x1UL << 3) /**< DMAOF Interrupt Enable */ +#define _CSEN_IEN_DMAOF_SHIFT 3 /**< Shift value for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_MASK 0x8UL /**< Bit mask for CSEN_DMAOF */ +#define _CSEN_IEN_DMAOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_DMAOF_DEFAULT (_CSEN_IEN_DMAOF_DEFAULT << 3) /**< Shifted mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT (0x1UL << 4) /**< APORTCONFLICT Interrupt Enable */ +#define _CSEN_IEN_APORTCONFLICT_SHIFT 4 /**< Shift value for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_MASK 0x10UL /**< Bit mask for CSEN_APORTCONFLICT */ +#define _CSEN_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CSEN_IEN */ +#define CSEN_IEN_APORTCONFLICT_DEFAULT (_CSEN_IEN_APORTCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for CSEN_IEN */ + +/** @} End of group EFM32PG12B_CSEN */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_devinfo.h new file mode 100644 index 0000000000..93f0a33b9b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_devinfo.h @@ -0,0 +1,1274 @@ +/**************************************************************************//** + * @file efm32pg12b_devinfo.h + * @brief EFM32PG12B_DEVINFO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_DEVINFO + * @{ + *****************************************************************************/ + +typedef struct +{ + __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ + uint32_t RESERVED0[7]; /**< Reserved for future use **/ + __IM uint32_t EXTINFO; /**< External Component description */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ + __IM uint32_t EUI48H; /**< OUI */ + __IM uint32_t CUSTOMINFO; /**< Custom information */ + __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ + __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ + __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ + __IM uint32_t PART; /**< Part description */ + __IM uint32_t DEVINFOREV; /**< Device information page revision */ + __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ + uint32_t RESERVED3[2]; /**< Reserved for future use **/ + __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ + __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ + __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ + __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ + uint32_t RESERVED4[4]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED5[2]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED6[2]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ + __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ + __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ + __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ + __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ + uint32_t RESERVED8[11]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ + uint32_t RESERVED9[2]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ + uint32_t RESERVED10[2]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ + __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ + __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ + uint32_t RESERVED11[1]; /**< Reserved for future use **/ + __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ + __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ + __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ + uint32_t RESERVED12[11]; /**< Reserved for future use **/ + __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ + __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ + __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ + uint32_t RESERVED13[3]; /**< Reserved for future use **/ + __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ + __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ + uint32_t RESERVED14[2]; /**< Reserved for future use **/ + __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ + __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ + __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ + __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ + __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ + __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ + __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */ + __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */ + __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */ + __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ + __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ + __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ + __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ + __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */ + uint32_t RESERVED15[3]; /**< Reserved for future use **/ + __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ + __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ + __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ + __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ +} DEVINFO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_DEVINFO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO CAL */ +#define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ +#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ +#define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ +#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ +#define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ +#define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */ +#define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ +#define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ +#define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ +#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ + +/* Bit fields for DEVINFO UNIQUEL */ +#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ +#define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ + +/* Bit fields for DEVINFO UNIQUEH */ +#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ +#define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ +#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ +#define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ +#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ +#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ + +/* Bit fields for DEVINFO DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */ +#define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ + +/* Bit fields for DEVINFO ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ +#define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ + +/* Bit fields for DEVINFO ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ +#define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ +#define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ + +/* Bit fields for DEVINFO ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ +#define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ + +/* Bit fields for DEVINFO ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ +#define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ + +/* Bit fields for DEVINFO HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ +#define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ +#define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ +#define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ +#define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ +#define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ +#define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ +#define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ +#define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ +#define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ + +/* Bit fields for DEVINFO VMONCAL0 */ +#define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL1 */ +#define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ +#define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ + +/* Bit fields for DEVINFO VMONCAL2 */ +#define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */ +#define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */ + +/* Bit fields for DEVINFO IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ +#define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ + +/* Bit fields for DEVINFO IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ +#define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ + +/* Bit fields for DEVINFO DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ +#define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ +#define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ + +/* Bit fields for DEVINFO DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ +#define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ + +/* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ +#define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ + +/* Bit fields for DEVINFO VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */ +#define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */ + +/* Bit fields for DEVINFO VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */ +#define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */ + +/* Bit fields for DEVINFO VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */ +#define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */ + +/* Bit fields for DEVINFO OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */ +#define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */ +#define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */ +#define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */ +#define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */ +#define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */ +#define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */ +#define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */ +#define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */ +#define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */ +#define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */ +#define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */ +#define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */ +#define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */ + +/* Bit fields for DEVINFO OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */ +#define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */ +#define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */ +#define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */ +#define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */ +#define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */ +#define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */ +#define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */ +#define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */ +#define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */ +#define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */ +#define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/* Bit fields for DEVINFO OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */ +#define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ +#define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ +#define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ +#define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ +#define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ +#define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ +#define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */ +#define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ +#define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ +#define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ +#define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ +#define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ +#define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ + +/** @} End of group EFM32PG12B_DEVINFO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dma_descriptor.h new file mode 100644 index 0000000000..0374bc139c --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dma_descriptor.h @@ -0,0 +1,52 @@ +/**************************************************************************//** + * @file efm32pg12b_dma_descriptor.h + * @brief EFM32PG12B_DMA_DESCRIPTOR register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_DMA_DESCRIPTOR + * @{ + *****************************************************************************/ +typedef struct +{ + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dmareq.h new file mode 100644 index 0000000000..9834e69604 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dmareq.h @@ -0,0 +1,110 @@ +/**************************************************************************//** + * @file efm32pg12b_dmareq.h + * @brief EFM32PG12B_DMAREQ register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +/**************************************************************************//** + * @defgroup EFM32PG12B_DMAREQ_BitFields + * @{ + *****************************************************************************/ +#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */ +#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */ +#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ +#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ +#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */ +#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */ +#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ +#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ +#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ +#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ +#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ +#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ +#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */ +#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */ +#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ +#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ +#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ +#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */ +#define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */ +#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */ +#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */ +#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */ +#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ +#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ +#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ +#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ +#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ +#define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */ +#define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */ +#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ +#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ +#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ +#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ +#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ +#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ +#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ +#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ +#define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */ +#define DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */ +#define DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */ +#define DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */ +#define DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */ +#define DMAREQ_WTIMER1_UFOF ((27 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */ +#define DMAREQ_WTIMER1_CC0 ((27 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */ +#define DMAREQ_WTIMER1_CC1 ((27 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */ +#define DMAREQ_WTIMER1_CC2 ((27 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */ +#define DMAREQ_WTIMER1_CC3 ((27 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */ +#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ +#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR /**< Alias for DMAREQ_CRYPTO0_DATA0WR */ +#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR /**< Alias for DMAREQ_CRYPTO0_DATA0XWR */ +#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD /**< Alias for DMAREQ_CRYPTO0_DATA0RD */ +#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR /**< Alias for DMAREQ_CRYPTO0_DATA1WR */ +#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */ +#define DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD /**< Alias for DMAREQ_CRYPTO0_DATA1RD */ +#define DMAREQ_CSEN_DATA ((50 << 16) + 0) /**< DMA channel select for CSEN_DATA */ +#define DMAREQ_CSEN_BSLN ((50 << 16) + 1) /**< DMA channel select for CSEN_BSLN */ +#define DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */ +#define DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) /**< DMA channel select for CRYPTO1_DATA0WR */ +#define DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) /**< DMA channel select for CRYPTO1_DATA0XWR */ +#define DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) /**< DMA channel select for CRYPTO1_DATA0RD */ +#define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */ +#define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */ + +/** @} End of group EFM32PG12B_DMAREQ */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_emu.h new file mode 100644 index 0000000000..a30a40a569 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_emu.h @@ -0,0 +1,1437 @@ +/**************************************************************************//** + * @file efm32pg12b_emu.h + * @brief EFM32PG12B_EMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_EMU + * @{ + * @brief EFM32PG12B_EMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ + __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */ + __IM uint32_t TEMP; /**< Value of last temperature measurement */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ + __IOM uint32_t PWRCFG; /**< Power Configuration Register */ + __IOM uint32_t PWRCTRL; /**< Power Control Register. */ + __IOM uint32_t DCDCCTRL; /**< DCDC Control */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ + __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ + __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ + __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ + __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ + __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ + + uint32_t RESERVED4[1]; /**< Reserved for future use **/ + __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ + + uint32_t RESERVED5[5]; /**< Reserved for future use **/ + __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ + __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ + __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ + __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ + + uint32_t RESERVED6[5]; /**< Reserved for future use **/ + __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ + __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ + + uint32_t RESERVED7[12]; /**< Reserved for future use **/ + __IOM uint32_t DCDCLPEM01CFG; /**< Configuration bits for low power mode to be applied during EM01, this field is only relevant if LP mode is used in EM01. */ + + uint32_t RESERVED8[4]; /**< Reserved for future use **/ + __IOM uint32_t EM23PERNORETAINCMD; /**< Clears corresponding bits in EM23PERNORETAINSTATUS unlocking access to peripheral */ + __IM uint32_t EM23PERNORETAINSTATUS; /**< Status indicating if peripherals were powered down in EM23, subsequently locking access to it. */ + __IOM uint32_t EM23PERNORETAINCTRL; /**< When set corresponding peripherals may get powered down in EM23 */ +} EMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_EMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ +#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ +#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ +#define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ +#define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ +#define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ +#define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically configures Flash, Ram and Frequency to wakeup from EM2 or EM3 at low voltage */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ +#define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ +#define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0x0417011FUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */ +#define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ +#define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */ +#define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ +#define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */ +#define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ +#define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */ +#define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ +#define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */ +#define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ +#define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */ +#define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */ +#define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */ +#define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is busy Scaling Voltage */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ +#define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ +#define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU RAM0CTRL */ +#define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */ +#define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */ +#define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 0 */ +#define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ +#define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ +#define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ +#define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */ +#define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ +#define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */ +#define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ +#define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */ +#define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ +#define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */ +#define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ +#define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xE31FC0FFUL /**< Mask for EMU_IF */ +#define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ +#define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ +#define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ +#define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ +#define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ +#define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ +#define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ +#define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ +#define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */ +#define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */ +#define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */ +#define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */ +#define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */ +#define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IFS */ +#define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ +#define _EMU_IFS_MASK 0xE31FC0FFUL /**< Mask for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ +#define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ +#define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ +#define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */ +#define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ +#define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ +#define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ +#define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ +#define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ +#define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ +#define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ + +/* Bit fields for EMU IFC */ +#define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ +#define _EMU_IFC_MASK 0xE31FC0FFUL /**< Mask for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ +#define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ +#define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ +#define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */ +#define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ +#define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ +#define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ +#define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ +#define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ +#define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ +#define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ +#define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ +#define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xE31FC0FFUL /**< Mask for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ +#define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ +#define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ +#define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ +#define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ +#define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ +#define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ +#define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ +#define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ +#define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ +#define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ +#define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ +#define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ +#define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */ +#define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ +#define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ +#define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ +#define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ +#define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ +#define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ +#define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ +#define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ +#define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ +#define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU PWRLOCK */ +#define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ +#define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ +#define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ + +/* Bit fields for EMU PWRCFG */ +#define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */ +#define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_UNCONFIGURED 0x00000000UL /**< Mode UNCONFIGURED for EMU_PWRCFG */ +#define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_UNCONFIGURED (_EMU_PWRCFG_PWRCFG_UNCONFIGURED << 0) /**< Shifted mode UNCONFIGURED for EMU_PWRCFG */ +#define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */ + +/* Bit fields for EMU PWRCTRL */ +#define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_MASK 0x00001420UL /**< Mask for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ +#define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ +#define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This field selects the input for the regulator. */ +#define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ +#define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ +#define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ +#define EMU_PWRCTRL_DVDDBODDIS (0x1UL << 12) /**< DVDD BOD Disable */ +#define _EMU_PWRCTRL_DVDDBODDIS_SHIFT 12 /**< Shift value for EMU_DVDDBODDIS */ +#define _EMU_PWRCTRL_DVDDBODDIS_MASK 0x1000UL /**< Bit mask for EMU_DVDDBODDIS */ +#define _EMU_PWRCTRL_DVDDBODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ +#define EMU_PWRCTRL_DVDDBODDIS_DEFAULT (_EMU_PWRCTRL_DVDDBODDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ + +/* Bit fields for EMU DCDCCTRL */ +#define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ +#define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ +#define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ +#define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ + +/* Bit fields for EMU DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP mode hysteresis in the state machine control */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator threshold on the high side */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ +#define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC into CCM mode immediately, based on LNFORCECCM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ +#define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ +#define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ +#define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ +#define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ +#define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ +#define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ +#define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ + +/* Bit fields for EMU DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ +#define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ +#define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ +#define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ + +/* Bit fields for EMU DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ +#define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ +#define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ +#define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ + +/* Bit fields for EMU DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ +#define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ +#define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ + +/* Bit fields for EMU DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ +#define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ +#define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ +#define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ +#define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ +#define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ + +/* Bit fields for EMU DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */ +#define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ +#define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ +#define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ +#define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ +#define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ + +/* Bit fields for EMU DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ +#define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ +#define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ +#define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ +#define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ +#define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ + +/* Bit fields for EMU DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ +#define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ +#define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ +#define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ + +/* Bit fields for EMU DCDCSYNC */ +#define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ +#define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ +#define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ +#define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ + +/* Bit fields for EMU VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ +#define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ +#define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ +#define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ + +/* Bit fields for EMU VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ +#define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ + +/* Bit fields for EMU VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ +#define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ + +/* Bit fields for EMU VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ +#define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ +#define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ +#define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ +#define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ +#define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ +#define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */ +#define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ +#define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ +#define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ +#define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ +#define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ + +/* Bit fields for EMU RAM1CTRL */ +#define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_MASK 0x00000003UL /**< Mask for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL /**< Mode BLK1 for EMU_RAM1CTRL */ +#define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0) /**< Shifted mode BLK1 for EMU_RAM1CTRL */ +#define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for EMU_RAM1CTRL */ + +/* Bit fields for EMU RAM2CTRL */ +#define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_MASK 0x00000001UL /**< Mask for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL /**< Bit mask for EMU_RAMPOWERDOWN */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ +#define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL /**< Mode BLK for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ +#define EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0) /**< Shifted mode BLK for EMU_RAM2CTRL */ + +/* Bit fields for EMU DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ +#define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ +#define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ + +/* Bit fields for EMU EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears status bit of ACMP0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears status bit of ACMP1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears status bit of PCNT0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears status bit of PCNT1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears status bit of PCNT2 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears status bit of I2C0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears status bit of I2C1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears status bit of DAC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears status bit of IDAC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears status bit of ADC0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears status bit of LETIMER0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears status bit of WDOG0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears status bit of WDOG1 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears status bit of LESENSE0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears status bit of CSEN and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ +#define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears status bit of LEUART0 and unlocks access to it */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ +#define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ +#define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ + +/* Bit fields for EMU EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ +#define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates if ACMP0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates if ACMP1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates if PCNT0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates if PCNT1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates if PCNT2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates if I2C0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates if I2C1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates if DAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates if IDAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates if ADC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates if LETIMER0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates if WDOG0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates if WDOG1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates if LESENSE0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates if CSEN powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates if LEUART0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ +#define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ +#define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ + +/* Bit fields for EMU EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ +#define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow power down of ACMP0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow power down of ACMP1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ +#define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow power down of PCNT0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow power down of PCNT1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow power down of PCNT2 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ +#define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow power down of I2C0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow power down of I2C1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ +#define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7) /**< Allow power down of DAC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7 /**< Shift value for EMU_DAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL /**< Bit mask for EMU_DAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow power down of IDAC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow power down of ADC0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ +#define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow power down of LETIMER0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow power down of WDOG0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow power down of WDOG1 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ +#define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow power down of LESENSE0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow power down of CSEN during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ +#define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow power down of LEUART0 during EM23 */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ +#define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ +#define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ + +/** @} End of group EFM32PG12B_EMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_etm.h new file mode 100644 index 0000000000..cc5c1862c5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_etm.h @@ -0,0 +1,781 @@ +/**************************************************************************//** + * @file efm32pg12b_etm.h + * @brief EFM32PG12B_ETM register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_ETM + * @{ + * @brief EFM32PG12B_ETM Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t ETMCR; /**< Main Control Register */ + __IM uint32_t ETMCCR; /**< Configuration Code Register */ + __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMSR; /**< ETM Status Register */ + __IM uint32_t ETMSCR; /**< ETM System Configuration Register */ + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */ + __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */ + uint32_t RESERVED3[68]; /**< Reserved for future use **/ + __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */ + uint32_t RESERVED4[39]; /**< Reserved for future use **/ + __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */ + __IM uint32_t ETMIDR; /**< ID Register */ + __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */ + uint32_t RESERVED5[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */ + uint32_t RESERVED6[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */ + uint32_t RESERVED7[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */ + uint32_t RESERVED8[1]; /**< Reserved for future use **/ + __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */ + uint32_t RESERVED9[66]; /**< Reserved for future use **/ + __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */ + uint32_t RESERVED10[754]; /**< Reserved for future use **/ + __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */ + uint32_t RESERVED11[1]; /**< Reserved for future use **/ + __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */ + uint32_t RESERVED12[1]; /**< Reserved for future use **/ + __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */ + uint32_t RESERVED13[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */ + uint32_t RESERVED14[1]; /**< Reserved for future use **/ + __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */ + uint32_t RESERVED15[39]; /**< Reserved for future use **/ + __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */ + __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */ + uint32_t RESERVED16[2]; /**< Reserved for future use **/ + __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */ + __IM uint32_t ETMLSR; /**< Lock Status Register */ + __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */ + uint32_t RESERVED17[4]; /**< Reserved for future use **/ + __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */ + __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */ + __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */ + __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */ + __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */ + __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */ + __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */ + __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */ + __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */ + __IM uint32_t ETMCIDR0; /**< Component ID0 Register */ + __IM uint32_t ETMCIDR1; /**< Component ID1 Register */ + __IM uint32_t ETMCIDR2; /**< Component ID2 Register */ + __IM uint32_t ETMCIDR3; /**< Component ID3 Register */ +} ETM_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_ETM_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for ETM ETMCR */ +#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */ +#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */ +#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */ +#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */ +#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */ +#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */ +#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */ +#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */ +#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */ +#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */ +#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */ +#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */ +#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */ +#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */ +#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */ +#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */ +#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */ +#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */ +#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */ +#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */ +#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */ +#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ +#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */ + +/* Bit fields for ETM ETMCCR */ +#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */ +#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */ +#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */ +#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */ +#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */ +#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */ +#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */ +#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */ +#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */ +#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */ +#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */ +#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */ +#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */ +#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */ +#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */ +#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */ +#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */ +#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */ +#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */ +#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */ +#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ +#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */ + +/* Bit fields for ETM ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ +#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */ +#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ +#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ + +/* Bit fields for ETM ETMSR */ +#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */ +#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */ +#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */ +#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */ +#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */ +#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */ +#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */ +#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */ +#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */ +#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ +#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */ + +/* Bit fields for ETM ETMSCR */ +#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */ +#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */ +#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */ +#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */ +#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */ +#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */ +#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */ +#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */ +#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */ +#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */ +#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */ +#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */ +#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */ +#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */ +#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ +#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */ + +/* Bit fields for ETM ETMTEEVR */ +#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ +#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ +#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ +#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */ +#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ +#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ + +/* Bit fields for ETM ETMTECR1 */ +#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */ +#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */ +#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */ +#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */ +#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */ +#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */ +#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */ +#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */ +#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */ + +/* Bit fields for ETM ETMFFLR */ +#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */ +#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */ +#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */ +#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */ + +/* Bit fields for ETM ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */ +#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */ +#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */ + +/* Bit fields for ETM ETMSYNCFR */ +#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */ +#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */ +#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */ +#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */ + +/* Bit fields for ETM ETMIDR */ +#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */ +#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */ +#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */ +#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */ +#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */ +#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */ +#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */ +#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */ +#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */ +#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */ +#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */ +#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */ +#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */ +#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */ +#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */ +#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */ +#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */ +#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */ + +/* Bit fields for ETM ETMCCER */ +#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */ +#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */ +#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */ +#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */ +#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */ +#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */ +#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */ +#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */ +#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */ +#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ +#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */ +#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */ +#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */ +#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */ +#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */ +#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */ +#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */ +#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */ +#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */ +#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */ +#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */ +#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */ +#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ +#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */ + +/* Bit fields for ETM ETMTESSEICR */ +#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */ +#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ +#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */ +#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ +#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ + +/* Bit fields for ETM ETMTSEVR */ +#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */ +#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */ +#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ +#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */ +#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ +#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ + +/* Bit fields for ETM ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */ +#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */ +#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */ +#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */ + +/* Bit fields for ETM ETMIDR2 */ +#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */ +#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */ +#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */ +#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */ +#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */ +#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */ +#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */ + +/* Bit fields for ETM ETMPDSR */ +#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */ +#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */ +#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */ +#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */ +#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */ + +/* Bit fields for ETM ETMISCIN */ +#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */ +#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */ +#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */ +#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */ +#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ +#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ + +/* Bit fields for ETM ITTRIGOUT */ +#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */ +#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */ +#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */ +#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */ + +/* Bit fields for ETM ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */ +#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */ +#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */ +#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */ +#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */ + +/* Bit fields for ETM ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */ +#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */ +#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */ +#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */ +#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */ + +/* Bit fields for ETM ETMITCTRL */ +#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */ +#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */ +#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */ +#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */ +#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */ + +/* Bit fields for ETM ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */ +#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */ +#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */ +#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */ + +/* Bit fields for ETM ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */ +#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */ +#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */ +#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */ +#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */ + +/* Bit fields for ETM ETMLAR */ +#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */ +#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */ +#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */ +#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */ +#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */ +#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */ + +/* Bit fields for ETM ETMLSR */ +#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */ +#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */ +#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */ +#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */ +#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */ +#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ +#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */ + +/* Bit fields for ETM ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */ +#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ +#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ + +/* Bit fields for ETM ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */ +#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */ +#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ +#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ + +/* Bit fields for ETM ETMPIDR4 */ +#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */ +#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ +#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */ +#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ +#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ + +/* Bit fields for ETM ETMPIDR5 */ +#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */ +#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */ + +/* Bit fields for ETM ETMPIDR6 */ +#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */ +#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */ + +/* Bit fields for ETM ETMPIDR7 */ +#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */ +#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */ + +/* Bit fields for ETM ETMPIDR0 */ +#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */ +#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */ +#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */ + +/* Bit fields for ETM ETMPIDR1 */ +#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */ +#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ +#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */ +#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ + +/* Bit fields for ETM ETMPIDR2 */ +#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */ +#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */ +#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */ +#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ +#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */ +#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */ +#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ +#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ + +/* Bit fields for ETM ETMPIDR3 */ +#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */ +#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ +#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */ +#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ +#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ + +/* Bit fields for ETM ETMCIDR0 */ +#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */ +#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */ +#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */ + +/* Bit fields for ETM ETMCIDR1 */ +#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */ +#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */ +#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */ + +/* Bit fields for ETM ETMCIDR2 */ +#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */ +#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */ +#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */ + +/* Bit fields for ETM ETMCIDR3 */ +#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */ +#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ +#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */ +#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */ + +/** @} End of group EFM32PG12B_ETM */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_fpueh.h new file mode 100644 index 0000000000..da66b3f2ac --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_fpueh.h @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file efm32pg12b_fpueh.h + * @brief EFM32PG12B_FPUEH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_FPUEH + * @{ + * @brief EFM32PG12B_FPUEH Register Declaration + *****************************************************************************/ +typedef struct +{ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} FPUEH_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_FPUEH_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for FPUEH IF */ +#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */ +#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */ +#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */ +#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */ +#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */ +#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */ +#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */ +#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */ +#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */ +#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */ + +/* Bit fields for FPUEH IFS */ +#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */ +#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */ +#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */ +#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */ +#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */ +#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */ +#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */ +#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */ +#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */ + +/* Bit fields for FPUEH IFC */ +#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */ +#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */ +#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */ +#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */ +#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */ +#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */ +#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */ +#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */ +#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */ + +/* Bit fields for FPUEH IEN */ +#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */ +#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */ +#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */ +#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */ +#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */ +#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */ +#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */ +#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */ +#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */ +#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */ +#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */ +#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */ +#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */ +#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */ +#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */ + +/** @} End of group EFM32PG12B_FPUEH */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpcrc.h new file mode 100644 index 0000000000..a8d497ecb4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpcrc.h @@ -0,0 +1,185 @@ +/**************************************************************************//** + * @file efm32pg12b_gpcrc.h + * @brief EFM32PG12B_GPCRC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_GPCRC + * @{ + * @brief EFM32PG12B_GPCRC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_GPCRC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */ +#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */ +#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFM32PG12B_GPCRC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio.h new file mode 100644 index 0000000000..f78983345a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio.h @@ -0,0 +1,1538 @@ +/**************************************************************************//** + * @file efm32pg12b_gpio.h + * @brief EFM32PG12B_GPIO register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_GPIO + * @{ + * @brief EFM32PG12B_GPIO Register Declaration + *****************************************************************************/ +typedef struct +{ + GPIO_P_TypeDef P[12]; /**< Port configuration bits */ + + uint32_t RESERVED0[112]; /**< Reserved for future use **/ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */ + __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low Register */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High Register */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */ + __IOM uint32_t EXTILEVEL; /**< External Interrupt Level Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wake up Enable Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register 1 */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t INSENSE; /**< Input Sense Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} GPIO_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_GPIO_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for GPIO P_CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00500050UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10711071UL /**< Mask for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH (0x1UL << 0) /**< Drive strength for port */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_MASK 0x1UL /**< Bit mask for GPIO_DRIVESTRENGTH */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTH_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_STRONG (_GPIO_P_CTRL_DRIVESTRENGTH_STRONG << 0) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTH_WEAK (_GPIO_P_CTRL_DRIVESTRENGTH_WEAK << 0) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT (0x1UL << 16) /**< Alternate drive strength for port */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_SHIFT 16 /**< Shift value for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK 0x10000UL /**< Bit mask for GPIO_DRIVESTRENGTHALT */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG 0x00000000UL /**< Mode STRONG for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK 0x00000001UL /**< Mode WEAK for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT (_GPIO_P_CTRL_DRIVESTRENGTHALT_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG (_GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG << 16) /**< Shifted mode STRONG for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK (_GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK << 16) /**< Shifted mode WEAK for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000005UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Alternate Data In Disable */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO P_MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL */ + +/* Bit fields for GPIO P_MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */ +#define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_PUSHPULLALT (_GPIO_P_MODEH_MODE8_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALT (_GPIO_P_MODEH_MODE8_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */ +#define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_PUSHPULLALT (_GPIO_P_MODEH_MODE9_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALT (_GPIO_P_MODEH_MODE9_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */ +#define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_PUSHPULLALT (_GPIO_P_MODEH_MODE10_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALT (_GPIO_P_MODEH_MODE10_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */ +#define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_PUSHPULLALT (_GPIO_P_MODEH_MODE11_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALT (_GPIO_P_MODEH_MODE11_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */ +#define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_PUSHPULLALT (_GPIO_P_MODEH_MODE12_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALT (_GPIO_P_MODEH_MODE12_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */ +#define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_PUSHPULLALT (_GPIO_P_MODEH_MODE13_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALT (_GPIO_P_MODEH_MODE13_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */ +#define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_PUSHPULLALT (_GPIO_P_MODEH_MODE14_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALT (_GPIO_P_MODEH_MODE14_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */ +#define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_PUSHPULLALT (_GPIO_P_MODEH_MODE15_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALT (_GPIO_P_MODEH_MODE15_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH */ + +/* Bit fields for GPIO P_DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */ +#define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */ +#define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */ + +/* Bit fields for GPIO P_DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ + +/* Bit fields for GPIO P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */ +#define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */ +#define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */ + +/* Bit fields for GPIO P_OVTDIS */ +#define _GPIO_P_OVTDIS_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_MASK 0x0000FFFFUL /**< Mask for GPIO_P_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_SHIFT 0 /**< Shift value for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_MASK 0xFFFFUL /**< Bit mask for GPIO_OVTDIS */ +#define _GPIO_P_OVTDIS_OVTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_OVTDIS */ +#define GPIO_P_OVTDIS_OVTDIS_DEFAULT (_GPIO_P_OVTDIS_OVTDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_OVTDIS */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTI (_GPIO_EXTIPSELL_EXTIPSEL0_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL0_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTK (_GPIO_EXTIPSELL_EXTIPSEL0_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTI (_GPIO_EXTIPSELL_EXTIPSEL1_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL1_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTK (_GPIO_EXTIPSELL_EXTIPSEL1_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTI (_GPIO_EXTIPSELL_EXTIPSEL2_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL2_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTK (_GPIO_EXTIPSELL_EXTIPSEL2_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTI (_GPIO_EXTIPSELL_EXTIPSEL3_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL3_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTK (_GPIO_EXTIPSELL_EXTIPSEL3_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTI (_GPIO_EXTIPSELL_EXTIPSEL4_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL4_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTK (_GPIO_EXTIPSELL_EXTIPSEL4_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTI (_GPIO_EXTIPSELL_EXTIPSEL5_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL5_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTK (_GPIO_EXTIPSELL_EXTIPSEL5_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTI (_GPIO_EXTIPSELL_EXTIPSEL6_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL6_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTK (_GPIO_EXTIPSELL_EXTIPSEL6_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTI (_GPIO_EXTIPSELL_EXTIPSEL7_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTJ (_GPIO_EXTIPSELL_EXTIPSEL7_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTK (_GPIO_EXTIPSELL_EXTIPSEL7_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0xFUL /**< Bit mask for GPIO_EXTIPSEL8 */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL8_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTI (_GPIO_EXTIPSELH_EXTIPSEL8_PORTI << 0) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL8_PORTJ << 0) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL8_PORTK (_GPIO_EXTIPSELH_EXTIPSEL8_PORTK << 0) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0xF0UL /**< Bit mask for GPIO_EXTIPSEL9 */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL9_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTI (_GPIO_EXTIPSELH_EXTIPSEL9_PORTI << 4) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL9_PORTJ << 4) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL9_PORTK (_GPIO_EXTIPSELH_EXTIPSEL9_PORTK << 4) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0xF00UL /**< Bit mask for GPIO_EXTIPSEL10 */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL10_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTI (_GPIO_EXTIPSELH_EXTIPSEL10_PORTI << 8) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL10_PORTJ << 8) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL10_PORTK (_GPIO_EXTIPSELH_EXTIPSEL10_PORTK << 8) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0xF000UL /**< Bit mask for GPIO_EXTIPSEL11 */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL11_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTI (_GPIO_EXTIPSELH_EXTIPSEL11_PORTI << 12) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL11_PORTJ << 12) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL11_PORTK (_GPIO_EXTIPSELH_EXTIPSEL11_PORTK << 12) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0xF0000UL /**< Bit mask for GPIO_EXTIPSEL12 */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL12_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTI (_GPIO_EXTIPSELH_EXTIPSEL12_PORTI << 16) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL12_PORTJ << 16) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL12_PORTK (_GPIO_EXTIPSELH_EXTIPSEL12_PORTK << 16) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0xF00000UL /**< Bit mask for GPIO_EXTIPSEL13 */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL13_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTI (_GPIO_EXTIPSELH_EXTIPSEL13_PORTI << 20) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL13_PORTJ << 20) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL13_PORTK (_GPIO_EXTIPSELH_EXTIPSEL13_PORTK << 20) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0xF000000UL /**< Bit mask for GPIO_EXTIPSEL14 */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL14_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTI (_GPIO_EXTIPSELH_EXTIPSEL14_PORTI << 24) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL14_PORTJ << 24) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL14_PORTK (_GPIO_EXTIPSELH_EXTIPSEL14_PORTK << 24) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0xF0000000UL /**< Bit mask for GPIO_EXTIPSEL15 */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTI 0x00000008UL /**< Mode PORTI for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTJ 0x00000009UL /**< Mode PORTJ for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL15_PORTK 0x0000000AUL /**< Mode PORTK for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTI (_GPIO_EXTIPSELH_EXTIPSEL15_PORTI << 28) /**< Shifted mode PORTI for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTJ (_GPIO_EXTIPSELH_EXTIPSEL15_PORTJ << 28) /**< Shifted mode PORTJ for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL15_PORTK (_GPIO_EXTIPSELH_EXTIPSEL15_PORTK << 28) /**< Shifted mode PORTK for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN4 << 16) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN5 << 16) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN6 << 16) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN7 << 16) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN4 << 20) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN5 << 20) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN6 << 20) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN7 << 20) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN4 << 24) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN5 << 24) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN6 << 24) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN7 << 24) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 0x00000000UL /**< Mode PIN4 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 0x00000001UL /**< Mode PIN5 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 0x00000002UL /**< Mode PIN6 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 0x00000003UL /**< Mode PIN7 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN4 << 28) /**< Shifted mode PIN4 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN5 << 28) /**< Shifted mode PIN5 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN6 << 28) /**< Shifted mode PIN6 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN7 << 28) /**< Shifted mode PIN7 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x32103210UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL8 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL8_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL9 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL9_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL10 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL10_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL11 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL11_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL12 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN12 << 16) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN13 << 16) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN14 << 16) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL12_PIN15 << 16) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL13 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN12 << 20) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN13 << 20) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN14 << 20) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL13_PIN15 << 20) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL14 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN12 << 24) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN13 << 24) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN14 << 24) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL14_PIN15 << 24) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL15 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 0x00000000UL /**< Mode PIN12 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 0x00000001UL /**< Mode PIN13 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 0x00000002UL /**< Mode PIN14 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 0x00000003UL /**< Mode PIN15 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN12 << 28) /**< Shifted mode PIN12 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN13 << 28) /**< Shifted mode PIN13 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN14 << 28) /**< Shifted mode PIN14 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 (_GPIO_EXTIPINSELH_EXTIPINSEL15_PIN15 << 28) /**< Shifted mode PIN15 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO EXTILEVEL */ +#define _GPIO_EXTILEVEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTILEVEL */ +#define _GPIO_EXTILEVEL_MASK 0x13130000UL /**< Mask for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0 (0x1UL << 16) /**< EM4 Wake Up Level for EM4WU0 Pin */ +#define _GPIO_EXTILEVEL_EM4WU0_SHIFT 16 /**< Shift value for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WU0 */ +#define _GPIO_EXTILEVEL_EM4WU0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU0_DEFAULT (_GPIO_EXTILEVEL_EM4WU0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1 (0x1UL << 17) /**< EM4 Wake Up Level for EM4WU1 Pin */ +#define _GPIO_EXTILEVEL_EM4WU1_SHIFT 17 /**< Shift value for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WU1 */ +#define _GPIO_EXTILEVEL_EM4WU1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU1_DEFAULT (_GPIO_EXTILEVEL_EM4WU1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4 (0x1UL << 20) /**< EM4 Wake Up Level for EM4WU4 Pin */ +#define _GPIO_EXTILEVEL_EM4WU4_SHIFT 20 /**< Shift value for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WU4 */ +#define _GPIO_EXTILEVEL_EM4WU4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU4_DEFAULT (_GPIO_EXTILEVEL_EM4WU4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8 (0x1UL << 24) /**< EM4 Wake Up Level for EM4WU8 Pin */ +#define _GPIO_EXTILEVEL_EM4WU8_SHIFT 24 /**< Shift value for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WU8 */ +#define _GPIO_EXTILEVEL_EM4WU8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU8_DEFAULT (_GPIO_EXTILEVEL_EM4WU8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9 (0x1UL << 25) /**< EM4 Wake Up Level for EM4WU9 Pin */ +#define _GPIO_EXTILEVEL_EM4WU9_SHIFT 25 /**< Shift value for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WU9 */ +#define _GPIO_EXTILEVEL_EM4WU9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU9_DEFAULT (_GPIO_EXTILEVEL_EM4WU9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU12 (0x1UL << 28) /**< EM4 Wake Up Level for EM4WU12 Pin */ +#define _GPIO_EXTILEVEL_EM4WU12_SHIFT 28 /**< Shift value for GPIO_EM4WU12 */ +#define _GPIO_EXTILEVEL_EM4WU12_MASK 0x10000000UL /**< Bit mask for GPIO_EM4WU12 */ +#define _GPIO_EXTILEVEL_EM4WU12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTILEVEL */ +#define GPIO_EXTILEVEL_EM4WU12_DEFAULT (_GPIO_EXTILEVEL_EM4WU12_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTILEVEL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IF */ +#define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IFS */ +#define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */ +#define _GPIO_IFS_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFS */ +#define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */ +#define _GPIO_IFS_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFS_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */ +#define GPIO_IFS_EM4WU_DEFAULT (_GPIO_IFS_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFS */ + +/* Bit fields for GPIO IFC */ +#define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */ +#define _GPIO_IFC_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IFC */ +#define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */ +#define _GPIO_IFC_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IFC_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */ +#define GPIO_IFC_EM4WU_DEFAULT (_GPIO_IFC_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IFC */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IEN */ +#define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */ +#define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */ +#define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define _GPIO_IEN_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WU_DEFAULT (_GPIO_IEN_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0xFFFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO ROUTEPEN */ +#define _GPIO_ROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_ROUTEPEN */ +#define _GPIO_ROUTEPEN_MASK 0x001F001FUL /**< Mask for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Serial Wire Clock and JTAG Test Clock Pin Enable */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_ROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Serial Wire Data and JTAG Test Mode Select Pin Enable */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_ROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_ROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_ROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDOPEN_DEFAULT (_GPIO_ROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_ROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_ROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_TDIPEN_DEFAULT (_GPIO_ROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN (0x1UL << 4) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_ROUTEPEN_SWVPEN_SHIFT 4 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_MASK 0x10UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_ROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_SWVPEN_DEFAULT (_GPIO_ROUTEPEN_SWVPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN (0x1UL << 16) /**< ETM Trace Clock Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_SHIFT 16 /**< Shift value for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_MASK 0x10000UL /**< Bit mask for GPIO_ETMTCLKPEN */ +#define _GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT (_GPIO_ROUTEPEN_ETMTCLKPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN (0x1UL << 17) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_SHIFT 17 /**< Shift value for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_MASK 0x20000UL /**< Bit mask for GPIO_ETMTD0PEN */ +#define _GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD0PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN (0x1UL << 18) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_SHIFT 18 /**< Shift value for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_MASK 0x40000UL /**< Bit mask for GPIO_ETMTD1PEN */ +#define _GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD1PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN (0x1UL << 19) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_SHIFT 19 /**< Shift value for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_MASK 0x80000UL /**< Bit mask for GPIO_ETMTD2PEN */ +#define _GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD2PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN (0x1UL << 20) /**< ETM Trace Data Pin Enable */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_SHIFT 20 /**< Shift value for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_MASK 0x100000UL /**< Bit mask for GPIO_ETMTD3PEN */ +#define _GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTEPEN */ +#define GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT (_GPIO_ROUTEPEN_ETMTD3PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTEPEN */ + +/* Bit fields for GPIO ROUTELOC0 */ +#define _GPIO_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_MASK 0x00000003UL /**< Mask for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_SHIFT 0 /**< Shift value for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_MASK 0x3UL /**< Bit mask for GPIO_SWVLOC */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC0 */ +#define _GPIO_ROUTELOC0_SWVLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC0 (_GPIO_ROUTELOC0_SWVLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_DEFAULT (_GPIO_ROUTELOC0_SWVLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC1 (_GPIO_ROUTELOC0_SWVLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC2 (_GPIO_ROUTELOC0_SWVLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC0 */ +#define GPIO_ROUTELOC0_SWVLOC_LOC3 (_GPIO_ROUTELOC0_SWVLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC0 */ + +/* Bit fields for GPIO ROUTELOC1 */ +#define _GPIO_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_MASK 0x0C30C303UL /**< Mask for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_SHIFT 0 /**< Shift value for GPIO_ETMTCLKLOC */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_MASK 0x3UL /**< Bit mask for GPIO_ETMTCLKLOC */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT (_GPIO_ROUTELOC1_ETMTCLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 (_GPIO_ROUTELOC1_ETMTCLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_SHIFT 8 /**< Shift value for GPIO_ETMTD0LOC */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_MASK 0x300UL /**< Bit mask for GPIO_ETMTD0LOC */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD0LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC0 << 8) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD0LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC1 << 8) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC2 << 8) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD0LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD0LOC_LOC3 << 8) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_SHIFT 14 /**< Shift value for GPIO_ETMTD1LOC */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_MASK 0xC000UL /**< Bit mask for GPIO_ETMTD1LOC */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD1LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC0 << 14) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD1LOC_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC1 << 14) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC2 << 14) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD1LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD1LOC_LOC3 << 14) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_SHIFT 20 /**< Shift value for GPIO_ETMTD2LOC */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_MASK 0x300000UL /**< Bit mask for GPIO_ETMTD2LOC */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD2LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC0 << 20) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD2LOC_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC1 << 20) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC2 << 20) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD2LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD2LOC_LOC3 << 20) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_SHIFT 26 /**< Shift value for GPIO_ETMTD3LOC */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_MASK 0xC000000UL /**< Bit mask for GPIO_ETMTD3LOC */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTELOC1 */ +#define _GPIO_ROUTELOC1_ETMTD3LOC_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC0 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC0 << 26) /**< Shifted mode LOC0 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT (_GPIO_ROUTELOC1_ETMTD3LOC_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC1 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC1 << 26) /**< Shifted mode LOC1 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC2 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC2 << 26) /**< Shifted mode LOC2 for GPIO_ROUTELOC1 */ +#define GPIO_ROUTELOC1_ETMTD3LOC_LOC3 (_GPIO_ROUTELOC1_ETMTD3LOC_LOC3 << 26) /**< Shifted mode LOC3 for GPIO_ROUTELOC1 */ + +/* Bit fields for GPIO INSENSE */ +#define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */ +#define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */ +#define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */ +#define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */ +#define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */ +#define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU (0x1UL << 1) /**< EM4WU Interrupt Sense Enable */ +#define _GPIO_INSENSE_EM4WU_SHIFT 1 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_MASK 0x2UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_INSENSE_EM4WU_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */ +#define GPIO_INSENSE_EM4WU_DEFAULT (_GPIO_INSENSE_EM4WU_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/** @} End of group EFM32PG12B_GPIO */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio_p.h new file mode 100644 index 0000000000..832c4e77e8 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio_p.h @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file efm32pg12b_gpio_p.h + * @brief EFM32PG12B_GPIO_P register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief GPIO_P EFM32PG12B GPIO P + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Port Control Register */ + __IOM uint32_t MODEL; /**< Port Pin Mode Low Register */ + __IOM uint32_t MODEH; /**< Port Pin Mode High Register */ + __IOM uint32_t DOUT; /**< Port Data Out Register */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */ + __IM uint32_t DIN; /**< Port Data In Register */ + __IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t OVTDIS; /**< Over Voltage Disable for all modes */ + uint32_t RESERVED2[1]; /**< Reserved future */ +} GPIO_P_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_i2c.h new file mode 100644 index 0000000000..0498ae4275 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_i2c.h @@ -0,0 +1,921 @@ +/**************************************************************************//** + * @file efm32pg12b_i2c.h + * @brief EFM32PG12B_I2C register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_I2C + * @{ + * @brief EFM32PG12B_I2C Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Slave Address Register */ + __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ +} I2C_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_I2C_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ +#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ +#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IFS */ +#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ +#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */ +#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ +#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */ +#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */ +#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */ +#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */ +#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */ +#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ +#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */ +#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */ +#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */ +#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */ +#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */ +#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */ +#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */ +#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ +#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */ +#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */ +#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ +#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */ + +/* Bit fields for I2C IFC */ +#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ +#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */ +#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ +#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */ +#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */ +#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */ +#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */ +#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */ +#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ +#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */ +#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */ +#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */ +#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */ +#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */ +#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */ +#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */ +#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ +#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */ +#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */ +#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ +#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ + +/* Bit fields for I2C ROUTEPEN */ +#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */ +#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ +#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ +#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ +#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ +#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */ +#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */ + +/* Bit fields for I2C ROUTELOC0 */ +#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */ +#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */ +#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */ +#define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */ +#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */ + +/** @} End of group EFM32PG12B_I2C */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_idac.h new file mode 100644 index 0000000000..e8620a05ae --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_idac.h @@ -0,0 +1,352 @@ +/**************************************************************************//** + * @file efm32pg12b_idac.h + * @brief EFM32PG12B_IDAC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_IDAC + * @{ + * @brief EFM32PG12B_IDAC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CURPROG; /**< Current Programming Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IM uint32_t APORTREQ; /**< APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */ +} IDAC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_IDAC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for IDAC CTRL */ +#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */ +#define _IDAC_CTRL_MASK 0x00FD7FFFUL /**< Mask for IDAC_CTRL */ +#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */ +#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */ +#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */ +#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */ +#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */ +#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */ +#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */ +#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */ +#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */ +#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */ +#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */ +#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */ +#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */ +#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */ +#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */ +#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */ +#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */ +#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */ +#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */ +#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */ +#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */ +#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */ +#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */ +#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */ +#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */ +#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */ +#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */ +#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */ + +/* Bit fields for IDAC CURPROG */ +#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */ +#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */ +#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */ +#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */ +#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */ +#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */ +#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */ +#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */ +#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */ +#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */ + +/* Bit fields for IDAC DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */ +#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */ +#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */ +#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */ + +/* Bit fields for IDAC STATUS */ +#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */ +#define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */ +#define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */ +#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */ +#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */ + +/* Bit fields for IDAC IF */ +#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */ +#define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */ +#define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ +#define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */ +#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */ +#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */ + +/* Bit fields for IDAC IFS */ +#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */ +#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */ +#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */ +#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */ + +/* Bit fields for IDAC IFC */ +#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */ +#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */ +#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */ +#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */ +#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */ + +/* Bit fields for IDAC IEN */ +#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */ +#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */ +#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */ +#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */ +#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */ +#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */ +#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */ + +/* Bit fields for IDAC APORTREQ */ +#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */ +#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */ +#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */ +#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */ +#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */ +#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */ +#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */ + +/* Bit fields for IDAC APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */ +#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */ +#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */ +#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */ + +/** @} End of group EFM32PG12B_IDAC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma.h new file mode 100644 index 0000000000..c2024268eb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma.h @@ -0,0 +1,643 @@ +/**************************************************************************//** + * @file efm32pg12b_ldma.h + * @brief EFM32PG12B_LDMA register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_LDMA + * @{ + * @brief EFM32PG12B_LDMA Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */ + uint32_t RESERVED0[5]; /**< Reserved for future use **/ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + uint32_t RESERVED1[7]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + + uint32_t RESERVED2[4]; /**< Reserved registers */ + LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */ +} LDMA_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_LDMA_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */ +#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */ +#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNC */ +#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */ +#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */ +#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */ +#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IFS */ +#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */ +#define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */ +#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */ +#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ +#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */ + +/* Bit fields for LDMA IFC */ +#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */ +#define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */ +#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */ +#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ +#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ +#define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */ +#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_REQSEL */ +#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR /**< Alias for mode CRYPTO0DATA0WR */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR 0x00000000UL /**< Mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR /**< Alias for mode CRYPTO0DATA0XWR */ +#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR 0x00000001UL /**< Mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD /**< Alias for mode CRYPTO0DATA0RD */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD 0x00000002UL /**< Mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR /**< Alias for mode CRYPTO0DATA1WR */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR 0x00000003UL /**< Mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD /**< Alias for mode CRYPTO0DATA1RD */ +#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD 0x00000004UL /**< Mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR << 0) /**< Shifted mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR << 0) /**< Shifted mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD << 0) /**< Shifted mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR << 0) /**< Shifted mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD << 0) /**< Shifted mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x0000001AUL /**< Mode WTIMER0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x0000001BUL /**< Mode WTIMER1 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 /**< Alias for mode CRYPTO0 */ +#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x00000032UL /**< Mode CSEN for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x00000033UL /**< Mode LESENSE for LDMA_CH_REQSEL */ +#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 0x00000034UL /**< Mode CRYPTO1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */ +#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 << 16) /**< Shifted mode CRYPTO1 for LDMA_CH_REQSEL */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */ +#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */ +#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFM32PG12B_LDMA */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma_ch.h new file mode 100644 index 0000000000..4fe331c8bc --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma_ch.h @@ -0,0 +1,53 @@ +/**************************************************************************//** + * @file efm32pg12b_ldma_ch.h + * @brief EFM32PG12B_LDMA_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LDMA_CH EFM32PG12B LDMA CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */ + uint32_t RESERVED0[5]; /**< Reserved future */ +} LDMA_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense.h new file mode 100644 index 0000000000..b3444ee1fe --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense.h @@ -0,0 +1,1867 @@ +/**************************************************************************//** + * @file efm32pg12b_lesense.h + * @brief EFM32PG12B_LESENSE register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_LESENSE + * @{ + * @brief EFM32PG12B_LESENSE Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t TIMCTRL; /**< Timing Control Register */ + __IOM uint32_t PERCTRL; /**< Peripheral Control Register */ + __IOM uint32_t DECCTRL; /**< Decoder control Register */ + __IOM uint32_t BIASCTRL; /**< Bias Control Register */ + __IOM uint32_t EVALCTRL; /**< LESENSE evaluation control */ + __IOM uint32_t PRSCTRL; /**< PRS control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t CHEN; /**< Channel enable Register */ + __IOM uint32_t SCANRES; /**< Scan result register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t PTR; /**< Result buffer pointers */ + __IM uint32_t BUFDATA; /**< Result buffer data register */ + __IM uint32_t CURCH; /**< Current channel index */ + __IOM uint32_t DECSTATE; /**< Current decoder state */ + __IOM uint32_t SENSORSTATE; /**< Decoder input register */ + __IOM uint32_t IDLECONF; /**< GPIO Idle phase configuration */ + __IOM uint32_t ALTEXCONF; /**< Alternative excite pin configuration */ + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */ + + uint32_t RESERVED1[38]; /**< Reserved registers */ + LESENSE_ST_TypeDef ST[32]; /**< Decoding states */ + + LESENSE_BUF_TypeDef BUF[16]; /**< Scanresult */ + + LESENSE_CH_TypeDef CH[16]; /**< Scanconfig */ +} LESENSE_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_LESENSE_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LESENSE CTRL */ +#define _LESENSE_CTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CTRL */ +#define _LESENSE_CTRL_MASK 0x007B29BFUL /**< Mask for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CTRL_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_DEFAULT (_LESENSE_CTRL_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PERIODIC (_LESENSE_CTRL_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_ONESHOT (_LESENSE_CTRL_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANMODE_PRS (_LESENSE_CTRL_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_SHIFT 2 /**< Shift value for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_MASK 0x3CUL /**< Bit mask for LESENSE_PRSSEL */ +#define _LESENSE_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_CTRL */ +#define _LESENSE_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_DEFAULT (_LESENSE_CTRL_PRSSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH0 (_LESENSE_CTRL_PRSSEL_PRSCH0 << 2) /**< Shifted mode PRSCH0 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH1 (_LESENSE_CTRL_PRSSEL_PRSCH1 << 2) /**< Shifted mode PRSCH1 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH2 (_LESENSE_CTRL_PRSSEL_PRSCH2 << 2) /**< Shifted mode PRSCH2 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH3 (_LESENSE_CTRL_PRSSEL_PRSCH3 << 2) /**< Shifted mode PRSCH3 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH4 (_LESENSE_CTRL_PRSSEL_PRSCH4 << 2) /**< Shifted mode PRSCH4 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH5 (_LESENSE_CTRL_PRSSEL_PRSCH5 << 2) /**< Shifted mode PRSCH5 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH6 (_LESENSE_CTRL_PRSSEL_PRSCH6 << 2) /**< Shifted mode PRSCH6 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH7 (_LESENSE_CTRL_PRSSEL_PRSCH7 << 2) /**< Shifted mode PRSCH7 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH8 (_LESENSE_CTRL_PRSSEL_PRSCH8 << 2) /**< Shifted mode PRSCH8 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH9 (_LESENSE_CTRL_PRSSEL_PRSCH9 << 2) /**< Shifted mode PRSCH9 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH10 (_LESENSE_CTRL_PRSSEL_PRSCH10 << 2) /**< Shifted mode PRSCH10 for LESENSE_CTRL */ +#define LESENSE_CTRL_PRSSEL_PRSCH11 (_LESENSE_CTRL_PRSSEL_PRSCH11 << 2) /**< Shifted mode PRSCH11 for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_SHIFT 7 /**< Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_MASK 0x180UL /**< Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CTRL_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DEFAULT (_LESENSE_CTRL_SCANCONF_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DIRMAP (_LESENSE_CTRL_SCANCONF_DIRMAP << 7) /**< Shifted mode DIRMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_INVMAP (_LESENSE_CTRL_SCANCONF_INVMAP << 7) /**< Shifted mode INVMAP for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_TOGGLE (_LESENSE_CTRL_SCANCONF_TOGGLE << 7) /**< Shifted mode TOGGLE for LESENSE_CTRL */ +#define LESENSE_CTRL_SCANCONF_DECDEF (_LESENSE_CTRL_SCANCONF_DECDEF << 7) /**< Shifted mode DECDEF for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP (0x1UL << 11) /**< Alternative excitation map */ +#define _LESENSE_CTRL_ALTEXMAP_SHIFT 11 /**< Shift value for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_MASK 0x800UL /**< Bit mask for LESENSE_ALTEXMAP */ +#define _LESENSE_CTRL_ALTEXMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_ALTEX 0x00000000UL /**< Mode ALTEX for LESENSE_CTRL */ +#define _LESENSE_CTRL_ALTEXMAP_CH 0x00000001UL /**< Mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_DEFAULT (_LESENSE_CTRL_ALTEXMAP_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_ALTEX (_LESENSE_CTRL_ALTEXMAP_ALTEX << 11) /**< Shifted mode ALTEX for LESENSE_CTRL */ +#define LESENSE_CTRL_ALTEXMAP_CH (_LESENSE_CTRL_ALTEXMAP_CH << 11) /**< Shifted mode CH for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE (0x1UL << 13) /**< Enable dual sample mode */ +#define _LESENSE_CTRL_DUALSAMPLE_SHIFT 13 /**< Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_MASK 0x2000UL /**< Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CTRL_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DUALSAMPLE_DEFAULT (_LESENSE_CTRL_DUALSAMPLE_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW (0x1UL << 16) /**< Result buffer overwrite */ +#define _LESENSE_CTRL_BUFOW_SHIFT 16 /**< Shift value for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_MASK 0x10000UL /**< Bit mask for LESENSE_BUFOW */ +#define _LESENSE_CTRL_BUFOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFOW_DEFAULT (_LESENSE_CTRL_BUFOW_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES (0x1UL << 17) /**< Enable storing of SCANRES */ +#define _LESENSE_CTRL_STRSCANRES_SHIFT 17 /**< Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_MASK 0x20000UL /**< Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CTRL_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_STRSCANRES_DEFAULT (_LESENSE_CTRL_STRSCANRES_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL (0x1UL << 19) /**< Result buffer interrupt and DMA trigger level */ +#define _LESENSE_CTRL_BUFIDL_SHIFT 19 /**< Shift value for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_MASK 0x80000UL /**< Bit mask for LESENSE_BUFIDL */ +#define _LESENSE_CTRL_BUFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_HALFFULL 0x00000000UL /**< Mode HALFFULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_BUFIDL_FULL 0x00000001UL /**< Mode FULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_DEFAULT (_LESENSE_CTRL_BUFIDL_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_HALFFULL (_LESENSE_CTRL_BUFIDL_HALFFULL << 19) /**< Shifted mode HALFFULL for LESENSE_CTRL */ +#define LESENSE_CTRL_BUFIDL_FULL (_LESENSE_CTRL_BUFIDL_FULL << 19) /**< Shifted mode FULL for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_SHIFT 20 /**< Shift value for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_MASK 0x300000UL /**< Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CTRL_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFDATAV 0x00000001UL /**< Mode BUFDATAV for LESENSE_CTRL */ +#define _LESENSE_CTRL_DMAWU_BUFLEVEL 0x00000002UL /**< Mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DEFAULT (_LESENSE_CTRL_DMAWU_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_DISABLE (_LESENSE_CTRL_DMAWU_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFDATAV (_LESENSE_CTRL_DMAWU_BUFDATAV << 20) /**< Shifted mode BUFDATAV for LESENSE_CTRL */ +#define LESENSE_CTRL_DMAWU_BUFLEVEL (_LESENSE_CTRL_DMAWU_BUFLEVEL << 20) /**< Shifted mode BUFLEVEL for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN (0x1UL << 22) /**< Debug Mode Run Enable */ +#define _LESENSE_CTRL_DEBUGRUN_SHIFT 22 /**< Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_MASK 0x400000UL /**< Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CTRL */ +#define LESENSE_CTRL_DEBUGRUN_DEFAULT (_LESENSE_CTRL_DEBUGRUN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_CTRL */ + +/* Bit fields for LESENSE TIMCTRL */ +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUXHFRCO startup configuration */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ + +/* Bit fields for LESENSE PERCTRL */ +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x3FF0014FUL /**< Mask for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN (0x1UL << 0) /**< VDAC CH0 enable. */ +#define _LESENSE_PERCTRL_DACCH0EN_SHIFT 0 /**< Shift value for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_MASK 0x1UL /**< Bit mask for LESENSE_DACCH0EN */ +#define _LESENSE_PERCTRL_DACCH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0EN_DEFAULT (_LESENSE_PERCTRL_DACCH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN (0x1UL << 1) /**< VDAC CH1 enable. */ +#define _LESENSE_PERCTRL_DACCH1EN_SHIFT 1 /**< Shift value for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_MASK 0x2UL /**< Bit mask for LESENSE_DACCH1EN */ +#define _LESENSE_PERCTRL_DACCH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1EN_DEFAULT (_LESENSE_PERCTRL_DACCH1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< VDAC CH0 data selection. */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA (0x1UL << 3) /**< VDAC CH1 data selection. */ +#define _LESENSE_PERCTRL_DACCH1DATA_SHIFT 3 /**< Shift value for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_MASK 0x8UL /**< Bit mask for LESENSE_DACCH1DATA */ +#define _LESENSE_PERCTRL_DACCH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH1DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DEFAULT (_LESENSE_PERCTRL_DACCH1DATA_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_DACDATA (_LESENSE_PERCTRL_DACCH1DATA_DACDATA << 3) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH1DATA_THRES (_LESENSE_PERCTRL_DACCH1DATA_THRES << 3) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< VDAC startup configuration */ +#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< VDAC conversion trigger configuration */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x300000UL /**< Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DISABLE (_LESENSE_PERCTRL_ACMP0MODE_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0xC00000UL /**< Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000001UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000002UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DISABLE (_LESENSE_PERCTRL_ACMP1MODE_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ +#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ +#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN (0x1UL << 26) /**< ACMP0 hysteresis enable */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_SHIFT 26 /**< Shift value for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_MASK 0x4000000UL /**< Bit mask for LESENSE_ACMP0HYSTEN */ +#define _LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP0HYSTEN_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN (0x1UL << 27) /**< ACMP1 hysteresis enable */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_SHIFT 27 /**< Shift value for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_MASK 0x8000000UL /**< Bit mask for LESENSE_ACMP1HYSTEN */ +#define _LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT (_LESENSE_PERCTRL_ACMP1HYSTEN_DEFAULT << 27) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_SHIFT 28 /**< Shift value for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_MASK 0x30000000UL /**< Bit mask for LESENSE_WARMUPMODE */ +#define _LESENSE_PERCTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM 0x00000001UL /**< Mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM 0x00000002UL /**< Mode KEEPDACWARM for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM 0x00000003UL /**< Mode KEEPACMPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_DEFAULT (_LESENSE_PERCTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_NORMAL (_LESENSE_PERCTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPWARM << 28) /**< Shifted mode KEEPACMPWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPDACWARM << 28) /**< Shifted mode KEEPDACWARM for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM (_LESENSE_PERCTRL_WARMUPMODE_KEEPACMPDACWARM << 28) /**< Shifted mode KEEPACMPDACWARM for LESENSE_PERCTRL */ + +/* Bit fields for LESENSE DECCTRL */ +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x1EF7BDFFUL /**< Mask for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE (0x1UL << 0) /**< Disable the decoder */ +#define _LESENSE_DECCTRL_DISABLE_SHIFT 0 /**< Shift value for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_MASK 0x1UL /**< Bit mask for LESENSE_DISABLE */ +#define _LESENSE_DECCTRL_DISABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DISABLE_DEFAULT (_LESENSE_DECCTRL_DISABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK (0x1UL << 1) /**< Enable check of current state */ +#define _LESENSE_DECCTRL_ERRCHK_SHIFT 1 /**< Shift value for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_MASK 0x2UL /**< Bit mask for LESENSE_ERRCHK */ +#define _LESENSE_DECCTRL_ERRCHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_ERRCHK_DEFAULT (_LESENSE_DECCTRL_ERRCHK_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt mapping */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt requests */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channels 0 and 1 */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT (0x1UL << 8) /**< LESENSE decoder input configuration */ +#define _LESENSE_DECCTRL_INPUT_SHIFT 8 /**< Shift value for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_MASK 0x100UL /**< Bit mask for LESENSE_INPUT */ +#define _LESENSE_DECCTRL_INPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_SENSORSTATE 0x00000000UL /**< Mode SENSORSTATE for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_INPUT_PRS 0x00000001UL /**< Mode PRS for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_DEFAULT (_LESENSE_DECCTRL_INPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_SENSORSTATE (_LESENSE_DECCTRL_INPUT_SENSORSTATE << 8) /**< Shifted mode SENSORSTATE for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INPUT_PRS (_LESENSE_DECCTRL_INPUT_PRS << 8) /**< Shifted mode PRS for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_SHIFT 10 /**< Shift value for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_MASK 0x3C00UL /**< Bit mask for LESENSE_PRSSEL0 */ +#define _LESENSE_DECCTRL_PRSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL0_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_DEFAULT (_LESENSE_DECCTRL_PRSSEL0_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH0 (_LESENSE_DECCTRL_PRSSEL0_PRSCH0 << 10) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH1 (_LESENSE_DECCTRL_PRSSEL0_PRSCH1 << 10) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH2 (_LESENSE_DECCTRL_PRSSEL0_PRSCH2 << 10) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH3 (_LESENSE_DECCTRL_PRSSEL0_PRSCH3 << 10) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH4 (_LESENSE_DECCTRL_PRSSEL0_PRSCH4 << 10) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH5 (_LESENSE_DECCTRL_PRSSEL0_PRSCH5 << 10) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH6 (_LESENSE_DECCTRL_PRSSEL0_PRSCH6 << 10) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH7 (_LESENSE_DECCTRL_PRSSEL0_PRSCH7 << 10) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH8 (_LESENSE_DECCTRL_PRSSEL0_PRSCH8 << 10) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH9 (_LESENSE_DECCTRL_PRSSEL0_PRSCH9 << 10) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH10 (_LESENSE_DECCTRL_PRSSEL0_PRSCH10 << 10) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL0_PRSCH11 (_LESENSE_DECCTRL_PRSSEL0_PRSCH11 << 10) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_SHIFT 15 /**< Shift value for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_MASK 0x78000UL /**< Bit mask for LESENSE_PRSSEL1 */ +#define _LESENSE_DECCTRL_PRSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL1_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_DEFAULT (_LESENSE_DECCTRL_PRSSEL1_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH0 (_LESENSE_DECCTRL_PRSSEL1_PRSCH0 << 15) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH1 (_LESENSE_DECCTRL_PRSSEL1_PRSCH1 << 15) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH2 (_LESENSE_DECCTRL_PRSSEL1_PRSCH2 << 15) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH3 (_LESENSE_DECCTRL_PRSSEL1_PRSCH3 << 15) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH4 (_LESENSE_DECCTRL_PRSSEL1_PRSCH4 << 15) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH5 (_LESENSE_DECCTRL_PRSSEL1_PRSCH5 << 15) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH6 (_LESENSE_DECCTRL_PRSSEL1_PRSCH6 << 15) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH7 (_LESENSE_DECCTRL_PRSSEL1_PRSCH7 << 15) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH8 (_LESENSE_DECCTRL_PRSSEL1_PRSCH8 << 15) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH9 (_LESENSE_DECCTRL_PRSSEL1_PRSCH9 << 15) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH10 (_LESENSE_DECCTRL_PRSSEL1_PRSCH10 << 15) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL1_PRSCH11 (_LESENSE_DECCTRL_PRSSEL1_PRSCH11 << 15) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_SHIFT 20 /**< Shift value for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_MASK 0xF00000UL /**< Bit mask for LESENSE_PRSSEL2 */ +#define _LESENSE_DECCTRL_PRSSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL2_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_DEFAULT (_LESENSE_DECCTRL_PRSSEL2_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH0 (_LESENSE_DECCTRL_PRSSEL2_PRSCH0 << 20) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH1 (_LESENSE_DECCTRL_PRSSEL2_PRSCH1 << 20) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH2 (_LESENSE_DECCTRL_PRSSEL2_PRSCH2 << 20) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH3 (_LESENSE_DECCTRL_PRSSEL2_PRSCH3 << 20) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH4 (_LESENSE_DECCTRL_PRSSEL2_PRSCH4 << 20) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH5 (_LESENSE_DECCTRL_PRSSEL2_PRSCH5 << 20) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH6 (_LESENSE_DECCTRL_PRSSEL2_PRSCH6 << 20) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH7 (_LESENSE_DECCTRL_PRSSEL2_PRSCH7 << 20) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH8 (_LESENSE_DECCTRL_PRSSEL2_PRSCH8 << 20) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH9 (_LESENSE_DECCTRL_PRSSEL2_PRSCH9 << 20) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH10 (_LESENSE_DECCTRL_PRSSEL2_PRSCH10 << 20) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL2_PRSCH11 (_LESENSE_DECCTRL_PRSSEL2_PRSCH11 << 20) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_SHIFT 25 /**< Shift value for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_MASK 0x1E000000UL /**< Bit mask for LESENSE_PRSSEL3 */ +#define _LESENSE_DECCTRL_PRSSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_PRSSEL3_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_DEFAULT (_LESENSE_DECCTRL_PRSSEL3_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH0 (_LESENSE_DECCTRL_PRSSEL3_PRSCH0 << 25) /**< Shifted mode PRSCH0 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH1 (_LESENSE_DECCTRL_PRSSEL3_PRSCH1 << 25) /**< Shifted mode PRSCH1 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH2 (_LESENSE_DECCTRL_PRSSEL3_PRSCH2 << 25) /**< Shifted mode PRSCH2 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH3 (_LESENSE_DECCTRL_PRSSEL3_PRSCH3 << 25) /**< Shifted mode PRSCH3 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH4 (_LESENSE_DECCTRL_PRSSEL3_PRSCH4 << 25) /**< Shifted mode PRSCH4 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH5 (_LESENSE_DECCTRL_PRSSEL3_PRSCH5 << 25) /**< Shifted mode PRSCH5 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH6 (_LESENSE_DECCTRL_PRSSEL3_PRSCH6 << 25) /**< Shifted mode PRSCH6 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH7 (_LESENSE_DECCTRL_PRSSEL3_PRSCH7 << 25) /**< Shifted mode PRSCH7 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH8 (_LESENSE_DECCTRL_PRSSEL3_PRSCH8 << 25) /**< Shifted mode PRSCH8 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH9 (_LESENSE_DECCTRL_PRSSEL3_PRSCH9 << 25) /**< Shifted mode PRSCH9 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH10 (_LESENSE_DECCTRL_PRSSEL3_PRSCH10 << 25) /**< Shifted mode PRSCH10 for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSSEL3_PRSCH11 (_LESENSE_DECCTRL_PRSSEL3_PRSCH11 << 25) /**< Shifted mode PRSCH11 for LESENSE_DECCTRL */ + +/* Bit fields for LESENSE BIASCTRL */ +#define _LESENSE_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_MASK 0x00000003UL /**< Mask for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_SHIFT 0 /**< Shift value for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_MASK 0x3UL /**< Bit mask for LESENSE_BIASMODE */ +#define _LESENSE_BIASCTRL_BIASMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DONTTOUCH 0x00000000UL /**< Mode DONTTOUCH for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE 0x00000001UL /**< Mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define _LESENSE_BIASCTRL_BIASMODE_HIGHACC 0x00000002UL /**< Mode HIGHACC for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DEFAULT (_LESENSE_BIASCTRL_BIASMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DONTTOUCH (_LESENSE_BIASCTRL_BIASMODE_DONTTOUCH << 0) /**< Shifted mode DONTTOUCH for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE (_LESENSE_BIASCTRL_BIASMODE_DUTYCYCLE << 0) /**< Shifted mode DUTYCYCLE for LESENSE_BIASCTRL */ +#define LESENSE_BIASCTRL_BIASMODE_HIGHACC (_LESENSE_BIASCTRL_BIASMODE_HIGHACC << 0) /**< Shifted mode HIGHACC for LESENSE_BIASCTRL */ + +/* Bit fields for LESENSE EVALCTRL */ +#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ +#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ + +/* Bit fields for LESENSE PRSCTRL */ +#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ +#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ + +/* Bit fields for LESENSE CMD */ +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ +#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ +#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ + +/* Bit fields for LESENSE CHEN */ +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ + +/* Bit fields for LESENSE SCANRES */ +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ + +/* Bit fields for LESENSE STATUS */ +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000003FUL /**< Mask for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV (0x1UL << 0) /**< Result data valid */ +#define _LESENSE_STATUS_BUFDATAV_SHIFT 0 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_MASK 0x1UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_STATUS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFDATAV_DEFAULT (_LESENSE_STATUS_BUFDATAV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL (0x1UL << 1) /**< Result buffer half full */ +#define _LESENSE_STATUS_BUFHALFFULL_SHIFT 1 /**< Shift value for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_MASK 0x2UL /**< Bit mask for LESENSE_BUFHALFFULL */ +#define _LESENSE_STATUS_BUFHALFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFHALFFULL_DEFAULT (_LESENSE_STATUS_BUFHALFFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL (0x1UL << 2) /**< Result buffer full */ +#define _LESENSE_STATUS_BUFFULL_SHIFT 2 /**< Shift value for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_MASK 0x4UL /**< Bit mask for LESENSE_BUFFULL */ +#define _LESENSE_STATUS_BUFFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_BUFFULL_DEFAULT (_LESENSE_STATUS_BUFFULL_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 3) /**< LESENSE periodic counter running */ +#define _LESENSE_STATUS_RUNNING_SHIFT 3 /**< Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x8UL /**< Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 4) /**< LESENSE scan active */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 4 /**< Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x10UL /**< Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE (0x1UL << 5) /**< LESENSE VDAC interface is active */ +#define _LESENSE_STATUS_DACACTIVE_SHIFT 5 /**< Shift value for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_MASK 0x20UL /**< Bit mask for LESENSE_DACACTIVE */ +#define _LESENSE_STATUS_DACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_DACACTIVE_DEFAULT (_LESENSE_STATUS_DACACTIVE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ + +/* Bit fields for LESENSE PTR */ +#define _LESENSE_PTR_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PTR */ +#define _LESENSE_PTR_MASK 0x000000FFUL /**< Mask for LESENSE_PTR */ +#define _LESENSE_PTR_RD_SHIFT 0 /**< Shift value for LESENSE_RD */ +#define _LESENSE_PTR_RD_MASK 0xFUL /**< Bit mask for LESENSE_RD */ +#define _LESENSE_PTR_RD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_RD_DEFAULT (_LESENSE_PTR_RD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PTR */ +#define _LESENSE_PTR_WR_SHIFT 4 /**< Shift value for LESENSE_WR */ +#define _LESENSE_PTR_WR_MASK 0xF0UL /**< Bit mask for LESENSE_WR */ +#define _LESENSE_PTR_WR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PTR */ +#define LESENSE_PTR_WR_DEFAULT (_LESENSE_PTR_WR_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_PTR */ + +/* Bit fields for LESENSE BUFDATA */ +#define _LESENSE_BUFDATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_SHIFT 0 /**< Shift value for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATA_DEFAULT (_LESENSE_BUFDATA_BUFDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ +#define _LESENSE_BUFDATA_BUFDATASRC_SHIFT 16 /**< Shift value for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_BUFDATASRC */ +#define _LESENSE_BUFDATA_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUFDATA */ +#define LESENSE_BUFDATA_BUFDATASRC_DEFAULT (_LESENSE_BUFDATA_BUFDATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUFDATA */ + +/* Bit fields for LESENSE CURCH */ +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ + +/* Bit fields for LESENSE DECSTATE */ +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ + +/* Bit fields for LESENSE SENSORSTATE */ +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE */ + +/* Bit fields for LESENSE IDLECONF */ +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_MASK 0x3UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IDLECONF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DEFAULT (_LESENSE_IDLECONF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DISABLE (_LESENSE_IDLECONF_CH0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_HIGH (_LESENSE_IDLECONF_CH0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_LOW (_LESENSE_IDLECONF_CH0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH0_DAC (_LESENSE_IDLECONF_CH0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_SHIFT 2 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_MASK 0xCUL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IDLECONF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DEFAULT (_LESENSE_IDLECONF_CH1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DISABLE (_LESENSE_IDLECONF_CH1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_HIGH (_LESENSE_IDLECONF_CH1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_LOW (_LESENSE_IDLECONF_CH1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH1_DAC (_LESENSE_IDLECONF_CH1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_SHIFT 4 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_MASK 0x30UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IDLECONF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DEFAULT (_LESENSE_IDLECONF_CH2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DISABLE (_LESENSE_IDLECONF_CH2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_HIGH (_LESENSE_IDLECONF_CH2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_LOW (_LESENSE_IDLECONF_CH2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH2_DAC (_LESENSE_IDLECONF_CH2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_SHIFT 6 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_MASK 0xC0UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IDLECONF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DEFAULT (_LESENSE_IDLECONF_CH3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DISABLE (_LESENSE_IDLECONF_CH3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_HIGH (_LESENSE_IDLECONF_CH3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_LOW (_LESENSE_IDLECONF_CH3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH3_DAC (_LESENSE_IDLECONF_CH3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_SHIFT 8 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_MASK 0x300UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IDLECONF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DEFAULT (_LESENSE_IDLECONF_CH4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DISABLE (_LESENSE_IDLECONF_CH4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_HIGH (_LESENSE_IDLECONF_CH4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_LOW (_LESENSE_IDLECONF_CH4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH4_DAC (_LESENSE_IDLECONF_CH4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_SHIFT 10 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_MASK 0xC00UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IDLECONF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DEFAULT (_LESENSE_IDLECONF_CH5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DISABLE (_LESENSE_IDLECONF_CH5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_HIGH (_LESENSE_IDLECONF_CH5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_LOW (_LESENSE_IDLECONF_CH5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH5_DAC (_LESENSE_IDLECONF_CH5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_SHIFT 12 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_MASK 0x3000UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IDLECONF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DEFAULT (_LESENSE_IDLECONF_CH6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DISABLE (_LESENSE_IDLECONF_CH6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_HIGH (_LESENSE_IDLECONF_CH6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_LOW (_LESENSE_IDLECONF_CH6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH6_DAC (_LESENSE_IDLECONF_CH6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_SHIFT 14 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_MASK 0xC000UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IDLECONF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DEFAULT (_LESENSE_IDLECONF_CH7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DISABLE (_LESENSE_IDLECONF_CH7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_HIGH (_LESENSE_IDLECONF_CH7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_LOW (_LESENSE_IDLECONF_CH7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH7_DAC (_LESENSE_IDLECONF_CH7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_SHIFT 16 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_MASK 0x30000UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IDLECONF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DEFAULT (_LESENSE_IDLECONF_CH8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DISABLE (_LESENSE_IDLECONF_CH8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_HIGH (_LESENSE_IDLECONF_CH8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_LOW (_LESENSE_IDLECONF_CH8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH8_DAC (_LESENSE_IDLECONF_CH8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_SHIFT 18 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_MASK 0xC0000UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IDLECONF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DEFAULT (_LESENSE_IDLECONF_CH9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DISABLE (_LESENSE_IDLECONF_CH9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_HIGH (_LESENSE_IDLECONF_CH9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_LOW (_LESENSE_IDLECONF_CH9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH9_DAC (_LESENSE_IDLECONF_CH9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_SHIFT 20 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_MASK 0x300000UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IDLECONF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DEFAULT (_LESENSE_IDLECONF_CH10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DISABLE (_LESENSE_IDLECONF_CH10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_HIGH (_LESENSE_IDLECONF_CH10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_LOW (_LESENSE_IDLECONF_CH10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH10_DAC (_LESENSE_IDLECONF_CH10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_SHIFT 22 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_MASK 0xC00000UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IDLECONF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DEFAULT (_LESENSE_IDLECONF_CH11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DISABLE (_LESENSE_IDLECONF_CH11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_HIGH (_LESENSE_IDLECONF_CH11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_LOW (_LESENSE_IDLECONF_CH11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH11_DAC (_LESENSE_IDLECONF_CH11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_SHIFT 24 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_MASK 0x3000000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IDLECONF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DEFAULT (_LESENSE_IDLECONF_CH12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DISABLE (_LESENSE_IDLECONF_CH12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_HIGH (_LESENSE_IDLECONF_CH12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_LOW (_LESENSE_IDLECONF_CH12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH12_DAC (_LESENSE_IDLECONF_CH12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_SHIFT 26 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_MASK 0xC000000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IDLECONF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DEFAULT (_LESENSE_IDLECONF_CH13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DISABLE (_LESENSE_IDLECONF_CH13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_HIGH (_LESENSE_IDLECONF_CH13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_LOW (_LESENSE_IDLECONF_CH13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH13_DAC (_LESENSE_IDLECONF_CH13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_SHIFT 28 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_MASK 0x30000000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IDLECONF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DEFAULT (_LESENSE_IDLECONF_CH14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DISABLE (_LESENSE_IDLECONF_CH14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_HIGH (_LESENSE_IDLECONF_CH14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_LOW (_LESENSE_IDLECONF_CH14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH14_DAC (_LESENSE_IDLECONF_CH14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_SHIFT 30 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IDLECONF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CH15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DEFAULT (_LESENSE_IDLECONF_CH15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DISABLE (_LESENSE_IDLECONF_CH15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_HIGH (_LESENSE_IDLECONF_CH15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_LOW (_LESENSE_IDLECONF_CH15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CH15_DAC (_LESENSE_IDLECONF_CH15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ + +/* Bit fields for LESENSE ALTEXCONF */ +#define _LESENSE_ALTEXCONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_SHIFT 0 /**< Shift value for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_MASK 0x3UL /**< Bit mask for LESENSE_IDLECONF0 */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF0_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_DISABLE (_LESENSE_ALTEXCONF_IDLECONF0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_HIGH (_LESENSE_ALTEXCONF_IDLECONF0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF0_LOW (_LESENSE_ALTEXCONF_IDLECONF0_LOW << 0) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_SHIFT 2 /**< Shift value for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_MASK 0xCUL /**< Bit mask for LESENSE_IDLECONF1 */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF1_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_DISABLE (_LESENSE_ALTEXCONF_IDLECONF1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_HIGH (_LESENSE_ALTEXCONF_IDLECONF1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF1_LOW (_LESENSE_ALTEXCONF_IDLECONF1_LOW << 2) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_SHIFT 4 /**< Shift value for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_MASK 0x30UL /**< Bit mask for LESENSE_IDLECONF2 */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF2_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_DISABLE (_LESENSE_ALTEXCONF_IDLECONF2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_HIGH (_LESENSE_ALTEXCONF_IDLECONF2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF2_LOW (_LESENSE_ALTEXCONF_IDLECONF2_LOW << 4) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_SHIFT 6 /**< Shift value for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_MASK 0xC0UL /**< Bit mask for LESENSE_IDLECONF3 */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF3_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_DISABLE (_LESENSE_ALTEXCONF_IDLECONF3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_HIGH (_LESENSE_ALTEXCONF_IDLECONF3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF3_LOW (_LESENSE_ALTEXCONF_IDLECONF3_LOW << 6) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_SHIFT 8 /**< Shift value for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_MASK 0x300UL /**< Bit mask for LESENSE_IDLECONF4 */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF4_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_DISABLE (_LESENSE_ALTEXCONF_IDLECONF4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_HIGH (_LESENSE_ALTEXCONF_IDLECONF4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF4_LOW (_LESENSE_ALTEXCONF_IDLECONF4_LOW << 8) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_SHIFT 10 /**< Shift value for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_MASK 0xC00UL /**< Bit mask for LESENSE_IDLECONF5 */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF5_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_DISABLE (_LESENSE_ALTEXCONF_IDLECONF5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_HIGH (_LESENSE_ALTEXCONF_IDLECONF5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF5_LOW (_LESENSE_ALTEXCONF_IDLECONF5_LOW << 10) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_SHIFT 12 /**< Shift value for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_MASK 0x3000UL /**< Bit mask for LESENSE_IDLECONF6 */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF6_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_DISABLE (_LESENSE_ALTEXCONF_IDLECONF6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_HIGH (_LESENSE_ALTEXCONF_IDLECONF6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF6_LOW (_LESENSE_ALTEXCONF_IDLECONF6_LOW << 12) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_SHIFT 14 /**< Shift value for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_MASK 0xC000UL /**< Bit mask for LESENSE_IDLECONF7 */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_ALTEXCONF */ +#define _LESENSE_ALTEXCONF_IDLECONF7_LOW 0x00000002UL /**< Mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DEFAULT (_LESENSE_ALTEXCONF_IDLECONF7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_DISABLE (_LESENSE_ALTEXCONF_IDLECONF7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_HIGH (_LESENSE_ALTEXCONF_IDLECONF7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_IDLECONF7_LOW (_LESENSE_ALTEXCONF_IDLECONF7_LOW << 14) /**< Shifted mode LOW for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0 (0x1UL << 16) /**< ALTEX0 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX0_SHIFT 16 /**< Shift value for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_MASK 0x10000UL /**< Bit mask for LESENSE_AEX0 */ +#define _LESENSE_ALTEXCONF_AEX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX0_DEFAULT (_LESENSE_ALTEXCONF_AEX0_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1 (0x1UL << 17) /**< ALTEX1 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX1_SHIFT 17 /**< Shift value for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_MASK 0x20000UL /**< Bit mask for LESENSE_AEX1 */ +#define _LESENSE_ALTEXCONF_AEX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX1_DEFAULT (_LESENSE_ALTEXCONF_AEX1_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2 (0x1UL << 18) /**< ALTEX2 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX2_SHIFT 18 /**< Shift value for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_MASK 0x40000UL /**< Bit mask for LESENSE_AEX2 */ +#define _LESENSE_ALTEXCONF_AEX2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX2_DEFAULT (_LESENSE_ALTEXCONF_AEX2_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3 (0x1UL << 19) /**< ALTEX3 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX3_SHIFT 19 /**< Shift value for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_MASK 0x80000UL /**< Bit mask for LESENSE_AEX3 */ +#define _LESENSE_ALTEXCONF_AEX3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX3_DEFAULT (_LESENSE_ALTEXCONF_AEX3_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4 (0x1UL << 20) /**< ALTEX4 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX4_SHIFT 20 /**< Shift value for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_MASK 0x100000UL /**< Bit mask for LESENSE_AEX4 */ +#define _LESENSE_ALTEXCONF_AEX4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX4_DEFAULT (_LESENSE_ALTEXCONF_AEX4_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5 (0x1UL << 21) /**< ALTEX5 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX5_SHIFT 21 /**< Shift value for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_MASK 0x200000UL /**< Bit mask for LESENSE_AEX5 */ +#define _LESENSE_ALTEXCONF_AEX5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX5_DEFAULT (_LESENSE_ALTEXCONF_AEX5_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6 (0x1UL << 22) /**< ALTEX6 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX6_SHIFT 22 /**< Shift value for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_MASK 0x400000UL /**< Bit mask for LESENSE_AEX6 */ +#define _LESENSE_ALTEXCONF_AEX6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX6_DEFAULT (_LESENSE_ALTEXCONF_AEX6_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7 (0x1UL << 23) /**< ALTEX7 always excite enable */ +#define _LESENSE_ALTEXCONF_AEX7_SHIFT 23 /**< Shift value for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_MASK 0x800000UL /**< Bit mask for LESENSE_AEX7 */ +#define _LESENSE_ALTEXCONF_AEX7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ALTEXCONF */ +#define LESENSE_ALTEXCONF_AEX7_DEFAULT (_LESENSE_ALTEXCONF_AEX7_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ALTEXCONF */ + +/* Bit fields for LESENSE IF */ +#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x007FFFFFUL /**< Mask for LESENSE_IF */ +#define LESENSE_IF_CH0 (0x1UL << 0) /**< CH0 interrupt flag */ +#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /**< CH1 interrupt flag */ +#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /**< CH2 interrupt flag */ +#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /**< CH3 interrupt flag */ +#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /**< CH4 interrupt flag */ +#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /**< CH5 interrupt flag */ +#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /**< CH6 interrupt flag */ +#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /**< CH7 interrupt flag */ +#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /**< CH8 interrupt flag */ +#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /**< CH9 interrupt flag */ +#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /**< CH10 interrupt flag */ +#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /**< CH11 interrupt flag */ +#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /**< CH12 interrupt flag */ +#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /**< CH13 interrupt flag */ +#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /**< CH14 interrupt flag */ +#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /**< CH15 interrupt flag */ +#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE interrupt flag */ +#define _LESENSE_IF_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IF_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANCOMPLETE_DEFAULT (_LESENSE_IF_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /**< DEC interrupt flag */ +#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR (0x1UL << 18) /**< DECERR interrupt flag */ +#define _LESENSE_IF_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IF_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DECERR_DEFAULT (_LESENSE_IF_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV (0x1UL << 19) /**< BUFDATAV interrupt flag */ +#define _LESENSE_IF_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IF_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFDATAV_DEFAULT (_LESENSE_IF_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL interrupt flag */ +#define _LESENSE_IF_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IF_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFLEVEL_DEFAULT (_LESENSE_IF_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF (0x1UL << 21) /**< BUFOF interrupt flag */ +#define _LESENSE_IF_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IF_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_BUFOF_DEFAULT (_LESENSE_IF_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 22) /**< CNTOF interrupt flag */ +#define _LESENSE_IF_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IF */ + +/* Bit fields for LESENSE IFS */ +#define _LESENSE_IFS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFS */ +#define _LESENSE_IFS_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFS */ +#define LESENSE_IFS_CH0 (0x1UL << 0) /**< Set CH0 Interrupt Flag */ +#define _LESENSE_IFS_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH0_DEFAULT (_LESENSE_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1 (0x1UL << 1) /**< Set CH1 Interrupt Flag */ +#define _LESENSE_IFS_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH1_DEFAULT (_LESENSE_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2 (0x1UL << 2) /**< Set CH2 Interrupt Flag */ +#define _LESENSE_IFS_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFS_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH2_DEFAULT (_LESENSE_IFS_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3 (0x1UL << 3) /**< Set CH3 Interrupt Flag */ +#define _LESENSE_IFS_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFS_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH3_DEFAULT (_LESENSE_IFS_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4 (0x1UL << 4) /**< Set CH4 Interrupt Flag */ +#define _LESENSE_IFS_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFS_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH4_DEFAULT (_LESENSE_IFS_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5 (0x1UL << 5) /**< Set CH5 Interrupt Flag */ +#define _LESENSE_IFS_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFS_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH5_DEFAULT (_LESENSE_IFS_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6 (0x1UL << 6) /**< Set CH6 Interrupt Flag */ +#define _LESENSE_IFS_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFS_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH6_DEFAULT (_LESENSE_IFS_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7 (0x1UL << 7) /**< Set CH7 Interrupt Flag */ +#define _LESENSE_IFS_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFS_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH7_DEFAULT (_LESENSE_IFS_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8 (0x1UL << 8) /**< Set CH8 Interrupt Flag */ +#define _LESENSE_IFS_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFS_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH8_DEFAULT (_LESENSE_IFS_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9 (0x1UL << 9) /**< Set CH9 Interrupt Flag */ +#define _LESENSE_IFS_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFS_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH9_DEFAULT (_LESENSE_IFS_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10 (0x1UL << 10) /**< Set CH10 Interrupt Flag */ +#define _LESENSE_IFS_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFS_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH10_DEFAULT (_LESENSE_IFS_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11 (0x1UL << 11) /**< Set CH11 Interrupt Flag */ +#define _LESENSE_IFS_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFS_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH11_DEFAULT (_LESENSE_IFS_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12 (0x1UL << 12) /**< Set CH12 Interrupt Flag */ +#define _LESENSE_IFS_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFS_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH12_DEFAULT (_LESENSE_IFS_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13 (0x1UL << 13) /**< Set CH13 Interrupt Flag */ +#define _LESENSE_IFS_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFS_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH13_DEFAULT (_LESENSE_IFS_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14 (0x1UL << 14) /**< Set CH14 Interrupt Flag */ +#define _LESENSE_IFS_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFS_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH14_DEFAULT (_LESENSE_IFS_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15 (0x1UL << 15) /**< Set CH15 Interrupt Flag */ +#define _LESENSE_IFS_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFS_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CH15_DEFAULT (_LESENSE_IFS_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE (0x1UL << 16) /**< Set SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFS_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFS_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_SCANCOMPLETE_DEFAULT (_LESENSE_IFS_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC (0x1UL << 17) /**< Set DEC Interrupt Flag */ +#define _LESENSE_IFS_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFS_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DEC_DEFAULT (_LESENSE_IFS_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR (0x1UL << 18) /**< Set DECERR Interrupt Flag */ +#define _LESENSE_IFS_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFS_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_DECERR_DEFAULT (_LESENSE_IFS_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV (0x1UL << 19) /**< Set BUFDATAV Interrupt Flag */ +#define _LESENSE_IFS_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFS_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFDATAV_DEFAULT (_LESENSE_IFS_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL (0x1UL << 20) /**< Set BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFS_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFS_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFLEVEL_DEFAULT (_LESENSE_IFS_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF (0x1UL << 21) /**< Set BUFOF Interrupt Flag */ +#define _LESENSE_IFS_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFS_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_BUFOF_DEFAULT (_LESENSE_IFS_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF (0x1UL << 22) /**< Set CNTOF Interrupt Flag */ +#define _LESENSE_IFS_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFS_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFS */ +#define LESENSE_IFS_CNTOF_DEFAULT (_LESENSE_IFS_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFS */ + +/* Bit fields for LESENSE IFC */ +#define _LESENSE_IFC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IFC */ +#define _LESENSE_IFC_MASK 0x007FFFFFUL /**< Mask for LESENSE_IFC */ +#define LESENSE_IFC_CH0 (0x1UL << 0) /**< Clear CH0 Interrupt Flag */ +#define _LESENSE_IFC_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH0_DEFAULT (_LESENSE_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1 (0x1UL << 1) /**< Clear CH1 Interrupt Flag */ +#define _LESENSE_IFC_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH1_DEFAULT (_LESENSE_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2 (0x1UL << 2) /**< Clear CH2 Interrupt Flag */ +#define _LESENSE_IFC_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IFC_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH2_DEFAULT (_LESENSE_IFC_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3 (0x1UL << 3) /**< Clear CH3 Interrupt Flag */ +#define _LESENSE_IFC_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IFC_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH3_DEFAULT (_LESENSE_IFC_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4 (0x1UL << 4) /**< Clear CH4 Interrupt Flag */ +#define _LESENSE_IFC_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IFC_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH4_DEFAULT (_LESENSE_IFC_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5 (0x1UL << 5) /**< Clear CH5 Interrupt Flag */ +#define _LESENSE_IFC_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IFC_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH5_DEFAULT (_LESENSE_IFC_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6 (0x1UL << 6) /**< Clear CH6 Interrupt Flag */ +#define _LESENSE_IFC_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IFC_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH6_DEFAULT (_LESENSE_IFC_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7 (0x1UL << 7) /**< Clear CH7 Interrupt Flag */ +#define _LESENSE_IFC_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IFC_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH7_DEFAULT (_LESENSE_IFC_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8 (0x1UL << 8) /**< Clear CH8 Interrupt Flag */ +#define _LESENSE_IFC_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IFC_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH8_DEFAULT (_LESENSE_IFC_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9 (0x1UL << 9) /**< Clear CH9 Interrupt Flag */ +#define _LESENSE_IFC_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IFC_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH9_DEFAULT (_LESENSE_IFC_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10 (0x1UL << 10) /**< Clear CH10 Interrupt Flag */ +#define _LESENSE_IFC_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IFC_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH10_DEFAULT (_LESENSE_IFC_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11 (0x1UL << 11) /**< Clear CH11 Interrupt Flag */ +#define _LESENSE_IFC_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IFC_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH11_DEFAULT (_LESENSE_IFC_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12 (0x1UL << 12) /**< Clear CH12 Interrupt Flag */ +#define _LESENSE_IFC_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IFC_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH12_DEFAULT (_LESENSE_IFC_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13 (0x1UL << 13) /**< Clear CH13 Interrupt Flag */ +#define _LESENSE_IFC_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IFC_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH13_DEFAULT (_LESENSE_IFC_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14 (0x1UL << 14) /**< Clear CH14 Interrupt Flag */ +#define _LESENSE_IFC_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IFC_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH14_DEFAULT (_LESENSE_IFC_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15 (0x1UL << 15) /**< Clear CH15 Interrupt Flag */ +#define _LESENSE_IFC_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IFC_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CH15_DEFAULT (_LESENSE_IFC_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE (0x1UL << 16) /**< Clear SCANCOMPLETE Interrupt Flag */ +#define _LESENSE_IFC_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IFC_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_SCANCOMPLETE_DEFAULT (_LESENSE_IFC_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC (0x1UL << 17) /**< Clear DEC Interrupt Flag */ +#define _LESENSE_IFC_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IFC_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DEC_DEFAULT (_LESENSE_IFC_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR (0x1UL << 18) /**< Clear DECERR Interrupt Flag */ +#define _LESENSE_IFC_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IFC_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_DECERR_DEFAULT (_LESENSE_IFC_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV (0x1UL << 19) /**< Clear BUFDATAV Interrupt Flag */ +#define _LESENSE_IFC_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IFC_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFDATAV_DEFAULT (_LESENSE_IFC_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL (0x1UL << 20) /**< Clear BUFLEVEL Interrupt Flag */ +#define _LESENSE_IFC_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IFC_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFLEVEL_DEFAULT (_LESENSE_IFC_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF (0x1UL << 21) /**< Clear BUFOF Interrupt Flag */ +#define _LESENSE_IFC_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IFC_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_BUFOF_DEFAULT (_LESENSE_IFC_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF (0x1UL << 22) /**< Clear CNTOF Interrupt Flag */ +#define _LESENSE_IFC_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IFC_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IFC */ +#define LESENSE_IFC_CNTOF_DEFAULT (_LESENSE_IFC_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IFC */ + +/* Bit fields for LESENSE IEN */ +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x007FFFFFUL /**< Mask for LESENSE_IEN */ +#define LESENSE_IEN_CH0 (0x1UL << 0) /**< CH0 Interrupt Enable */ +#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /**< CH1 Interrupt Enable */ +#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /**< CH2 Interrupt Enable */ +#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /**< CH3 Interrupt Enable */ +#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /**< CH4 Interrupt Enable */ +#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /**< CH5 Interrupt Enable */ +#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /**< CH6 Interrupt Enable */ +#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /**< CH7 Interrupt Enable */ +#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /**< CH8 Interrupt Enable */ +#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /**< CH9 Interrupt Enable */ +#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /**< CH10 Interrupt Enable */ +#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /**< CH11 Interrupt Enable */ +#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /**< CH12 Interrupt Enable */ +#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /**< CH13 Interrupt Enable */ +#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /**< CH14 Interrupt Enable */ +#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /**< CH15 Interrupt Enable */ +#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE (0x1UL << 16) /**< SCANCOMPLETE Interrupt Enable */ +#define _LESENSE_IEN_SCANCOMPLETE_SHIFT 16 /**< Shift value for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANCOMPLETE */ +#define _LESENSE_IEN_SCANCOMPLETE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANCOMPLETE_DEFAULT (_LESENSE_IEN_SCANCOMPLETE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /**< DEC Interrupt Enable */ +#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR (0x1UL << 18) /**< DECERR Interrupt Enable */ +#define _LESENSE_IEN_DECERR_SHIFT 18 /**< Shift value for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_MASK 0x40000UL /**< Bit mask for LESENSE_DECERR */ +#define _LESENSE_IEN_DECERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DECERR_DEFAULT (_LESENSE_IEN_DECERR_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV (0x1UL << 19) /**< BUFDATAV Interrupt Enable */ +#define _LESENSE_IEN_BUFDATAV_SHIFT 19 /**< Shift value for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_MASK 0x80000UL /**< Bit mask for LESENSE_BUFDATAV */ +#define _LESENSE_IEN_BUFDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFDATAV_DEFAULT (_LESENSE_IEN_BUFDATAV_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL (0x1UL << 20) /**< BUFLEVEL Interrupt Enable */ +#define _LESENSE_IEN_BUFLEVEL_SHIFT 20 /**< Shift value for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_MASK 0x100000UL /**< Bit mask for LESENSE_BUFLEVEL */ +#define _LESENSE_IEN_BUFLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFLEVEL_DEFAULT (_LESENSE_IEN_BUFLEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF (0x1UL << 21) /**< BUFOF Interrupt Enable */ +#define _LESENSE_IEN_BUFOF_SHIFT 21 /**< Shift value for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_MASK 0x200000UL /**< Bit mask for LESENSE_BUFOF */ +#define _LESENSE_IEN_BUFOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_BUFOF_DEFAULT (_LESENSE_IEN_BUFOF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 22) /**< CNTOF Interrupt Enable */ +#define _LESENSE_IEN_CNTOF_SHIFT 22 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x400000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IEN */ + +/* Bit fields for LESENSE SYNCBUSY */ +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x00000080UL /**< Mask for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 7) /**< CMD Register Busy */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 7 /**< Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x80UL /**< Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ + +/* Bit fields for LESENSE ROUTEPEN */ +#define _LESENSE_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ROUTEPEN */ +#define _LESENSE_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for LESENSE_CH0PEN */ +#define _LESENSE_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH0PEN_DEFAULT (_LESENSE_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH0 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for LESENSE_CH1PEN */ +#define _LESENSE_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH1PEN_DEFAULT (_LESENSE_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for LESENSE_CH2PEN */ +#define _LESENSE_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH2PEN_DEFAULT (_LESENSE_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for LESENSE_CH3PEN */ +#define _LESENSE_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH3PEN_DEFAULT (_LESENSE_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for LESENSE_CH4PEN */ +#define _LESENSE_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH4PEN_DEFAULT (_LESENSE_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for LESENSE_CH5PEN */ +#define _LESENSE_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH5PEN_DEFAULT (_LESENSE_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for LESENSE_CH6PEN */ +#define _LESENSE_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH6PEN_DEFAULT (_LESENSE_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for LESENSE_CH7PEN */ +#define _LESENSE_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH7PEN_DEFAULT (_LESENSE_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for LESENSE_CH8PEN */ +#define _LESENSE_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH8PEN_DEFAULT (_LESENSE_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for LESENSE_CH9PEN */ +#define _LESENSE_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH9PEN_DEFAULT (_LESENSE_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for LESENSE_CH10PEN */ +#define _LESENSE_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH10PEN_DEFAULT (_LESENSE_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for LESENSE_CH11PEN */ +#define _LESENSE_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH11PEN_DEFAULT (_LESENSE_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for LESENSE_CH12PEN */ +#define _LESENSE_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH12PEN_DEFAULT (_LESENSE_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for LESENSE_CH13PEN */ +#define _LESENSE_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH13PEN_DEFAULT (_LESENSE_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for LESENSE_CH14PEN */ +#define _LESENSE_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH14PEN_DEFAULT (_LESENSE_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ +#define _LESENSE_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for LESENSE_CH15PEN */ +#define _LESENSE_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_CH15PEN_DEFAULT (_LESENSE_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN (0x1UL << 16) /**< ALTEX0 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_SHIFT 16 /**< Shift value for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_MASK 0x10000UL /**< Bit mask for LESENSE_ALTEX0PEN */ +#define _LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN (0x1UL << 17) /**< ALTEX1 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_SHIFT 17 /**< Shift value for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_MASK 0x20000UL /**< Bit mask for LESENSE_ALTEX1PEN */ +#define _LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN (0x1UL << 18) /**< ALTEX2 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_SHIFT 18 /**< Shift value for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX2PEN */ +#define _LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN (0x1UL << 19) /**< ALTEX3 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_SHIFT 19 /**< Shift value for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_MASK 0x80000UL /**< Bit mask for LESENSE_ALTEX3PEN */ +#define _LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN (0x1UL << 20) /**< ALTEX4 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_SHIFT 20 /**< Shift value for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_MASK 0x100000UL /**< Bit mask for LESENSE_ALTEX4PEN */ +#define _LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX4PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN (0x1UL << 21) /**< ALTEX5 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_SHIFT 21 /**< Shift value for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX5PEN */ +#define _LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX5PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN (0x1UL << 22) /**< ALTEX6 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_SHIFT 22 /**< Shift value for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_MASK 0x400000UL /**< Bit mask for LESENSE_ALTEX6PEN */ +#define _LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX6PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN (0x1UL << 23) /**< ALTEX7 Pin Enable */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_SHIFT 23 /**< Shift value for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_MASK 0x800000UL /**< Bit mask for LESENSE_ALTEX7PEN */ +#define _LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ROUTEPEN */ +#define LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT (_LESENSE_ROUTEPEN_ALTEX7PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for LESENSE_ROUTEPEN */ + +/* Bit fields for LESENSE ST_TCONFA */ +#define _LESENSE_ST_TCONFA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK 0x0007DFFFUL /**< Mask for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFA_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_COMP_DEFAULT (_LESENSE_ST_TCONFA_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFA_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_MASK_DEFAULT (_LESENSE_ST_TCONFA_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFA_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN (0x1UL << 14) /**< Enable state descriptor chaining */ +#define _LESENSE_ST_TCONFA_CHAIN_SHIFT 14 /**< Shift value for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_MASK 0x4000UL /**< Bit mask for LESENSE_CHAIN */ +#define _LESENSE_ST_TCONFA_CHAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_CHAIN_DEFAULT (_LESENSE_ST_TCONFA_CHAIN_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF (0x1UL << 15) /**< Set interrupt flag enable */ +#define _LESENSE_ST_TCONFA_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFA_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_SETIF_DEFAULT (_LESENSE_ST_TCONFA_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFA_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define _LESENSE_ST_TCONFA_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DEFAULT (_LESENSE_ST_TCONFA_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_NONE (_LESENSE_ST_TCONFA_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UP (_LESENSE_ST_TCONFA_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS0 (_LESENSE_ST_TCONFA_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS1 (_LESENSE_ST_TCONFA_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWN (_LESENSE_ST_TCONFA_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS01 (_LESENSE_ST_TCONFA_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS2 (_LESENSE_ST_TCONFA_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS02 (_LESENSE_ST_TCONFA_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS12 (_LESENSE_ST_TCONFA_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFA_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFA */ +#define LESENSE_ST_TCONFA_PRSACT_PRS012 (_LESENSE_ST_TCONFA_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFA */ + +/* Bit fields for LESENSE ST_TCONFB */ +#define _LESENSE_ST_TCONFB_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK 0x00079FFFUL /**< Mask for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_COMP_SHIFT 0 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_MASK 0xFUL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_ST_TCONFB_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_COMP_DEFAULT (_LESENSE_ST_TCONFB_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_MASK_SHIFT 4 /**< Shift value for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_MASK 0xF0UL /**< Bit mask for LESENSE_MASK */ +#define _LESENSE_ST_TCONFB_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_MASK_DEFAULT (_LESENSE_ST_TCONFB_MASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_SHIFT 8 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT (_LESENSE_ST_TCONFB_NEXTSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF (0x1UL << 15) /**< Set interrupt flag */ +#define _LESENSE_ST_TCONFB_SETIF_SHIFT 15 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_MASK 0x8000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_TCONFB_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_SETIF_DEFAULT (_LESENSE_ST_TCONFB_SETIF_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_SHIFT 16 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_MASK 0x70000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_TCONFB_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define _LESENSE_ST_TCONFB_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DEFAULT (_LESENSE_ST_TCONFB_PRSACT_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_NONE (_LESENSE_ST_TCONFB_PRSACT_NONE << 16) /**< Shifted mode NONE for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UP (_LESENSE_ST_TCONFB_PRSACT_UP << 16) /**< Shifted mode UP for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS0 (_LESENSE_ST_TCONFB_PRSACT_PRS0 << 16) /**< Shifted mode PRS0 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS1 (_LESENSE_ST_TCONFB_PRSACT_PRS1 << 16) /**< Shifted mode PRS1 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWN (_LESENSE_ST_TCONFB_PRSACT_DOWN << 16) /**< Shifted mode DOWN for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS01 (_LESENSE_ST_TCONFB_PRSACT_PRS01 << 16) /**< Shifted mode PRS01 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS2 (_LESENSE_ST_TCONFB_PRSACT_PRS2 << 16) /**< Shifted mode PRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS02 (_LESENSE_ST_TCONFB_PRSACT_PRS02 << 16) /**< Shifted mode PRS02 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_UPANDPRS2 << 16) /**< Shifted mode UPANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS12 (_LESENSE_ST_TCONFB_PRSACT_PRS12 << 16) /**< Shifted mode PRS12 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 (_LESENSE_ST_TCONFB_PRSACT_DOWNANDPRS2 << 16) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_TCONFB */ +#define LESENSE_ST_TCONFB_PRSACT_PRS012 (_LESENSE_ST_TCONFB_PRSACT_PRS012 << 16) /**< Shifted mode PRS012 for LESENSE_ST_TCONFB */ + +/* Bit fields for LESENSE BUF_DATA */ +#define _LESENSE_BUF_DATA_RESETVALUE 0x00000000UL /**< Default value for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_MASK 0x000FFFFFUL /**< Mask for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATA_SHIFT 0 /**< Shift value for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_MASK 0xFFFFUL /**< Bit mask for LESENSE_DATA */ +#define _LESENSE_BUF_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATA_DEFAULT (_LESENSE_BUF_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ +#define _LESENSE_BUF_DATA_DATASRC_SHIFT 16 /**< Shift value for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_MASK 0xF0000UL /**< Bit mask for LESENSE_DATASRC */ +#define _LESENSE_BUF_DATA_DATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_BUF_DATA */ +#define LESENSE_BUF_DATA_DATASRC_DEFAULT (_LESENSE_BUF_DATA_DATASRC_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_BUF_DATA */ + +/* Bit fields for LESENSE CH_TIMING */ +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ + +/* Bit fields for LESENSE CH_INTERACT */ +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x003FFFFFUL /**< Mask for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 12 /**< Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x3000UL /**< Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 12) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 12) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 12) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 12) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 14 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0x1C000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 14) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 14) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 14) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 14) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 14) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 17 /**< Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x60000UL /**< Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 17) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 17) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 17) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 17) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 19) /**< Select clock used for excitation timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 19 /**< Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x80000UL /**< Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 20) /**< Select clock used for timing of sample delay */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 20 /**< Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x100000UL /**< Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 21) /**< Use alternative excite pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 21 /**< Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x200000UL /**< Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT */ + +/* Bit fields for LESENSE CH_EVAL */ +#define _LESENSE_CH_EVAL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MASK 0x007FFFFFUL /**< Mask for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMPTHRES_SHIFT 0 /**< Shift value for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_COMPTHRES */ +#define _LESENSE_CH_EVAL_COMPTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMPTHRES_DEFAULT (_LESENSE_CH_EVAL_COMPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP (0x1UL << 16) /**< Select mode for threshold comparison */ +#define _LESENSE_CH_EVAL_COMP_SHIFT 16 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_MASK 0x10000UL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVAL_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_DEFAULT (_LESENSE_CH_EVAL_COMP_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_LESS (_LESENSE_CH_EVAL_COMP_LESS << 16) /**< Shifted mode LESS for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_COMP_GE (_LESENSE_CH_EVAL_COMP_GE << 16) /**< Shifted mode GE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE (0x1UL << 17) /**< Send result to decoder */ +#define _LESENSE_CH_EVAL_DECODE_SHIFT 17 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_MASK 0x20000UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVAL_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_DECODE_DEFAULT (_LESENSE_CH_EVAL_DECODE_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_SHIFT 18 /**< Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_MASK 0xC0000UL /**< Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DEFAULT (_LESENSE_CH_EVAL_STRSAMPLE_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DISABLE (_LESENSE_CH_EVAL_STRSAMPLE_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATA (_LESENSE_CH_EVAL_STRSAMPLE_DATA << 18) /**< Shifted mode DATA for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_STRSAMPLE_DATASRC (_LESENSE_CH_EVAL_STRSAMPLE_DATASRC << 18) /**< Shifted mode DATASRC for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV (0x1UL << 20) /**< Enable inversion of result */ +#define _LESENSE_CH_EVAL_SCANRESINV_SHIFT 20 /**< Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_MASK 0x100000UL /**< Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVAL_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_SCANRESINV_DEFAULT (_LESENSE_CH_EVAL_SCANRESINV_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SHIFT 21 /**< Shift value for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_MASK 0x600000UL /**< Bit mask for LESENSE_MODE */ +#define _LESENSE_CH_EVAL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define _LESENSE_CH_EVAL_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_DEFAULT (_LESENSE_CH_EVAL_MODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_THRES (_LESENSE_CH_EVAL_MODE_THRES << 21) /**< Shifted mode THRES for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_SLIDINGWIN (_LESENSE_CH_EVAL_MODE_SLIDINGWIN << 21) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVAL */ +#define LESENSE_CH_EVAL_MODE_STEPDET (_LESENSE_CH_EVAL_MODE_STEPDET << 21) /**< Shifted mode STEPDET for LESENSE_CH_EVAL */ + +/** @} End of group EFM32PG12B_LESENSE */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_buf.h new file mode 100644 index 0000000000..2d4dc6bb58 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_buf.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efm32pg12b_lesense_buf.h + * @brief EFM32PG12B_LESENSE_BUF register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_BUF EFM32PG12B LESENSE BUF + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t DATA; /**< Scan results */ +} LESENSE_BUF_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_ch.h new file mode 100644 index 0000000000..219d835d0e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_ch.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efm32pg12b_lesense_ch.h + * @brief EFM32PG12B_LESENSE_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_CH EFM32PG12B LESENSE CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t TIMING; /**< Scan configuration */ + __IOM uint32_t INTERACT; /**< Scan configuration */ + __IOM uint32_t EVAL; /**< Scan configuration */ + uint32_t RESERVED0[1]; /**< Reserved future */ +} LESENSE_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_st.h new file mode 100644 index 0000000000..d1fa3a040b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_st.h @@ -0,0 +1,47 @@ +/**************************************************************************//** + * @file efm32pg12b_lesense_st.h + * @brief EFM32PG12B_LESENSE_ST register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief LESENSE_ST EFM32PG12B LESENSE ST + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t TCONFA; /**< State transition configuration A */ + __IOM uint32_t TCONFB; /**< State transition configuration B */ +} LESENSE_ST_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_letimer.h new file mode 100644 index 0000000000..1554f37d2e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_letimer.h @@ -0,0 +1,620 @@ +/**************************************************************************//** + * @file efm32pg12b_letimer.h + * @brief EFM32PG12B_LETIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_LETIMER + * @{ + * @brief EFM32PG12B_LETIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[2]; /**< Reserved for future use **/ + __IOM uint32_t PRSSEL; /**< PRS Input Select Register */ +} LETIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_LETIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */ +#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IFS */ +#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */ +#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */ +#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */ +#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */ +#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */ +#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */ +#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */ +#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */ +#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */ + +/* Bit fields for LETIMER IFC */ +#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */ +#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */ +#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */ +#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */ +#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */ +#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */ +#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */ +#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */ +#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */ +#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER ROUTEPEN */ +#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */ +#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */ +#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */ +#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */ +#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */ +#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */ + +/* Bit fields for LETIMER ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */ +#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */ +#define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */ + +/* Bit fields for LETIMER PRSSEL */ +#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */ +#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */ +#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */ + +/** @} End of group EFM32PG12B_LETIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_leuart.h new file mode 100644 index 0000000000..348761e48e --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_leuart.h @@ -0,0 +1,835 @@ +/**************************************************************************//** + * @file efm32pg12b_leuart.h + * @brief EFM32PG12B_LEUART register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_LEUART + * @{ + * @brief EFM32PG12B_LEUART Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IOM uint32_t STARTFRAME; /**< Start Frame Register */ + __IOM uint32_t SIGFRAME; /**< Signal Frame Register */ + __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PULSECTRL; /**< Pulse Control Register */ + + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[2]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< LEUART Input Register */ +} LEUART_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_LEUART_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for LEUART CTRL */ +#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ +#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */ +#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ +#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */ +#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ +#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ +#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ +#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ +#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ +#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */ +#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */ +#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ +#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ +#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */ +#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */ +#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */ +#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ +#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ +#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */ +#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ +#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */ +#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ +#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */ +#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ +#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */ +#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ +#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ +#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */ +#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ +#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */ +#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ +#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */ +#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ +#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */ +#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ +#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ +#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ +#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ +#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ + +/* Bit fields for LEUART CMD */ +#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ +#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ +#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ +#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ +#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ +#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ +#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ +#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ +#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ +#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */ +#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ +#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ +#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ + +/* Bit fields for LEUART STATUS */ +#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */ +#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */ +#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ +#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ +#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */ +#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ +#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */ +#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ +#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */ +#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */ +#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */ +#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */ +#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ +#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */ + +/* Bit fields for LEUART CLKDIV */ +#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */ +#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */ +#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ +#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ + +/* Bit fields for LEUART STARTFRAME */ +#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ +#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ + +/* Bit fields for LEUART SIGFRAME */ +#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ +#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ + +/* Bit fields for LEUART RXDATAX */ +#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ +#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */ +#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */ +#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ +#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ + +/* Bit fields for LEUART RXDATA */ +#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ +#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ +#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ +#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ + +/* Bit fields for LEUART RXDATAXP */ +#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ +#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ +#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */ +#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ +#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */ +#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ +#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ +#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ + +/* Bit fields for LEUART TXDATAX */ +#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ +#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ +#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */ +#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ +#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ +#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ +#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ + +/* Bit fields for LEUART TXDATA */ +#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ +#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ +#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ + +/* Bit fields for LEUART IF */ +#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ +#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ +#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */ +#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */ +#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */ +#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */ +#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */ +#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */ +#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */ +#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ +#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */ + +/* Bit fields for LEUART IFS */ +#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ +#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ +#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */ +#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */ +#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */ +#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */ +#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */ +#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */ +#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */ +#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */ +#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ +#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ + +/* Bit fields for LEUART IFC */ +#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ +#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ +#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */ +#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */ +#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */ +#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */ +#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */ +#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */ +#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */ +#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */ +#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ +#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ + +/* Bit fields for LEUART IEN */ +#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ +#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ +#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ +#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ +#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ +#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ +#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */ +#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ +#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */ +#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ +#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */ +#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ +#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */ +#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ +#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ +#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */ +#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ +#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ +#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */ +#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ +#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */ +#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ +#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */ +#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ +#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ +#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ + +/* Bit fields for LEUART PULSECTRL */ +#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ +#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ +#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */ +#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ +#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */ +#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ +#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ +#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ + +/* Bit fields for LEUART FREEZE */ +#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ +#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ +#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ +#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ +#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ + +/* Bit fields for LEUART SYNCBUSY */ +#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ +#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ +#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ +#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */ +#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ +#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */ +#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ +#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */ +#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ +#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */ +#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ +#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */ +#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ +#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */ +#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ +#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ +#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ + +/* Bit fields for LEUART ROUTEPEN */ +#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */ +#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ +#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ +#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ +#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ + +/* Bit fields for LEUART ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */ +#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */ +#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */ +#define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */ +#define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */ + +/* Bit fields for LEUART INPUT */ +#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */ +#define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */ +#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */ +#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */ +#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */ +#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ +#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */ + +/** @} End of group EFM32PG12B_LEUART */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_msc.h new file mode 100644 index 0000000000..4864b6f19b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_msc.h @@ -0,0 +1,664 @@ +/**************************************************************************//** + * @file efm32pg12b_msc.h + * @brief EFM32PG12B_MSC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_MSC + * @{ + * @brief EFM32PG12B_MSC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Memory System Control Register */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ + __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ + __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ + + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ + + uint32_t RESERVED3[1]; /**< Reserved for future use **/ + __IOM uint32_t STARTUP; /**< Startup Control */ + + uint32_t RESERVED4[4]; /**< Reserved for future use **/ + __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ + __IOM uint32_t CMD; /**< Command Register */ + + uint32_t RESERVED5[6]; /**< Reserved for future use **/ + __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader read and write enable, write once register */ + __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ + __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ + + uint32_t RESERVED6[25]; /**< Reserved for future use **/ + __IOM uint32_t RAMCTRL; /**< RAM Control enable Register */ +} MSC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_MSC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC CTRL */ +#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ +#define _MSC_CTRL_MASK 0x0000001FUL /**< Mask for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ +#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ +#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ +#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */ +#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ +#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ +#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ +#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ +#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ +#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ +#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ +#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ +#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ +#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ +#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ +#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ +#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ +#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ +#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ +#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ +#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ +#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ +#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ +#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ +#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */ +#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ +#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ +#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ +#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ +#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ +#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */ +#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ +#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ +#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ +#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ +#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ +#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ +#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ +#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ +#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ +#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ +#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x0000017FUL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ +#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ +#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */ +#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash controller write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ +#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IFS */ +#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ +#define _MSC_IFS_MASK 0x0000017FUL /**< Mask for MSC_IFS */ +#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ +#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ +#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ +#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ +#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ +#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ +#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ +#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ +#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ +#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ + +/* Bit fields for MSC IFC */ +#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ +#define _MSC_IFC_MASK 0x0000017FUL /**< Mask for MSC_IFC */ +#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ +#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ +#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ +#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ +#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ +#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ +#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ +#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ +#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ +#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x0000017FUL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ +#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ +#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ +#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ +#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ +#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ +#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ +#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ +#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ +#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ +#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ +#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ +#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC CACHECMD */ +#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ +#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ +#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ +#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ +#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ +#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ +#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ + +/* Bit fields for MSC CACHEHITS */ +#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ +#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ +#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ + +/* Bit fields for MSC CACHEMISSES */ +#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ +#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ +#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ + +/* Bit fields for MSC MASSLOCK */ +#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ +#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ + +/* Bit fields for MSC STARTUP */ +#define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */ +#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ +#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ +#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ +#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ +#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ +#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ +#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ +#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ +#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ +#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ +#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ +#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ +#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ + +/* Bit fields for MSC BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ +#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ +#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ +#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ +#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ +#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Enable */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ +#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Eanble */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ +#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ +#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ + +/* Bit fields for MSC AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ +#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software unlock AAP command */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ +#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ +#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ + +/* Bit fields for MSC CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ +#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ +#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ + +/* Bit fields for MSC RAMCTRL */ +#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ +#define _MSC_RAMCTRL_MASK 0x00090101UL /**< Mask for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */ +#define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */ +#define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */ +#define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */ +#define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */ +#define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */ +#define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ +#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ +#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMSEQCACHEEN (0x1UL << 19) /**< RAMSEQ CACHE Enable */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_SHIFT 19 /**< Shift value for MSC_RAMSEQCACHEEN */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_MASK 0x80000UL /**< Bit mask for MSC_RAMSEQCACHEEN */ +#define _MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ +#define MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ + +/** @} End of group EFM32PG12B_MSC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_pcnt.h new file mode 100644 index 0000000000..d7ae695a97 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_pcnt.h @@ -0,0 +1,706 @@ +/**************************************************************************//** + * @file efm32pg12b_pcnt.h + * @brief EFM32PG12B_PCNT register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_PCNT + * @{ + * @brief EFM32PG12B_PCNT Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Top Value Buffer Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[4]; /**< Reserved for future use **/ + __IOM uint32_t FREEZE; /**< Freeze Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + uint32_t RESERVED2[7]; /**< Reserved for future use **/ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t INPUT; /**< PCNT Input Register */ + __IOM uint32_t OVSCFG; /**< Oversampling Config Register */ +} PCNT_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_PCNT_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */ +#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */ +#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */ +#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */ +#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */ +#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */ +#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */ +#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */ +#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */ +#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */ +#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */ +#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */ +#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */ +#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */ +#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */ +#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */ +#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */ +#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */ +#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */ +#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */ +#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */ +#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */ +#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */ +#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS gate enable */ +#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */ +#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS polarity select */ +#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */ +#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */ +#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */ +#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */ +#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High frequency value select */ +#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */ +#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */ +#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */ +#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered compare Interrupt Read Flag */ +#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */ +#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IFS */ +#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */ +#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */ +#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */ +#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */ +#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */ +#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */ +#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */ +#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */ +#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ +#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */ + +/* Bit fields for PCNT IFC */ +#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */ +#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */ +#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */ +#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */ +#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */ +#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */ +#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */ +#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */ +#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ +#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */ +#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */ +#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */ +#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */ +#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT ROUTELOC0 */ +#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */ +#define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */ +#define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */ + +/* Bit fields for PCNT FREEZE */ +#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */ +#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ +#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */ +#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */ +#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */ +#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */ +#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */ +#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT INPUT */ +#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */ +#define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */ +#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */ +#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */ +#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ +#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */ +#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ +#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */ + +/* Bit fields for PCNT OVSCFG */ +#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */ +#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */ +#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */ + +/** @} End of group EFM32PG12B_PCNT */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs.h new file mode 100644 index 0000000000..969bfbc771 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs.h @@ -0,0 +1,1089 @@ +/**************************************************************************//** + * @file efm32pg12b_prs.h + * @brief EFM32PG12B_PRS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_PRS + * @{ + * @brief EFM32PG12B_PRS Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t SWLEVEL; /**< Software Level Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED1[5]; /**< Reserved for future use **/ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ + __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ + uint32_t RESERVED2[1]; /**< Reserved for future use **/ + __IM uint32_t PEEK; /**< PRS Channel Values */ + + uint32_t RESERVED3[3]; /**< Reserved registers */ + PRS_CH_TypeDef CH[12]; /**< Channel registers */ +} PRS_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_PRS_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS SWPULSE */ +#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ +#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ +#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ +#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ +#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ +#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ +#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ +#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ +#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ +#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ +#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ +#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ +#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ +#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ +#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ + +/* Bit fields for PRS SWLEVEL */ +#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ +#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ +#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ +#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ +#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ +#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ +#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ +#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ +#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ +#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ +#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ +#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ +#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ +#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ +#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ + +/* Bit fields for PRS ROUTEPEN */ +#define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ +#define _PRS_ROUTEPEN_MASK 0x00000FFFUL /**< Mask for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ +#define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ +#define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ +#define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ +#define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ +#define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ +#define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ +#define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ +#define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ +#define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ +#define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ +#define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ +#define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ +#define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ +#define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ +#define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ +#define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ +#define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ +#define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ +#define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ +#define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ +#define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ +#define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ +#define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ +#define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ +#define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ + +/* Bit fields for PRS ROUTELOC0 */ +#define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_MASK 0x0F07070FUL /**< Mask for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_MASK 0xFUL /**< Bit mask for PRS_CH0LOC */ +#define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC4 (_PRS_ROUTELOC0_CH0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC5 (_PRS_ROUTELOC0_CH0LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC6 (_PRS_ROUTELOC0_CH0LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC7 (_PRS_ROUTELOC0_CH0LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC8 (_PRS_ROUTELOC0_CH0LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC9 (_PRS_ROUTELOC0_CH0LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC10 (_PRS_ROUTELOC0_CH0LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC11 (_PRS_ROUTELOC0_CH0LOC_LOC11 << 0) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC12 (_PRS_ROUTELOC0_CH0LOC_LOC12 << 0) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH0LOC_LOC13 (_PRS_ROUTELOC0_CH0LOC_LOC13 << 0) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_MASK 0x700UL /**< Bit mask for PRS_CH1LOC */ +#define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH1LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC4 (_PRS_ROUTELOC0_CH1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC5 (_PRS_ROUTELOC0_CH1LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC6 (_PRS_ROUTELOC0_CH1LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH1LOC_LOC7 (_PRS_ROUTELOC0_CH1LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_MASK 0x70000UL /**< Bit mask for PRS_CH2LOC */ +#define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH2LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC4 (_PRS_ROUTELOC0_CH2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC5 (_PRS_ROUTELOC0_CH2LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC6 (_PRS_ROUTELOC0_CH2LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH2LOC_LOC7 (_PRS_ROUTELOC0_CH2LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH3LOC */ +#define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC0 */ +#define _PRS_ROUTELOC0_CH3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC4 (_PRS_ROUTELOC0_CH3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC5 (_PRS_ROUTELOC0_CH3LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC6 (_PRS_ROUTELOC0_CH3LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC7 (_PRS_ROUTELOC0_CH3LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC8 (_PRS_ROUTELOC0_CH3LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC9 (_PRS_ROUTELOC0_CH3LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC10 (_PRS_ROUTELOC0_CH3LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC11 (_PRS_ROUTELOC0_CH3LOC_LOC11 << 24) /**< Shifted mode LOC11 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC12 (_PRS_ROUTELOC0_CH3LOC_LOC12 << 24) /**< Shifted mode LOC12 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC13 (_PRS_ROUTELOC0_CH3LOC_LOC13 << 24) /**< Shifted mode LOC13 for PRS_ROUTELOC0 */ +#define PRS_ROUTELOC0_CH3LOC_LOC14 (_PRS_ROUTELOC0_CH3LOC_LOC14 << 24) /**< Shifted mode LOC14 for PRS_ROUTELOC0 */ + +/* Bit fields for PRS ROUTELOC1 */ +#define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_MASK 0x0F1F0707UL /**< Mask for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_MASK 0x7UL /**< Bit mask for PRS_CH4LOC */ +#define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH4LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC3 (_PRS_ROUTELOC1_CH4LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC4 (_PRS_ROUTELOC1_CH4LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC5 (_PRS_ROUTELOC1_CH4LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH4LOC_LOC6 (_PRS_ROUTELOC1_CH4LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_MASK 0x700UL /**< Bit mask for PRS_CH5LOC */ +#define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH5LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC3 (_PRS_ROUTELOC1_CH5LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC4 (_PRS_ROUTELOC1_CH5LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC5 (_PRS_ROUTELOC1_CH5LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH5LOC_LOC6 (_PRS_ROUTELOC1_CH5LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_MASK 0x1F0000UL /**< Bit mask for PRS_CH6LOC */ +#define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH6LOC_LOC17 0x00000011UL /**< Mode LOC17 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC3 (_PRS_ROUTELOC1_CH6LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC4 (_PRS_ROUTELOC1_CH6LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC5 (_PRS_ROUTELOC1_CH6LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC6 (_PRS_ROUTELOC1_CH6LOC_LOC6 << 16) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC7 (_PRS_ROUTELOC1_CH6LOC_LOC7 << 16) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC8 (_PRS_ROUTELOC1_CH6LOC_LOC8 << 16) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC9 (_PRS_ROUTELOC1_CH6LOC_LOC9 << 16) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC10 (_PRS_ROUTELOC1_CH6LOC_LOC10 << 16) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC11 (_PRS_ROUTELOC1_CH6LOC_LOC11 << 16) /**< Shifted mode LOC11 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC12 (_PRS_ROUTELOC1_CH6LOC_LOC12 << 16) /**< Shifted mode LOC12 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC13 (_PRS_ROUTELOC1_CH6LOC_LOC13 << 16) /**< Shifted mode LOC13 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC14 (_PRS_ROUTELOC1_CH6LOC_LOC14 << 16) /**< Shifted mode LOC14 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC15 (_PRS_ROUTELOC1_CH6LOC_LOC15 << 16) /**< Shifted mode LOC15 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC16 (_PRS_ROUTELOC1_CH6LOC_LOC16 << 16) /**< Shifted mode LOC16 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH6LOC_LOC17 (_PRS_ROUTELOC1_CH6LOC_LOC17 << 16) /**< Shifted mode LOC17 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_MASK 0xF000000UL /**< Bit mask for PRS_CH7LOC */ +#define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC1 */ +#define _PRS_ROUTELOC1_CH7LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC3 (_PRS_ROUTELOC1_CH7LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC4 (_PRS_ROUTELOC1_CH7LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC5 (_PRS_ROUTELOC1_CH7LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC6 (_PRS_ROUTELOC1_CH7LOC_LOC6 << 24) /**< Shifted mode LOC6 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC7 (_PRS_ROUTELOC1_CH7LOC_LOC7 << 24) /**< Shifted mode LOC7 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC8 (_PRS_ROUTELOC1_CH7LOC_LOC8 << 24) /**< Shifted mode LOC8 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC9 (_PRS_ROUTELOC1_CH7LOC_LOC9 << 24) /**< Shifted mode LOC9 for PRS_ROUTELOC1 */ +#define PRS_ROUTELOC1_CH7LOC_LOC10 (_PRS_ROUTELOC1_CH7LOC_LOC10 << 24) /**< Shifted mode LOC10 for PRS_ROUTELOC1 */ + +/* Bit fields for PRS ROUTELOC2 */ +#define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_MASK 0x07071F0FUL /**< Mask for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_MASK 0xFUL /**< Bit mask for PRS_CH8LOC */ +#define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH8LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC3 (_PRS_ROUTELOC2_CH8LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC4 (_PRS_ROUTELOC2_CH8LOC_LOC4 << 0) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC5 (_PRS_ROUTELOC2_CH8LOC_LOC5 << 0) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC6 (_PRS_ROUTELOC2_CH8LOC_LOC6 << 0) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC7 (_PRS_ROUTELOC2_CH8LOC_LOC7 << 0) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC8 (_PRS_ROUTELOC2_CH8LOC_LOC8 << 0) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC9 (_PRS_ROUTELOC2_CH8LOC_LOC9 << 0) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH8LOC_LOC10 (_PRS_ROUTELOC2_CH8LOC_LOC10 << 0) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_MASK 0x1F00UL /**< Bit mask for PRS_CH9LOC */ +#define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC6 0x00000006UL /**< Mode LOC6 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC7 0x00000007UL /**< Mode LOC7 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC8 0x00000008UL /**< Mode LOC8 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC9 0x00000009UL /**< Mode LOC9 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC10 0x0000000AUL /**< Mode LOC10 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC11 0x0000000BUL /**< Mode LOC11 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC12 0x0000000CUL /**< Mode LOC12 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC13 0x0000000DUL /**< Mode LOC13 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC14 0x0000000EUL /**< Mode LOC14 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC15 0x0000000FUL /**< Mode LOC15 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH9LOC_LOC16 0x00000010UL /**< Mode LOC16 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC3 (_PRS_ROUTELOC2_CH9LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC4 (_PRS_ROUTELOC2_CH9LOC_LOC4 << 8) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC5 (_PRS_ROUTELOC2_CH9LOC_LOC5 << 8) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC6 (_PRS_ROUTELOC2_CH9LOC_LOC6 << 8) /**< Shifted mode LOC6 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC7 (_PRS_ROUTELOC2_CH9LOC_LOC7 << 8) /**< Shifted mode LOC7 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC8 (_PRS_ROUTELOC2_CH9LOC_LOC8 << 8) /**< Shifted mode LOC8 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC9 (_PRS_ROUTELOC2_CH9LOC_LOC9 << 8) /**< Shifted mode LOC9 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC10 (_PRS_ROUTELOC2_CH9LOC_LOC10 << 8) /**< Shifted mode LOC10 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC11 (_PRS_ROUTELOC2_CH9LOC_LOC11 << 8) /**< Shifted mode LOC11 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC12 (_PRS_ROUTELOC2_CH9LOC_LOC12 << 8) /**< Shifted mode LOC12 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC13 (_PRS_ROUTELOC2_CH9LOC_LOC13 << 8) /**< Shifted mode LOC13 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC14 (_PRS_ROUTELOC2_CH9LOC_LOC14 << 8) /**< Shifted mode LOC14 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC15 (_PRS_ROUTELOC2_CH9LOC_LOC15 << 8) /**< Shifted mode LOC15 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH9LOC_LOC16 (_PRS_ROUTELOC2_CH9LOC_LOC16 << 8) /**< Shifted mode LOC16 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_MASK 0x70000UL /**< Bit mask for PRS_CH10LOC */ +#define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH10LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC3 (_PRS_ROUTELOC2_CH10LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC4 (_PRS_ROUTELOC2_CH10LOC_LOC4 << 16) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH10LOC_LOC5 (_PRS_ROUTELOC2_CH10LOC_LOC5 << 16) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_MASK 0x7000000UL /**< Bit mask for PRS_CH11LOC */ +#define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC4 0x00000004UL /**< Mode LOC4 for PRS_ROUTELOC2 */ +#define _PRS_ROUTELOC2_CH11LOC_LOC5 0x00000005UL /**< Mode LOC5 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC3 (_PRS_ROUTELOC2_CH11LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC4 (_PRS_ROUTELOC2_CH11LOC_LOC4 << 24) /**< Shifted mode LOC4 for PRS_ROUTELOC2 */ +#define PRS_ROUTELOC2_CH11LOC_LOC5 (_PRS_ROUTELOC2_CH11LOC_LOC5 << 24) /**< Shifted mode LOC5 for PRS_ROUTELOC2 */ + +/* Bit fields for PRS CTRL */ +#define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ +#define _PRS_CTRL_MASK 0x0000001FUL /**< Mask for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ +#define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ +#define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_MASK 0x1EUL /**< Bit mask for PRS_SEVONPRSSEL */ +#define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ +#define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ +#define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ + +/* Bit fields for PRS DMAREQ0 */ +#define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ +#define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ +#define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ + +/* Bit fields for PRS DMAREQ1 */ +#define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_MASK 0x000003C0UL /**< Mask for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_MASK 0x3C0UL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ +#define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ +#define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ + +/* Bit fields for PRS PEEK */ +#define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ +#define _PRS_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_PEEK */ +#define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ +#define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ + +/* Bit fields for PRS CH_CTRL */ +#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000002UL /**< Mode PRSH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000003UL /**< Mode ACMP0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000004UL /**< Mode ACMP1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000005UL /**< Mode ADC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000007UL /**< Mode LESENSEL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000008UL /**< Mode LESENSEH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x00000009UL /**< Mode LESENSED for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000000AUL /**< Mode LESENSE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_RTCC 0x0000000BUL /**< Mode RTCC for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x0000000CUL /**< Mode GPIOL for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000DUL /**< Mode GPIOH for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000EUL /**< Mode LETIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000FUL /**< Mode PCNT0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x00000010UL /**< Mode PCNT1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x00000011UL /**< Mode PCNT2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000012UL /**< Mode CMU for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000018UL /**< Mode VDAC0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x0000001AUL /**< Mode CRYOTIMER for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x0000003EUL /**< Mode WTIMER0 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x0000003FUL /**< Mode WTIMER1 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ +#define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ +#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ +#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ +#define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ +#define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ +#define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ +#define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ +#define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ +#define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ +#define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ +#define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ +#define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous reflex */ +#define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ +#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ +#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ + +/** @} End of group EFM32PG12B_PRS */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_ch.h new file mode 100644 index 0000000000..59bdce89ab --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_ch.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efm32pg12b_prs_ch.h + * @brief EFM32PG12B_PRS_CH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief PRS_CH EFM32PG12B PRS CH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Channel Control Register */ +} PRS_CH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_signals.h new file mode 100644 index 0000000000..38f4b3dca2 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_signals.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file efm32pg12b_prs_signals.h + * @brief EFM32PG12B_PRS_SIGNALS register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @addtogroup EFM32PG12B_PRS_Signals + * @{ + * @brief PRS Signal names + *****************************************************************************/ +#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ +#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ +#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ +#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ +#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ +#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ +#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ +#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ +#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ +#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ +#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ +#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ +#define PRS_ACMP0_OUT ((3 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ACMP1_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ +#define PRS_ADC0_SINGLE ((5 << 8) + 0) /**< PRS ADC single conversion done */ +#define PRS_ADC0_SCAN ((5 << 8) + 1) /**< PRS ADC scan conversion done */ +#define PRS_LESENSE_SCANRES0 ((7 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ +#define PRS_LESENSE_SCANRES1 ((7 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ +#define PRS_LESENSE_SCANRES2 ((7 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ +#define PRS_LESENSE_SCANRES3 ((7 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ +#define PRS_LESENSE_SCANRES4 ((7 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ +#define PRS_LESENSE_SCANRES5 ((7 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ +#define PRS_LESENSE_SCANRES6 ((7 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ +#define PRS_LESENSE_SCANRES7 ((7 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ +#define PRS_LESENSE_SCANRES8 ((8 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ +#define PRS_LESENSE_SCANRES9 ((8 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ +#define PRS_LESENSE_SCANRES10 ((8 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ +#define PRS_LESENSE_SCANRES11 ((8 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ +#define PRS_LESENSE_SCANRES12 ((8 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ +#define PRS_LESENSE_SCANRES13 ((8 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ +#define PRS_LESENSE_SCANRES14 ((8 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ +#define PRS_LESENSE_SCANRES15 ((8 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ +#define PRS_LESENSE_DEC0 ((9 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ +#define PRS_LESENSE_DEC1 ((9 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ +#define PRS_LESENSE_DEC2 ((9 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ +#define PRS_LESENSE_DECCMP ((9 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ +#define PRS_LESENSE_MEASACT ((10 << 8) + 0) /**< PRS LESENSE Measurement active */ +#define PRS_RTCC_CCV0 ((11 << 8) + 1) /**< PRS RTCC Compare 0 */ +#define PRS_RTCC_CCV1 ((11 << 8) + 2) /**< PRS RTCC Compare 1 */ +#define PRS_RTCC_CCV2 ((11 << 8) + 3) /**< PRS RTCC Compare 2 */ +#define PRS_GPIO_PIN0 ((12 << 8) + 0) /**< PRS GPIO pin 0 */ +#define PRS_GPIO_PIN1 ((12 << 8) + 1) /**< PRS GPIO pin 1 */ +#define PRS_GPIO_PIN2 ((12 << 8) + 2) /**< PRS GPIO pin 2 */ +#define PRS_GPIO_PIN3 ((12 << 8) + 3) /**< PRS GPIO pin 3 */ +#define PRS_GPIO_PIN4 ((12 << 8) + 4) /**< PRS GPIO pin 4 */ +#define PRS_GPIO_PIN5 ((12 << 8) + 5) /**< PRS GPIO pin 5 */ +#define PRS_GPIO_PIN6 ((12 << 8) + 6) /**< PRS GPIO pin 6 */ +#define PRS_GPIO_PIN7 ((12 << 8) + 7) /**< PRS GPIO pin 7 */ +#define PRS_GPIO_PIN8 ((13 << 8) + 0) /**< PRS GPIO pin 8 */ +#define PRS_GPIO_PIN9 ((13 << 8) + 1) /**< PRS GPIO pin 9 */ +#define PRS_GPIO_PIN10 ((13 << 8) + 2) /**< PRS GPIO pin 10 */ +#define PRS_GPIO_PIN11 ((13 << 8) + 3) /**< PRS GPIO pin 11 */ +#define PRS_GPIO_PIN12 ((13 << 8) + 4) /**< PRS GPIO pin 12 */ +#define PRS_GPIO_PIN13 ((13 << 8) + 5) /**< PRS GPIO pin 13 */ +#define PRS_GPIO_PIN14 ((13 << 8) + 6) /**< PRS GPIO pin 14 */ +#define PRS_GPIO_PIN15 ((13 << 8) + 7) /**< PRS GPIO pin 15 */ +#define PRS_LETIMER0_CH0 ((14 << 8) + 0) /**< PRS LETIMER CH0 Out */ +#define PRS_LETIMER0_CH1 ((14 << 8) + 1) /**< PRS LETIMER CH1 Out */ +#define PRS_PCNT0_TCC ((15 << 8) + 0) /**< PRS PCNT0 Triggered compare match */ +#define PRS_PCNT0_UFOF ((15 << 8) + 1) /**< PRS PCNT0 Counter overflow or underflow */ +#define PRS_PCNT0_DIR ((15 << 8) + 2) /**< PRS PCNT0 Counter direction */ +#define PRS_PCNT1_TCC ((16 << 8) + 0) /**< PRS PCNT1 Triggered compare match */ +#define PRS_PCNT1_UFOF ((16 << 8) + 1) /**< PRS PCNT1 Counter overflow or underflow */ +#define PRS_PCNT1_DIR ((16 << 8) + 2) /**< PRS PCNT1 Counter direction */ +#define PRS_PCNT2_TCC ((17 << 8) + 0) /**< PRS PCNT2 Triggered compare match */ +#define PRS_PCNT2_UFOF ((17 << 8) + 1) /**< PRS PCNT2 Counter overflow or underflow */ +#define PRS_PCNT2_DIR ((17 << 8) + 2) /**< PRS PCNT2 Counter direction */ +#define PRS_CMU_CLKOUT0 ((18 << 8) + 0) /**< PRS Clock Output 0 */ +#define PRS_CMU_CLKOUT1 ((18 << 8) + 1) /**< PRS Clock Output 1 */ +#define PRS_VDAC0_CH0 ((24 << 8) + 0) /**< PRS DAC ch0 conversion done */ +#define PRS_VDAC0_CH1 ((24 << 8) + 1) /**< PRS DAC ch1 conversion done */ +#define PRS_VDAC0_OPA0 ((24 << 8) + 2) /**< PRS OPA0 warmedup or outputvalid based on OPA0PRSOUTMODE mode in OPACTRL. */ +#define PRS_VDAC0_OPA1 ((24 << 8) + 3) /**< PRS OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL. */ +#define PRS_VDAC0_OPA2 ((24 << 8) + 4) /**< PRS OPA2 warmedup or outputvalid based on OPA2PRSOUTMODE mode in OPACTRL. */ +#define PRS_CRYOTIMER_PERIOD ((26 << 8) + 0) /**< PRS CRYOTIMER Output */ +#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS USART 0 IRDA out */ +#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS USART 0 TX complete */ +#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS USART 0 RX Data Valid */ +#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS USART 0 RTS */ +#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS USART 0 TX */ +#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS USART 0 CS */ +#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS USART 1 TX complete */ +#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS USART 1 RX Data Valid */ +#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS USART 1 RTS */ +#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS USART 1 TX */ +#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS USART 1 CS */ +#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ +#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS USART 2 TX complete */ +#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS USART 2 RX Data Valid */ +#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS USART 2 RTS */ +#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS USART 2 TX */ +#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS USART 2 CS */ +#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS USART 3 TX complete */ +#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS USART 3 RX Data Valid */ +#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS USART 3 RTS */ +#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS USART 3 TX */ +#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS USART 3 CS */ +#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS Timer 0 Underflow */ +#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS Timer 0 Overflow */ +#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */ +#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */ +#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */ +#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS Timer 1 Underflow */ +#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS Timer 1 Overflow */ +#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */ +#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */ +#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */ +#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */ +#define PRS_WTIMER0_UF ((62 << 8) + 0) /**< PRS Timer 2 Underflow */ +#define PRS_WTIMER0_OF ((62 << 8) + 1) /**< PRS Timer 2 Overflow */ +#define PRS_WTIMER0_CC0 ((62 << 8) + 2) /**< PRS Timer 2 Compare/Capture 0 */ +#define PRS_WTIMER0_CC1 ((62 << 8) + 3) /**< PRS Timer 2 Compare/Capture 1 */ +#define PRS_WTIMER0_CC2 ((62 << 8) + 4) /**< PRS Timer 2 Compare/Capture 2 */ +#define PRS_WTIMER1_UF ((63 << 8) + 0) /**< PRS Timer 3 Underflow */ +#define PRS_WTIMER1_OF ((63 << 8) + 1) /**< PRS Timer 3 Overflow */ +#define PRS_WTIMER1_CC0 ((63 << 8) + 2) /**< PRS Timer 3 Compare/Capture 0 */ +#define PRS_WTIMER1_CC1 ((63 << 8) + 3) /**< PRS Timer 3 Compare/Capture 1 */ +#define PRS_WTIMER1_CC2 ((63 << 8) + 4) /**< PRS Timer 3 Compare/Capture 2 */ +#define PRS_WTIMER1_CC3 ((63 << 8) + 5) /**< PRS Timer 3 Compare/Capture 3 */ +#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ +#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ +#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ + +/** @} End of group EFM32PG12B_PRS */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rmu.h new file mode 100644 index 0000000000..c7e01b16ff --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rmu.h @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file efm32pg12b_rmu.h + * @brief EFM32PG12B_RMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_RMU + * @{ + * @brief EFM32PG12B_RMU Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t RSTCAUSE; /**< Reset Cause Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t RST; /**< Reset Control Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ +} RMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_RMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for RMU CTRL */ +#define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */ +#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */ +#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */ +#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */ +#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */ +#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ +#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */ +#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */ +#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ +#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */ + +/* Bit fields for RMU RSTCAUSE */ +#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ +#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */ +#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ +#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */ +#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */ +#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */ +#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */ +#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */ +#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */ +#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */ +#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */ +#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */ +#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */ +#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */ +#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */ +#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */ +#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */ +#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */ +#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */ +#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ + +/* Bit fields for RMU CMD */ +#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ +#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ +#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ +#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ +#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ +#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ + +/* Bit fields for RMU RST */ +#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */ +#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */ + +/* Bit fields for RMU LOCK */ +#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */ +#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */ +#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */ +#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */ +#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */ + +/** @} End of group EFM32PG12B_RMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_romtable.h new file mode 100644 index 0000000000..6c1c2920e5 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_romtable.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file efm32pg12b_romtable.h + * @brief EFM32PG12B_ROMTABLE register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_ROMTABLE + * @{ + * @brief Chip Information, Revision numbers + *****************************************************************************/ +typedef struct +{ + __IM uint32_t PID4; /**< JEP_106_BANK */ + __IM uint32_t PID5; /**< Unused */ + __IM uint32_t PID6; /**< Unused */ + __IM uint32_t PID7; /**< Unused */ + __IM uint32_t PID0; /**< Chip family LSB, chip major revision */ + __IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */ + __IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */ + __IM uint32_t PID3; /**< Chip minor rev LSB */ + __IM uint32_t CID0; /**< Unused */ +} ROMTABLE_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_ROMTABLE_BitFields + * @{ + *****************************************************************************/ +/* Bit fields for EFM32PG12B_ROMTABLE */ +#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */ +#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */ +#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */ +#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */ +#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */ +#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */ + +/** @} End of group EFM32PG12B_ROMTABLE */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc.h new file mode 100644 index 0000000000..9b2746102a --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc.h @@ -0,0 +1,695 @@ +/**************************************************************************//** + * @file efm32pg12b_rtcc.h + * @brief EFM32PG12B_RTCC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_RTCC + * @{ + * @brief EFM32PG12B_RTCC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */ + __IOM uint32_t TIME; /**< Time of day register */ + __IOM uint32_t DATE; /**< Date register */ + __IM uint32_t IF; /**< RTCC Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ + + RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */ + + uint32_t RESERVED0[37]; /**< Reserved registers */ + RTCC_RET_TypeDef RET[32]; /**< RetentionReg */ +} RTCC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_RTCC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for RTCC CTRL */ +#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */ +#define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */ +#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */ +#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ +#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */ +#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */ +#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */ +#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */ +#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */ +#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */ +#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */ +#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */ +#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */ +#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */ +#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */ +#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */ +#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */ +#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */ +#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */ +#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */ +#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */ +#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */ +#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */ +#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ +#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */ + +/* Bit fields for RTCC PRECNT */ +#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ +#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ +#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ + +/* Bit fields for RTCC CNT */ +#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ +#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ +#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ +#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ + +/* Bit fields for RTCC COMBCNT */ +#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ + +/* Bit fields for RTCC TIME */ +#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */ +#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */ +#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */ +#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */ +#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */ +#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */ +#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */ +#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */ +#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */ +#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */ +#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */ +#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */ +#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */ +#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ +#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */ + +/* Bit fields for RTCC DATE */ +#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */ +#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */ +#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */ +#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */ +#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */ +#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ +#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */ +#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */ +#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */ +#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */ +#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */ +#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */ +#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ +#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */ + +/* Bit fields for RTCC IF */ +#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ +#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */ +#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */ +#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */ +#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */ +#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */ +#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */ +#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */ +#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */ +#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */ +#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */ +#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */ +#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */ + +/* Bit fields for RTCC IFS */ +#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */ +#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */ +#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */ +#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */ +#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */ +#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */ +#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */ +#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */ +#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */ +#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */ +#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */ +#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */ +#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ +#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */ + +/* Bit fields for RTCC IFC */ +#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */ +#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */ +#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */ +#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */ +#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */ +#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */ +#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */ +#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */ +#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */ +#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */ +#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */ +#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */ +#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ +#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */ + +/* Bit fields for RTCC IEN */ +#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ +#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */ +#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */ +#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */ +#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */ +#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */ +#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ +#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */ +#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */ +#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ +#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */ +#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ +#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */ +#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ +#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */ +#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ +#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */ +#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ +#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */ + +/* Bit fields for RTCC STATUS */ +#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ +#define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */ + +/* Bit fields for RTCC CMD */ +#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ +#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */ +#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */ +#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ + +/* Bit fields for RTCC SYNCBUSY */ +#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ +#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */ +#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */ +#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ + +/* Bit fields for RTCC POWERDOWN */ +#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */ +#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */ +#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */ +#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */ +#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */ + +/* Bit fields for RTCC LOCK */ +#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ +#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ + +/* Bit fields for RTCC EM4WUEN */ +#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */ +#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ +#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */ +#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */ +#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */ + +/* Bit fields for RTCC CC_CTRL */ +#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */ +#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */ +#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */ +#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */ +#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */ +#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */ +#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */ + +/* Bit fields for RTCC CC_CCV */ +#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */ +#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */ +#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */ +#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */ +#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */ + +/* Bit fields for RTCC CC_TIME */ +#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */ +#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */ +#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */ +#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */ +#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */ +#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */ +#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */ +#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */ +#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */ +#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ +#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */ +#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ +#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ + +/* Bit fields for RTCC CC_DATE */ +#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */ +#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */ +#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */ +#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ +#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */ +#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ +#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ + +/* Bit fields for RTCC RET_REG */ +#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */ +#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */ +#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */ +#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */ +#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */ +#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */ + +/** @} End of group EFM32PG12B_RTCC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_cc.h new file mode 100644 index 0000000000..b799cad536 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_cc.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efm32pg12b_rtcc_cc.h + * @brief EFM32PG12B_RTCC_CC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief RTCC_CC EFM32PG12B RTCC CC + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< Capture/Compare Value Register */ + __IOM uint32_t TIME; /**< Capture/Compare Time Register */ + __IOM uint32_t DATE; /**< Capture/Compare Date Register */ +} RTCC_CC_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_ret.h new file mode 100644 index 0000000000..025cbd11ad --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_ret.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efm32pg12b_rtcc_ret.h + * @brief EFM32PG12B_RTCC_RET register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief RTCC_RET EFM32PG12B RTCC RET + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t REG; /**< Retention register */ +} RTCC_RET_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_smu.h new file mode 100644 index 0000000000..6340d9e2e0 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_smu.h @@ -0,0 +1,400 @@ +/**************************************************************************//** + * @file efm32pg12b_smu.h + * @brief EFM32PG12B_SMU register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_SMU + * @{ + * @brief EFM32PG12B_SMU Register Declaration + *****************************************************************************/ +typedef struct +{ + uint32_t RESERVED0[3]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + + uint32_t RESERVED1[9]; /**< Reserved for future use **/ + __IOM uint32_t PPUCTRL; /**< PPU Control Register */ + uint32_t RESERVED2[3]; /**< Reserved for future use **/ + __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ + + uint32_t RESERVED3[14]; /**< Reserved for future use **/ + __IM uint32_t PPUFS; /**< PPU Fault Status */ +} SMU_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_SMU_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IFS */ +#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ +#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ +#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ +#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ +#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ + +/* Bit fields for SMU IFC */ +#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ +#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ +#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ +#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ +#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU PPUCTRL */ +#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ +#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ +#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ +#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ +#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0x3BFF7FA7UL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ +#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ +#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0 (0x1UL << 2) /**< Analog to Digital Converter 0 access control bit */ +#define _SMU_PPUPATD0_ADC0_SHIFT 2 /**< Shift value for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_MASK 0x4UL /**< Bit mask for SMU_ADC0 */ +#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 5) /**< Clock Management Unit access control bit */ +#define _SMU_PPUPATD0_CMU_SHIFT 5 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */ +#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */ +#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) /**< Advanced Encryption Standard Accelerator 0 access control bit */ +#define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 /**< Shift value for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL /**< Bit mask for SMU_CRYPTO0 */ +#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator 1 access control bit */ +#define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 /**< Shift value for SMU_CRYPTO1 */ +#define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL /**< Bit mask for SMU_CRYPTO1 */ +#define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */ +#define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */ +#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */ +#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 13) /**< Energy Management Unit access control bit */ +#define _SMU_PPUPATD0_EMU_SHIFT 13 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2000UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH (0x1UL << 14) /**< FPU Exception Handler access control bit */ +#define _SMU_PPUPATD0_FPUEH_SHIFT 14 /**< Shift value for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL /**< Bit mask for SMU_FPUEH */ +#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */ +#define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */ +#define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */ +#define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */ +#define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */ +#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */ +#define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 22) /**< Linked Direct Memory Access Controller access control bit */ +#define _SMU_PPUPATD0_LDMA_SHIFT 22 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x400000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE (0x1UL << 23) /**< Low Energy Sensor Interface access control bit */ +#define _SMU_PPUPATD0_LESENSE_SHIFT 23 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) /**< Low Energy Timer 0 access control bit */ +#define _SMU_PPUPATD0_LETIMER0_SHIFT 24 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0 (0x1UL << 25) /**< Low Energy UART 0 access control bit */ +#define _SMU_PPUPATD0_LEUART0_SHIFT 25 /**< Shift value for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL /**< Bit mask for SMU_LEUART0 */ +#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT0 (0x1UL << 27) /**< Pulse Counter 0 access control bit */ +#define _SMU_PPUPATD0_PCNT0_SHIFT 27 /**< Shift value for SMU_PCNT0 */ +#define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL /**< Bit mask for SMU_PCNT0 */ +#define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT1 (0x1UL << 28) /**< Pulse Counter 1 access control bit */ +#define _SMU_PPUPATD0_PCNT1_SHIFT 28 /**< Shift value for SMU_PCNT1 */ +#define _SMU_PPUPATD0_PCNT1_MASK 0x10000000UL /**< Bit mask for SMU_PCNT1 */ +#define _SMU_PPUPATD0_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT1_DEFAULT (_SMU_PPUPATD0_PCNT1_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT2 (0x1UL << 29) /**< Pulse Counter 2 access control bit */ +#define _SMU_PPUPATD0_PCNT2_SHIFT 29 /**< Shift value for SMU_PCNT2 */ +#define _SMU_PPUPATD0_PCNT2_MASK 0x20000000UL /**< Bit mask for SMU_PCNT2 */ +#define _SMU_PPUPATD0_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PCNT2_DEFAULT (_SMU_PPUPATD0_PCNT2_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x0000FFEEUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU (0x1UL << 1) /**< Reset Management Unit access control bit */ +#define _SMU_PPUPATD1_RMU_SHIFT 1 /**< Shift value for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_MASK 0x2UL /**< Bit mask for SMU_RMU */ +#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 2) /**< Real-Time Counter and Calendar access control bit */ +#define _SMU_PPUPATD1_RTCC_SHIFT 2 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x4UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< Security Management Unit access control bit */ +#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0 (0x1UL << 5) /**< Timer 0 access control bit */ +#define _SMU_PPUPATD1_TIMER0_SHIFT 5 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_MASK 0x20UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1 (0x1UL << 6) /**< Timer 1 access control bit */ +#define _SMU_PPUPATD1_TIMER1_SHIFT 6 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_MASK 0x40UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0 (0x1UL << 7) /**< True Random Number Generator 0 access control bit */ +#define _SMU_PPUPATD1_TRNG0_SHIFT 7 /**< Shift value for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_MASK 0x80UL /**< Bit mask for SMU_TRNG0 */ +#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ +#define _SMU_PPUPATD1_USART0_SHIFT 8 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_MASK 0x100UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ +#define _SMU_PPUPATD1_USART1_SHIFT 9 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_MASK 0x200UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ +#define _SMU_PPUPATD1_USART2_SHIFT 10 /**< Shift value for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_MASK 0x400UL /**< Bit mask for SMU_USART2 */ +#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ +#define _SMU_PPUPATD1_USART3_SHIFT 11 /**< Shift value for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_MASK 0x800UL /**< Bit mask for SMU_USART3 */ +#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 12) /**< Watchdog 0 access control bit */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 12 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x1000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 13) /**< Watchdog 1 access control bit */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 13 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x2000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0 (0x1UL << 14) /**< Wide Timer 0 access control bit */ +#define _SMU_PPUPATD1_WTIMER0_SHIFT 14 /**< Shift value for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_MASK 0x4000UL /**< Bit mask for SMU_WTIMER0 */ +#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1 (0x1UL << 15) /**< Wide Timer 1 access control bit */ +#define _SMU_PPUPATD1_WTIMER1_SHIFT 15 /**< Shift value for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_MASK 0x8000UL /**< Bit mask for SMU_WTIMER1 */ +#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ +#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL /**< Mode ADC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL /**< Mode CMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL /**< Mode CRYOTIMER for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL /**< Mode CRYPTO0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL /**< Mode CRYPTO1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL /**< Mode EMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL /**< Mode FPUEH for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL /**< Mode LDMA for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL /**< Mode LESENSE for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL /**< Mode LETIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL /**< Mode LEUART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL /**< Mode PCNT0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT1 0x0000001CUL /**< Mode PCNT1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_PCNT2 0x0000001DUL /**< Mode PCNT2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RMU 0x00000021UL /**< Mode RMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_RTCC 0x00000022UL /**< Mode RTCC for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_SMU 0x00000023UL /**< Mode SMU for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000025UL /**< Mode TIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TIMER1 0x00000026UL /**< Mode TIMER1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART0 0x00000028UL /**< Mode USART0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART1 0x00000029UL /**< Mode USART1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART2 0x0000002AUL /**< Mode USART2 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_USART3 0x0000002BUL /**< Mode USART3 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002CUL /**< Mode WDOG0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002DUL /**< Mode WDOG1 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002EUL /**< Mode WTIMER0 for SMU_PPUFS */ +#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000002FUL /**< Mode WTIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) /**< Shifted mode CRYPTO1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ +#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ + +/** @} End of group EFM32PG12B_SMU */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer.h new file mode 100644 index 0000000000..5750bf9d40 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer.h @@ -0,0 +1,1575 @@ +/**************************************************************************//** + * @file efm32pg12b_timer.h + * @brief EFM32PG12B_TIMER register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_TIMER + * @{ + * @brief EFM32PG12B_TIMER Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + uint32_t RESERVED1[1]; /**< Reserved for future use **/ + __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ + + uint32_t RESERVED2[8]; /**< Reserved registers */ + TIMER_CC_TypeDef CC[4]; /**< Compare/Capture Channel */ + + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTTIME; /**< DTI Time Control Register */ + __IOM uint32_t DTFC; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_TIMER_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */ +#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */ +#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */ +#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */ +#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */ +#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */ +#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */ +#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */ +#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */ +#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */ +#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */ +#define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ +#define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ +#define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ +#define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ +#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ +#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ +#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ +#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ +#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ +#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ +#define _TIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ +#define _TIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCVBV3_DEFAULT (_TIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ +#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ +#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ +#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ +#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ +#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ +#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ +#define _TIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ +#define _TIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICV3_DEFAULT (_TIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ +#define _TIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ +#define _TIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_DEFAULT (_TIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_LOWRISE (_TIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL3_HIGHFALL (_TIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x00000FF7UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ +#define _TIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC3_DEFAULT (_TIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ +#define _TIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICBOF3_DEFAULT (_TIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IFS */ +#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */ +#define _TIMER_IFS_MASK 0x00000FF7UL /**< Mask for TIMER_IFS */ +#define TIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ +#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ +#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ +#define _TIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_DIRCHG_DEFAULT (_TIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ +#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ +#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ +#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ +#define _TIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_CC3_DEFAULT (_TIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ +#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ +#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ +#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ +#define _TIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */ +#define TIMER_IFS_ICBOF3_DEFAULT (_TIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFS */ + +/* Bit fields for TIMER IFC */ +#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */ +#define _TIMER_IFC_MASK 0x00000FF7UL /**< Mask for TIMER_IFC */ +#define TIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ +#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ +#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ +#define _TIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_DIRCHG_DEFAULT (_TIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ +#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ +#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ +#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ +#define _TIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_CC3_DEFAULT (_TIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ +#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ +#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ +#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ +#define _TIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */ +#define TIMER_IFC_ICBOF3_DEFAULT (_TIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IFC */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x00000FF7UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ +#define _TIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ +#define _TIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ +#define _TIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC3_DEFAULT (_TIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ +#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ +#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ +#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ +#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ +#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ +#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ +#define _TIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ +#define _TIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICBOF3_DEFAULT (_TIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ +#define _TIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_LOCK */ +#define _TIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_DEFAULT (_TIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCK (_TIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_TIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_LOCKED (_TIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_LOCK */ +#define TIMER_LOCK_TIMERLOCKKEY_UNLOCK (_TIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER ROUTEPEN */ +#define _TIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTEPEN */ +#define _TIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ +#define _TIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ +#define _TIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC0PEN_DEFAULT (_TIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ +#define _TIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ +#define _TIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC1PEN_DEFAULT (_TIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ +#define _TIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ +#define _TIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC2PEN_DEFAULT (_TIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ +#define _TIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ +#define _TIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CC3PEN_DEFAULT (_TIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ +#define _TIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ +#define _TIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ +#define _TIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ +#define _TIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTEPEN */ +#define TIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_TIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTEPEN */ + +/* Bit fields for TIMER ROUTELOC0 */ +#define _TIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC0 (_TIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_DEFAULT (_TIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC1 (_TIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC2 (_TIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC3 (_TIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC4 (_TIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC5 (_TIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC6 (_TIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC7 (_TIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC8 (_TIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC9 (_TIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC10 (_TIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC11 (_TIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC12 (_TIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC13 (_TIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC14 (_TIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC15 (_TIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC16 (_TIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC17 (_TIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC18 (_TIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC19 (_TIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC20 (_TIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC21 (_TIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC22 (_TIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC23 (_TIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC24 (_TIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC25 (_TIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC26 (_TIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC27 (_TIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC28 (_TIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC29 (_TIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC30 (_TIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC0LOC_LOC31 (_TIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC0 (_TIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_DEFAULT (_TIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC1 (_TIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC2 (_TIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC3 (_TIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC4 (_TIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC5 (_TIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC6 (_TIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC7 (_TIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC8 (_TIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC9 (_TIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC10 (_TIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC11 (_TIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC12 (_TIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC13 (_TIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC14 (_TIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC15 (_TIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC16 (_TIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC17 (_TIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC18 (_TIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC19 (_TIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC20 (_TIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC21 (_TIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC22 (_TIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC23 (_TIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC24 (_TIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC25 (_TIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC26 (_TIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC27 (_TIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC28 (_TIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC29 (_TIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC30 (_TIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC1LOC_LOC31 (_TIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC0 (_TIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_DEFAULT (_TIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC1 (_TIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC2 (_TIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC3 (_TIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC4 (_TIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC5 (_TIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC6 (_TIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC7 (_TIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC8 (_TIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC9 (_TIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC10 (_TIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC11 (_TIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC12 (_TIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC13 (_TIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC14 (_TIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC15 (_TIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC16 (_TIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC17 (_TIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC18 (_TIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC19 (_TIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC20 (_TIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC21 (_TIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC22 (_TIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC23 (_TIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC24 (_TIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC25 (_TIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC26 (_TIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC27 (_TIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC28 (_TIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC29 (_TIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC30 (_TIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC2LOC_LOC31 (_TIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC0 */ +#define _TIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC0 (_TIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_DEFAULT (_TIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC1 (_TIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC2 (_TIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC3 (_TIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC4 (_TIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC5 (_TIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC6 (_TIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC7 (_TIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC8 (_TIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC9 (_TIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC10 (_TIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC11 (_TIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC12 (_TIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC13 (_TIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC14 (_TIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC15 (_TIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC16 (_TIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC17 (_TIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC18 (_TIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC19 (_TIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC20 (_TIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC21 (_TIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC22 (_TIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC23 (_TIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC24 (_TIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC25 (_TIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC26 (_TIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC27 (_TIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC28 (_TIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC29 (_TIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC30 (_TIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for TIMER_ROUTELOC0 */ +#define TIMER_ROUTELOC0_CC3LOC_LOC31 (_TIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for TIMER_ROUTELOC0 */ + +/* Bit fields for TIMER ROUTELOC2 */ +#define _TIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC0 (_TIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC1 (_TIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC2 (_TIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC3 (_TIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC4 (_TIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC5 (_TIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC6 (_TIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC7 (_TIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC8 (_TIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC9 (_TIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC10 (_TIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC11 (_TIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC12 (_TIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC13 (_TIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC14 (_TIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC15 (_TIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC16 (_TIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC17 (_TIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC18 (_TIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC19 (_TIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC20 (_TIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC21 (_TIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC22 (_TIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC23 (_TIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC24 (_TIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC25 (_TIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC26 (_TIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC27 (_TIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC28 (_TIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC29 (_TIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC30 (_TIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI0LOC_LOC31 (_TIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC0 (_TIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC1 (_TIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC2 (_TIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC3 (_TIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC4 (_TIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC5 (_TIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC6 (_TIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC7 (_TIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC8 (_TIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC9 (_TIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC10 (_TIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC11 (_TIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC12 (_TIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC13 (_TIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC14 (_TIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC15 (_TIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC16 (_TIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC17 (_TIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC18 (_TIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC19 (_TIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC20 (_TIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC21 (_TIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC22 (_TIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC23 (_TIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC24 (_TIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC25 (_TIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC26 (_TIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC27 (_TIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC28 (_TIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC29 (_TIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC30 (_TIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI1LOC_LOC31 (_TIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for TIMER_ROUTELOC2 */ +#define _TIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC0 (_TIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_TIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC1 (_TIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC2 (_TIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC3 (_TIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC4 (_TIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC5 (_TIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC6 (_TIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC7 (_TIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC8 (_TIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC9 (_TIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC10 (_TIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC11 (_TIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC12 (_TIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC13 (_TIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC14 (_TIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC15 (_TIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC16 (_TIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC17 (_TIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC18 (_TIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC19 (_TIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC20 (_TIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC21 (_TIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC22 (_TIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC23 (_TIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC24 (_TIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC25 (_TIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC26 (_TIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC27 (_TIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC28 (_TIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC29 (_TIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC30 (_TIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for TIMER_ROUTELOC2 */ +#define TIMER_ROUTELOC2_CDTI2LOC_LOC31 (_TIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for TIMER_ROUTELOC2 */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ +#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ +#define _TIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_DEFAULT (_TIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_PULSE (_TIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_PRSCONF_LEVEL (_TIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ +#define _TIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ +#define _TIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_CCV */ +#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */ +#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */ +#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */ +#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */ + +/* Bit fields for TIMER CC_CCVP */ +#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */ +#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */ +#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */ +#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */ + +/* Bit fields for TIMER CC_CCVB */ +#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */ +#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */ +#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */ +#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ +#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTAR_DEFAULT (_TIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTFATS_DEFAULT (_TIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ +#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTTIME */ +#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */ +#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */ +#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */ +#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */ +#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */ + +/* Bit fields for TIMER DTFC */ +#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */ +#define _TIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ +#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH8 (_TIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH9 (_TIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH10 (_TIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FSEL_PRSCH11 (_TIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ +#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTFC */ +#define _TIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH8 (_TIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH9 (_TIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH10 (_TIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FSEL_PRSCH11 (_TIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */ +#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */ +#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */ +#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ +#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */ +#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFM32PG12B_TIMER */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer_cc.h new file mode 100644 index 0000000000..aa5c7b26dd --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer_cc.h @@ -0,0 +1,49 @@ +/**************************************************************************//** + * @file efm32pg12b_timer_cc.h + * @brief EFM32PG12B_TIMER_CC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief TIMER_CC EFM32PG12B TIMER CC + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t CCV; /**< CC Channel Value Register */ + __IM uint32_t CCVP; /**< CC Channel Value Peek Register */ + __IOM uint32_t CCVB; /**< CC Channel Buffer Register */ +} TIMER_CC_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_trng.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_trng.h new file mode 100644 index 0000000000..5a60ff8276 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_trng.h @@ -0,0 +1,279 @@ +/**************************************************************************//** + * @file efm32pg12b_trng.h + * @brief EFM32PG12B_TRNG register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_TRNG + * @{ + * @brief EFM32PG12B_TRNG Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CONTROL; /**< Main Control Register */ + __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ + __IOM uint32_t KEY0; /**< Key Register 0 */ + __IOM uint32_t KEY1; /**< Key Register 1 */ + __IOM uint32_t KEY2; /**< Key Register 2 */ + __IOM uint32_t KEY3; /**< Key Register 3 */ + __IOM uint32_t TESTDATA; /**< Test Data Register */ + + uint32_t RESERVED1[3]; /**< Reserved for future use **/ + __IOM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ + uint32_t RESERVED2[50]; /**< Reserved for future use **/ + __IM uint32_t FIFO; /**< FIFO Data */ +} TRNG_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_TRNG_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for TRNG CONTROL */ +#define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */ +#define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ +#define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */ +#define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */ +#define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */ +#define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */ +#define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */ +#define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */ +#define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ +#define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */ +#define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */ +#define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */ +#define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */ +#define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */ +#define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */ +#define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */ +#define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */ +#define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */ +#define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */ +#define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */ +#define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */ +#define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */ +#define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */ +#define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */ +#define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ +#define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */ +#define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */ +#define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ +#define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */ +#define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ +#define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */ +#define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */ + +/* Bit fields for TRNG FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */ +#define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */ +#define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */ + +/* Bit fields for TRNG FIFODEPTH */ +#define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */ +#define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */ +#define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */ + +/* Bit fields for TRNG KEY0 */ +#define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */ +#define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */ +#define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */ +#define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */ + +/* Bit fields for TRNG KEY1 */ +#define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */ +#define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */ +#define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */ +#define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */ + +/* Bit fields for TRNG KEY2 */ +#define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */ +#define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */ +#define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */ +#define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */ + +/* Bit fields for TRNG KEY3 */ +#define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */ +#define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */ +#define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */ +#define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */ + +/* Bit fields for TRNG TESTDATA */ +#define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */ +#define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */ +#define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */ + +/* Bit fields for TRNG STATUS */ +#define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */ +#define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ +#define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */ +#define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */ +#define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */ +#define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */ +#define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */ +#define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */ +#define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */ +#define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */ +#define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */ +#define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */ +#define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */ +#define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */ +#define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */ +#define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ +#define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */ +#define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ +#define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */ + +/* Bit fields for TRNG INITWAITVAL */ +#define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */ +#define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */ +#define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */ + +/* Bit fields for TRNG FIFO */ +#define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */ +#define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */ +#define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ +#define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */ +#define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */ + +/** @} End of group EFM32PG12B_TRNG */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_usart.h new file mode 100644 index 0000000000..1942df3840 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_usart.h @@ -0,0 +1,1972 @@ +/**************************************************************************//** + * @file efm32pg12b_usart.h + * @brief EFM32PG12B_USART register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_USART + * @{ + * @brief EFM32PG12B_USART Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + uint32_t RESERVED0[1]; /**< Reserved for future use **/ + __IOM uint32_t INPUT; /**< USART Input Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */ + __IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */ + __IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */ + __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ + __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ + __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ +} USART_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_USART_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */ +#define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IFS */ +#define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ +#define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */ +#define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ +#define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ +#define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ +#define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ +#define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ +#define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ +#define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ +#define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ +#define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ +#define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ +#define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ +#define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ +#define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ +#define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ +#define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ +#define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ +#define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */ + +/* Bit fields for USART IFC */ +#define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ +#define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */ +#define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ +#define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ +#define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ +#define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ +#define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ +#define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ +#define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ +#define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ +#define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ +#define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ +#define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ +#define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ +#define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ +#define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ +#define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ +#define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ +#define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ +#define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ +#define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */ +#define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */ +#define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */ +#define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */ + +/* Bit fields for USART INPUT */ +#define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ +#define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */ +#define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ +#define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ +#define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */ +#define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ +#define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */ +#define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */ +#define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ +#define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ +#define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ + +/* Bit fields for USART ROUTEPEN */ +#define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */ +#define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ +#define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ +#define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ +#define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ +#define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ +#define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ +#define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ +#define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ +#define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ +#define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ +#define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ +#define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ +#define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ +#define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ + +/* Bit fields for USART ROUTELOC0 */ +#define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */ +#define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */ +#define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */ +#define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */ +#define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ +#define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ +#define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ + +/* Bit fields for USART ROUTELOC1 */ +#define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */ +#define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */ +#define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ +#define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ +#define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ + +/** @} End of group EFM32PG12B_USART */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac.h new file mode 100644 index 0000000000..a75ff39573 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac.h @@ -0,0 +1,1539 @@ +/**************************************************************************//** + * @file efm32pg12b_vdac.h + * @brief EFM32PG12B_VDAC register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_VDAC + * @{ + * @brief EFM32PG12B_VDAC Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */ + __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */ + __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */ + __IOM uint32_t COMBDATA; /**< Combined Data Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + + uint32_t RESERVED0[27]; /**< Reserved registers */ + VDAC_OPA_TypeDef OPA[3]; /**< OPA Registers */ +} VDAC_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_VDAC_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for VDAC CTRL */ +#define _VDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CTRL */ +#define _VDAC_CTRL_MASK 0x937F0771UL /**< Mask for VDAC_CTRL */ +#define VDAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CTRL_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DIFF_DEFAULT (_VDAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE (0x1UL << 4) /**< Sine Mode */ +#define _VDAC_CTRL_SINEMODE_SHIFT 4 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_MASK 0x10UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_SINEMODE_DEFAULT (_VDAC_CTRL_SINEMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS (0x1UL << 5) /**< PRS Controlled Output Enable */ +#define _VDAC_CTRL_OUTENPRS_SHIFT 5 /**< Shift value for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_MASK 0x20UL /**< Bit mask for VDAC_OUTENPRS */ +#define _VDAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_OUTENPRS_DEFAULT (_VDAC_CTRL_OUTENPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST (0x1UL << 6) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CTRL_CH0PRESCRST_SHIFT 6 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_MASK 0x40UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_CH0PRESCRST_DEFAULT (_VDAC_CTRL_CH0PRESCRST_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_MASK 0x700UL /**< Bit mask for VDAC_REFSEL */ +#define _VDAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25LN 0x00000000UL /**< Mode 1V25LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5LN 0x00000001UL /**< Mode 2V5LN for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_1V25 0x00000002UL /**< Mode 1V25 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_2V5 0x00000003UL /**< Mode 2V5 for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_VDD 0x00000004UL /**< Mode VDD for VDAC_CTRL */ +#define _VDAC_CTRL_REFSEL_EXT 0x00000006UL /**< Mode EXT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_DEFAULT (_VDAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25LN (_VDAC_CTRL_REFSEL_1V25LN << 8) /**< Shifted mode 1V25LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5LN (_VDAC_CTRL_REFSEL_2V5LN << 8) /**< Shifted mode 2V5LN for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_1V25 (_VDAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_2V5 (_VDAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_VDD (_VDAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for VDAC_CTRL */ +#define VDAC_CTRL_REFSEL_EXT (_VDAC_CTRL_REFSEL_EXT << 8) /**< Shifted mode EXT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_SHIFT 16 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_MASK 0x7F0000UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_DEFAULT (_VDAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_PRESC_NODIVISION (_VDAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_SHIFT 24 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_MASK 0x3000000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CTRL_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_8CYCLES 0x00000000UL /**< Mode 8CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_16CYCLES 0x00000001UL /**< Mode 16CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_32CYCLES 0x00000002UL /**< Mode 32CYCLES for VDAC_CTRL */ +#define _VDAC_CTRL_REFRESHPERIOD_64CYCLES 0x00000003UL /**< Mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_DEFAULT (_VDAC_CTRL_REFRESHPERIOD_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_8CYCLES (_VDAC_CTRL_REFRESHPERIOD_8CYCLES << 24) /**< Shifted mode 8CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_16CYCLES (_VDAC_CTRL_REFRESHPERIOD_16CYCLES << 24) /**< Shifted mode 16CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_32CYCLES (_VDAC_CTRL_REFRESHPERIOD_32CYCLES << 24) /**< Shifted mode 32CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_REFRESHPERIOD_64CYCLES (_VDAC_CTRL_REFRESHPERIOD_64CYCLES << 24) /**< Shifted mode 64CYCLES for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE (0x1UL << 28) /**< Warm-up Mode */ +#define _VDAC_CTRL_WARMUPMODE_SHIFT 28 /**< Shift value for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_MASK 0x10000000UL /**< Bit mask for VDAC_WARMUPMODE */ +#define _VDAC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CTRL */ +#define _VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_DEFAULT (_VDAC_CTRL_WARMUPMODE_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_NORMAL (_VDAC_CTRL_WARMUPMODE_NORMAL << 28) /**< Shifted mode NORMAL for VDAC_CTRL */ +#define VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY (_VDAC_CTRL_WARMUPMODE_KEEPINSTANDBY << 28) /**< Shifted mode KEEPINSTANDBY for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE (0x1UL << 31) /**< Clock Mode */ +#define _VDAC_CTRL_DACCLKMODE_SHIFT 31 /**< Shift value for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_MASK 0x80000000UL /**< Bit mask for VDAC_DACCLKMODE */ +#define _VDAC_CTRL_DACCLKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_SYNC 0x00000000UL /**< Mode SYNC for VDAC_CTRL */ +#define _VDAC_CTRL_DACCLKMODE_ASYNC 0x00000001UL /**< Mode ASYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_DEFAULT (_VDAC_CTRL_DACCLKMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_SYNC (_VDAC_CTRL_DACCLKMODE_SYNC << 31) /**< Shifted mode SYNC for VDAC_CTRL */ +#define VDAC_CTRL_DACCLKMODE_ASYNC (_VDAC_CTRL_DACCLKMODE_ASYNC << 31) /**< Shifted mode ASYNC for VDAC_CTRL */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x0000000CUL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0x7777003FUL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL (0x1UL << 2) /**< Channel 0 Buffer Level */ +#define _VDAC_STATUS_CH0BL_SHIFT 2 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_MASK 0x4UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_STATUS_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0BL_DEFAULT (_VDAC_STATUS_CH0BL_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL (0x1UL << 3) /**< Channel 1 Buffer Level */ +#define _VDAC_STATUS_CH1BL_SHIFT 3 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_MASK 0x8UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_STATUS_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1BL_DEFAULT (_VDAC_STATUS_CH1BL_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warm */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warm */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT (_VDAC_STATUS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS (0x1UL << 20) /**< OPA0 Enabled Status */ +#define _VDAC_STATUS_OPA0ENS_SHIFT 20 /**< Shift value for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_MASK 0x100000UL /**< Bit mask for VDAC_OPA0ENS */ +#define _VDAC_STATUS_OPA0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0ENS_DEFAULT (_VDAC_STATUS_OPA0ENS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS (0x1UL << 21) /**< OPA1 Enabled Status */ +#define _VDAC_STATUS_OPA1ENS_SHIFT 21 /**< Shift value for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_MASK 0x200000UL /**< Bit mask for VDAC_OPA1ENS */ +#define _VDAC_STATUS_OPA1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1ENS_DEFAULT (_VDAC_STATUS_OPA1ENS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS (0x1UL << 22) /**< OPA2 Enabled Status */ +#define _VDAC_STATUS_OPA2ENS_SHIFT 22 /**< Shift value for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_MASK 0x400000UL /**< Bit mask for VDAC_OPA2ENS */ +#define _VDAC_STATUS_OPA2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2ENS_DEFAULT (_VDAC_STATUS_OPA2ENS_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM (0x1UL << 24) /**< OPA0 Warm Status */ +#define _VDAC_STATUS_OPA0WARM_SHIFT 24 /**< Shift value for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_MASK 0x1000000UL /**< Bit mask for VDAC_OPA0WARM */ +#define _VDAC_STATUS_OPA0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0WARM_DEFAULT (_VDAC_STATUS_OPA0WARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM (0x1UL << 25) /**< OPA1 Warm Status */ +#define _VDAC_STATUS_OPA1WARM_SHIFT 25 /**< Shift value for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_MASK 0x2000000UL /**< Bit mask for VDAC_OPA1WARM */ +#define _VDAC_STATUS_OPA1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1WARM_DEFAULT (_VDAC_STATUS_OPA1WARM_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM (0x1UL << 26) /**< OPA2 Warm Status */ +#define _VDAC_STATUS_OPA2WARM_SHIFT 26 /**< Shift value for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_MASK 0x4000000UL /**< Bit mask for VDAC_OPA2WARM */ +#define _VDAC_STATUS_OPA2WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2WARM_DEFAULT (_VDAC_STATUS_OPA2WARM_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Status */ +#define _VDAC_STATUS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_STATUS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA0OUTVALID_DEFAULT (_VDAC_STATUS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Status */ +#define _VDAC_STATUS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_STATUS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA1OUTVALID_DEFAULT (_VDAC_STATUS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID (0x1UL << 30) /**< OPA2 Output Valid Status */ +#define _VDAC_STATUS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_STATUS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_OPA2OUTVALID_DEFAULT (_VDAC_STATUS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CTRL */ +#define _VDAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH0CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_DEFAULT (_VDAC_CH0CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_CONTINUOUS (_VDAC_CH0CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH0CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_DEFAULT (_VDAC_CH0CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SW (_VDAC_CH0CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_PRS (_VDAC_CH0CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_REFRESH (_VDAC_CH0CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWPRS (_VDAC_CH0CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_SWREFRESH (_VDAC_CH0CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_TRIGMODE_LESENSE (_VDAC_CH0CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC (0x1UL << 8) /**< Channel 0 PRS Asynchronous Enable */ +#define _VDAC_CH0CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH0CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSASYNC_DEFAULT (_VDAC_CH0CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH0CTRL */ +#define _VDAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_DEFAULT (_VDAC_CH0CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH0 (_VDAC_CH0CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH1 (_VDAC_CH0CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH2 (_VDAC_CH0CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH3 (_VDAC_CH0CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH4 (_VDAC_CH0CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH5 (_VDAC_CH0CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH6 (_VDAC_CH0CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH7 (_VDAC_CH0CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH8 (_VDAC_CH0CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH9 (_VDAC_CH0CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH10 (_VDAC_CH0CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH0CTRL */ +#define VDAC_CH0CTRL_PRSSEL_PRSCH11 (_VDAC_CH0CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH0CTRL */ + +/* Bit fields for VDAC CH1CTRL */ +#define _VDAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_MASK 0x0000F171UL /**< Mask for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE (0x1UL << 0) /**< Conversion Mode */ +#define _VDAC_CH1CTRL_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_DEFAULT (_VDAC_CH1CTRL_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_CONTINUOUS (_VDAC_CH1CTRL_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_CONVMODE_SAMPLEOFF (_VDAC_CH1CTRL_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CTRL_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SW 0x00000000UL /**< Mode SW for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_PRS 0x00000001UL /**< Mode PRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_REFRESH 0x00000002UL /**< Mode REFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWPRS 0x00000003UL /**< Mode SWPRS for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_SWREFRESH 0x00000004UL /**< Mode SWREFRESH for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_TRIGMODE_LESENSE 0x00000005UL /**< Mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_DEFAULT (_VDAC_CH1CTRL_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SW (_VDAC_CH1CTRL_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_PRS (_VDAC_CH1CTRL_TRIGMODE_PRS << 4) /**< Shifted mode PRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_REFRESH (_VDAC_CH1CTRL_TRIGMODE_REFRESH << 4) /**< Shifted mode REFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWPRS (_VDAC_CH1CTRL_TRIGMODE_SWPRS << 4) /**< Shifted mode SWPRS for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_SWREFRESH (_VDAC_CH1CTRL_TRIGMODE_SWREFRESH << 4) /**< Shifted mode SWREFRESH for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_TRIGMODE_LESENSE (_VDAC_CH1CTRL_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC (0x1UL << 8) /**< Channel 1 PRS Asynchronous Enable */ +#define _VDAC_CH1CTRL_PRSASYNC_SHIFT 8 /**< Shift value for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_MASK 0x100UL /**< Bit mask for VDAC_PRSASYNC */ +#define _VDAC_CH1CTRL_PRSASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSASYNC_DEFAULT (_VDAC_CH1CTRL_PRSASYNC_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_SHIFT 12 /**< Shift value for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_MASK 0xF000UL /**< Bit mask for VDAC_PRSSEL */ +#define _VDAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_CH1CTRL */ +#define _VDAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_DEFAULT (_VDAC_CH1CTRL_PRSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH0 (_VDAC_CH1CTRL_PRSSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH1 (_VDAC_CH1CTRL_PRSSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH2 (_VDAC_CH1CTRL_PRSSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH3 (_VDAC_CH1CTRL_PRSSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH4 (_VDAC_CH1CTRL_PRSSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH5 (_VDAC_CH1CTRL_PRSSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH6 (_VDAC_CH1CTRL_PRSSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH7 (_VDAC_CH1CTRL_PRSSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH8 (_VDAC_CH1CTRL_PRSSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH9 (_VDAC_CH1CTRL_PRSSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH10 (_VDAC_CH1CTRL_PRSSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for VDAC_CH1CTRL */ +#define VDAC_CH1CTRL_PRSSEL_PRSCH11 (_VDAC_CH1CTRL_PRSSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for VDAC_CH1CTRL */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x003F000FUL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 2) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 2 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x4UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 3) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 3 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x8UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN (0x1UL << 16) /**< OPA0 Enable */ +#define _VDAC_CMD_OPA0EN_SHIFT 16 /**< Shift value for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_MASK 0x10000UL /**< Bit mask for VDAC_OPA0EN */ +#define _VDAC_CMD_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0EN_DEFAULT (_VDAC_CMD_OPA0EN_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS (0x1UL << 17) /**< OPA0 Disable */ +#define _VDAC_CMD_OPA0DIS_SHIFT 17 /**< Shift value for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_MASK 0x20000UL /**< Bit mask for VDAC_OPA0DIS */ +#define _VDAC_CMD_OPA0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA0DIS_DEFAULT (_VDAC_CMD_OPA0DIS_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN (0x1UL << 18) /**< OPA1 Enable */ +#define _VDAC_CMD_OPA1EN_SHIFT 18 /**< Shift value for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_MASK 0x40000UL /**< Bit mask for VDAC_OPA1EN */ +#define _VDAC_CMD_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1EN_DEFAULT (_VDAC_CMD_OPA1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS (0x1UL << 19) /**< OPA1 Disable */ +#define _VDAC_CMD_OPA1DIS_SHIFT 19 /**< Shift value for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_MASK 0x80000UL /**< Bit mask for VDAC_OPA1DIS */ +#define _VDAC_CMD_OPA1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA1DIS_DEFAULT (_VDAC_CMD_OPA1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN (0x1UL << 20) /**< OPA2 Enable */ +#define _VDAC_CMD_OPA2EN_SHIFT 20 /**< Shift value for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_MASK 0x100000UL /**< Bit mask for VDAC_OPA2EN */ +#define _VDAC_CMD_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2EN_DEFAULT (_VDAC_CMD_OPA2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS (0x1UL << 21) /**< OPA2 Disable */ +#define _VDAC_CMD_OPA2DIS_SHIFT 21 /**< Shift value for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_MASK 0x200000UL /**< Bit mask for VDAC_OPA2DIS */ +#define _VDAC_CMD_OPA2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_OPA2DIS_DEFAULT (_VDAC_CMD_OPA2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x000000C0UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x707780FFUL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< Channel 0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< Channel 1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 2) /**< Channel 0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 3) /**< Channel 1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL (0x1UL << 6) /**< Channel 0 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IF_CH0BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0BL_DEFAULT (_VDAC_IF_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL (0x1UL << 7) /**< Channel 1 Buffer Level Interrupt Flag */ +#define _VDAC_IF_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IF_CH1BL_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1BL_DEFAULT (_VDAC_IF_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR (0x1UL << 15) /**< EM2/3 Entry Error Flag */ +#define _VDAC_IF_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IF_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_EM23ERR_DEFAULT (_VDAC_IF_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IF_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0APORTCONFLICT_DEFAULT (_VDAC_IF_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IF_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1APORTCONFLICT_DEFAULT (_VDAC_IF_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2 Bus Conflict Output Interrupt Flag */ +#define _VDAC_IF_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IF_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2APORTCONFLICT_DEFAULT (_VDAC_IF_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IF_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IF_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2 PRS Trigger Mode Error Interrupt Flag */ +#define _VDAC_IF_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IF_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IF_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID (0x1UL << 28) /**< OPA0 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IF_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA0OUTVALID_DEFAULT (_VDAC_IF_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID (0x1UL << 29) /**< OPA1 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IF_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA1OUTVALID_DEFAULT (_VDAC_IF_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID (0x1UL << 30) /**< OPA3 Output Valid Interrupt Flag */ +#define _VDAC_IF_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IF_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_OPA2OUTVALID_DEFAULT (_VDAC_IF_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IFS */ +#define _VDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFS */ +#define _VDAC_IFS_MASK 0x7077803FUL /**< Mask for VDAC_IFS */ +#define VDAC_IFS_CH0CD (0x1UL << 0) /**< Set CH0CD Interrupt Flag */ +#define _VDAC_IFS_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFS_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0CD_DEFAULT (_VDAC_IFS_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD (0x1UL << 1) /**< Set CH1CD Interrupt Flag */ +#define _VDAC_IFS_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFS_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1CD_DEFAULT (_VDAC_IFS_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF (0x1UL << 2) /**< Set CH0OF Interrupt Flag */ +#define _VDAC_IFS_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFS_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0OF_DEFAULT (_VDAC_IFS_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF (0x1UL << 3) /**< Set CH1OF Interrupt Flag */ +#define _VDAC_IFS_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFS_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1OF_DEFAULT (_VDAC_IFS_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF (0x1UL << 4) /**< Set CH0UF Interrupt Flag */ +#define _VDAC_IFS_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH0UF_DEFAULT (_VDAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF (0x1UL << 5) /**< Set CH1UF Interrupt Flag */ +#define _VDAC_IFS_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_CH1UF_DEFAULT (_VDAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR (0x1UL << 15) /**< Set EM23ERR Interrupt Flag */ +#define _VDAC_IFS_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFS_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_EM23ERR_DEFAULT (_VDAC_IFS_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT (0x1UL << 16) /**< Set OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFS_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT (0x1UL << 17) /**< Set OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFS_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT (0x1UL << 18) /**< Set OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFS_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFS_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFS_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR (0x1UL << 20) /**< Set OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR (0x1UL << 21) /**< Set OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR (0x1UL << 22) /**< Set OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFS_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID (0x1UL << 28) /**< Set OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFS_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA0OUTVALID_DEFAULT (_VDAC_IFS_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID (0x1UL << 29) /**< Set OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFS_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA1OUTVALID_DEFAULT (_VDAC_IFS_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID (0x1UL << 30) /**< Set OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFS_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFS_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFS */ +#define VDAC_IFS_OPA2OUTVALID_DEFAULT (_VDAC_IFS_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFS */ + +/* Bit fields for VDAC IFC */ +#define _VDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for VDAC_IFC */ +#define _VDAC_IFC_MASK 0x7077803FUL /**< Mask for VDAC_IFC */ +#define VDAC_IFC_CH0CD (0x1UL << 0) /**< Clear CH0CD Interrupt Flag */ +#define _VDAC_IFC_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IFC_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0CD_DEFAULT (_VDAC_IFC_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD (0x1UL << 1) /**< Clear CH1CD Interrupt Flag */ +#define _VDAC_IFC_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IFC_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1CD_DEFAULT (_VDAC_IFC_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF (0x1UL << 2) /**< Clear CH0OF Interrupt Flag */ +#define _VDAC_IFC_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IFC_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0OF_DEFAULT (_VDAC_IFC_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF (0x1UL << 3) /**< Clear CH1OF Interrupt Flag */ +#define _VDAC_IFC_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IFC_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1OF_DEFAULT (_VDAC_IFC_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF (0x1UL << 4) /**< Clear CH0UF Interrupt Flag */ +#define _VDAC_IFC_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH0UF_DEFAULT (_VDAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF (0x1UL << 5) /**< Clear CH1UF Interrupt Flag */ +#define _VDAC_IFC_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_CH1UF_DEFAULT (_VDAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR (0x1UL << 15) /**< Clear EM23ERR Interrupt Flag */ +#define _VDAC_IFC_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IFC_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_EM23ERR_DEFAULT (_VDAC_IFC_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT (0x1UL << 16) /**< Clear OPA0APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IFC_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT (0x1UL << 17) /**< Clear OPA1APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IFC_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT (0x1UL << 18) /**< Clear OPA2APORTCONFLICT Interrupt Flag */ +#define _VDAC_IFC_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IFC_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2APORTCONFLICT_DEFAULT (_VDAC_IFC_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR (0x1UL << 20) /**< Clear OPA0PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR (0x1UL << 21) /**< Clear OPA1PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR (0x1UL << 22) /**< Clear OPA2PRSTIMEDERR Interrupt Flag */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IFC_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID (0x1UL << 28) /**< Clear OPA0OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IFC_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA0OUTVALID_DEFAULT (_VDAC_IFC_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID (0x1UL << 29) /**< Clear OPA1OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IFC_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA1OUTVALID_DEFAULT (_VDAC_IFC_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID (0x1UL << 30) /**< Clear OPA2OUTVALID Interrupt Flag */ +#define _VDAC_IFC_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IFC_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IFC */ +#define VDAC_IFC_OPA2OUTVALID_DEFAULT (_VDAC_IFC_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IFC */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x707780FFUL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0CD Interrupt Enable */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1CD Interrupt Enable */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 2) /**< CH0OF Interrupt Enable */ +#define _VDAC_IEN_CH0OF_SHIFT 2 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x4UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 3) /**< CH1OF Interrupt Enable */ +#define _VDAC_IEN_CH1OF_SHIFT 3 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x8UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 4) /**< CH0UF Interrupt Enable */ +#define _VDAC_IEN_CH0UF_SHIFT 4 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 5) /**< CH1UF Interrupt Enable */ +#define _VDAC_IEN_CH1UF_SHIFT 5 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL (0x1UL << 6) /**< CH0BL Interrupt Enable */ +#define _VDAC_IEN_CH0BL_SHIFT 6 /**< Shift value for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_MASK 0x40UL /**< Bit mask for VDAC_CH0BL */ +#define _VDAC_IEN_CH0BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0BL_DEFAULT (_VDAC_IEN_CH0BL_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL (0x1UL << 7) /**< CH1BL Interrupt Enable */ +#define _VDAC_IEN_CH1BL_SHIFT 7 /**< Shift value for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_MASK 0x80UL /**< Bit mask for VDAC_CH1BL */ +#define _VDAC_IEN_CH1BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1BL_DEFAULT (_VDAC_IEN_CH1BL_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR (0x1UL << 15) /**< EM23ERR Interrupt Enable */ +#define _VDAC_IEN_EM23ERR_SHIFT 15 /**< Shift value for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_MASK 0x8000UL /**< Bit mask for VDAC_EM23ERR */ +#define _VDAC_IEN_EM23ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_EM23ERR_DEFAULT (_VDAC_IEN_EM23ERR_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT (0x1UL << 16) /**< OPA0APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA0APORTCONFLICT_SHIFT 16 /**< Shift value for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_MASK 0x10000UL /**< Bit mask for VDAC_OPA0APORTCONFLICT */ +#define _VDAC_IEN_OPA0APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA0APORTCONFLICT_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT (0x1UL << 17) /**< OPA1APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA1APORTCONFLICT_SHIFT 17 /**< Shift value for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_MASK 0x20000UL /**< Bit mask for VDAC_OPA1APORTCONFLICT */ +#define _VDAC_IEN_OPA1APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA1APORTCONFLICT_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT (0x1UL << 18) /**< OPA2APORTCONFLICT Interrupt Enable */ +#define _VDAC_IEN_OPA2APORTCONFLICT_SHIFT 18 /**< Shift value for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_MASK 0x40000UL /**< Bit mask for VDAC_OPA2APORTCONFLICT */ +#define _VDAC_IEN_OPA2APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2APORTCONFLICT_DEFAULT (_VDAC_IEN_OPA2APORTCONFLICT_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR (0x1UL << 20) /**< OPA0PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_SHIFT 20 /**< Shift value for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_MASK 0x100000UL /**< Bit mask for VDAC_OPA0PRSTIMEDERR */ +#define _VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA0PRSTIMEDERR_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR (0x1UL << 21) /**< OPA1PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_SHIFT 21 /**< Shift value for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_MASK 0x200000UL /**< Bit mask for VDAC_OPA1PRSTIMEDERR */ +#define _VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA1PRSTIMEDERR_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR (0x1UL << 22) /**< OPA2PRSTIMEDERR Interrupt Enable */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_SHIFT 22 /**< Shift value for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_MASK 0x400000UL /**< Bit mask for VDAC_OPA2PRSTIMEDERR */ +#define _VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT (_VDAC_IEN_OPA2PRSTIMEDERR_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID (0x1UL << 28) /**< OPA0OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA0OUTVALID_SHIFT 28 /**< Shift value for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_MASK 0x10000000UL /**< Bit mask for VDAC_OPA0OUTVALID */ +#define _VDAC_IEN_OPA0OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA0OUTVALID_DEFAULT (_VDAC_IEN_OPA0OUTVALID_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID (0x1UL << 29) /**< OPA1OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA1OUTVALID_SHIFT 29 /**< Shift value for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_MASK 0x20000000UL /**< Bit mask for VDAC_OPA1OUTVALID */ +#define _VDAC_IEN_OPA1OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA1OUTVALID_DEFAULT (_VDAC_IEN_OPA1OUTVALID_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID (0x1UL << 30) /**< OPA2OUTVALID Interrupt Enable */ +#define _VDAC_IEN_OPA2OUTVALID_SHIFT 30 /**< Shift value for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_MASK 0x40000000UL /**< Bit mask for VDAC_OPA2OUTVALID */ +#define _VDAC_IEN_OPA2OUTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_OPA2OUTVALID_DEFAULT (_VDAC_IEN_OPA2OUTVALID_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0DATA */ +#define _VDAC_CH0DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH0DATA */ +#define _VDAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH0DATA */ +#define VDAC_CH0DATA_DATA_DEFAULT (_VDAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0DATA */ + +/* Bit fields for VDAC CH1DATA */ +#define _VDAC_CH1DATA_RESETVALUE 0x00000800UL /**< Default value for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for VDAC_CH1DATA */ +#define _VDAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1DATA_DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_CH1DATA */ +#define VDAC_CH1DATA_DATA_DEFAULT (_VDAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1DATA */ + +/* Bit fields for VDAC COMBDATA */ +#define _VDAC_COMBDATA_RESETVALUE 0x08000800UL /**< Default value for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for VDAC_CH0DATA */ +#define _VDAC_COMBDATA_CH0DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH0DATA_DEFAULT (_VDAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ +#define _VDAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for VDAC_CH1DATA */ +#define _VDAC_COMBDATA_CH1DATA_DEFAULT 0x00000800UL /**< Mode DEFAULT for VDAC_COMBDATA */ +#define VDAC_COMBDATA_CH1DATA_DEFAULT (_VDAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_COMBDATA */ + +/* Bit fields for VDAC CAL */ +#define _VDAC_CAL_RESETVALUE 0x00082004UL /**< Default value for VDAC_CAL */ +#define _VDAC_CAL_MASK 0x000F3F07UL /**< Mask for VDAC_CAL */ +#define _VDAC_CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for VDAC_OFFSETTRIM */ +#define _VDAC_CAL_OFFSETTRIM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_OFFSETTRIM_DEFAULT (_VDAC_CAL_OFFSETTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIM_SHIFT 8 /**< Shift value for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_MASK 0x3F00UL /**< Bit mask for VDAC_GAINERRTRIM */ +#define _VDAC_CAL_GAINERRTRIM_DEFAULT 0x00000020UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIM_DEFAULT (_VDAC_CAL_GAINERRTRIM_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CAL */ +#define _VDAC_CAL_GAINERRTRIMCH1_SHIFT 16 /**< Shift value for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_MASK 0xF0000UL /**< Bit mask for VDAC_GAINERRTRIMCH1 */ +#define _VDAC_CAL_GAINERRTRIMCH1_DEFAULT 0x00000008UL /**< Mode DEFAULT for VDAC_CAL */ +#define VDAC_CAL_GAINERRTRIMCH1_DEFAULT (_VDAC_CAL_GAINERRTRIMCH1_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CAL */ + +/* Bit fields for VDAC OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTREQ */ +#define _VDAC_OPA_APORTREQ_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the bus connected to APORT2X is requested */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XREQ */ +#define _VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1X is requested */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YREQ */ +#define _VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ (0x1UL << 4) /**< 1 if the bus connected to APORT2X is requested */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XREQ */ +#define _VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2XREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YREQ */ +#define _VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT2YREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ (0x1UL << 6) /**< 1 if the bus connected to APORT3X is requested */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XREQ */ +#define _VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3XREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YREQ */ +#define _VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT3YREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ (0x1UL << 8) /**< 1 if the bus connected to APORT4X is requested */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XREQ */ +#define _VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4XREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is requested */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YREQ */ +#define _VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTREQ */ +#define VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT (_VDAC_OPA_APORTREQ_APORT4YREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTREQ */ + +/* Bit fields for VDAC OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for VDAC_OPA_APORTCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_MASK 0x000003FCUL /**< Mask for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORT1XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for VDAC_OPAAPORT1YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT (0x1UL << 4) /**< 1 if the bus connected to APORT2X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_SHIFT 4 /**< Shift value for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_MASK 0x10UL /**< Bit mask for VDAC_OPAAPORT2XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2XCONFLICT_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT (0x1UL << 5) /**< 1 if the bus connected to APORT2Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_SHIFT 5 /**< Shift value for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_MASK 0x20UL /**< Bit mask for VDAC_OPAAPORT2YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT2YCONFLICT_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT (0x1UL << 6) /**< 1 if the bus connected to APORT3X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_SHIFT 6 /**< Shift value for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_MASK 0x40UL /**< Bit mask for VDAC_OPAAPORT3XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3XCONFLICT_DEFAULT << 6) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT (0x1UL << 7) /**< 1 if the bus connected to APORT3Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_SHIFT 7 /**< Shift value for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_MASK 0x80UL /**< Bit mask for VDAC_OPAAPORT3YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT3YCONFLICT_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT (0x1UL << 8) /**< 1 if the bus connected to APORT4X is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_SHIFT 8 /**< Shift value for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_MASK 0x100UL /**< Bit mask for VDAC_OPAAPORT4XCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4XCONFLICT_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT (0x1UL << 9) /**< 1 if the bus connected to APORT4Y is in conflict with another peripheral */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_SHIFT 9 /**< Shift value for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_MASK 0x200UL /**< Bit mask for VDAC_OPAAPORT4YCONFLICT */ +#define _VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_APORTCONFLICT */ +#define VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT (_VDAC_OPA_APORTCONFLICT_APORT4YCONFLICT_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_APORTCONFLICT */ + +/* Bit fields for VDAC OPA_CTRL */ +#define _VDAC_OPA_CTRL_RESETVALUE 0x0000000EUL /**< Default value for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_MASK 0x00313F1FUL /**< Mask for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT 0 /**< Shift value for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_MASK 0x3UL /**< Bit mask for VDAC_OPADRIVESTRENGTH */ +#define _VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT (_VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW (0x1UL << 2) /**< OPAx unity gain bandwidth scale. */ +#define _VDAC_OPA_CTRL_INCBW_SHIFT 2 /**< Shift value for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_MASK 0x4UL /**< Bit mask for VDAC_OPAINCBW */ +#define _VDAC_OPA_CTRL_INCBW_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_INCBW_DEFAULT (_VDAC_OPA_CTRL_INCBW_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS (0x1UL << 3) /**< High Common Mode Disable. */ +#define _VDAC_OPA_CTRL_HCMDIS_SHIFT 3 /**< Shift value for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_MASK 0x8UL /**< Bit mask for VDAC_OPAHCMDIS */ +#define _VDAC_OPA_CTRL_HCMDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_HCMDIS_DEFAULT (_VDAC_OPA_CTRL_HCMDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE (0x1UL << 4) /**< Scale OPAx output driving strength. */ +#define _VDAC_OPA_CTRL_OUTSCALE_SHIFT 4 /**< Shift value for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_MASK 0x10UL /**< Bit mask for VDAC_OPAOUTSCALE */ +#define _VDAC_OPA_CTRL_OUTSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_FULL 0x00000000UL /**< Mode FULL for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_OUTSCALE_HALF 0x00000001UL /**< Mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_DEFAULT (_VDAC_OPA_CTRL_OUTSCALE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_FULL (_VDAC_OPA_CTRL_OUTSCALE_FULL << 4) /**< Shifted mode FULL for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_OUTSCALE_HALF (_VDAC_OPA_CTRL_OUTSCALE_HALF << 4) /**< Shifted mode HALF for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN (0x1UL << 8) /**< OPAx PRS Trigger Enable */ +#define _VDAC_OPA_CTRL_PRSEN_SHIFT 8 /**< Shift value for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_MASK 0x100UL /**< Bit mask for VDAC_OPAPRSEN */ +#define _VDAC_OPA_CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSEN_DEFAULT (_VDAC_OPA_CTRL_PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE (0x1UL << 9) /**< OPAx PRS Trigger Mode */ +#define _VDAC_OPA_CTRL_PRSMODE_SHIFT 9 /**< Shift value for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_MASK 0x200UL /**< Bit mask for VDAC_OPAPRSMODE */ +#define _VDAC_OPA_CTRL_PRSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_PULSED 0x00000000UL /**< Mode PULSED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSMODE_TIMED 0x00000001UL /**< Mode TIMED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_DEFAULT (_VDAC_OPA_CTRL_PRSMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_PULSED (_VDAC_OPA_CTRL_PRSMODE_PULSED << 9) /**< Shifted mode PULSED for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSMODE_TIMED (_VDAC_OPA_CTRL_PRSMODE_TIMED << 9) /**< Shifted mode TIMED for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_SHIFT 10 /**< Shift value for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_MASK 0x3C00UL /**< Bit mask for VDAC_OPAPRSSEL */ +#define _VDAC_OPA_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_DEFAULT (_VDAC_OPA_CTRL_PRSSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH0 (_VDAC_OPA_CTRL_PRSSEL_PRSCH0 << 10) /**< Shifted mode PRSCH0 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH1 (_VDAC_OPA_CTRL_PRSSEL_PRSCH1 << 10) /**< Shifted mode PRSCH1 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH2 (_VDAC_OPA_CTRL_PRSSEL_PRSCH2 << 10) /**< Shifted mode PRSCH2 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH3 (_VDAC_OPA_CTRL_PRSSEL_PRSCH3 << 10) /**< Shifted mode PRSCH3 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH4 (_VDAC_OPA_CTRL_PRSSEL_PRSCH4 << 10) /**< Shifted mode PRSCH4 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH5 (_VDAC_OPA_CTRL_PRSSEL_PRSCH5 << 10) /**< Shifted mode PRSCH5 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH6 (_VDAC_OPA_CTRL_PRSSEL_PRSCH6 << 10) /**< Shifted mode PRSCH6 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH7 (_VDAC_OPA_CTRL_PRSSEL_PRSCH7 << 10) /**< Shifted mode PRSCH7 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH8 (_VDAC_OPA_CTRL_PRSSEL_PRSCH8 << 10) /**< Shifted mode PRSCH8 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH9 (_VDAC_OPA_CTRL_PRSSEL_PRSCH9 << 10) /**< Shifted mode PRSCH9 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH10 (_VDAC_OPA_CTRL_PRSSEL_PRSCH10 << 10) /**< Shifted mode PRSCH10 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSSEL_PRSCH11 (_VDAC_OPA_CTRL_PRSSEL_PRSCH11 << 10) /**< Shifted mode PRSCH11 for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE (0x1UL << 16) /**< OPAx PRS Output Select. */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_SHIFT 16 /**< Shift value for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_MASK 0x10000UL /**< Bit mask for VDAC_OPAPRSOUTMODE */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_WARM 0x00000000UL /**< Mode WARM for VDAC_OPA_CTRL */ +#define _VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID 0x00000001UL /**< Mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT (_VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_WARM (_VDAC_OPA_CTRL_PRSOUTMODE_WARM << 16) /**< Shifted mode WARM for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID (_VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID << 16) /**< Shifted mode OUTVALID for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS (0x1UL << 20) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_SHIFT 20 /**< Shift value for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_MASK 0x100000UL /**< Bit mask for VDAC_OPAAPORTXMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTXMASTERDIS_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS (0x1UL << 21) /**< APORT Bus Master Disable */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_SHIFT 21 /**< Shift value for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_MASK 0x200000UL /**< Bit mask for VDAC_OPAAPORTYMASTERDIS */ +#define _VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CTRL */ +#define VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT (_VDAC_OPA_CTRL_APORTYMASTERDIS_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_OPA_CTRL */ + +/* Bit fields for VDAC OPA_TIMER */ +#define _VDAC_OPA_TIMER_RESETVALUE 0x00010700UL /**< Default value for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_MASK 0x03FF7F3FUL /**< Mask for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_STARTUPDLY_SHIFT 0 /**< Shift value for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_MASK 0x3FUL /**< Bit mask for VDAC_OPASTARTUPDLY */ +#define _VDAC_OPA_TIMER_STARTUPDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_STARTUPDLY_DEFAULT (_VDAC_OPA_TIMER_STARTUPDLY_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_WARMUPTIME_SHIFT 8 /**< Shift value for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_MASK 0x7F00UL /**< Bit mask for VDAC_OPAWARMUPTIME */ +#define _VDAC_OPA_TIMER_WARMUPTIME_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_WARMUPTIME_DEFAULT (_VDAC_OPA_TIMER_WARMUPTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ +#define _VDAC_OPA_TIMER_SETTLETIME_SHIFT 16 /**< Shift value for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_MASK 0x3FF0000UL /**< Bit mask for VDAC_OPASETTLETIME */ +#define _VDAC_OPA_TIMER_SETTLETIME_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_TIMER */ +#define VDAC_OPA_TIMER_SETTLETIME_DEFAULT (_VDAC_OPA_TIMER_SETTLETIME_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_TIMER */ + +/* Bit fields for VDAC OPA_MUX */ +#define _VDAC_OPA_MUX_RESETVALUE 0x0016F2F1UL /**< Default value for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_MASK 0x0717FFFFUL /**< Mask for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_SHIFT 0 /**< Shift value for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_MASK 0xFFUL /**< Bit mask for VDAC_OPAPOSSEL */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH2 0x00000021UL /**< Mode APORT1XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH4 0x00000022UL /**< Mode APORT1XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH6 0x00000023UL /**< Mode APORT1XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH8 0x00000024UL /**< Mode APORT1XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH10 0x00000025UL /**< Mode APORT1XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH12 0x00000026UL /**< Mode APORT1XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH14 0x00000027UL /**< Mode APORT1XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH16 0x00000028UL /**< Mode APORT1XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH18 0x00000029UL /**< Mode APORT1XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH20 0x0000002AUL /**< Mode APORT1XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH22 0x0000002BUL /**< Mode APORT1XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH24 0x0000002CUL /**< Mode APORT1XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH26 0x0000002DUL /**< Mode APORT1XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH28 0x0000002EUL /**< Mode APORT1XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT1XCH30 0x0000002FUL /**< Mode APORT1XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH1 0x00000040UL /**< Mode APORT2XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH3 0x00000041UL /**< Mode APORT2XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH5 0x00000042UL /**< Mode APORT2XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH7 0x00000043UL /**< Mode APORT2XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH9 0x00000044UL /**< Mode APORT2XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH11 0x00000045UL /**< Mode APORT2XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH13 0x00000046UL /**< Mode APORT2XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH15 0x00000047UL /**< Mode APORT2XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH17 0x00000048UL /**< Mode APORT2XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH19 0x00000049UL /**< Mode APORT2XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH21 0x0000004AUL /**< Mode APORT2XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH23 0x0000004BUL /**< Mode APORT2XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH25 0x0000004CUL /**< Mode APORT2XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH27 0x0000004DUL /**< Mode APORT2XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH29 0x0000004EUL /**< Mode APORT2XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT2XCH31 0x0000004FUL /**< Mode APORT2XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH0 0x00000060UL /**< Mode APORT3XCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH2 0x00000061UL /**< Mode APORT3XCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH4 0x00000062UL /**< Mode APORT3XCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH6 0x00000063UL /**< Mode APORT3XCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH8 0x00000064UL /**< Mode APORT3XCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH10 0x00000065UL /**< Mode APORT3XCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH12 0x00000066UL /**< Mode APORT3XCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH14 0x00000067UL /**< Mode APORT3XCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH16 0x00000068UL /**< Mode APORT3XCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH18 0x00000069UL /**< Mode APORT3XCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH20 0x0000006AUL /**< Mode APORT3XCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH22 0x0000006BUL /**< Mode APORT3XCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH24 0x0000006CUL /**< Mode APORT3XCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH26 0x0000006DUL /**< Mode APORT3XCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH28 0x0000006EUL /**< Mode APORT3XCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT3XCH30 0x0000006FUL /**< Mode APORT3XCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH1 0x00000080UL /**< Mode APORT4XCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH3 0x00000081UL /**< Mode APORT4XCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH5 0x00000082UL /**< Mode APORT4XCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH7 0x00000083UL /**< Mode APORT4XCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH9 0x00000084UL /**< Mode APORT4XCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH11 0x00000085UL /**< Mode APORT4XCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH13 0x00000086UL /**< Mode APORT4XCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH15 0x00000087UL /**< Mode APORT4XCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH17 0x00000088UL /**< Mode APORT4XCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH19 0x00000089UL /**< Mode APORT4XCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH21 0x0000008AUL /**< Mode APORT4XCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH23 0x0000008BUL /**< Mode APORT4XCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH25 0x0000008CUL /**< Mode APORT4XCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH27 0x0000008DUL /**< Mode APORT4XCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH29 0x0000008EUL /**< Mode APORT4XCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_APORT4XCH31 0x0000008FUL /**< Mode APORT4XCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DEFAULT 0x000000F1UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_DAC 0x000000F1UL /**< Mode DAC for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_POSPAD 0x000000F2UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPANEXT 0x000000F3UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_POSSEL_OPATAP 0x000000F4UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH0 (_VDAC_OPA_MUX_POSSEL_APORT1XCH0 << 0) /**< Shifted mode APORT1XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH2 (_VDAC_OPA_MUX_POSSEL_APORT1XCH2 << 0) /**< Shifted mode APORT1XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH4 (_VDAC_OPA_MUX_POSSEL_APORT1XCH4 << 0) /**< Shifted mode APORT1XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH6 (_VDAC_OPA_MUX_POSSEL_APORT1XCH6 << 0) /**< Shifted mode APORT1XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH8 (_VDAC_OPA_MUX_POSSEL_APORT1XCH8 << 0) /**< Shifted mode APORT1XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH10 (_VDAC_OPA_MUX_POSSEL_APORT1XCH10 << 0) /**< Shifted mode APORT1XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH12 (_VDAC_OPA_MUX_POSSEL_APORT1XCH12 << 0) /**< Shifted mode APORT1XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH14 (_VDAC_OPA_MUX_POSSEL_APORT1XCH14 << 0) /**< Shifted mode APORT1XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH16 (_VDAC_OPA_MUX_POSSEL_APORT1XCH16 << 0) /**< Shifted mode APORT1XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH18 (_VDAC_OPA_MUX_POSSEL_APORT1XCH18 << 0) /**< Shifted mode APORT1XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH20 (_VDAC_OPA_MUX_POSSEL_APORT1XCH20 << 0) /**< Shifted mode APORT1XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH22 (_VDAC_OPA_MUX_POSSEL_APORT1XCH22 << 0) /**< Shifted mode APORT1XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH24 (_VDAC_OPA_MUX_POSSEL_APORT1XCH24 << 0) /**< Shifted mode APORT1XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH26 (_VDAC_OPA_MUX_POSSEL_APORT1XCH26 << 0) /**< Shifted mode APORT1XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH28 (_VDAC_OPA_MUX_POSSEL_APORT1XCH28 << 0) /**< Shifted mode APORT1XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT1XCH30 (_VDAC_OPA_MUX_POSSEL_APORT1XCH30 << 0) /**< Shifted mode APORT1XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH1 (_VDAC_OPA_MUX_POSSEL_APORT2XCH1 << 0) /**< Shifted mode APORT2XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH3 (_VDAC_OPA_MUX_POSSEL_APORT2XCH3 << 0) /**< Shifted mode APORT2XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH5 (_VDAC_OPA_MUX_POSSEL_APORT2XCH5 << 0) /**< Shifted mode APORT2XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH7 (_VDAC_OPA_MUX_POSSEL_APORT2XCH7 << 0) /**< Shifted mode APORT2XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH9 (_VDAC_OPA_MUX_POSSEL_APORT2XCH9 << 0) /**< Shifted mode APORT2XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH11 (_VDAC_OPA_MUX_POSSEL_APORT2XCH11 << 0) /**< Shifted mode APORT2XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH13 (_VDAC_OPA_MUX_POSSEL_APORT2XCH13 << 0) /**< Shifted mode APORT2XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH15 (_VDAC_OPA_MUX_POSSEL_APORT2XCH15 << 0) /**< Shifted mode APORT2XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH17 (_VDAC_OPA_MUX_POSSEL_APORT2XCH17 << 0) /**< Shifted mode APORT2XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH19 (_VDAC_OPA_MUX_POSSEL_APORT2XCH19 << 0) /**< Shifted mode APORT2XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH21 (_VDAC_OPA_MUX_POSSEL_APORT2XCH21 << 0) /**< Shifted mode APORT2XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH23 (_VDAC_OPA_MUX_POSSEL_APORT2XCH23 << 0) /**< Shifted mode APORT2XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH25 (_VDAC_OPA_MUX_POSSEL_APORT2XCH25 << 0) /**< Shifted mode APORT2XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH27 (_VDAC_OPA_MUX_POSSEL_APORT2XCH27 << 0) /**< Shifted mode APORT2XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH29 (_VDAC_OPA_MUX_POSSEL_APORT2XCH29 << 0) /**< Shifted mode APORT2XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT2XCH31 (_VDAC_OPA_MUX_POSSEL_APORT2XCH31 << 0) /**< Shifted mode APORT2XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH0 (_VDAC_OPA_MUX_POSSEL_APORT3XCH0 << 0) /**< Shifted mode APORT3XCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH2 (_VDAC_OPA_MUX_POSSEL_APORT3XCH2 << 0) /**< Shifted mode APORT3XCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH4 (_VDAC_OPA_MUX_POSSEL_APORT3XCH4 << 0) /**< Shifted mode APORT3XCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH6 (_VDAC_OPA_MUX_POSSEL_APORT3XCH6 << 0) /**< Shifted mode APORT3XCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH8 (_VDAC_OPA_MUX_POSSEL_APORT3XCH8 << 0) /**< Shifted mode APORT3XCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH10 (_VDAC_OPA_MUX_POSSEL_APORT3XCH10 << 0) /**< Shifted mode APORT3XCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH12 (_VDAC_OPA_MUX_POSSEL_APORT3XCH12 << 0) /**< Shifted mode APORT3XCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH14 (_VDAC_OPA_MUX_POSSEL_APORT3XCH14 << 0) /**< Shifted mode APORT3XCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH16 (_VDAC_OPA_MUX_POSSEL_APORT3XCH16 << 0) /**< Shifted mode APORT3XCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH18 (_VDAC_OPA_MUX_POSSEL_APORT3XCH18 << 0) /**< Shifted mode APORT3XCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH20 (_VDAC_OPA_MUX_POSSEL_APORT3XCH20 << 0) /**< Shifted mode APORT3XCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH22 (_VDAC_OPA_MUX_POSSEL_APORT3XCH22 << 0) /**< Shifted mode APORT3XCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH24 (_VDAC_OPA_MUX_POSSEL_APORT3XCH24 << 0) /**< Shifted mode APORT3XCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH26 (_VDAC_OPA_MUX_POSSEL_APORT3XCH26 << 0) /**< Shifted mode APORT3XCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH28 (_VDAC_OPA_MUX_POSSEL_APORT3XCH28 << 0) /**< Shifted mode APORT3XCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT3XCH30 (_VDAC_OPA_MUX_POSSEL_APORT3XCH30 << 0) /**< Shifted mode APORT3XCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH1 (_VDAC_OPA_MUX_POSSEL_APORT4XCH1 << 0) /**< Shifted mode APORT4XCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH3 (_VDAC_OPA_MUX_POSSEL_APORT4XCH3 << 0) /**< Shifted mode APORT4XCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH5 (_VDAC_OPA_MUX_POSSEL_APORT4XCH5 << 0) /**< Shifted mode APORT4XCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH7 (_VDAC_OPA_MUX_POSSEL_APORT4XCH7 << 0) /**< Shifted mode APORT4XCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH9 (_VDAC_OPA_MUX_POSSEL_APORT4XCH9 << 0) /**< Shifted mode APORT4XCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH11 (_VDAC_OPA_MUX_POSSEL_APORT4XCH11 << 0) /**< Shifted mode APORT4XCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH13 (_VDAC_OPA_MUX_POSSEL_APORT4XCH13 << 0) /**< Shifted mode APORT4XCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH15 (_VDAC_OPA_MUX_POSSEL_APORT4XCH15 << 0) /**< Shifted mode APORT4XCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH17 (_VDAC_OPA_MUX_POSSEL_APORT4XCH17 << 0) /**< Shifted mode APORT4XCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH19 (_VDAC_OPA_MUX_POSSEL_APORT4XCH19 << 0) /**< Shifted mode APORT4XCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH21 (_VDAC_OPA_MUX_POSSEL_APORT4XCH21 << 0) /**< Shifted mode APORT4XCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH23 (_VDAC_OPA_MUX_POSSEL_APORT4XCH23 << 0) /**< Shifted mode APORT4XCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH25 (_VDAC_OPA_MUX_POSSEL_APORT4XCH25 << 0) /**< Shifted mode APORT4XCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH27 (_VDAC_OPA_MUX_POSSEL_APORT4XCH27 << 0) /**< Shifted mode APORT4XCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH29 (_VDAC_OPA_MUX_POSSEL_APORT4XCH29 << 0) /**< Shifted mode APORT4XCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_APORT4XCH31 (_VDAC_OPA_MUX_POSSEL_APORT4XCH31 << 0) /**< Shifted mode APORT4XCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DISABLE (_VDAC_OPA_MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DEFAULT (_VDAC_OPA_MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_DAC (_VDAC_OPA_MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_POSPAD (_VDAC_OPA_MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPANEXT (_VDAC_OPA_MUX_POSSEL_OPANEXT << 0) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_POSSEL_OPATAP (_VDAC_OPA_MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_SHIFT 8 /**< Shift value for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_MASK 0xFF00UL /**< Bit mask for VDAC_OPANEGSEL */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DISABLE 0x000000F0UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_UG 0x000000F1UL /**< Mode UG for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_DEFAULT 0x000000F2UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_OPATAP 0x000000F2UL /**< Mode OPATAP for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_NEGSEL_NEGPAD 0x000000F3UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH1 << 8) /**< Shifted mode APORT1YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH3 << 8) /**< Shifted mode APORT1YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH5 << 8) /**< Shifted mode APORT1YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH7 << 8) /**< Shifted mode APORT1YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH9 << 8) /**< Shifted mode APORT1YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH11 << 8) /**< Shifted mode APORT1YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH13 << 8) /**< Shifted mode APORT1YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH15 << 8) /**< Shifted mode APORT1YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH17 << 8) /**< Shifted mode APORT1YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH19 << 8) /**< Shifted mode APORT1YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH21 << 8) /**< Shifted mode APORT1YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH23 << 8) /**< Shifted mode APORT1YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH25 << 8) /**< Shifted mode APORT1YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH27 << 8) /**< Shifted mode APORT1YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH29 << 8) /**< Shifted mode APORT1YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT1YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT1YCH31 << 8) /**< Shifted mode APORT1YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH0 << 8) /**< Shifted mode APORT2YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH2 << 8) /**< Shifted mode APORT2YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH4 << 8) /**< Shifted mode APORT2YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH6 << 8) /**< Shifted mode APORT2YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH8 << 8) /**< Shifted mode APORT2YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH10 << 8) /**< Shifted mode APORT2YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH12 << 8) /**< Shifted mode APORT2YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH14 << 8) /**< Shifted mode APORT2YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH16 << 8) /**< Shifted mode APORT2YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH18 << 8) /**< Shifted mode APORT2YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH20 << 8) /**< Shifted mode APORT2YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH22 << 8) /**< Shifted mode APORT2YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH24 << 8) /**< Shifted mode APORT2YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH26 << 8) /**< Shifted mode APORT2YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH28 << 8) /**< Shifted mode APORT2YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT2YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT2YCH30 << 8) /**< Shifted mode APORT2YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH1 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH1 << 8) /**< Shifted mode APORT3YCH1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH3 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH3 << 8) /**< Shifted mode APORT3YCH3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH5 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH5 << 8) /**< Shifted mode APORT3YCH5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH7 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH7 << 8) /**< Shifted mode APORT3YCH7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH9 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH9 << 8) /**< Shifted mode APORT3YCH9 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH11 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH11 << 8) /**< Shifted mode APORT3YCH11 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH13 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH13 << 8) /**< Shifted mode APORT3YCH13 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH15 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH15 << 8) /**< Shifted mode APORT3YCH15 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH17 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH17 << 8) /**< Shifted mode APORT3YCH17 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH19 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH19 << 8) /**< Shifted mode APORT3YCH19 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH21 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH21 << 8) /**< Shifted mode APORT3YCH21 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH23 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH23 << 8) /**< Shifted mode APORT3YCH23 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH25 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH25 << 8) /**< Shifted mode APORT3YCH25 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH27 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH27 << 8) /**< Shifted mode APORT3YCH27 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH29 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH29 << 8) /**< Shifted mode APORT3YCH29 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT3YCH31 (_VDAC_OPA_MUX_NEGSEL_APORT3YCH31 << 8) /**< Shifted mode APORT3YCH31 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH0 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH0 << 8) /**< Shifted mode APORT4YCH0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH2 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH2 << 8) /**< Shifted mode APORT4YCH2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH4 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH4 << 8) /**< Shifted mode APORT4YCH4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH6 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH6 << 8) /**< Shifted mode APORT4YCH6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH8 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH8 << 8) /**< Shifted mode APORT4YCH8 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH10 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH10 << 8) /**< Shifted mode APORT4YCH10 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH12 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH12 << 8) /**< Shifted mode APORT4YCH12 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH14 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH14 << 8) /**< Shifted mode APORT4YCH14 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH16 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH16 << 8) /**< Shifted mode APORT4YCH16 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH18 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH18 << 8) /**< Shifted mode APORT4YCH18 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH20 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH20 << 8) /**< Shifted mode APORT4YCH20 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH22 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH22 << 8) /**< Shifted mode APORT4YCH22 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH24 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH24 << 8) /**< Shifted mode APORT4YCH24 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH26 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH26 << 8) /**< Shifted mode APORT4YCH26 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH28 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH28 << 8) /**< Shifted mode APORT4YCH28 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_APORT4YCH30 (_VDAC_OPA_MUX_NEGSEL_APORT4YCH30 << 8) /**< Shifted mode APORT4YCH30 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DISABLE (_VDAC_OPA_MUX_NEGSEL_DISABLE << 8) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_UG (_VDAC_OPA_MUX_NEGSEL_UG << 8) /**< Shifted mode UG for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_DEFAULT (_VDAC_OPA_MUX_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_OPATAP (_VDAC_OPA_MUX_NEGSEL_OPATAP << 8) /**< Shifted mode OPATAP for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_NEGSEL_NEGPAD (_VDAC_OPA_MUX_NEGSEL_NEGPAD << 8) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_SHIFT 16 /**< Shift value for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_MASK 0x70000UL /**< Bit mask for VDAC_OPARESINMUX */ +#define _VDAC_OPA_MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_OPANEXT 0x00000001UL /**< Mode OPANEXT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_COMPAD 0x00000004UL /**< Mode COMPAD for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_CENTER 0x00000005UL /**< Mode CENTER for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_DEFAULT 0x00000006UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESINMUX_VSS 0x00000006UL /**< Mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DISABLE (_VDAC_OPA_MUX_RESINMUX_DISABLE << 16) /**< Shifted mode DISABLE for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_OPANEXT (_VDAC_OPA_MUX_RESINMUX_OPANEXT << 16) /**< Shifted mode OPANEXT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_NEGPAD (_VDAC_OPA_MUX_RESINMUX_NEGPAD << 16) /**< Shifted mode NEGPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_POSPAD (_VDAC_OPA_MUX_RESINMUX_POSPAD << 16) /**< Shifted mode POSPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_COMPAD (_VDAC_OPA_MUX_RESINMUX_COMPAD << 16) /**< Shifted mode COMPAD for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_CENTER (_VDAC_OPA_MUX_RESINMUX_CENTER << 16) /**< Shifted mode CENTER for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_DEFAULT (_VDAC_OPA_MUX_RESINMUX_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESINMUX_VSS (_VDAC_OPA_MUX_RESINMUX_VSS << 16) /**< Shifted mode VSS for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X (0x1UL << 20) /**< OPAx Dedicated 3x gain resistor ladder. */ +#define _VDAC_OPA_MUX_GAIN3X_SHIFT 20 /**< Shift value for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_MASK 0x100000UL /**< Bit mask for VDAC_OPAGAIN3X */ +#define _VDAC_OPA_MUX_GAIN3X_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_GAIN3X_DEFAULT (_VDAC_OPA_MUX_GAIN3X_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_SHIFT 24 /**< Shift value for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_MASK 0x7000000UL /**< Bit mask for VDAC_OPARESSEL */ +#define _VDAC_OPA_MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for VDAC_OPA_MUX */ +#define _VDAC_OPA_MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_DEFAULT (_VDAC_OPA_MUX_RESSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES0 (_VDAC_OPA_MUX_RESSEL_RES0 << 24) /**< Shifted mode RES0 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES1 (_VDAC_OPA_MUX_RESSEL_RES1 << 24) /**< Shifted mode RES1 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES2 (_VDAC_OPA_MUX_RESSEL_RES2 << 24) /**< Shifted mode RES2 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES3 (_VDAC_OPA_MUX_RESSEL_RES3 << 24) /**< Shifted mode RES3 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES4 (_VDAC_OPA_MUX_RESSEL_RES4 << 24) /**< Shifted mode RES4 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES5 (_VDAC_OPA_MUX_RESSEL_RES5 << 24) /**< Shifted mode RES5 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES6 (_VDAC_OPA_MUX_RESSEL_RES6 << 24) /**< Shifted mode RES6 for VDAC_OPA_MUX */ +#define VDAC_OPA_MUX_RESSEL_RES7 (_VDAC_OPA_MUX_RESSEL_RES7 << 24) /**< Shifted mode RES7 for VDAC_OPA_MUX */ + +/* Bit fields for VDAC OPA_OUT */ +#define _VDAC_OPA_OUT_RESETVALUE 0x00000001UL /**< Default value for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_MASK 0x00FF01FFUL /**< Mask for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN (0x1UL << 0) /**< OPAx Main Output Enable */ +#define _VDAC_OPA_OUT_MAINOUTEN_SHIFT 0 /**< Shift value for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_MASK 0x1UL /**< Bit mask for VDAC_OPAMAINOUTEN */ +#define _VDAC_OPA_OUT_MAINOUTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_MAINOUTEN_DEFAULT (_VDAC_OPA_OUT_MAINOUTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN (0x1UL << 1) /**< OPAx Alternative Output Enable */ +#define _VDAC_OPA_OUT_ALTOUTEN_SHIFT 1 /**< Shift value for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_MASK 0x2UL /**< Bit mask for VDAC_OPAALTOUTEN */ +#define _VDAC_OPA_OUT_ALTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN (0x1UL << 2) /**< OPAx Aport Output Enable */ +#define _VDAC_OPA_OUT_APORTOUTEN_SHIFT 2 /**< Shift value for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_MASK 0x4UL /**< Bit mask for VDAC_OPAAPORTOUTEN */ +#define _VDAC_OPA_OUT_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTEN_DEFAULT (_VDAC_OPA_OUT_APORTOUTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT (0x1UL << 3) /**< OPAx Main and Alternative Output Short */ +#define _VDAC_OPA_OUT_SHORT_SHIFT 3 /**< Shift value for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_MASK 0x8UL /**< Bit mask for VDAC_OPASHORT */ +#define _VDAC_OPA_OUT_SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_SHORT_DEFAULT (_VDAC_OPA_OUT_SHORT_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_SHIFT 4 /**< Shift value for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_MASK 0x1F0UL /**< Bit mask for VDAC_OPAALTOUTPADEN */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT0 0x00000001UL /**< Mode OUT0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT1 0x00000002UL /**< Mode OUT1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT2 0x00000004UL /**< Mode OUT2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT3 0x00000008UL /**< Mode OUT3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_ALTOUTPADEN_OUT4 0x00000010UL /**< Mode OUT4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT (_VDAC_OPA_OUT_ALTOUTPADEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT0 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT0 << 4) /**< Shifted mode OUT0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT1 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT1 << 4) /**< Shifted mode OUT1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT2 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT2 << 4) /**< Shifted mode OUT2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT3 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT3 << 4) /**< Shifted mode OUT3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_ALTOUTPADEN_OUT4 (_VDAC_OPA_OUT_ALTOUTPADEN_OUT4 << 4) /**< Shifted mode OUT4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_SHIFT 16 /**< Shift value for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_MASK 0xFF0000UL /**< Bit mask for VDAC_OPAAPORTOUTSEL */ +#define _VDAC_OPA_OUT_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 0x00000030UL /**< Mode APORT1YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 0x00000031UL /**< Mode APORT1YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 0x00000032UL /**< Mode APORT1YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 0x00000033UL /**< Mode APORT1YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 0x00000034UL /**< Mode APORT1YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 0x00000035UL /**< Mode APORT1YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 0x00000036UL /**< Mode APORT1YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 0x00000037UL /**< Mode APORT1YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 0x00000038UL /**< Mode APORT1YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 0x00000039UL /**< Mode APORT1YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 0x0000003AUL /**< Mode APORT1YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 0x0000003BUL /**< Mode APORT1YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 0x0000003CUL /**< Mode APORT1YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 0x0000003DUL /**< Mode APORT1YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 0x0000003EUL /**< Mode APORT1YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 0x00000050UL /**< Mode APORT2YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 0x00000051UL /**< Mode APORT2YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 0x00000052UL /**< Mode APORT2YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 0x00000053UL /**< Mode APORT2YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 0x00000054UL /**< Mode APORT2YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 0x00000055UL /**< Mode APORT2YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 0x00000056UL /**< Mode APORT2YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 0x00000057UL /**< Mode APORT2YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 0x00000058UL /**< Mode APORT2YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 0x00000059UL /**< Mode APORT2YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 0x0000005AUL /**< Mode APORT2YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 0x0000005BUL /**< Mode APORT2YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 0x0000005CUL /**< Mode APORT2YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 0x0000005DUL /**< Mode APORT2YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 0x0000005EUL /**< Mode APORT2YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 0x0000005FUL /**< Mode APORT2YCH30 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 0x00000070UL /**< Mode APORT3YCH1 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 0x00000071UL /**< Mode APORT3YCH3 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 0x00000072UL /**< Mode APORT3YCH5 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 0x00000073UL /**< Mode APORT3YCH7 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 0x00000074UL /**< Mode APORT3YCH9 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 0x00000075UL /**< Mode APORT3YCH11 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 0x00000076UL /**< Mode APORT3YCH13 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 0x00000077UL /**< Mode APORT3YCH15 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 0x00000078UL /**< Mode APORT3YCH17 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 0x00000079UL /**< Mode APORT3YCH19 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 0x0000007AUL /**< Mode APORT3YCH21 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 0x0000007BUL /**< Mode APORT3YCH23 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 0x0000007CUL /**< Mode APORT3YCH25 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 0x0000007DUL /**< Mode APORT3YCH27 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 0x0000007EUL /**< Mode APORT3YCH29 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 0x0000007FUL /**< Mode APORT3YCH31 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 0x00000090UL /**< Mode APORT4YCH0 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 0x00000091UL /**< Mode APORT4YCH2 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 0x00000092UL /**< Mode APORT4YCH4 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 0x00000093UL /**< Mode APORT4YCH6 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 0x00000094UL /**< Mode APORT4YCH8 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 0x00000095UL /**< Mode APORT4YCH10 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 0x00000096UL /**< Mode APORT4YCH12 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 0x00000097UL /**< Mode APORT4YCH14 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 0x00000098UL /**< Mode APORT4YCH16 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 0x00000099UL /**< Mode APORT4YCH18 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 0x0000009AUL /**< Mode APORT4YCH20 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 0x0000009BUL /**< Mode APORT4YCH22 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 0x0000009CUL /**< Mode APORT4YCH24 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 0x0000009DUL /**< Mode APORT4YCH26 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 0x0000009EUL /**< Mode APORT4YCH28 for VDAC_OPA_OUT */ +#define _VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 0x0000009FUL /**< Mode APORT4YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_DEFAULT (_VDAC_OPA_OUT_APORTOUTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1 << 16) /**< Shifted mode APORT1YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3 << 16) /**< Shifted mode APORT1YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5 << 16) /**< Shifted mode APORT1YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7 << 16) /**< Shifted mode APORT1YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9 << 16) /**< Shifted mode APORT1YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11 << 16) /**< Shifted mode APORT1YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13 << 16) /**< Shifted mode APORT1YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15 << 16) /**< Shifted mode APORT1YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17 << 16) /**< Shifted mode APORT1YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19 << 16) /**< Shifted mode APORT1YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21 << 16) /**< Shifted mode APORT1YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23 << 16) /**< Shifted mode APORT1YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25 << 16) /**< Shifted mode APORT1YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27 << 16) /**< Shifted mode APORT1YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29 << 16) /**< Shifted mode APORT1YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31 << 16) /**< Shifted mode APORT1YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0 << 16) /**< Shifted mode APORT2YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2 << 16) /**< Shifted mode APORT2YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4 << 16) /**< Shifted mode APORT2YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6 << 16) /**< Shifted mode APORT2YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8 << 16) /**< Shifted mode APORT2YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10 << 16) /**< Shifted mode APORT2YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12 << 16) /**< Shifted mode APORT2YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14 << 16) /**< Shifted mode APORT2YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16 << 16) /**< Shifted mode APORT2YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18 << 16) /**< Shifted mode APORT2YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20 << 16) /**< Shifted mode APORT2YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22 << 16) /**< Shifted mode APORT2YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24 << 16) /**< Shifted mode APORT2YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26 << 16) /**< Shifted mode APORT2YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28 << 16) /**< Shifted mode APORT2YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30 << 16) /**< Shifted mode APORT2YCH30 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1 << 16) /**< Shifted mode APORT3YCH1 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3 << 16) /**< Shifted mode APORT3YCH3 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5 << 16) /**< Shifted mode APORT3YCH5 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7 << 16) /**< Shifted mode APORT3YCH7 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9 << 16) /**< Shifted mode APORT3YCH9 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11 << 16) /**< Shifted mode APORT3YCH11 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13 << 16) /**< Shifted mode APORT3YCH13 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15 << 16) /**< Shifted mode APORT3YCH15 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17 << 16) /**< Shifted mode APORT3YCH17 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19 << 16) /**< Shifted mode APORT3YCH19 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21 << 16) /**< Shifted mode APORT3YCH21 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23 << 16) /**< Shifted mode APORT3YCH23 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25 << 16) /**< Shifted mode APORT3YCH25 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27 << 16) /**< Shifted mode APORT3YCH27 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29 << 16) /**< Shifted mode APORT3YCH29 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 (_VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31 << 16) /**< Shifted mode APORT3YCH31 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0 << 16) /**< Shifted mode APORT4YCH0 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2 << 16) /**< Shifted mode APORT4YCH2 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4 << 16) /**< Shifted mode APORT4YCH4 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6 << 16) /**< Shifted mode APORT4YCH6 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8 << 16) /**< Shifted mode APORT4YCH8 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10 << 16) /**< Shifted mode APORT4YCH10 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12 << 16) /**< Shifted mode APORT4YCH12 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14 << 16) /**< Shifted mode APORT4YCH14 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16 << 16) /**< Shifted mode APORT4YCH16 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18 << 16) /**< Shifted mode APORT4YCH18 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20 << 16) /**< Shifted mode APORT4YCH20 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22 << 16) /**< Shifted mode APORT4YCH22 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24 << 16) /**< Shifted mode APORT4YCH24 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26 << 16) /**< Shifted mode APORT4YCH26 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28 << 16) /**< Shifted mode APORT4YCH28 for VDAC_OPA_OUT */ +#define VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 (_VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30 << 16) /**< Shifted mode APORT4YCH30 for VDAC_OPA_OUT */ + +/* Bit fields for VDAC OPA_CAL */ +#define _VDAC_OPA_CAL_RESETVALUE 0x000080E7UL /**< Default value for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_MASK 0x7DF6EDEFUL /**< Mask for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM1_SHIFT 0 /**< Shift value for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_MASK 0xFUL /**< Bit mask for VDAC_OPACM1 */ +#define _VDAC_OPA_CAL_CM1_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM1_DEFAULT (_VDAC_OPA_CAL_CM1_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM2_SHIFT 5 /**< Shift value for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_MASK 0x1E0UL /**< Bit mask for VDAC_OPACM2 */ +#define _VDAC_OPA_CAL_CM2_DEFAULT 0x00000007UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM2_DEFAULT (_VDAC_OPA_CAL_CM2_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_CM3_SHIFT 10 /**< Shift value for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_MASK 0xC00UL /**< Bit mask for VDAC_OPACM3 */ +#define _VDAC_OPA_CAL_CM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_CM3_DEFAULT (_VDAC_OPA_CAL_CM3_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM_SHIFT 13 /**< Shift value for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_MASK 0xE000UL /**< Bit mask for VDAC_OPAGM */ +#define _VDAC_OPA_CAL_GM_DEFAULT 0x00000004UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM_DEFAULT (_VDAC_OPA_CAL_GM_DEFAULT << 13) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_GM3_SHIFT 17 /**< Shift value for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_MASK 0x60000UL /**< Bit mask for VDAC_OPAGM3 */ +#define _VDAC_OPA_CAL_GM3_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_GM3_DEFAULT (_VDAC_OPA_CAL_GM3_DEFAULT << 17) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETP_SHIFT 20 /**< Shift value for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_MASK 0x1F00000UL /**< Bit mask for VDAC_OPAOFFSETP */ +#define _VDAC_OPA_CAL_OFFSETP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETP_DEFAULT (_VDAC_OPA_CAL_OFFSETP_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ +#define _VDAC_OPA_CAL_OFFSETN_SHIFT 26 /**< Shift value for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_MASK 0x7C000000UL /**< Bit mask for VDAC_OPAOFFSETN */ +#define _VDAC_OPA_CAL_OFFSETN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OPA_CAL */ +#define VDAC_OPA_CAL_OFFSETN_DEFAULT (_VDAC_OPA_CAL_OFFSETN_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_OPA_CAL */ + +/** @} End of group EFM32PG12B_VDAC */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac_opa.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac_opa.h new file mode 100644 index 0000000000..a082dfbff8 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac_opa.h @@ -0,0 +1,53 @@ +/**************************************************************************//** + * @file efm32pg12b_vdac_opa.h + * @brief EFM32PG12B_VDAC_OPA register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief VDAC_OPA EFM32PG12B VDAC OPA + *****************************************************************************/ +typedef struct +{ + __IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */ + __IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */ + __IOM uint32_t CTRL; /**< Operational Amplifier Control Register */ + __IOM uint32_t TIMER; /**< Operational Amplifier Timer Control Register */ + __IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */ + __IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */ + __IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */ + uint32_t RESERVED0[1]; /**< Reserved future */ +} VDAC_OPA_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog.h new file mode 100644 index 0000000000..53114a019b --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog.h @@ -0,0 +1,335 @@ +/**************************************************************************//** + * @file efm32pg12b_wdog.h + * @brief EFM32PG12B_WDOG register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFM32PG12B_WDOG + * @{ + * @brief EFM32PG12B_WDOG Register Declaration + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + + WDOG_PCH_TypeDef PCH[2]; /**< PCH */ + + uint32_t RESERVED0[2]; /**< Reserved for future use **/ + __IM uint32_t IF; /**< Watchdog Interrupt Flags */ + __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ + __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ +} WDOG_TypeDef; /** @} */ + +/**************************************************************************//** + * @defgroup EFM32PG12B_WDOG_BitFields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG CTRL */ +#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */ +#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */ +#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */ +#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ +#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */ +#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */ +#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */ +#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */ +#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */ +#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */ +#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */ +#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */ +#define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */ +#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */ +#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */ +#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */ +#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */ +#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */ +#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */ +#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */ +#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */ +#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/* Bit fields for WDOG PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */ +#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */ +#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IFS */ +#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */ +#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */ +#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */ +#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */ +#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */ +#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */ +#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */ +#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */ +#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */ + +/* Bit fields for WDOG IFC */ +#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */ +#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */ +#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */ +#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */ +#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */ +#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */ +#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */ +#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */ +#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/** @} End of group EFM32PG12B_WDOG */ +/** @} End of group Parts */ + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog_pch.h new file mode 100644 index 0000000000..6c8b7edadb --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog_pch.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file efm32pg12b_wdog_pch.h + * @brief EFM32PG12B_WDOG_PCH register and bit field definitions + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief WDOG_PCH EFM32PG12B WDOG PCH + *****************************************************************************/ +typedef struct +{ + __IOM uint32_t PRSCTRL; /**< PRS Control Register */ +} WDOG_PCH_TypeDef; + +/** @} End of group Parts */ + + diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/em_device.h new file mode 100644 index 0000000000..0b5751daa3 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/em_device.h @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file em_device.h + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + * + * + * @endverbatim + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H + +#if defined(EFM32PG12B500F1024GL125) +#include "efm32pg12b500f1024gl125.h" + +#elif defined(EFM32PG12B500F1024GM48) +#include "efm32pg12b500f1024gm48.h" + +#elif defined(EFM32PG12B500F1024IL125) +#include "efm32pg12b500f1024il125.h" + +#elif defined(EFM32PG12B500F1024IM48) +#include "efm32pg12b500f1024im48.h" + +#elif defined(EFM32PG12B500F512GL125) +#include "efm32pg12b500f512gl125.h" + +#elif defined(EFM32PG12B500F512GM48) +#include "efm32pg12b500f512gm48.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif +#endif /* EM_DEVICE_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.c new file mode 100644 index 0000000000..25ade0ffc4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.c @@ -0,0 +1,384 @@ +/***************************************************************************//** + * @file system_efm32pg12b.c + * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** LFRCO frequency, tuned to below frequency during manufacturing. */ +#define EFM32_LFRCO_FREQ (32768UL) +#define EFM32_ULFRCO_FREQ (1000UL) + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* System oscillator frequencies. These frequencies are normally constant */ +/* for a target, but they are made configurable in order to allow run-time */ +/* handling of different boards. The crystal oscillator clocks can be set */ +/* compile time to a non-default value by defining respective EFM_nFXO_FREQ */ +/* values according to board design. By defining the EFM_nFXO_FREQ to 0, */ +/* one indicates that the oscillator is not present, in order to save some */ +/* SW footprint. */ + +#ifndef EFM32_HFRCO_MAX_FREQ +#define EFM32_HFRCO_MAX_FREQ (38000000UL) +#endif + +#ifndef EFM32_HFXO_FREQ +#define EFM32_HFXO_FREQ (40000000UL) +#endif + +#ifndef EFM32_HFRCO_STARTUP_FREQ +#define EFM32_HFRCO_STARTUP_FREQ (19000000UL) +#endif + + +/* Do not define variable if HF crystal oscillator not present */ +#if (EFM32_HFXO_FREQ > 0UL) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System HFXO clock. */ +static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + +#ifndef EFM32_LFXO_FREQ +#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) +#endif +/* Do not define variable if LF crystal oscillator not present */ +#if (EFM32_LFXO_FREQ > 0UL) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** System LFXO clock. */ +static uint32_t SystemLFXOClock = 32768UL; +/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ +#endif + + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock; + + +/** + * @brief + * System HFRCO frequency + * + * @note + * This is an EFM32 proprietary variable, not part of the CMSIS definition. + * + * @details + * Frequency of the system HFRCO oscillator + */ +uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ; + + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current core clock frequency. + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemCoreClockGet(void) +{ + uint32_t ret; + uint32_t presc; + + ret = SystemHFClockGet(); + presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >> + _CMU_HFCOREPRESC_PRESC_SHIFT; + ret /= (presc + 1); + + /* Keep CMSIS system clock variable up-to-date */ + SystemCoreClock = ret; + + return ret; +} + + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \ + EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ); +} + + +/***************************************************************************//** + * @brief + * Get the current HFCLK frequency. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * The current HFCLK frequency in Hz. + ******************************************************************************/ +uint32_t SystemHFClockGet(void) +{ + uint32_t ret; + + switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) + { + case CMU_HFCLKSTATUS_SELECTED_LFXO: +#if (EFM32_LFXO_FREQ > 0) + ret = SystemLFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + case CMU_HFCLKSTATUS_SELECTED_LFRCO: + ret = EFM32_LFRCO_FREQ; + break; + + case CMU_HFCLKSTATUS_SELECTED_HFXO: +#if (EFM32_HFXO_FREQ > 0) + ret = SystemHFXOClock; +#else + /* We should not get here, since core should not be clocked. May */ + /* be caused by a misconfiguration though. */ + ret = 0; +#endif + break; + + default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */ + ret = SystemHfrcoFreq; + break; + } + + return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT)); +} + + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * HFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0) + return SystemHFXOClock; +#else + return 0; +#endif +} + + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_HFXO_FREQ > 0) + SystemHFXOClock = freq; + + /* Update core clock frequency if HFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO) + { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} + + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Set floating point coprosessor access mode. */ + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif +} + + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + /* Currently we assume that this frequency is properly tuned during */ + /* manufacturing and is not changed after reset. If future requirements */ + /* for re-tuning by user, we can add support for that. */ + return EFM32_LFRCO_FREQ; +} + + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + /* The ULFRCO frequency is not tuned, and can be very inaccurate */ + return EFM32_ULFRCO_FREQ; +} + + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0) + return SystemLFXOClock; +#else + return 0; +#endif +} + + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is an EFM32 proprietary function, not part of the CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + /* External crystal oscillator present? */ +#if (EFM32_LFXO_FREQ > 0) + SystemLFXOClock = freq; + + /* Update core clock frequency if LFXO is used to clock core */ + if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO) + { + /* The function will update the global variable */ + SystemCoreClockGet(); + } +#else + (void)freq; /* Unused parameter */ +#endif +} diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.h new file mode 100644 index 0000000000..feb8ceef0d --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.h @@ -0,0 +1,129 @@ +/***************************************************************************//** + * @file system_efm32pg12b.h + * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. + * @version 5.1.2 + ****************************************************************************** + * @section License + * Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com + ****************************************************************************** + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software.@n + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software.@n + * 3. This notice may not be removed or altered from any source distribution. + * + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. + * has no obligation to support this Software. Silicon Laboratories, Inc. is + * providing the Software "AS IS", with no express or implied warranties of any + * kind, including, but not limited to, any implied warranties of + * merchantability or fitness for any particular purpose or warranties against + * infringement of any proprietary rights of a third party. + * + * Silicon Laboratories, Inc. will not be liable for any consequential, + * incidental, or special damages, or any other relief, or for any claim by + * any third party, arising from your use of this Software. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFM32_H +#define SYSTEM_EFM32_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void EMU_IRQHandler(void); +void WDOG0_IRQHandler(void); +void LDMA_IRQHandler(void); +void GPIO_EVEN_IRQHandler(void); +void TIMER0_IRQHandler(void); +void USART0_RX_IRQHandler(void); +void USART0_TX_IRQHandler(void); +void ACMP0_IRQHandler(void); +void ADC0_IRQHandler(void); +void IDAC0_IRQHandler(void); +void I2C0_IRQHandler(void); +void GPIO_ODD_IRQHandler(void); +void TIMER1_IRQHandler(void); +void USART1_RX_IRQHandler(void); +void USART1_TX_IRQHandler(void); +void LEUART0_IRQHandler(void); +void PCNT0_IRQHandler(void); +void CMU_IRQHandler(void); +void MSC_IRQHandler(void); +void LETIMER0_IRQHandler(void); +void RTCC_IRQHandler(void); +void CRYOTIMER_IRQHandler(void); + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); +#endif + +uint32_t SystemCoreClockGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EFM CMU + * API, this variable will be kept updated. This function is only provided + * for CMSIS compliance and if a user modifies the the core clock outside + * the CMU API. + *****************************************************************************/ +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemCoreClockGet(); +} + +uint32_t SystemMaxCoreClockGet(void); + +void SystemInit(void); +uint32_t SystemHFClockGet(void); + +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); + +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFM32_H */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c index 34aed53b18..66b1d7416a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c @@ -47,7 +47,10 @@ void mbed_sdk_init() // Initialize the HFXO using the settings from the WSTK bspconfig.h // Note: This configures things like the capacitive tuning CTUNE variable // which can vary based on your hardware design. - CMU_HFXOInit(&hfxoInit); + CMU_HFXOInit(&hfxoInit); +#else + CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_STK_DEFAULT; + CMU_HFXOInit(&hfxoInit); #endif #endif diff --git a/targets/TARGET_Silicon_Labs/mbed_rtx.h b/targets/TARGET_Silicon_Labs/mbed_rtx.h index 69e953272e..51dfdbb16d 100644 --- a/targets/TARGET_Silicon_Labs/mbed_rtx.h +++ b/targets/TARGET_Silicon_Labs/mbed_rtx.h @@ -115,7 +115,7 @@ extern uint32_t STACK$$Base; #define OS_MAINSTKSIZE 256 #endif -#elif defined(TARGET_EFR32MG12) +#elif defined(TARGET_EFR32MG12) || defined(TARGET_EFM32PG12) #ifndef INITIAL_SP #define INITIAL_SP (0x20040000UL) diff --git a/targets/targets.json b/targets/targets.json index c55d0e0d47..caebe3d835 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2335,6 +2335,58 @@ "macro_name": "HFRCO_FREQUENCY_ENUM" } } + }, + "EFM32PG12B500F1024": { + "inherits": ["EFM32"], + "extra_labels_add": ["EFM32PG12", "1024K"], + "core": "Cortex-M4F", + "macros": ["EFM32PG12B500F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], + "release_versions": ["2", "5"], + "device_name": "EFM32PG12B500F1024", + "public": false + }, + "EFM32PG12_STK3402": { + "inherits": ["EFM32PG12B500F1024"], + "device_has": ["AES", "SHA", "ECC", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "forced_reset_timeout": 2, + "config": { + "hf_clock_src": { + "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator", + "value": "HFXO", + "macro_name": "CORE_CLOCK_SOURCE" + }, + "hfxo_clock_freq": { + "help": "Value: External crystal frequency in hertz", + "value": "40000000", + "macro_name": "HFXO_FREQUENCY" + }, + "lf_clock_src": { + "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator", + "value": "LFXO", + "macro_name": "LOW_ENERGY_CLOCK_SOURCE" + }, + "lfxo_clock_freq": { + "help": "Value: External crystal frequency in hertz", + "value": "32768", + "macro_name": "LFXO_FREQUENCY" + }, + "hfrco_clock_freq": { + "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select", + "value": "32000000", + "macro_name": "HFRCO_FREQUENCY" + }, + "hfrco_band_select": { + "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!", + "value": "cmuHFRCOFreq_32M0Hz", + "macro_name": "HFRCO_FREQUENCY_ENUM" + }, + "board_controller_enable": { + "help": "Pin to pull high for enabling the USB serial port", + "value": "PA5", + "macro_name": "EFM_BC_EN" + } + } }, "EFR32MG12P332F1024GL125": { "inherits": ["EFM32"], From 8067bf629f8e1288149623d96db75b9932df1521 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Tue, 14 Mar 2017 14:23:19 +0100 Subject: [PATCH 06/10] Update clock calibration structs to match latest Gecko SDK --- .../device_peripherals.h | 21 +++++++++++++++++++ .../device_peripherals.h | 7 ++++--- .../device_peripherals.h | 3 ++- .../device_peripherals.h | 3 ++- 4 files changed, 29 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h index baa35e5ba0..3147299bbd 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG/TARGET_EFM32PG_STK3401/device_peripherals.h @@ -33,4 +33,25 @@ #define PWM_TIMER_CLOCK cmuClock_TIMER1 #define PWM_ROUTE TIMER_ROUTE_LOCATION_LOC1 +/* Crystal Calibration */ +#if !defined(CMU_HFXOINIT_STK_DEFAULT) +#define CMU_HFXOINIT_STK_DEFAULT \ +{ \ + true, /* Low-power mode for EFM32 */ \ + false, /* Disable auto-start on EM0/1 entry */ \ + false, /* Disable auto-select on EM0/1 entry */ \ + false, /* Disable auto-start and select on RAC wakeup */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + 0x142, /* Steady-state CTUNE for STK boards without load caps */ \ + _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ + 0x20, /* Matching errata fix in CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ +} +#endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h index 93f2510639..13cbb9af1a 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_EFR32MG1_BRD4150/device_peripherals.h @@ -44,13 +44,14 @@ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ 0x142, /* Steady-state CTUNE for WSTK boards without load caps */ \ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ - _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ - 0x7, /* Recommended steady-state XO core bias current */ \ + 0x20, /* Matching errata fix in CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ 0x6, /* Recommended peak detection threshold */ \ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ 0xA, /* Recommended peak detection timeout */ \ - _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + 0x4, /* Recommended steady timeout */ \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ } #endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_THUNDERBOARD_SENSE/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_THUNDERBOARD_SENSE/device_peripherals.h index 93f2510639..976dce7aba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_THUNDERBOARD_SENSE/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/TARGET_THUNDERBOARD_SENSE/device_peripherals.h @@ -42,7 +42,7 @@ false, /* Disable auto-select on EM0/1 entry */ \ false, /* Disable auto-start and select on RAC wakeup */ \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - 0x142, /* Steady-state CTUNE for WSTK boards without load caps */ \ + 0x142, /* Steady-state CTUNE for TBSENSE boards without load caps */ \ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ 0x7, /* Recommended steady-state XO core bias current */ \ @@ -51,6 +51,7 @@ 0xA, /* Recommended peak detection timeout */ \ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ } #endif #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h index 93f2510639..976dce7aba 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/TARGET_THUNDERBOARD_SENSE_12/device_peripherals.h @@ -42,7 +42,7 @@ false, /* Disable auto-select on EM0/1 entry */ \ false, /* Disable auto-start and select on RAC wakeup */ \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - 0x142, /* Steady-state CTUNE for WSTK boards without load caps */ \ + 0x142, /* Steady-state CTUNE for TBSENSE boards without load caps */ \ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ 0x7, /* Recommended steady-state XO core bias current */ \ @@ -51,6 +51,7 @@ 0xA, /* Recommended peak detection timeout */ \ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ } #endif #endif From d710ec4e12858980c965cb9f40d96dc0f485df90 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Tue, 14 Mar 2017 17:00:44 +0100 Subject: [PATCH 07/10] Bugfix for EFM32PG12 and EFR32MG12 * Off by one error in the linker scripts reserved one word too little for the vector table * Re-apply uvisor changes to emlib. To allow uvisor to run, we should make accesses to the romtable through uvisor's secure read gateway * Copypasta in target name (EFM32PG12, not EFR32PG12) * Copypasta in the pin definitions (thanks @akselsm) * Forgot to update PortName for extra ports on MG/PG12 --- .../PeripheralNames.h | 0 .../PeripheralPins.c | 0 .../PeripheralPins.h | 0 .../TARGET_EFM32PG12_STK3402/PinNames.h | 0 .../device_peripherals.h | 0 .../device/TOOLCHAIN_ARM_STD/efr32pg12b.sct | 2 +- .../TOOLCHAIN_ARM_STD/startup_efm32pg12b.s | 0 .../device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld | 4 ++-- .../TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S | 0 .../TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf | 4 ++-- .../device/TOOLCHAIN_IAR/startup_efm32pg12b.s | 0 .../device/efm32pg12b500f1024gl125.h | 0 .../device/efm32pg12b500f1024gm48.h | 0 .../device/efm32pg12b500f1024il125.h | 0 .../device/efm32pg12b500f1024im48.h | 0 .../device/efm32pg12b500f512gl125.h | 0 .../device/efm32pg12b500f512gm48.h | 0 .../device/efm32pg12b_acmp.h | 0 .../device/efm32pg12b_adc.h | 0 .../device/efm32pg12b_af_pins.h | 0 .../device/efm32pg12b_af_ports.h | 0 .../device/efm32pg12b_cmu.h | 0 .../device/efm32pg12b_cryotimer.h | 0 .../device/efm32pg12b_crypto.h | 0 .../device/efm32pg12b_csen.h | 0 .../device/efm32pg12b_devinfo.h | 0 .../device/efm32pg12b_dma_descriptor.h | 0 .../device/efm32pg12b_dmareq.h | 0 .../device/efm32pg12b_emu.h | 0 .../device/efm32pg12b_etm.h | 0 .../device/efm32pg12b_fpueh.h | 0 .../device/efm32pg12b_gpcrc.h | 0 .../device/efm32pg12b_gpio.h | 0 .../device/efm32pg12b_gpio_p.h | 0 .../device/efm32pg12b_i2c.h | 0 .../device/efm32pg12b_idac.h | 0 .../device/efm32pg12b_ldma.h | 0 .../device/efm32pg12b_ldma_ch.h | 0 .../device/efm32pg12b_lesense.h | 0 .../device/efm32pg12b_lesense_buf.h | 0 .../device/efm32pg12b_lesense_ch.h | 0 .../device/efm32pg12b_lesense_st.h | 0 .../device/efm32pg12b_letimer.h | 0 .../device/efm32pg12b_leuart.h | 0 .../device/efm32pg12b_msc.h | 0 .../device/efm32pg12b_pcnt.h | 0 .../device/efm32pg12b_prs.h | 0 .../device/efm32pg12b_prs_ch.h | 0 .../device/efm32pg12b_prs_signals.h | 0 .../device/efm32pg12b_rmu.h | 0 .../device/efm32pg12b_romtable.h | 0 .../device/efm32pg12b_rtcc.h | 0 .../device/efm32pg12b_rtcc_cc.h | 0 .../device/efm32pg12b_rtcc_ret.h | 0 .../device/efm32pg12b_smu.h | 0 .../device/efm32pg12b_timer.h | 0 .../device/efm32pg12b_timer_cc.h | 0 .../device/efm32pg12b_trng.h | 0 .../device/efm32pg12b_usart.h | 0 .../device/efm32pg12b_vdac.h | 0 .../device/efm32pg12b_vdac_opa.h | 0 .../device/efm32pg12b_wdog.h | 0 .../device/efm32pg12b_wdog_pch.h | 0 .../device/em_device.h | 0 .../device/system_efm32pg12b.c | 0 .../device/system_efm32pg12b.h | 0 .../device/TOOLCHAIN_ARM_STD/efr32mg12p.sct | 2 +- .../device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld | 4 ++-- .../TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf | 4 ++-- .../TARGET_EFM32/common/CommonPinNames.h | 22 +++++++++---------- .../TARGET_EFM32/common/PortNames.h | 15 ++++++++++--- .../TARGET_EFM32/emlib/src/em_system.c | 16 +++++++++----- targets/targets.json | 8 +++---- 73 files changed, 48 insertions(+), 33 deletions(-) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/PeripheralNames.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/PeripheralPins.c (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/PeripheralPins.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/TARGET_EFM32PG12_STK3402/PinNames.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/TARGET_EFM32PG12_STK3402/device_peripherals.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct (89%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld (98%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf (92%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/TOOLCHAIN_IAR/startup_efm32pg12b.s (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b500f1024gl125.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b500f1024gm48.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b500f1024il125.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b500f1024im48.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b500f512gl125.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b500f512gm48.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_acmp.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_adc.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_af_pins.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_af_ports.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_cmu.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_cryotimer.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_crypto.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_csen.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_devinfo.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_dma_descriptor.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_dmareq.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_emu.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_etm.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_fpueh.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_gpcrc.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_gpio.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_gpio_p.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_i2c.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_idac.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_ldma.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_ldma_ch.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_lesense.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_lesense_buf.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_lesense_ch.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_lesense_st.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_letimer.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_leuart.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_msc.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_pcnt.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_prs.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_prs_ch.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_prs_signals.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_rmu.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_romtable.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_rtcc.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_rtcc_cc.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_rtcc_ret.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_smu.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_timer.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_timer_cc.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_trng.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_usart.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_vdac.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_vdac_opa.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_wdog.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/efm32pg12b_wdog_pch.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/em_device.h (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/system_efm32pg12b.c (100%) rename targets/TARGET_Silicon_Labs/TARGET_EFM32/{TARGET_EFR32PG12 => TARGET_EFM32PG12}/device/system_efm32pg12b.h (100%) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralNames.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralNames.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralNames.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.c similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.c rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.c diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralPins.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/PeripheralPins.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/PinNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/PinNames.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/PinNames.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/PinNames.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/TARGET_EFM32PG12_STK3402/device_peripherals.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct similarity index 89% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct index 974cbb0c37..19a1e79085 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/efr32pg12b.sct @@ -8,7 +8,7 @@ LR_IROM1 0x00000000 0x00100000 { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x20000108 0x0003FEF8 { ; RW data + RW_IRAM1 0x2000010C 0x0003FEF4 { ; RW data .ANY (+RW +ZI) } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld similarity index 98% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld index 492a76f10f..43cea81279 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/efm32pg12b.ld @@ -17,8 +17,8 @@ MEMORY /* MBED: mbed needs to be able to dynamically set the interrupt vector table. * We make room for the table at the very beginning of RAM, i.e. at - * 0x20000000. We need (16+50 * sizeof(uint32_t) = 264 bytes for EFM32PG */ -__vector_size = 0x108; + * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */ +__vector_size = 0x10C; /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf similarity index 92% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf index f90304bbbb..ed9fa118f6 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/EFM32PG12B500F1024GL125.icf @@ -10,8 +10,8 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_end__ = (0x00000000+0x00100000-1); define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000107; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000108; +define symbol __NVIC_end__ = 0x2000010B; +define symbol __ICFEDIT_region_RAM_start__ = 0x2000010C; define symbol __ICFEDIT_region_RAM_end__ = (0x20000000+0x00040000-1); /*-Sizes-*/ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gl125.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gl125.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gl125.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gm48.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024gm48.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024gm48.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024il125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024il125.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024il125.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024il125.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024im48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024im48.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f1024im48.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f1024im48.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gl125.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gl125.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gl125.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gl125.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gm48.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gm48.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b500f512gm48.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gm48.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_acmp.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_acmp.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_acmp.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_acmp.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_adc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_adc.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_adc.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_adc.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_pins.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_pins.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_pins.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_pins.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_ports.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_ports.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_af_ports.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_af_ports.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cmu.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cmu.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cmu.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cryotimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cryotimer.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_cryotimer.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_cryotimer.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_crypto.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_crypto.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_crypto.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_crypto.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_csen.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_csen.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_csen.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_csen.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_devinfo.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_devinfo.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_devinfo.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_devinfo.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dma_descriptor.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dma_descriptor.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dma_descriptor.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dma_descriptor.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dmareq.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dmareq.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_dmareq.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_dmareq.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_emu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_emu.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_emu.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_emu.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_etm.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_etm.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_etm.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_etm.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_fpueh.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_fpueh.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_fpueh.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_fpueh.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpcrc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpcrc.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpcrc.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpcrc.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio_p.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio_p.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_gpio_p.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpio_p.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_i2c.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_i2c.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_i2c.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_i2c.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_idac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_idac.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_idac.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_idac.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma_ch.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_ldma_ch.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_ldma_ch.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_buf.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_buf.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_buf.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_buf.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_ch.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_ch.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_ch.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_st.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_st.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_lesense_st.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_lesense_st.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_letimer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_letimer.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_letimer.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_letimer.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_leuart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_leuart.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_leuart.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_leuart.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_msc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_msc.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_msc.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_msc.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_pcnt.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_pcnt.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_pcnt.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_pcnt.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_ch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_ch.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_ch.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_ch.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_signals.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_signals.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_prs_signals.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_prs_signals.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rmu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rmu.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rmu.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rmu.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_romtable.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_romtable.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_romtable.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_romtable.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_cc.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_cc.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_cc.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_ret.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_ret.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_rtcc_ret.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc_ret.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_smu.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_smu.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_smu.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_smu.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer_cc.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer_cc.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_timer_cc.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_timer_cc.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_trng.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_trng.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_trng.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_trng.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_usart.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_usart.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_usart.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_usart.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac_opa.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac_opa.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_vdac_opa.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_vdac_opa.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog_pch.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog_pch.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/efm32pg12b_wdog_pch.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_wdog_pch.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/em_device.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/em_device.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/em_device.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/em_device.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.c similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.c rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.c diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.h similarity index 100% rename from targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/device/system_efm32pg12b.h rename to targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/system_efm32pg12b.h diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct index 974cbb0c37..19a1e79085 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/efr32mg12p.sct @@ -8,7 +8,7 @@ LR_IROM1 0x00000000 0x00100000 { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x20000108 0x0003FEF8 { ; RW data + RW_IRAM1 0x2000010C 0x0003FEF4 { ; RW data .ANY (+RW +ZI) } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld index 2d17d8743e..cf05746430 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_GCC_ARM/efr32mg12p.ld @@ -17,8 +17,8 @@ MEMORY /* MBED: mbed needs to be able to dynamically set the interrupt vector table. * We make room for the table at the very beginning of RAM, i.e. at - * 0x20000000. We need (16+50 * sizeof(uint32_t) = 264 bytes for EFM32PG */ -__vector_size = 0x108; + * 0x20000000. We need (16+51 * sizeof(uint32_t) = 268 bytes for EFM32PG */ +__vector_size = 0x10C; /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf index 8d652ba1e0..a40090df01 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/efr32mg12p332f1024gl125.icf @@ -7,8 +7,8 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000107; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000108; +define symbol __NVIC_end__ = 0x2000010B; +define symbol __ICFEDIT_region_RAM_start__ = 0x2000010C; define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; /*-Sizes-*/ /*Heap 1/4 of ram and stack 1/8*/ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h index e03eac196b..47bc0c03fb 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/CommonPinNames.h @@ -30,17 +30,17 @@ * bits represent port number (A = 0, B = 1, ...) */ #define EFM32_STANDARD_PIN_DEFINITIONS \ - PA0 = 0 << 4, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, \ - PB0 = 1 << 4, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, \ - PC0 = 2 << 4, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, \ - PD0 = 3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, \ - PE0 = 4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, \ - PF0 = 5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, \ - PG0 = 6 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \ - PH0 = 7 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \ - PI0 = 7 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \ - PJ0 = 7 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \ - PK0 = 7 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \ + PA0 = 0 << 4, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, \ + PB0 = 1 << 4, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, \ + PC0 = 2 << 4, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, \ + PD0 = 3 << 4, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, \ + PE0 = 4 << 4, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, \ + PF0 = 5 << 4, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11, PF12, PF13, PF14, PF15, \ + PG0 = 6 << 4, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, PG11, PG12, PG13, PG14, PG15, \ + PH0 = 7 << 4, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, \ + PI0 = 8 << 4, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15, \ + PJ0 = 9 << 4, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, \ + PK0 = 10 << 4, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, PK15, \ NC = (int) 0xFFFFFFFF #ifdef __cplusplus diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h index ebece26ee9..65c44da139 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/PortNames.h @@ -46,13 +46,22 @@ typedef enum { PortE = gpioPortE, /**< Port E */ #endif #if ( _GPIO_PORT_F_PIN_COUNT > 0 ) - PortF = gpioPortF /**< Port F */ + PortF = gpioPortF, /**< Port F */ #endif #if defined( _GPIO_PORT_G_PIN_COUNT ) && ( _GPIO_PORT_G_PIN_COUNT > 0 ) - PortG = gpioPortG /**< Port F */ + PortG = gpioPortG, /**< Port G */ #endif #if defined( _GPIO_PORT_H_PIN_COUNT ) && ( _GPIO_PORT_H_PIN_COUNT > 0 ) - PortH = gpioPortH /**< Port F */ + PortH = gpioPortH, /**< Port H */ +#endif +#if defined( _GPIO_PORT_I_PIN_COUNT ) && ( _GPIO_PORT_I_PIN_COUNT > 0 ) + PortI = gpioPortI, /**< Port I */ +#endif +#if defined( _GPIO_PORT_J_PIN_COUNT ) && ( _GPIO_PORT_J_PIN_COUNT > 0 ) + PortJ = gpioPortJ, /**< Port J */ +#endif +#if defined( _GPIO_PORT_K_PIN_COUNT ) && ( _GPIO_PORT_K_PIN_COUNT > 0 ) + PortK = gpioPortK, /**< Port K */ #endif } PortName; diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c index cac903b062..4476b7f57f 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c @@ -33,6 +33,7 @@ #include "em_system.h" #include "em_assert.h" #include +#include "core_cmSecureAccess.h" /***************************************************************************//** * @addtogroup emlib @@ -60,20 +61,25 @@ void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) uint8_t tmp; EFM_ASSERT(rev); + + uint32_t pid0 = SECURE_READ(&(ROMTABLE->PID0)); + uint32_t pid1 = SECURE_READ(&(ROMTABLE->PID1)); + uint32_t pid2 = SECURE_READ(&(ROMTABLE->PID2)); + uint32_t pid3 = SECURE_READ(&(ROMTABLE->PID3)); /* CHIP FAMILY bit [5:2] */ - tmp = (((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); + tmp = (((pid1 & _ROMTABLE_PID1_FAMILYMSB_MASK) >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); /* CHIP FAMILY bit [1:0] */ - tmp |= ((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); + tmp |= ((pid0 & _ROMTABLE_PID0_FAMILYLSB_MASK) >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); rev->family = tmp; /* CHIP MAJOR bit [3:0] */ - rev->major = (ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; + rev->major = (pid0 & _ROMTABLE_PID0_REVMAJOR_MASK) >> _ROMTABLE_PID0_REVMAJOR_SHIFT; /* CHIP MINOR bit [7:4] */ - tmp = (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + tmp = (((pid2 & _ROMTABLE_PID2_REVMINORMSB_MASK) >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); /* CHIP MINOR bit [3:0] */ - tmp |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + tmp |= ((pid3 & _ROMTABLE_PID3_REVMINORLSB_MASK) >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); rev->minor = tmp; } diff --git a/targets/targets.json b/targets/targets.json index caebe3d835..ff8680fc42 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2336,18 +2336,18 @@ } } }, - "EFM32PG12B500F1024": { + "EFM32PG12B500F1024GL125": { "inherits": ["EFM32"], "extra_labels_add": ["EFM32PG12", "1024K"], "core": "Cortex-M4F", - "macros": ["EFM32PG12B500F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], - "device_name": "EFM32PG12B500F1024", + "device_name": "EFM32PG12B500F1024GL125", "public": false }, "EFM32PG12_STK3402": { - "inherits": ["EFM32PG12B500F1024"], + "inherits": ["EFM32PG12B500F1024GL125"], "device_has": ["AES", "SHA", "ECC", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, "config": { From 2ee05def53799e0a563dc8526790b42a704dc257 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Thu, 16 Mar 2017 11:51:33 +0100 Subject: [PATCH 08/10] EFR32 radio driver small fixes * Reduce verbosity of EFR32 radio driver when debug tracing is on. * Correctly pass pending bit of received ACK to the stack. --- .../TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index bc677ff89f..20b6e45faf 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -288,8 +288,6 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h data_length + 3 }; - tr_debug("Called TX, len %d, chan %d\n", data_length, channel); - switch(radio_state) { case RADIO_UNINIT: tr_debug("Radio uninit\n"); @@ -329,6 +327,8 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h txOpt.waitForAck = false; } + //tr_debug("Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0); + if(RAIL_TxStartWithOptions(channel, &txOpt, &RAIL_CcaCsma, (RAIL_CsmaConfig_t*) &csma_config) == 0) { //Save packet number and sequence current_tx_handle = tx_handle; @@ -614,7 +614,6 @@ void RAILCb_RfReady(void) { * @param[in] status A bit field that defines what event caused the callback */ void RAILCb_TxRadioStatus(uint8_t status) { - tr_debug("Packet TX error %d\n", status); if(device_driver.phy_tx_done_cb != NULL) { if(status == RAIL_TX_CONFIG_BUFFER_UNDERFLOW || status == RAIL_TX_CONFIG_CHANNEL_BUSY || @@ -626,6 +625,8 @@ void RAILCb_TxRadioStatus(uint8_t status) { PHY_LINK_CCA_FAIL, 8, 1); + } else { + tr_debug("Packet TX error %d\n", status); } } radio_state = RADIO_RX; @@ -645,7 +646,13 @@ void RAILCb_TxRadioStatus(uint8_t status) { * @param[in] status The event that triggered this callback */ void RAILCb_RxRadioStatus(uint8_t status) { - tr_debug("RXE %d\n", status); + switch(status) { + case RAIL_RX_CONFIG_ADDRESS_FILTERED: + break; + default: + tr_debug("RXE %d\n", status); + break; + } } /** @@ -729,7 +736,7 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { //tr_debug("rACK\n"); device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, - PHY_LINK_TX_DONE, + last_ack_pending_bit ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE, 1, 1); } else { @@ -787,6 +794,7 @@ void RAILCb_IEEE802154_DataRequestCommand(RAIL_IEEE802154_Address_t *address) { */ void RAILCb_RxAckTimeout(void) { if(waiting_for_ack) { + tr_debug("nACK\n"); waiting_for_ack = false; device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, From b3883115e65a308a17a1ede4e0e12eab7a864e2e Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Thu, 16 Mar 2017 15:23:51 +0100 Subject: [PATCH 09/10] Pass Travis Removing device_name for devices that haven't shown up in the Keil package manager yet to avoid Travis from tripping on our PR --- targets/targets.json | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index ff8680fc42..6d3bc5cc6a 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2343,7 +2343,6 @@ "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], - "device_name": "EFM32PG12B500F1024GL125", "public": false }, "EFM32PG12_STK3402": { @@ -2395,7 +2394,6 @@ "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], - "device_name": "EFR32MG12P332F1024GL125", "public": false }, "THUNDERBOARD_SENSE_12": { From d2173574d06da44c95b019910417d93f6c9d21b9 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Fri, 17 Mar 2017 13:01:50 +0100 Subject: [PATCH 10/10] Stop using device_has for non-mbed options As asked by @0xc0170 in PR #3934, we won't be using device_has for indicating RF/Crypto features any longer. RF config options moved to the SL_RAIL lib.json, crypto config options will come with mbedTLS integration. --- .../TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp | 40 +++++++++---------- .../TARGET_EFM32/common/mbed_overrides.c | 2 +- .../TARGET_SL_RAIL/mbed_lib.json | 31 +++++++++++++- targets/targets.json | 28 ++++++------- 4 files changed, 64 insertions(+), 37 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index 20b6e45faf..875abbb48a 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -80,7 +80,7 @@ static const RAIL_ChannelConfigEntry_t entry[] = { }; #if MBED_CONF_SL_RAIL_BAND == 868 -#ifndef DEVICE_RF_SUBGHZ +#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG #error "Sub-Gigahertz band is not supported on this target." #endif static const RAIL_ChannelConfig_t channels = { @@ -88,7 +88,7 @@ static const RAIL_ChannelConfig_t channels = { 1 }; #elif MBED_CONF_SL_RAIL_BAND == 915 -#ifndef DEVICE_RF_SUBGHZ +#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG #error "Sub-Gigahertz band is not supported on this target." #endif static const RAIL_ChannelConfig_t channels = { @@ -96,7 +96,7 @@ static const RAIL_ChannelConfig_t channels = { 1 }; #elif MBED_CONF_SL_RAIL_BAND == 2400 -#ifndef DEVICE_RF_2P4GHZ +#ifndef MBED_CONF_SL_RAIL_HAS_2P4 #error "2.4GHz band is not supported on this target." #endif static const RAIL_ChannelConfig_t channels = { @@ -113,7 +113,7 @@ static const RAIL_IEEE802154_Config_t config = { false, false, static const RAIL_Init_t railInitParams = { 140, 38400000, RAIL_CAL_ALL_PENDING }; -#if defined (DEVICE_RF_2P4GHZ) +#if defined (MBED_CONF_SL_RAIL_HAS_2P4) // Set up the PA for 2.4 GHz operation static const RADIO_PAInit_t paInit2p4 = { PA_SEL_2P4_HP, /* Power Amplifier mode */ @@ -124,7 +124,7 @@ static const RADIO_PAInit_t paInit2p4 = { }; #endif -#if defined (DEVICE_RF_SUBGHZ) +#if defined (MBED_CONF_SL_RAIL_HAS_SUBGIG) // Set up the PA for sub-GHz operation static const RADIO_PAInit_t paInitSubGhz = { PA_SEL_SUBGIG, /* Power Amplifier mode */ @@ -175,21 +175,19 @@ static int8_t rf_device_register(void) #endif // Set up PTI since it makes life so much easier -#if defined(DEVICE_SL_PTI) +#if defined(MBED_CONF_SL_RAIL_PTI) && (MBED_CONF_SL_RAIL_PTI == 1) RADIO_PTIInit_t ptiInit = { - RADIO_PTI_MODE_UART, - 1600000, - 6, - // TODO: Configure PTI pinout using config system. - // Not very urgent, since all boards use the same pins now. - gpioPortB, - 12, - 6, - gpioPortB, - 11, - 6, - gpioPortB, - 13, + MBED_CONF_SL_RAIL_PTI_MODE, + MBED_CONF_SL_RAIL_PTI_BAUDRATE, + MBED_CONF_SL_RAIL_PTI_DOUT_LOCATION, + MBED_CONF_SL_RAIL_PTI_DOUT_PORT, + MBED_CONF_SL_RAIL_PTI_DOUT_PIN, + MBED_CONF_SL_RAIL_PTI_DCLK_LOCATION, + MBED_CONF_SL_RAIL_PTI_DCLK_PORT, + MBED_CONF_SL_RAIL_PTI_DCLK_PIN, + MBED_CONF_SL_RAIL_PTI_DFRAME_LOCATION, + MBED_CONF_SL_RAIL_PTI_DFRAME_PORT, + MBED_CONF_SL_RAIL_PTI_DFRAME_PIN }; RADIO_PTI_Init(&ptiInit); @@ -198,13 +196,13 @@ static int8_t rf_device_register(void) // Set up RAIL RAIL_RfInit(&railInitParams); RAIL_ChannelConfig(&channels); -#if MBED_CONF_SL_RAIL_BAND == 2400 +#if (MBED_CONF_SL_RAIL_BAND == 2400) RAIL_RadioConfig((void*) ieee802154_config_base); channel = 11; #elif (MBED_CONF_SL_RAIL_BAND == 915) RAIL_RadioConfig((void*) ieee802154_config_915); channel = 1; -#elif MBED_CONF_SL_RAIL_BAND == 868 +#elif (MBED_CONF_SL_RAIL_BAND == 868) RAIL_RadioConfig((void*) ieee802154_config_863); channel = 0; #endif diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c index 66b1d7416a..c003213959 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/common/mbed_overrides.c @@ -42,7 +42,7 @@ void mbed_sdk_init() EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; EMU_DCDCInit(&dcdcInit); -#if defined(DEVICE_RF_2P4GHZ) || defined(DEVICE_RF_SUBGHZ) +#if defined(_EFR_DEVICE) CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_WSTK_DEFAULT; // Initialize the HFXO using the settings from the WSTK bspconfig.h // Note: This configures things like the capacitive tuning CTUNE variable diff --git a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json index fc7c7e0822..1725bc8fd7 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json +++ b/targets/TARGET_Silicon_Labs/TARGET_SL_RAIL/mbed_lib.json @@ -1,6 +1,35 @@ { "name": "sl-rail", "config": { - "band": 2400 + "band": { + "help" : "Configure this to 2400, 915 or 868 depending on which band you want to run on (and have available on the board)", + "value" : 2400 + }, + "PTI": true, + "has-2p4": false, + "has-subgig": false, + "pti-mode": "RADIO_PTI_MODE_UART", + "pti-baudrate" : 1600000, + "pti-dout-location": 6, + "pti-dout-port": "gpioPortB", + "pti-dout-pin": 12, + "pti-dclk-location": 6, + "pti-dclk-port": "gpioPortB", + "pti-dclk-pin": 11, + "pti-dframe-location": 6, + "pti-dframe-port": "gpioPortB", + "pti-dframe-pin": 13 + }, + "target_overrides": { + "THUNDERBOARD_SENSE": { + "sl-rail.has-2p4": true + }, + "THUNDERBOARD_SENSE_12": { + "sl-rail.has-2p4": true + }, + "EFR32MG1_BRD4150": { + "sl-rail.has-2p4": true, + "sl-rail.has-subgig": true + } } } diff --git a/targets/targets.json b/targets/targets.json index 6d3bc5cc6a..a08f523ac5 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1920,7 +1920,7 @@ }, "EFM32GG990F1024": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32GG", "1024K"], + "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"], "core": "Cortex-M3", "macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -1973,7 +1973,7 @@ }, "EFM32LG990F256": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32LG", "256K"], + "extra_labels_add": ["EFM32LG", "256K", "SL_AES"], "core": "Cortex-M3", "macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2026,7 +2026,7 @@ }, "EFM32WG990F256": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32WG", "256K"], + "extra_labels_add": ["EFM32WG", "256K", "SL_AES"], "core": "Cortex-M4F", "macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2079,7 +2079,7 @@ }, "EFM32ZG222F32": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32ZG", "32K"], + "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"], "core": "Cortex-M0+", "default_toolchain": "uARM", "macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"], @@ -2133,7 +2133,7 @@ }, "EFM32HG322F64": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32HG", "64K"], + "extra_labels_add": ["EFM32HG", "64K", "SL_AES"], "core": "Cortex-M0+", "default_toolchain": "uARM", "macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"], @@ -2187,7 +2187,7 @@ }, "EFM32PG1B100F256GM32": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32PG", "256K"], + "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"], "core": "Cortex-M4F", "macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2239,7 +2239,7 @@ }, "EFR32MG1P132F256GM48": { "inherits": ["EFM32"], - "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL"], + "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", "macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2249,7 +2249,7 @@ }, "EFR32MG1P233F256GM48": { "inherits": ["EFM32"], - "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL"], + "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", "macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2258,7 +2258,7 @@ }, "EFR32MG1_BRD4150": { "inherits": ["EFR32MG1P132F256GM48"], - "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "RF_SUBGHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, "config": { "hf_clock_src": { @@ -2301,7 +2301,7 @@ }, "THUNDERBOARD_SENSE": { "inherits": ["EFR32MG1P233F256GM48"], - "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 5, "config": { "hf_clock_src": { @@ -2338,7 +2338,7 @@ }, "EFM32PG12B500F1024GL125": { "inherits": ["EFM32"], - "extra_labels_add": ["EFM32PG12", "1024K"], + "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"], "core": "Cortex-M4F", "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2347,7 +2347,7 @@ }, "EFM32PG12_STK3402": { "inherits": ["EFM32PG12B500F1024GL125"], - "device_has": ["AES", "SHA", "ECC", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 2, "config": { "hf_clock_src": { @@ -2389,7 +2389,7 @@ }, "EFR32MG12P332F1024GL125": { "inherits": ["EFM32"], - "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL"], + "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], @@ -2398,7 +2398,7 @@ }, "THUNDERBOARD_SENSE_12": { "inherits": ["EFR32MG12P332F1024GL125"], - "device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "forced_reset_timeout": 5, "config": { "hf_clock_src": {